2 * Copyright (C) 2007 Ben Skeggs.
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "nouveau_drv.h"
30 #include "nouveau_dma.h"
33 nouveau_dma_pre_init(struct nouveau_channel *chan)
35 chan->dma.max = (chan->pushbuf_bo->bo.mem.size >> 2) - 2;
37 chan->dma.cur = chan->dma.put;
38 chan->dma.free = chan->dma.max - chan->dma.cur;
42 nouveau_dma_init(struct nouveau_channel *chan)
44 struct drm_device *dev = chan->dev;
45 struct drm_nouveau_private *dev_priv = dev->dev_private;
46 struct nouveau_gpuobj *m2mf = NULL;
47 struct nouveau_gpuobj *nvsw = NULL;
50 /* Create NV_MEMORY_TO_MEMORY_FORMAT for buffer moves */
51 ret = nouveau_gpuobj_gr_new(chan, dev_priv->card_type < NV_50 ?
52 0x0039 : 0x5039, &m2mf);
56 ret = nouveau_gpuobj_ref_add(dev, chan, NvM2MF, m2mf, NULL);
60 /* Create an NV_SW object for various sync purposes */
61 ret = nouveau_gpuobj_sw_new(chan, NV_SW, &nvsw);
65 ret = nouveau_gpuobj_ref_add(dev, chan, NvSw, nvsw, NULL);
69 /* NV_MEMORY_TO_MEMORY_FORMAT requires a notifier object */
70 ret = nouveau_notifier_alloc(chan, NvNotify0, 32, &chan->m2mf_ntfy);
75 ret = nouveau_bo_map(chan->pushbuf_bo);
79 /* Map M2MF notifier object - fbcon. */
80 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
81 ret = nouveau_bo_map(chan->notifier_bo);
86 /* Insert NOPS for NOUVEAU_DMA_SKIPS */
87 ret = RING_SPACE(chan, NOUVEAU_DMA_SKIPS);
91 for (i = 0; i < NOUVEAU_DMA_SKIPS; i++)
94 /* Initialise NV_MEMORY_TO_MEMORY_FORMAT */
95 ret = RING_SPACE(chan, 4);
98 BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NAME, 1);
99 OUT_RING(chan, NvM2MF);
100 BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY, 1);
101 OUT_RING(chan, NvNotify0);
103 /* Initialise NV_SW */
104 ret = RING_SPACE(chan, 2);
107 BEGIN_RING(chan, NvSubSw, 0, 1);
108 OUT_RING(chan, NvSw);
110 /* Sit back and pray the channel works.. */
117 OUT_RINGp(struct nouveau_channel *chan, const void *data, unsigned nr_dwords)
120 u32 *mem = ttm_kmap_obj_virtual(&chan->pushbuf_bo->kmap, &is_iomem);
121 mem = &mem[chan->dma.cur];
123 memcpy_toio((void __force __iomem *)mem, data, nr_dwords * 4);
125 memcpy(mem, data, nr_dwords * 4);
126 chan->dma.cur += nr_dwords;
130 READ_GET(struct nouveau_channel *chan, uint32_t *get)
134 val = nvchan_rd32(chan, chan->user_get);
135 if (val < chan->pushbuf_base ||
136 val > chan->pushbuf_base + (chan->dma.max << 2)) {
137 /* meaningless to dma_wait() except to know whether the
138 * GPU has stalled or not
144 *get = (val - chan->pushbuf_base) >> 2;
149 nouveau_dma_wait(struct nouveau_channel *chan, int size)
151 uint32_t get, prev_get = 0, cnt = 0;
154 while (chan->dma.free < size) {
155 /* reset counter as long as GET is still advancing, this is
156 * to avoid misdetecting a GPU lockup if the GPU happens to
157 * just be processing an operation that takes a long time
159 get_valid = READ_GET(chan, &get);
160 if (get != prev_get) {
165 if ((++cnt & 0xff) == 0) {
171 /* loop until we have a usable GET pointer. the value
172 * we read from the GPU may be outside the main ring if
173 * PFIFO is processing a buffer called from the main ring,
174 * discard these values until something sensible is seen.
176 * the other case we discard GET is while the GPU is fetching
177 * from the SKIPS area, so the code below doesn't have to deal
178 * with some fun corner cases.
180 if (!get_valid || get < NOUVEAU_DMA_SKIPS)
183 if (get <= chan->dma.cur) {
184 /* engine is fetching behind us, or is completely
185 * idle (GET == PUT) so we have free space up until
186 * the end of the push buffer
188 * we can only hit that path once per call due to
189 * looping back to the beginning of the push buffer,
190 * we'll hit the fetching-ahead-of-us path from that
193 * the *one* exception to that rule is if we read
194 * GET==PUT, in which case the below conditional will
195 * always succeed and break us out of the wait loop.
197 chan->dma.free = chan->dma.max - chan->dma.cur;
198 if (chan->dma.free >= size)
201 /* not enough space left at the end of the push buffer,
202 * instruct the GPU to jump back to the start right
203 * after processing the currently pending commands.
205 OUT_RING(chan, chan->pushbuf_base | 0x20000000);
206 WRITE_PUT(NOUVEAU_DMA_SKIPS);
208 /* we're now submitting commands at the start of
212 chan->dma.put = NOUVEAU_DMA_SKIPS;
215 /* engine fetching ahead of us, we have space up until the
216 * current GET pointer. the "- 1" is to ensure there's
217 * space left to emit a jump back to the beginning of the
218 * push buffer if we require it. we can never get GET == PUT
219 * here, so this is safe.
221 chan->dma.free = get - chan->dma.cur - 1;