drivers/gpu/drm/nouveau/nouveau_bo.c

   1 /*
   2  * Copyright 2007 Dave Airlied
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24 /*
  25  * Authors: Dave Airlied <airlied@linux.ie>
  26  *          Ben Skeggs   <darktama@iinet.net.au>
  27  *          Jeremy Kolb  <jkolb@brandeis.edu>
  28  */
  29
  30 #include <linux/dma-mapping.h>
  31 #include <drm/ttm/ttm_tt.h>
  32
  33 #include "nouveau_drv.h"
  34 #include "nouveau_chan.h"
  35 #include "nouveau_fence.h"
  36
  37 #include "nouveau_bo.h"
  38 #include "nouveau_ttm.h"
  39 #include "nouveau_gem.h"
  40 #include "nouveau_mem.h"
  41 #include "nouveau_vmm.h"
  42
  43 #include <nvif/class.h>
  44 #include <nvif/if500b.h>
  45 #include <nvif/if900b.h>
  46
  47 static int nouveau_ttm_tt_bind(struct ttm_device *bdev, struct ttm_tt *ttm,
  48                                struct ttm_resource *reg);
  49 static void nouveau_ttm_tt_unbind(struct ttm_device *bdev, struct ttm_tt *ttm);
  50
  51 /*
  52  * NV10-NV40 tiling helpers
  53  */
  54
  55 static void
  56 nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg,
  57                            u32 addr, u32 size, u32 pitch, u32 flags)
  58 {
  59         struct nouveau_drm *drm = nouveau_drm(dev);
  60         int i = reg - drm->tile.reg;
  61         struct nvkm_fb *fb = nvxx_fb(&drm->client.device);
  62         struct nvkm_fb_tile *tile = &fb->tile.region[i];
  63
  64         nouveau_fence_unref(&reg->fence);
  65
  66         if (tile->pitch)
  67                 nvkm_fb_tile_fini(fb, i, tile);
  68
  69         if (pitch)
  70                 nvkm_fb_tile_init(fb, i, addr, size, pitch, flags, tile);
  71
  72         nvkm_fb_tile_prog(fb, i, tile);
  73 }
  74
  75 static struct nouveau_drm_tile *
  76 nv10_bo_get_tile_region(struct drm_device *dev, int i)
  77 {
  78         struct nouveau_drm *drm = nouveau_drm(dev);
  79         struct nouveau_drm_tile *tile = &drm->tile.reg[i];
  80
  81         spin_lock(&drm->tile.lock);
  82
  83         if (!tile->used &&
  84             (!tile->fence || nouveau_fence_done(tile->fence)))
  85                 tile->used = true;
  86         else
  87                 tile = NULL;
  88
  89         spin_unlock(&drm->tile.lock);
  90         return tile;
  91 }
  92
  93 static void
  94 nv10_bo_put_tile_region(struct drm_device *dev, struct nouveau_drm_tile *tile,
  95                         struct dma_fence *fence)
  96 {
  97         struct nouveau_drm *drm = nouveau_drm(dev);
  98
  99         if (tile) {
 100                 spin_lock(&drm->tile.lock);
 101                 tile->fence = (struct nouveau_fence *)dma_fence_get(fence);
 102                 tile->used = false;
 103                 spin_unlock(&drm->tile.lock);
 104         }
 105 }
 106
 107 static struct nouveau_drm_tile *
 108 nv10_bo_set_tiling(struct drm_device *dev, u32 addr,
 109                    u32 size, u32 pitch, u32 zeta)
 110 {
 111         struct nouveau_drm *drm = nouveau_drm(dev);
 112         struct nvkm_fb *fb = nvxx_fb(&drm->client.device);
 113         struct nouveau_drm_tile *tile, *found = NULL;
 114         int i;
 115
 116         for (i = 0; i < fb->tile.regions; i++) {
 117                 tile = nv10_bo_get_tile_region(dev, i);
 118
 119                 if (pitch && !found) {
 120                         found = tile;
 121                         continue;
 122
 123                 } else if (tile && fb->tile.region[i].pitch) {
 124                         /* Kill an unused tile region. */
 125                         nv10_bo_update_tile_region(dev, tile, 0, 0, 0, 0);
 126                 }
 127
 128                 nv10_bo_put_tile_region(dev, tile, NULL);
 129         }
 130
 131         if (found)
 132                 nv10_bo_update_tile_region(dev, found, addr, size, pitch, zeta);
 133         return found;
 134 }
 135
 136 static void
 137 nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
 138 {
 139         struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
 140         struct drm_device *dev = drm->dev;
 141         struct nouveau_bo *nvbo = nouveau_bo(bo);
 142
 143         WARN_ON(nvbo->bo.pin_count > 0);
 144         nouveau_bo_del_io_reserve_lru(bo);
 145         nv10_bo_put_tile_region(dev, nvbo->tile, NULL);
 146
 147         /*
 148          * If nouveau_bo_new() allocated this buffer, the GEM object was never
 149          * initialized, so don't attempt to release it.
 150          */
 151         if (bo->base.dev) {
 152                 /* Gem objects not being shared with other VMs get their
 153                  * dma_resv from a root GEM object.
 154                  */
 155                 if (nvbo->no_share)
 156                         drm_gem_object_put(nvbo->r_obj);
 157
 158                 drm_gem_object_release(&bo->base);
 159         } else {
 160                 dma_resv_fini(&bo->base._resv);
 161         }
 162
 163         kfree(nvbo);
 164 }
 165
 166 static inline u64
 167 roundup_64(u64 x, u32 y)
 168 {
 169         x += y - 1;
 170         do_div(x, y);
 171         return x * y;
 172 }
 173
 174 static void
 175 nouveau_bo_fixup_align(struct nouveau_bo *nvbo, int *align, u64 *size)
 176 {
 177         struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
 178         struct nvif_device *device = &drm->client.device;
 179
 180         if (device->info.family < NV_DEVICE_INFO_V0_TESLA) {
 181                 if (nvbo->mode) {
 182                         if (device->info.chipset >= 0x40) {
 183                                 *align = 65536;
 184                                 *size = roundup_64(*size, 64 * nvbo->mode);
 185
 186                         } else if (device->info.chipset >= 0x30) {
 187                                 *align = 32768;
 188                                 *size = roundup_64(*size, 64 * nvbo->mode);
 189
 190                         } else if (device->info.chipset >= 0x20) {
 191                                 *align = 16384;
 192                                 *size = roundup_64(*size, 64 * nvbo->mode);
 193
 194                         } else if (device->info.chipset >= 0x10) {
 195                                 *align = 16384;
 196                                 *size = roundup_64(*size, 32 * nvbo->mode);
 197                         }
 198                 }
 199         } else {
 200                 *size = roundup_64(*size, (1 << nvbo->page));
 201                 *align = max((1 <<  nvbo->page), *align);
 202         }
 203
 204         *size = roundup_64(*size, PAGE_SIZE);
 205 }
 206
 207 struct nouveau_bo *
 208 nouveau_bo_alloc(struct nouveau_cli *cli, u64 *size, int *align, u32 domain,
 209                  u32 tile_mode, u32 tile_flags, bool internal)
 210 {
 211         struct nouveau_drm *drm = cli->drm;
 212         struct nouveau_bo *nvbo;
 213         struct nvif_mmu *mmu = &cli->mmu;
 214         struct nvif_vmm *vmm = &nouveau_cli_vmm(cli)->vmm;
 215         int i, pi = -1;
 216
 217         if (!*size) {
 218                 NV_WARN(drm, "skipped size %016llx\n", *size);
 219                 return ERR_PTR(-EINVAL);
 220         }
 221
 222         nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL);
 223         if (!nvbo)
 224                 return ERR_PTR(-ENOMEM);
 225
 226         INIT_LIST_HEAD(&nvbo->head);
 227         INIT_LIST_HEAD(&nvbo->entry);
 228         INIT_LIST_HEAD(&nvbo->vma_list);
 229         nvbo->bo.bdev = &drm->ttm.bdev;
 230
 231         /* This is confusing, and doesn't actually mean we want an uncached
 232          * mapping, but is what NOUVEAU_GEM_DOMAIN_COHERENT gets translated
 233          * into in nouveau_gem_new().
 234          */
 235         if (domain & NOUVEAU_GEM_DOMAIN_COHERENT) {
 236                 /* Determine if we can get a cache-coherent map, forcing
 237                  * uncached mapping if we can't.
 238                  */
 239                 if (!nouveau_drm_use_coherent_gpu_mapping(drm))
 240                         nvbo->force_coherent = true;
 241         }
 242
 243         nvbo->contig = !(tile_flags & NOUVEAU_GEM_TILE_NONCONTIG);
 244         if (!nouveau_cli_uvmm(cli) || internal) {
 245                 /* for BO noVM allocs, don't assign kinds */
 246                 if (cli->device.info.family >= NV_DEVICE_INFO_V0_FERMI) {
 247                         nvbo->kind = (tile_flags & 0x0000ff00) >> 8;
 248                         if (!nvif_mmu_kind_valid(mmu, nvbo->kind)) {
 249                                 kfree(nvbo);
 250                                 return ERR_PTR(-EINVAL);
 251                         }
 252
 253                         nvbo->comp = mmu->kind[nvbo->kind] != nvbo->kind;
 254                 } else if (cli->device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
 255                         nvbo->kind = (tile_flags & 0x00007f00) >> 8;
 256                         nvbo->comp = (tile_flags & 0x00030000) >> 16;
 257                         if (!nvif_mmu_kind_valid(mmu, nvbo->kind)) {
 258                                 kfree(nvbo);
 259                                 return ERR_PTR(-EINVAL);
 260                         }
 261                 } else {
 262                         nvbo->zeta = (tile_flags & 0x00000007);
 263                 }
 264                 nvbo->mode = tile_mode;
 265
 266                 /* Determine the desirable target GPU page size for the buffer. */
 267                 for (i = 0; i < vmm->page_nr; i++) {
 268                         /* Because we cannot currently allow VMM maps to fail
 269                          * during buffer migration, we need to determine page
 270                          * size for the buffer up-front, and pre-allocate its
 271                          * page tables.
 272                          *
 273                          * Skip page sizes that can't support needed domains.
 274                          */
 275                         if (cli->device.info.family > NV_DEVICE_INFO_V0_CURIE &&
 276                             (domain & NOUVEAU_GEM_DOMAIN_VRAM) && !vmm->page[i].vram)
 277                                 continue;
 278                         if ((domain & NOUVEAU_GEM_DOMAIN_GART) &&
 279                             (!vmm->page[i].host || vmm->page[i].shift > PAGE_SHIFT))
 280                                 continue;
 281
 282                         /* Select this page size if it's the first that supports
 283                          * the potential memory domains, or when it's compatible
 284                          * with the requested compression settings.
 285                          */
 286                         if (pi < 0 || !nvbo->comp || vmm->page[i].comp)
 287                                 pi = i;
 288
 289                         /* Stop once the buffer is larger than the current page size. */
 290                         if (*size >= 1ULL << vmm->page[i].shift)
 291                                 break;
 292                 }
 293
 294                 if (WARN_ON(pi < 0)) {
 295                         kfree(nvbo);
 296                         return ERR_PTR(-EINVAL);
 297                 }
 298
 299                 /* Disable compression if suitable settings couldn't be found. */
 300                 if (nvbo->comp && !vmm->page[pi].comp) {
 301                         if (mmu->object.oclass >= NVIF_CLASS_MMU_GF100)
 302                                 nvbo->kind = mmu->kind[nvbo->kind];
 303                         nvbo->comp = 0;
 304                 }
 305                 nvbo->page = vmm->page[pi].shift;
 306         } else {
 307                 /* reject other tile flags when in VM mode. */
 308                 if (tile_mode)
 309                         return ERR_PTR(-EINVAL);
 310                 if (tile_flags & ~NOUVEAU_GEM_TILE_NONCONTIG)
 311                         return ERR_PTR(-EINVAL);
 312
 313                 /* Determine the desirable target GPU page size for the buffer. */
 314                 for (i = 0; i < vmm->page_nr; i++) {
 315                         /* Because we cannot currently allow VMM maps to fail
 316                          * during buffer migration, we need to determine page
 317                          * size for the buffer up-front, and pre-allocate its
 318                          * page tables.
 319                          *
 320                          * Skip page sizes that can't support needed domains.
 321                          */
 322                         if ((domain & NOUVEAU_GEM_DOMAIN_VRAM) && !vmm->page[i].vram)
 323                                 continue;
 324                         if ((domain & NOUVEAU_GEM_DOMAIN_GART) &&
 325                             (!vmm->page[i].host || vmm->page[i].shift > PAGE_SHIFT))
 326                                 continue;
 327
 328                         /* pick the last one as it will be smallest. */
 329                         pi = i;
 330
 331                         /* Stop once the buffer is larger than the current page size. */
 332                         if (*size >= 1ULL << vmm->page[i].shift)
 333                                 break;
 334                 }
 335                 if (WARN_ON(pi < 0)) {
 336                         kfree(nvbo);
 337                         return ERR_PTR(-EINVAL);
 338                 }
 339                 nvbo->page = vmm->page[pi].shift;
 340         }
 341
 342         nouveau_bo_fixup_align(nvbo, align, size);
 343
 344         return nvbo;
 345 }
 346
 347 int
 348 nouveau_bo_init(struct nouveau_bo *nvbo, u64 size, int align, u32 domain,
 349                 struct sg_table *sg, struct dma_resv *robj)
 350 {
 351         int type = sg ? ttm_bo_type_sg : ttm_bo_type_device;
 352         int ret;
 353         struct ttm_operation_ctx ctx = {
 354                 .interruptible = false,
 355                 .no_wait_gpu = false,
 356                 .resv = robj,
 357         };
 358
 359         nouveau_bo_placement_set(nvbo, domain, 0);
 360         INIT_LIST_HEAD(&nvbo->io_reserve_lru);
 361
 362         ret = ttm_bo_init_reserved(nvbo->bo.bdev, &nvbo->bo, type,
 363                                    &nvbo->placement, align >> PAGE_SHIFT, &ctx,
 364                                    sg, robj, nouveau_bo_del_ttm);
 365         if (ret) {
 366                 /* ttm will call nouveau_bo_del_ttm if it fails.. */
 367                 return ret;
 368         }
 369
 370         if (!robj)
 371                 ttm_bo_unreserve(&nvbo->bo);
 372
 373         return 0;
 374 }
 375
 376 int
 377 nouveau_bo_new(struct nouveau_cli *cli, u64 size, int align,
 378                uint32_t domain, uint32_t tile_mode, uint32_t tile_flags,
 379                struct sg_table *sg, struct dma_resv *robj,
 380                struct nouveau_bo **pnvbo)
 381 {
 382         struct nouveau_bo *nvbo;
 383         int ret;
 384
 385         nvbo = nouveau_bo_alloc(cli, &size, &align, domain, tile_mode,
 386                                 tile_flags, true);
 387         if (IS_ERR(nvbo))
 388                 return PTR_ERR(nvbo);
 389
 390         nvbo->bo.base.size = size;
 391         dma_resv_init(&nvbo->bo.base._resv);
 392         drm_vma_node_reset(&nvbo->bo.base.vma_node);
 393
 394         /* This must be called before ttm_bo_init_reserved(). Subsequent
 395          * bo_move() callbacks might already iterate the GEMs GPUVA list.
 396          */
 397         drm_gem_gpuva_init(&nvbo->bo.base);
 398
 399         ret = nouveau_bo_init(nvbo, size, align, domain, sg, robj);
 400         if (ret)
 401                 return ret;
 402
 403         *pnvbo = nvbo;
 404         return 0;
 405 }
 406
 407 static void
 408 set_placement_range(struct nouveau_bo *nvbo, uint32_t domain)
 409 {
 410         struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
 411         u64 vram_size = drm->client.device.info.ram_size;
 412         unsigned i, fpfn, lpfn;
 413
 414         if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CELSIUS &&
 415             nvbo->mode && (domain & NOUVEAU_GEM_DOMAIN_VRAM) &&
 416             nvbo->bo.base.size < vram_size / 4) {
 417                 /*
 418                  * Make sure that the color and depth buffers are handled
 419                  * by independent memory controller units. Up to a 9x
 420                  * speed up when alpha-blending and depth-test are enabled
 421                  * at the same time.
 422                  */
 423                 if (nvbo->zeta) {
 424                         fpfn = (vram_size / 2) >> PAGE_SHIFT;
 425                         lpfn = ~0;
 426                 } else {
 427                         fpfn = 0;
 428                         lpfn = (vram_size / 2) >> PAGE_SHIFT;
 429                 }
 430                 for (i = 0; i < nvbo->placement.num_placement; ++i) {
 431                         nvbo->placements[i].fpfn = fpfn;
 432                         nvbo->placements[i].lpfn = lpfn;
 433                 }
 434         }
 435 }
 436
 437 void
 438 nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t domain,
 439                          uint32_t busy)
 440 {
 441         unsigned int *n = &nvbo->placement.num_placement;
 442         struct ttm_place *pl = nvbo->placements;
 443
 444         domain |= busy;
 445
 446         *n = 0;
 447         if (domain & NOUVEAU_GEM_DOMAIN_VRAM) {
 448                 pl[*n].mem_type = TTM_PL_VRAM;
 449                 pl[*n].flags = busy & NOUVEAU_GEM_DOMAIN_VRAM ?
 450                         TTM_PL_FLAG_FALLBACK : 0;
 451                 (*n)++;
 452         }
 453         if (domain & NOUVEAU_GEM_DOMAIN_GART) {
 454                 pl[*n].mem_type = TTM_PL_TT;
 455                 pl[*n].flags = busy & NOUVEAU_GEM_DOMAIN_GART ?
 456                         TTM_PL_FLAG_FALLBACK : 0;
 457                 (*n)++;
 458         }
 459         if (domain & NOUVEAU_GEM_DOMAIN_CPU) {
 460                 pl[*n].mem_type = TTM_PL_SYSTEM;
 461                 pl[*n].flags = busy & NOUVEAU_GEM_DOMAIN_CPU ?
 462                         TTM_PL_FLAG_FALLBACK : 0;
 463                 (*n)++;
 464         }
 465
 466         nvbo->placement.placement = nvbo->placements;
 467         set_placement_range(nvbo, domain);
 468 }
 469
 470 int nouveau_bo_pin_locked(struct nouveau_bo *nvbo, uint32_t domain, bool contig)
 471 {
 472         struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
 473         struct ttm_buffer_object *bo = &nvbo->bo;
 474         bool force = false, evict = false;
 475         int ret = 0;
 476
 477         dma_resv_assert_held(bo->base.resv);
 478
 479         if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA &&
 480             domain == NOUVEAU_GEM_DOMAIN_VRAM && contig) {
 481                 if (!nvbo->contig) {
 482                         nvbo->contig = true;
 483                         force = true;
 484                         evict = true;
 485                 }
 486         }
 487
 488         if (nvbo->bo.pin_count) {
 489                 bool error = evict;
 490
 491                 switch (bo->resource->mem_type) {
 492                 case TTM_PL_VRAM:
 493                         error |= !(domain & NOUVEAU_GEM_DOMAIN_VRAM);
 494                         break;
 495                 case TTM_PL_TT:
 496                         error |= !(domain & NOUVEAU_GEM_DOMAIN_GART);
 497                         break;
 498                 default:
 499                         break;
 500                 }
 501
 502                 if (error) {
 503                         NV_ERROR(drm, "bo %p pinned elsewhere: "
 504                                       "0x%08x vs 0x%08x\n", bo,
 505                                  bo->resource->mem_type, domain);
 506                         ret = -EBUSY;
 507                 }
 508                 ttm_bo_pin(&nvbo->bo);
 509                 goto out;
 510         }
 511
 512         if (evict) {
 513                 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_GART, 0);
 514                 ret = nouveau_bo_validate(nvbo, false, false);
 515                 if (ret)
 516                         goto out;
 517         }
 518
 519         nouveau_bo_placement_set(nvbo, domain, 0);
 520         ret = nouveau_bo_validate(nvbo, false, false);
 521         if (ret)
 522                 goto out;
 523
 524         ttm_bo_pin(&nvbo->bo);
 525
 526         switch (bo->resource->mem_type) {
 527         case TTM_PL_VRAM:
 528                 drm->gem.vram_available -= bo->base.size;
 529                 break;
 530         case TTM_PL_TT:
 531                 drm->gem.gart_available -= bo->base.size;
 532                 break;
 533         default:
 534                 break;
 535         }
 536
 537 out:
 538         if (force && ret)
 539                 nvbo->contig = false;
 540         return ret;
 541 }
 542
 543 void nouveau_bo_unpin_locked(struct nouveau_bo *nvbo)
 544 {
 545         struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
 546         struct ttm_buffer_object *bo = &nvbo->bo;
 547
 548         dma_resv_assert_held(bo->base.resv);
 549
 550         ttm_bo_unpin(&nvbo->bo);
 551         if (!nvbo->bo.pin_count) {
 552                 switch (bo->resource->mem_type) {
 553                 case TTM_PL_VRAM:
 554                         drm->gem.vram_available += bo->base.size;
 555                         break;
 556                 case TTM_PL_TT:
 557                         drm->gem.gart_available += bo->base.size;
 558                         break;
 559                 default:
 560                         break;
 561                 }
 562         }
 563 }
 564
 565 int nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t domain, bool contig)
 566 {
 567         struct ttm_buffer_object *bo = &nvbo->bo;
 568         int ret;
 569
 570         ret = ttm_bo_reserve(bo, false, false, NULL);
 571         if (ret)
 572                 return ret;
 573         ret = nouveau_bo_pin_locked(nvbo, domain, contig);
 574         ttm_bo_unreserve(bo);
 575
 576         return ret;
 577 }
 578
 579 int nouveau_bo_unpin(struct nouveau_bo *nvbo)
 580 {
 581         struct ttm_buffer_object *bo = &nvbo->bo;
 582         int ret;
 583
 584         ret = ttm_bo_reserve(bo, false, false, NULL);
 585         if (ret)
 586                 return ret;
 587         nouveau_bo_unpin_locked(nvbo);
 588         ttm_bo_unreserve(bo);
 589
 590         return 0;
 591 }
 592
 593 int
 594 nouveau_bo_map(struct nouveau_bo *nvbo)
 595 {
 596         int ret;
 597
 598         ret = ttm_bo_reserve(&nvbo->bo, false, false, NULL);
 599         if (ret)
 600                 return ret;
 601
 602         ret = ttm_bo_kmap(&nvbo->bo, 0, PFN_UP(nvbo->bo.base.size), &nvbo->kmap);
 603
 604         ttm_bo_unreserve(&nvbo->bo);
 605         return ret;
 606 }
 607
 608 void
 609 nouveau_bo_unmap(struct nouveau_bo *nvbo)
 610 {
 611         if (!nvbo)
 612                 return;
 613
 614         ttm_bo_kunmap(&nvbo->kmap);
 615 }
 616
 617 void
 618 nouveau_bo_sync_for_device(struct nouveau_bo *nvbo)
 619 {
 620         struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
 621         struct ttm_tt *ttm_dma = (struct ttm_tt *)nvbo->bo.ttm;
 622         int i, j;
 623
 624         if (!ttm_dma || !ttm_dma->dma_address)
 625                 return;
 626         if (!ttm_dma->pages) {
 627                 NV_DEBUG(drm, "ttm_dma 0x%p: pages NULL\n", ttm_dma);
 628                 return;
 629         }
 630
 631         /* Don't waste time looping if the object is coherent */
 632         if (nvbo->force_coherent)
 633                 return;
 634
 635         i = 0;
 636         while (i < ttm_dma->num_pages) {
 637                 struct page *p = ttm_dma->pages[i];
 638                 size_t num_pages = 1;
 639
 640                 for (j = i + 1; j < ttm_dma->num_pages; ++j) {
 641                         if (++p != ttm_dma->pages[j])
 642                                 break;
 643
 644                         ++num_pages;
 645                 }
 646                 dma_sync_single_for_device(drm->dev->dev,
 647                                            ttm_dma->dma_address[i],
 648                                            num_pages * PAGE_SIZE, DMA_TO_DEVICE);
 649                 i += num_pages;
 650         }
 651 }
 652
 653 void
 654 nouveau_bo_sync_for_cpu(struct nouveau_bo *nvbo)
 655 {
 656         struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
 657         struct ttm_tt *ttm_dma = (struct ttm_tt *)nvbo->bo.ttm;
 658         int i, j;
 659
 660         if (!ttm_dma || !ttm_dma->dma_address)
 661                 return;
 662         if (!ttm_dma->pages) {
 663                 NV_DEBUG(drm, "ttm_dma 0x%p: pages NULL\n", ttm_dma);
 664                 return;
 665         }
 666
 667         /* Don't waste time looping if the object is coherent */
 668         if (nvbo->force_coherent)
 669                 return;
 670
 671         i = 0;
 672         while (i < ttm_dma->num_pages) {
 673                 struct page *p = ttm_dma->pages[i];
 674                 size_t num_pages = 1;
 675
 676                 for (j = i + 1; j < ttm_dma->num_pages; ++j) {
 677                         if (++p != ttm_dma->pages[j])
 678                                 break;
 679
 680                         ++num_pages;
 681                 }
 682
 683                 dma_sync_single_for_cpu(drm->dev->dev, ttm_dma->dma_address[i],
 684                                         num_pages * PAGE_SIZE, DMA_FROM_DEVICE);
 685                 i += num_pages;
 686         }
 687 }
 688
 689 void nouveau_bo_add_io_reserve_lru(struct ttm_buffer_object *bo)
 690 {
 691         struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
 692         struct nouveau_bo *nvbo = nouveau_bo(bo);
 693
 694         mutex_lock(&drm->ttm.io_reserve_mutex);
 695         list_move_tail(&nvbo->io_reserve_lru, &drm->ttm.io_reserve_lru);
 696         mutex_unlock(&drm->ttm.io_reserve_mutex);
 697 }
 698
 699 void nouveau_bo_del_io_reserve_lru(struct ttm_buffer_object *bo)
 700 {
 701         struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
 702         struct nouveau_bo *nvbo = nouveau_bo(bo);
 703
 704         mutex_lock(&drm->ttm.io_reserve_mutex);
 705         list_del_init(&nvbo->io_reserve_lru);
 706         mutex_unlock(&drm->ttm.io_reserve_mutex);
 707 }
 708
 709 int
 710 nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible,
 711                     bool no_wait_gpu)
 712 {
 713         struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu };
 714         int ret;
 715
 716         ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement, &ctx);
 717         if (ret)
 718                 return ret;
 719
 720         nouveau_bo_sync_for_device(nvbo);
 721
 722         return 0;
 723 }
 724
 725 void
 726 nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
 727 {
 728         bool is_iomem;
 729         u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
 730
 731         mem += index;
 732
 733         if (is_iomem)
 734                 iowrite16_native(val, (void __force __iomem *)mem);
 735         else
 736                 *mem = val;
 737 }
 738
 739 u32
 740 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index)
 741 {
 742         bool is_iomem;
 743         u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
 744
 745         mem += index;
 746
 747         if (is_iomem)
 748                 return ioread32_native((void __force __iomem *)mem);
 749         else
 750                 return *mem;
 751 }
 752
 753 void
 754 nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)
 755 {
 756         bool is_iomem;
 757         u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
 758
 759         mem += index;
 760
 761         if (is_iomem)
 762                 iowrite32_native(val, (void __force __iomem *)mem);
 763         else
 764                 *mem = val;
 765 }
 766
 767 static struct ttm_tt *
 768 nouveau_ttm_tt_create(struct ttm_buffer_object *bo, uint32_t page_flags)
 769 {
 770 #if IS_ENABLED(CONFIG_AGP)
 771         struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
 772
 773         if (drm->agp.bridge) {
 774                 return ttm_agp_tt_create(bo, drm->agp.bridge, page_flags);
 775         }
 776 #endif
 777
 778         return nouveau_sgdma_create_ttm(bo, page_flags);
 779 }
 780
 781 static int
 782 nouveau_ttm_tt_bind(struct ttm_device *bdev, struct ttm_tt *ttm,
 783                     struct ttm_resource *reg)
 784 {
 785 #if IS_ENABLED(CONFIG_AGP)
 786         struct nouveau_drm *drm = nouveau_bdev(bdev);
 787 #endif
 788         if (!reg)
 789                 return -EINVAL;
 790 #if IS_ENABLED(CONFIG_AGP)
 791         if (drm->agp.bridge)
 792                 return ttm_agp_bind(ttm, reg);
 793 #endif
 794         return nouveau_sgdma_bind(bdev, ttm, reg);
 795 }
 796
 797 static void
 798 nouveau_ttm_tt_unbind(struct ttm_device *bdev, struct ttm_tt *ttm)
 799 {
 800 #if IS_ENABLED(CONFIG_AGP)
 801         struct nouveau_drm *drm = nouveau_bdev(bdev);
 802
 803         if (drm->agp.bridge) {
 804                 ttm_agp_unbind(ttm);
 805                 return;
 806         }
 807 #endif
 808         nouveau_sgdma_unbind(bdev, ttm);
 809 }
 810
 811 static void
 812 nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
 813 {
 814         struct nouveau_bo *nvbo = nouveau_bo(bo);
 815
 816         switch (bo->resource->mem_type) {
 817         case TTM_PL_VRAM:
 818                 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_GART,
 819                                          NOUVEAU_GEM_DOMAIN_CPU);
 820                 break;
 821         default:
 822                 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_CPU, 0);
 823                 break;
 824         }
 825
 826         *pl = nvbo->placement;
 827 }
 828
 829 static int
 830 nouveau_bo_move_prep(struct nouveau_drm *drm, struct ttm_buffer_object *bo,
 831                      struct ttm_resource *reg)
 832 {
 833         struct nouveau_mem *old_mem = nouveau_mem(bo->resource);
 834         struct nouveau_mem *new_mem = nouveau_mem(reg);
 835         struct nvif_vmm *vmm = &drm->client.vmm.vmm;
 836         int ret;
 837
 838         ret = nvif_vmm_get(vmm, LAZY, false, old_mem->mem.page, 0,
 839                            old_mem->mem.size, &old_mem->vma[0]);
 840         if (ret)
 841                 return ret;
 842
 843         ret = nvif_vmm_get(vmm, LAZY, false, new_mem->mem.page, 0,
 844                            new_mem->mem.size, &old_mem->vma[1]);
 845         if (ret)
 846                 goto done;
 847
 848         ret = nouveau_mem_map(old_mem, vmm, &old_mem->vma[0]);
 849         if (ret)
 850                 goto done;
 851
 852         ret = nouveau_mem_map(new_mem, vmm, &old_mem->vma[1]);
 853 done:
 854         if (ret) {
 855                 nvif_vmm_put(vmm, &old_mem->vma[1]);
 856                 nvif_vmm_put(vmm, &old_mem->vma[0]);
 857         }
 858         return 0;
 859 }
 860
 861 static int
 862 nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict,
 863                      struct ttm_operation_ctx *ctx,
 864                      struct ttm_resource *new_reg)
 865 {
 866         struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
 867         struct nouveau_channel *chan = drm->ttm.chan;
 868         struct nouveau_cli *cli = (void *)chan->user.client;
 869         struct nouveau_fence *fence;
 870         int ret;
 871
 872         /* create temporary vmas for the transfer and attach them to the
 873          * old nvkm_mem node, these will get cleaned up after ttm has
 874          * destroyed the ttm_resource
 875          */
 876         if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
 877                 ret = nouveau_bo_move_prep(drm, bo, new_reg);
 878                 if (ret)
 879                         return ret;
 880         }
 881
 882         if (drm_drv_uses_atomic_modeset(drm->dev))
 883                 mutex_lock(&cli->mutex);
 884         else
 885                 mutex_lock_nested(&cli->mutex, SINGLE_DEPTH_NESTING);
 886
 887         ret = nouveau_fence_sync(nouveau_bo(bo), chan, true, ctx->interruptible);
 888         if (ret)
 889                 goto out_unlock;
 890
 891         ret = drm->ttm.move(chan, bo, bo->resource, new_reg);
 892         if (ret)
 893                 goto out_unlock;
 894
 895         ret = nouveau_fence_new(&fence, chan);
 896         if (ret)
 897                 goto out_unlock;
 898
 899         /* TODO: figure out a better solution here
 900          *
 901          * wait on the fence here explicitly as going through
 902          * ttm_bo_move_accel_cleanup somehow doesn't seem to do it.
 903          *
 904          * Without this the operation can timeout and we'll fallback to a
 905          * software copy, which might take several minutes to finish.
 906          */
 907         nouveau_fence_wait(fence, false, false);
 908         ret = ttm_bo_move_accel_cleanup(bo, &fence->base, evict, false,
 909                                         new_reg);
 910         nouveau_fence_unref(&fence);
 911
 912 out_unlock:
 913         mutex_unlock(&cli->mutex);
 914         return ret;
 915 }
 916
 917 void
 918 nouveau_bo_move_init(struct nouveau_drm *drm)
 919 {
 920         static const struct _method_table {
 921                 const char *name;
 922                 int engine;
 923                 s32 oclass;
 924                 int (*exec)(struct nouveau_channel *,
 925                             struct ttm_buffer_object *,
 926                             struct ttm_resource *, struct ttm_resource *);
 927                 int (*init)(struct nouveau_channel *, u32 handle);
 928         } _methods[] = {
 929                 {  "COPY", 4, 0xc7b5, nve0_bo_move_copy, nve0_bo_move_init },
 930                 {  "GRCE", 0, 0xc7b5, nve0_bo_move_copy, nvc0_bo_move_init },
 931                 {  "COPY", 4, 0xc6b5, nve0_bo_move_copy, nve0_bo_move_init },
 932                 {  "GRCE", 0, 0xc6b5, nve0_bo_move_copy, nvc0_bo_move_init },
 933                 {  "COPY", 4, 0xc5b5, nve0_bo_move_copy, nve0_bo_move_init },
 934                 {  "GRCE", 0, 0xc5b5, nve0_bo_move_copy, nvc0_bo_move_init },
 935                 {  "COPY", 4, 0xc3b5, nve0_bo_move_copy, nve0_bo_move_init },
 936                 {  "GRCE", 0, 0xc3b5, nve0_bo_move_copy, nvc0_bo_move_init },
 937                 {  "COPY", 4, 0xc1b5, nve0_bo_move_copy, nve0_bo_move_init },
 938                 {  "GRCE", 0, 0xc1b5, nve0_bo_move_copy, nvc0_bo_move_init },
 939                 {  "COPY", 4, 0xc0b5, nve0_bo_move_copy, nve0_bo_move_init },
 940                 {  "GRCE", 0, 0xc0b5, nve0_bo_move_copy, nvc0_bo_move_init },
 941                 {  "COPY", 4, 0xb0b5, nve0_bo_move_copy, nve0_bo_move_init },
 942                 {  "GRCE", 0, 0xb0b5, nve0_bo_move_copy, nvc0_bo_move_init },
 943                 {  "COPY", 4, 0xa0b5, nve0_bo_move_copy, nve0_bo_move_init },
 944                 {  "GRCE", 0, 0xa0b5, nve0_bo_move_copy, nvc0_bo_move_init },
 945                 { "COPY1", 5, 0x90b8, nvc0_bo_move_copy, nvc0_bo_move_init },
 946                 { "COPY0", 4, 0x90b5, nvc0_bo_move_copy, nvc0_bo_move_init },
 947                 {  "COPY", 0, 0x85b5, nva3_bo_move_copy, nv50_bo_move_init },
 948                 { "CRYPT", 0, 0x74c1, nv84_bo_move_exec, nv50_bo_move_init },
 949                 {  "M2MF", 0, 0x9039, nvc0_bo_move_m2mf, nvc0_bo_move_init },
 950                 {  "M2MF", 0, 0x5039, nv50_bo_move_m2mf, nv50_bo_move_init },
 951                 {  "M2MF", 0, 0x0039, nv04_bo_move_m2mf, nv04_bo_move_init },
 952                 {},
 953         };
 954         const struct _method_table *mthd = _methods;
 955         const char *name = "CPU";
 956         int ret;
 957
 958         do {
 959                 struct nouveau_channel *chan;
 960
 961                 if (mthd->engine)
 962                         chan = drm->cechan;
 963                 else
 964                         chan = drm->channel;
 965                 if (chan == NULL)
 966                         continue;
 967
 968                 ret = nvif_object_ctor(&chan->user, "ttmBoMove",
 969                                        mthd->oclass | (mthd->engine << 16),
 970                                        mthd->oclass, NULL, 0,
 971                                        &drm->ttm.copy);
 972                 if (ret == 0) {
 973                         ret = mthd->init(chan, drm->ttm.copy.handle);
 974                         if (ret) {
 975                                 nvif_object_dtor(&drm->ttm.copy);
 976                                 continue;
 977                         }
 978
 979                         drm->ttm.move = mthd->exec;
 980                         drm->ttm.chan = chan;
 981                         name = mthd->name;
 982                         break;
 983                 }
 984         } while ((++mthd)->exec);
 985
 986         NV_INFO(drm, "MM: using %s for buffer copies\n", name);
 987 }
 988
 989 static void nouveau_bo_move_ntfy(struct ttm_buffer_object *bo,
 990                                  struct ttm_resource *new_reg)
 991 {
 992         struct nouveau_mem *mem = new_reg ? nouveau_mem(new_reg) : NULL;
 993         struct nouveau_bo *nvbo = nouveau_bo(bo);
 994         struct nouveau_vma *vma;
 995         long ret;
 996
 997         /* ttm can now (stupidly) pass the driver bos it didn't create... */
 998         if (bo->destroy != nouveau_bo_del_ttm)
 999                 return;
1000
1001         nouveau_bo_del_io_reserve_lru(bo);
1002
1003         if (mem && new_reg->mem_type != TTM_PL_SYSTEM &&
1004             mem->mem.page == nvbo->page) {
1005                 list_for_each_entry(vma, &nvbo->vma_list, head) {
1006                         nouveau_vma_map(vma, mem);
1007                 }
1008                 nouveau_uvmm_bo_map_all(nvbo, mem);
1009         } else {
1010                 list_for_each_entry(vma, &nvbo->vma_list, head) {
1011                         ret = dma_resv_wait_timeout(bo->base.resv,
1012                                                     DMA_RESV_USAGE_BOOKKEEP,
1013                                                     false, 15 * HZ);
1014                         WARN_ON(ret <= 0);
1015                         nouveau_vma_unmap(vma);
1016                 }
1017                 nouveau_uvmm_bo_unmap_all(nvbo);
1018         }
1019
1020         if (new_reg)
1021                 nvbo->offset = (new_reg->start << PAGE_SHIFT);
1022
1023 }
1024
1025 static int
1026 nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_resource *new_reg,
1027                    struct nouveau_drm_tile **new_tile)
1028 {
1029         struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1030         struct drm_device *dev = drm->dev;
1031         struct nouveau_bo *nvbo = nouveau_bo(bo);
1032         u64 offset = new_reg->start << PAGE_SHIFT;
1033
1034         *new_tile = NULL;
1035         if (new_reg->mem_type != TTM_PL_VRAM)
1036                 return 0;
1037
1038         if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) {
1039                 *new_tile = nv10_bo_set_tiling(dev, offset, bo->base.size,
1040                                                nvbo->mode, nvbo->zeta);
1041         }
1042
1043         return 0;
1044 }
1045
1046 static void
1047 nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo,
1048                       struct nouveau_drm_tile *new_tile,
1049                       struct nouveau_drm_tile **old_tile)
1050 {
1051         struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1052         struct drm_device *dev = drm->dev;
1053         struct dma_fence *fence;
1054         int ret;
1055
1056         ret = dma_resv_get_singleton(bo->base.resv, DMA_RESV_USAGE_WRITE,
1057                                      &fence);
1058         if (ret)
1059                 dma_resv_wait_timeout(bo->base.resv, DMA_RESV_USAGE_WRITE,
1060                                       false, MAX_SCHEDULE_TIMEOUT);
1061
1062         nv10_bo_put_tile_region(dev, *old_tile, fence);
1063         *old_tile = new_tile;
1064 }
1065
1066 static int
1067 nouveau_bo_move(struct ttm_buffer_object *bo, bool evict,
1068                 struct ttm_operation_ctx *ctx,
1069                 struct ttm_resource *new_reg,
1070                 struct ttm_place *hop)
1071 {
1072         struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1073         struct nouveau_bo *nvbo = nouveau_bo(bo);
1074         struct drm_gem_object *obj = &bo->base;
1075         struct ttm_resource *old_reg = bo->resource;
1076         struct nouveau_drm_tile *new_tile = NULL;
1077         int ret = 0;
1078
1079         if (new_reg->mem_type == TTM_PL_TT) {
1080                 ret = nouveau_ttm_tt_bind(bo->bdev, bo->ttm, new_reg);
1081                 if (ret)
1082                         return ret;
1083         }
1084
1085         drm_gpuvm_bo_gem_evict(obj, evict);
1086         nouveau_bo_move_ntfy(bo, new_reg);
1087         ret = ttm_bo_wait_ctx(bo, ctx);
1088         if (ret)
1089                 goto out_ntfy;
1090
1091         if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) {
1092                 ret = nouveau_bo_vm_bind(bo, new_reg, &new_tile);
1093                 if (ret)
1094                         goto out_ntfy;
1095         }
1096
1097         /* Fake bo copy. */
1098         if (!old_reg || (old_reg->mem_type == TTM_PL_SYSTEM &&
1099                          !bo->ttm)) {
1100                 ttm_bo_move_null(bo, new_reg);
1101                 goto out;
1102         }
1103
1104         if (old_reg->mem_type == TTM_PL_SYSTEM &&
1105             new_reg->mem_type == TTM_PL_TT) {
1106                 ttm_bo_move_null(bo, new_reg);
1107                 goto out;
1108         }
1109
1110         if (old_reg->mem_type == TTM_PL_TT &&
1111             new_reg->mem_type == TTM_PL_SYSTEM) {
1112                 nouveau_ttm_tt_unbind(bo->bdev, bo->ttm);
1113                 ttm_resource_free(bo, &bo->resource);
1114                 ttm_bo_assign_mem(bo, new_reg);
1115                 goto out;
1116         }
1117
1118         /* Hardware assisted copy. */
1119         if (drm->ttm.move) {
1120                 if ((old_reg->mem_type == TTM_PL_SYSTEM &&
1121                      new_reg->mem_type == TTM_PL_VRAM) ||
1122                     (old_reg->mem_type == TTM_PL_VRAM &&
1123                      new_reg->mem_type == TTM_PL_SYSTEM)) {
1124                         hop->fpfn = 0;
1125                         hop->lpfn = 0;
1126                         hop->mem_type = TTM_PL_TT;
1127                         hop->flags = 0;
1128                         return -EMULTIHOP;
1129                 }
1130                 ret = nouveau_bo_move_m2mf(bo, evict, ctx,
1131                                            new_reg);
1132         } else
1133                 ret = -ENODEV;
1134
1135         if (ret) {
1136                 /* Fallback to software copy. */
1137                 ret = ttm_bo_move_memcpy(bo, ctx, new_reg);
1138         }
1139
1140 out:
1141         if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) {
1142                 if (ret)
1143                         nouveau_bo_vm_cleanup(bo, NULL, &new_tile);
1144                 else
1145                         nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile);
1146         }
1147 out_ntfy:
1148         if (ret) {
1149                 nouveau_bo_move_ntfy(bo, bo->resource);
1150                 drm_gpuvm_bo_gem_evict(obj, !evict);
1151         }
1152         return ret;
1153 }
1154
1155 static void
1156 nouveau_ttm_io_mem_free_locked(struct nouveau_drm *drm,
1157                                struct ttm_resource *reg)
1158 {
1159         struct nouveau_mem *mem = nouveau_mem(reg);
1160
1161         if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) {
1162                 switch (reg->mem_type) {
1163                 case TTM_PL_TT:
1164                         if (mem->kind)
1165                                 nvif_object_unmap_handle(&mem->mem.object);
1166                         break;
1167                 case TTM_PL_VRAM:
1168                         nvif_object_unmap_handle(&mem->mem.object);
1169                         break;
1170                 default:
1171                         break;
1172                 }
1173         }
1174 }
1175
1176 static int
1177 nouveau_ttm_io_mem_reserve(struct ttm_device *bdev, struct ttm_resource *reg)
1178 {
1179         struct nouveau_drm *drm = nouveau_bdev(bdev);
1180         struct nvkm_device *device = nvxx_device(&drm->client.device);
1181         struct nouveau_mem *mem = nouveau_mem(reg);
1182         struct nvif_mmu *mmu = &drm->client.mmu;
1183         int ret;
1184
1185         mutex_lock(&drm->ttm.io_reserve_mutex);
1186 retry:
1187         switch (reg->mem_type) {
1188         case TTM_PL_SYSTEM:
1189                 /* System memory */
1190                 ret = 0;
1191                 goto out;
1192         case TTM_PL_TT:
1193 #if IS_ENABLED(CONFIG_AGP)
1194                 if (drm->agp.bridge) {
1195                         reg->bus.offset = (reg->start << PAGE_SHIFT) +
1196                                 drm->agp.base;
1197                         reg->bus.is_iomem = !drm->agp.cma;
1198                         reg->bus.caching = ttm_write_combined;
1199                 }
1200 #endif
1201                 if (drm->client.mem->oclass < NVIF_CLASS_MEM_NV50 ||
1202                     !mem->kind) {
1203                         /* untiled */
1204                         ret = 0;
1205                         break;
1206                 }
1207                 fallthrough;    /* tiled memory */
1208         case TTM_PL_VRAM:
1209                 reg->bus.offset = (reg->start << PAGE_SHIFT) +
1210                         device->func->resource_addr(device, 1);
1211                 reg->bus.is_iomem = true;
1212
1213                 /* Some BARs do not support being ioremapped WC */
1214                 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA &&
1215                     mmu->type[drm->ttm.type_vram].type & NVIF_MEM_UNCACHED)
1216                         reg->bus.caching = ttm_uncached;
1217                 else
1218                         reg->bus.caching = ttm_write_combined;
1219
1220                 if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) {
1221                         union {
1222                                 struct nv50_mem_map_v0 nv50;
1223                                 struct gf100_mem_map_v0 gf100;
1224                         } args;
1225                         u64 handle, length;
1226                         u32 argc = 0;
1227
1228                         switch (mem->mem.object.oclass) {
1229                         case NVIF_CLASS_MEM_NV50:
1230                                 args.nv50.version = 0;
1231                                 args.nv50.ro = 0;
1232                                 args.nv50.kind = mem->kind;
1233                                 args.nv50.comp = mem->comp;
1234                                 argc = sizeof(args.nv50);
1235                                 break;
1236                         case NVIF_CLASS_MEM_GF100:
1237                                 args.gf100.version = 0;
1238                                 args.gf100.ro = 0;
1239                                 args.gf100.kind = mem->kind;
1240                                 argc = sizeof(args.gf100);
1241                                 break;
1242                         default:
1243                                 WARN_ON(1);
1244                                 break;
1245                         }
1246
1247                         ret = nvif_object_map_handle(&mem->mem.object,
1248                                                      &args, argc,
1249                                                      &handle, &length);
1250                         if (ret != 1) {
1251                                 if (WARN_ON(ret == 0))
1252                                         ret = -EINVAL;
1253                                 goto out;
1254                         }
1255
1256                         reg->bus.offset = handle;
1257                 }
1258                 ret = 0;
1259                 break;
1260         default:
1261                 ret = -EINVAL;
1262         }
1263
1264 out:
1265         if (ret == -ENOSPC) {
1266                 struct nouveau_bo *nvbo;
1267
1268                 nvbo = list_first_entry_or_null(&drm->ttm.io_reserve_lru,
1269                                                 typeof(*nvbo),
1270                                                 io_reserve_lru);
1271                 if (nvbo) {
1272                         list_del_init(&nvbo->io_reserve_lru);
1273                         drm_vma_node_unmap(&nvbo->bo.base.vma_node,
1274                                            bdev->dev_mapping);
1275                         nouveau_ttm_io_mem_free_locked(drm, nvbo->bo.resource);
1276                         nvbo->bo.resource->bus.offset = 0;
1277                         nvbo->bo.resource->bus.addr = NULL;
1278                         goto retry;
1279                 }
1280
1281         }
1282         mutex_unlock(&drm->ttm.io_reserve_mutex);
1283         return ret;
1284 }
1285
1286 static void
1287 nouveau_ttm_io_mem_free(struct ttm_device *bdev, struct ttm_resource *reg)
1288 {
1289         struct nouveau_drm *drm = nouveau_bdev(bdev);
1290
1291         mutex_lock(&drm->ttm.io_reserve_mutex);
1292         nouveau_ttm_io_mem_free_locked(drm, reg);
1293         mutex_unlock(&drm->ttm.io_reserve_mutex);
1294 }
1295
1296 vm_fault_t nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo)
1297 {
1298         struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1299         struct nouveau_bo *nvbo = nouveau_bo(bo);
1300         struct nvkm_device *device = nvxx_device(&drm->client.device);
1301         u32 mappable = device->func->resource_size(device, 1) >> PAGE_SHIFT;
1302         int i, ret;
1303
1304         /* as long as the bo isn't in vram, and isn't tiled, we've got
1305          * nothing to do here.
1306          */
1307         if (bo->resource->mem_type != TTM_PL_VRAM) {
1308                 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA ||
1309                     !nvbo->kind)
1310                         return 0;
1311
1312                 if (bo->resource->mem_type != TTM_PL_SYSTEM)
1313                         return 0;
1314
1315                 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_GART, 0);
1316
1317         } else {
1318                 /* make sure bo is in mappable vram */
1319                 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA ||
1320                     bo->resource->start + PFN_UP(bo->resource->size) < mappable)
1321                         return 0;
1322
1323                 for (i = 0; i < nvbo->placement.num_placement; ++i) {
1324                         nvbo->placements[i].fpfn = 0;
1325                         nvbo->placements[i].lpfn = mappable;
1326                 }
1327
1328                 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_VRAM, 0);
1329         }
1330
1331         ret = nouveau_bo_validate(nvbo, false, false);
1332         if (unlikely(ret == -EBUSY || ret == -ERESTARTSYS))
1333                 return VM_FAULT_NOPAGE;
1334         else if (unlikely(ret))
1335                 return VM_FAULT_SIGBUS;
1336
1337         ttm_bo_move_to_lru_tail_unlocked(bo);
1338         return 0;
1339 }
1340
1341 static int
1342 nouveau_ttm_tt_populate(struct ttm_device *bdev,
1343                         struct ttm_tt *ttm, struct ttm_operation_ctx *ctx)
1344 {
1345         struct ttm_tt *ttm_dma = (void *)ttm;
1346         struct nouveau_drm *drm;
1347         bool slave = !!(ttm->page_flags & TTM_TT_FLAG_EXTERNAL);
1348
1349         if (ttm_tt_is_populated(ttm))
1350                 return 0;
1351
1352         if (slave && ttm->sg) {
1353                 drm_prime_sg_to_dma_addr_array(ttm->sg, ttm_dma->dma_address,
1354                                                ttm->num_pages);
1355                 return 0;
1356         }
1357
1358         drm = nouveau_bdev(bdev);
1359
1360         return ttm_pool_alloc(&drm->ttm.bdev.pool, ttm, ctx);
1361 }
1362
1363 static void
1364 nouveau_ttm_tt_unpopulate(struct ttm_device *bdev,
1365                           struct ttm_tt *ttm)
1366 {
1367         struct nouveau_drm *drm;
1368         bool slave = !!(ttm->page_flags & TTM_TT_FLAG_EXTERNAL);
1369
1370         if (slave)
1371                 return;
1372
1373         nouveau_ttm_tt_unbind(bdev, ttm);
1374
1375         drm = nouveau_bdev(bdev);
1376
1377         return ttm_pool_free(&drm->ttm.bdev.pool, ttm);
1378 }
1379
1380 static void
1381 nouveau_ttm_tt_destroy(struct ttm_device *bdev,
1382                        struct ttm_tt *ttm)
1383 {
1384 #if IS_ENABLED(CONFIG_AGP)
1385         struct nouveau_drm *drm = nouveau_bdev(bdev);
1386         if (drm->agp.bridge) {
1387                 ttm_agp_destroy(ttm);
1388                 return;
1389         }
1390 #endif
1391         nouveau_sgdma_destroy(bdev, ttm);
1392 }
1393
1394 void
1395 nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence, bool exclusive)
1396 {
1397         struct dma_resv *resv = nvbo->bo.base.resv;
1398
1399         if (!fence)
1400                 return;
1401
1402         dma_resv_add_fence(resv, &fence->base, exclusive ?
1403                            DMA_RESV_USAGE_WRITE : DMA_RESV_USAGE_READ);
1404 }
1405
1406 static void
1407 nouveau_bo_delete_mem_notify(struct ttm_buffer_object *bo)
1408 {
1409         nouveau_bo_move_ntfy(bo, NULL);
1410 }
1411
1412 struct ttm_device_funcs nouveau_bo_driver = {
1413         .ttm_tt_create = &nouveau_ttm_tt_create,
1414         .ttm_tt_populate = &nouveau_ttm_tt_populate,
1415         .ttm_tt_unpopulate = &nouveau_ttm_tt_unpopulate,
1416         .ttm_tt_destroy = &nouveau_ttm_tt_destroy,
1417         .eviction_valuable = ttm_bo_eviction_valuable,
1418         .evict_flags = nouveau_bo_evict_flags,
1419         .delete_mem_notify = nouveau_bo_delete_mem_notify,
1420         .move = nouveau_bo_move,
1421         .io_mem_reserve = &nouveau_ttm_io_mem_reserve,
1422         .io_mem_free = &nouveau_ttm_io_mem_free,
1423 };