2 * Copyright 2005-2006 Erik Waling
3 * Copyright 2006 Stephane Marchesin
4 * Copyright 2007-2009 Stuart Bennett
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
20 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
21 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 #define NV_DEBUG_NOTRACE
27 #include "nouveau_drv.h"
28 #include "nouveau_hw.h"
30 /* these defines are made up */
31 #define NV_CIO_CRE_44_HEADA 0x0
32 #define NV_CIO_CRE_44_HEADB 0x3
33 #define FEATURE_MOBILE 0x10 /* also FEATURE_QUADRO for BMP */
34 #define LEGACY_I2C_CRT 0x80
35 #define LEGACY_I2C_PANEL 0x81
36 #define LEGACY_I2C_TV 0x82
40 #define BIOSLOG(sip, fmt, arg...) NV_DEBUG(sip->dev, fmt, ##arg)
41 #define LOG_OLD_VALUE(x)
43 #define ROM16(x) le16_to_cpu(*(uint16_t *)&(x))
44 #define ROM32(x) le32_to_cpu(*(uint32_t *)&(x))
51 static bool nv_cksum(const uint8_t *data, unsigned int length)
54 * There's a few checksums in the BIOS, so here's a generic checking
60 for (i = 0; i < length; i++)
70 score_vbios(struct drm_device *dev, const uint8_t *data, const bool writeable)
72 if (!(data[0] == 0x55 && data[1] == 0xAA)) {
73 NV_TRACEWARN(dev, "... BIOS signature not found\n");
77 if (nv_cksum(data, data[2] * 512)) {
78 NV_TRACEWARN(dev, "... BIOS checksum invalid\n");
79 /* if a ro image is somewhat bad, it's probably all rubbish */
80 return writeable ? 2 : 1;
82 NV_TRACE(dev, "... appears to be valid\n");
87 static void load_vbios_prom(struct drm_device *dev, uint8_t *data)
89 struct drm_nouveau_private *dev_priv = dev->dev_private;
90 uint32_t pci_nv_20, save_pci_nv_20;
94 if (dev_priv->card_type >= NV_50)
97 pci_nv_20 = NV_PBUS_PCI_NV_20;
99 /* enable ROM access */
100 save_pci_nv_20 = nvReadMC(dev, pci_nv_20);
101 nvWriteMC(dev, pci_nv_20,
102 save_pci_nv_20 & ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED);
104 /* bail if no rom signature */
105 if (nv_rd08(dev, NV_PROM_OFFSET) != 0x55 ||
106 nv_rd08(dev, NV_PROM_OFFSET + 1) != 0xaa)
109 /* additional check (see note below) - read PCI record header */
110 pcir_ptr = nv_rd08(dev, NV_PROM_OFFSET + 0x18) |
111 nv_rd08(dev, NV_PROM_OFFSET + 0x19) << 8;
112 if (nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr) != 'P' ||
113 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 1) != 'C' ||
114 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 2) != 'I' ||
115 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 3) != 'R')
118 /* on some 6600GT/6800LE prom reads are messed up. nvclock alleges a
119 * a good read may be obtained by waiting or re-reading (cargocult: 5x)
120 * each byte. we'll hope pramin has something usable instead
122 for (i = 0; i < NV_PROM_SIZE; i++)
123 data[i] = nv_rd08(dev, NV_PROM_OFFSET + i);
126 /* disable ROM access */
127 nvWriteMC(dev, pci_nv_20,
128 save_pci_nv_20 | NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED);
131 static void load_vbios_pramin(struct drm_device *dev, uint8_t *data)
133 struct drm_nouveau_private *dev_priv = dev->dev_private;
134 uint32_t old_bar0_pramin = 0;
137 if (dev_priv->card_type >= NV_50) {
138 uint32_t vbios_vram = (nv_rd32(dev, 0x619f04) & ~0xff) << 8;
141 vbios_vram = (nv_rd32(dev, 0x1700) << 16) + 0xf0000;
143 old_bar0_pramin = nv_rd32(dev, 0x1700);
144 nv_wr32(dev, 0x1700, vbios_vram >> 16);
147 /* bail if no rom signature */
148 if (nv_rd08(dev, NV_PRAMIN_OFFSET) != 0x55 ||
149 nv_rd08(dev, NV_PRAMIN_OFFSET + 1) != 0xaa)
152 for (i = 0; i < NV_PROM_SIZE; i++)
153 data[i] = nv_rd08(dev, NV_PRAMIN_OFFSET + i);
156 if (dev_priv->card_type >= NV_50)
157 nv_wr32(dev, 0x1700, old_bar0_pramin);
160 static void load_vbios_pci(struct drm_device *dev, uint8_t *data)
162 void __iomem *rom = NULL;
166 ret = pci_enable_rom(dev->pdev);
170 rom = pci_map_rom(dev->pdev, &rom_len);
173 memcpy_fromio(data, rom, rom_len);
174 pci_unmap_rom(dev->pdev, rom);
177 pci_disable_rom(dev->pdev);
182 void (*loadbios)(struct drm_device *, uint8_t *);
186 static struct methods nv04_methods[] = {
187 { "PROM", load_vbios_prom, false },
188 { "PRAMIN", load_vbios_pramin, true },
189 { "PCIROM", load_vbios_pci, true },
192 static struct methods nv50_methods[] = {
193 { "PRAMIN", load_vbios_pramin, true },
194 { "PROM", load_vbios_prom, false },
195 { "PCIROM", load_vbios_pci, true },
200 static bool NVShadowVBIOS(struct drm_device *dev, uint8_t *data)
202 struct drm_nouveau_private *dev_priv = dev->dev_private;
203 struct methods *methods;
206 int scores[METHODCNT];
209 methods = nv04_methods;
210 for (i = 0; i < METHODCNT; i++)
211 if (!strcasecmp(nouveau_vbios, methods[i].desc))
215 NV_INFO(dev, "Attempting to use BIOS image from %s\n",
218 methods[i].loadbios(dev, data);
219 if (score_vbios(dev, data, methods[i].rw))
223 NV_ERROR(dev, "VBIOS source \'%s\' invalid\n", nouveau_vbios);
226 if (dev_priv->card_type < NV_50)
227 methods = nv04_methods;
229 methods = nv50_methods;
231 for (i = 0; i < METHODCNT; i++) {
232 NV_TRACE(dev, "Attempting to load BIOS image from %s\n",
234 data[0] = data[1] = 0; /* avoid reuse of previous image */
235 methods[i].loadbios(dev, data);
236 scores[i] = score_vbios(dev, data, methods[i].rw);
237 if (scores[i] == testscore)
241 while (--testscore > 0) {
242 for (i = 0; i < METHODCNT; i++) {
243 if (scores[i] == testscore) {
244 NV_TRACE(dev, "Using BIOS image from %s\n",
246 methods[i].loadbios(dev, data);
252 NV_ERROR(dev, "No valid BIOS image found\n");
256 struct init_tbl_entry {
259 int (*handler)(struct nvbios *, uint16_t, struct init_exec *);
268 static int parse_init_table(struct nvbios *, unsigned int, struct init_exec *);
270 #define MACRO_INDEX_SIZE 2
272 #define CONDITION_SIZE 12
273 #define IO_FLAG_CONDITION_SIZE 9
274 #define IO_CONDITION_SIZE 5
275 #define MEM_INIT_SIZE 66
277 static void still_alive(void)
286 munge_reg(struct nvbios *bios, uint32_t reg)
288 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
289 struct dcb_entry *dcbent = bios->display.output;
291 if (dev_priv->card_type < NV_50)
294 if (reg & 0x40000000) {
297 reg += (ffs(dcbent->or) - 1) * 0x800;
298 if ((reg & 0x20000000) && !(dcbent->sorconf.link & 1))
307 valid_reg(struct nvbios *bios, uint32_t reg)
309 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
310 struct drm_device *dev = bios->dev;
312 /* C51 has misaligned regs on purpose. Marvellous */
313 if (reg & 0x2 || (reg & 0x1 && dev_priv->VBIOS.pub.chip_version != 0x51)) {
314 NV_ERROR(dev, "========== misaligned reg 0x%08X ==========\n",
319 * Warn on C51 regs that have not been verified accessible in
322 if (reg & 0x1 && dev_priv->VBIOS.pub.chip_version == 0x51 &&
323 reg != 0x130d && reg != 0x1311 && reg != 0x60081d)
324 NV_WARN(dev, "=== C51 misaligned reg 0x%08X not verified ===\n",
327 /* Trust the init scripts on G80 */
328 if (dev_priv->card_type >= NV_50)
331 #define WITHIN(x, y, z) ((x >= y) && (x < y + z))
332 if (WITHIN(reg, NV_PMC_OFFSET, NV_PMC_SIZE))
334 if (WITHIN(reg, NV_PBUS_OFFSET, NV_PBUS_SIZE))
336 if (WITHIN(reg, NV_PFIFO_OFFSET, NV_PFIFO_SIZE))
338 if (dev_priv->VBIOS.pub.chip_version >= 0x30 &&
339 (WITHIN(reg, 0x4000, 0x600) || reg == 0x00004600))
341 if (dev_priv->VBIOS.pub.chip_version >= 0x40 &&
342 WITHIN(reg, 0xc000, 0x48))
344 if (dev_priv->VBIOS.pub.chip_version >= 0x17 && reg == 0x0000d204)
346 if (dev_priv->VBIOS.pub.chip_version >= 0x40) {
347 if (reg == 0x00011014 || reg == 0x00020328)
349 if (WITHIN(reg, 0x88000, NV_PBUS_SIZE)) /* new PBUS */
352 if (WITHIN(reg, NV_PFB_OFFSET, NV_PFB_SIZE))
354 if (WITHIN(reg, NV_PEXTDEV_OFFSET, NV_PEXTDEV_SIZE))
356 if (WITHIN(reg, NV_PCRTC0_OFFSET, NV_PCRTC0_SIZE * 2))
358 if (WITHIN(reg, NV_PRAMDAC0_OFFSET, NV_PRAMDAC0_SIZE * 2))
360 if (dev_priv->VBIOS.pub.chip_version >= 0x17 && reg == 0x0070fff0)
362 if (dev_priv->VBIOS.pub.chip_version == 0x51 &&
363 WITHIN(reg, NV_PRAMIN_OFFSET, NV_PRAMIN_SIZE))
367 NV_ERROR(dev, "========== unknown reg 0x%08X ==========\n", reg);
373 valid_idx_port(struct nvbios *bios, uint16_t port)
375 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
376 struct drm_device *dev = bios->dev;
379 * If adding more ports here, the read/write functions below will need
380 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is
381 * used for the port in question
383 if (dev_priv->card_type < NV_50) {
384 if (port == NV_CIO_CRX__COLOR)
386 if (port == NV_VIO_SRX)
389 if (port == NV_CIO_CRX__COLOR)
393 NV_ERROR(dev, "========== unknown indexed io port 0x%04X ==========\n",
400 valid_port(struct nvbios *bios, uint16_t port)
402 struct drm_device *dev = bios->dev;
405 * If adding more ports here, the read/write functions below will need
406 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is
407 * used for the port in question
409 if (port == NV_VIO_VSE2)
412 NV_ERROR(dev, "========== unknown io port 0x%04X ==========\n", port);
418 bios_rd32(struct nvbios *bios, uint32_t reg)
422 reg = munge_reg(bios, reg);
423 if (!valid_reg(bios, reg))
427 * C51 sometimes uses regs with bit0 set in the address. For these
428 * cases there should exist a translation in a BIOS table to an IO
429 * port address which the BIOS uses for accessing the reg
431 * These only seem to appear for the power control regs to a flat panel,
432 * and the GPIO regs at 0x60081*. In C51 mmio traces the normal regs
433 * for 0x1308 and 0x1310 are used - hence the mask below. An S3
434 * suspend-resume mmio trace from a C51 will be required to see if this
435 * is true for the power microcode in 0x14.., or whether the direct IO
436 * port access method is needed
441 data = nv_rd32(bios->dev, reg);
443 BIOSLOG(bios, " Read: Reg: 0x%08X, Data: 0x%08X\n", reg, data);
449 bios_wr32(struct nvbios *bios, uint32_t reg, uint32_t data)
451 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
453 reg = munge_reg(bios, reg);
454 if (!valid_reg(bios, reg))
457 /* see note in bios_rd32 */
461 LOG_OLD_VALUE(bios_rd32(bios, reg));
462 BIOSLOG(bios, " Write: Reg: 0x%08X, Data: 0x%08X\n", reg, data);
464 if (dev_priv->VBIOS.execute) {
466 nv_wr32(bios->dev, reg, data);
471 bios_idxprt_rd(struct nvbios *bios, uint16_t port, uint8_t index)
473 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
474 struct drm_device *dev = bios->dev;
477 if (!valid_idx_port(bios, port))
480 if (dev_priv->card_type < NV_50) {
481 if (port == NV_VIO_SRX)
482 data = NVReadVgaSeq(dev, bios->state.crtchead, index);
483 else /* assume NV_CIO_CRX__COLOR */
484 data = NVReadVgaCrtc(dev, bios->state.crtchead, index);
488 data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3));
489 data = (data32 >> ((index & 3) << 3)) & 0xff;
492 BIOSLOG(bios, " Indexed IO read: Port: 0x%04X, Index: 0x%02X, "
493 "Head: 0x%02X, Data: 0x%02X\n",
494 port, index, bios->state.crtchead, data);
499 bios_idxprt_wr(struct nvbios *bios, uint16_t port, uint8_t index, uint8_t data)
501 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
502 struct drm_device *dev = bios->dev;
504 if (!valid_idx_port(bios, port))
508 * The current head is maintained in the nvbios member state.crtchead.
509 * We trap changes to CR44 and update the head variable and hence the
510 * register set written.
511 * As CR44 only exists on CRTC0, we update crtchead to head0 in advance
512 * of the write, and to head1 after the write
514 if (port == NV_CIO_CRX__COLOR && index == NV_CIO_CRE_44 &&
515 data != NV_CIO_CRE_44_HEADB)
516 bios->state.crtchead = 0;
518 LOG_OLD_VALUE(bios_idxprt_rd(bios, port, index));
519 BIOSLOG(bios, " Indexed IO write: Port: 0x%04X, Index: 0x%02X, "
520 "Head: 0x%02X, Data: 0x%02X\n",
521 port, index, bios->state.crtchead, data);
523 if (bios->execute && dev_priv->card_type < NV_50) {
525 if (port == NV_VIO_SRX)
526 NVWriteVgaSeq(dev, bios->state.crtchead, index, data);
527 else /* assume NV_CIO_CRX__COLOR */
528 NVWriteVgaCrtc(dev, bios->state.crtchead, index, data);
531 uint32_t data32, shift = (index & 3) << 3;
535 data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3));
536 data32 &= ~(0xff << shift);
537 data32 |= (data << shift);
538 bios_wr32(bios, NV50_PDISPLAY_VGACRTC(index & ~3), data32);
541 if (port == NV_CIO_CRX__COLOR &&
542 index == NV_CIO_CRE_44 && data == NV_CIO_CRE_44_HEADB)
543 bios->state.crtchead = 1;
547 bios_port_rd(struct nvbios *bios, uint16_t port)
549 uint8_t data, head = bios->state.crtchead;
551 if (!valid_port(bios, port))
554 data = NVReadPRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port);
556 BIOSLOG(bios, " IO read: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
563 bios_port_wr(struct nvbios *bios, uint16_t port, uint8_t data)
565 int head = bios->state.crtchead;
567 if (!valid_port(bios, port))
570 LOG_OLD_VALUE(bios_port_rd(bios, port));
571 BIOSLOG(bios, " IO write: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
578 NVWritePRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port, data);
582 io_flag_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
585 * The IO flag condition entry has 2 bytes for the CRTC port; 1 byte
586 * for the CRTC index; 1 byte for the mask to apply to the value
587 * retrieved from the CRTC; 1 byte for the shift right to apply to the
588 * masked CRTC value; 2 bytes for the offset to the flag array, to
589 * which the shifted value is added; 1 byte for the mask applied to the
590 * value read from the flag array; and 1 byte for the value to compare
591 * against the masked byte from the flag table.
594 uint16_t condptr = bios->io_flag_condition_tbl_ptr + cond * IO_FLAG_CONDITION_SIZE;
595 uint16_t crtcport = ROM16(bios->data[condptr]);
596 uint8_t crtcindex = bios->data[condptr + 2];
597 uint8_t mask = bios->data[condptr + 3];
598 uint8_t shift = bios->data[condptr + 4];
599 uint16_t flagarray = ROM16(bios->data[condptr + 5]);
600 uint8_t flagarraymask = bios->data[condptr + 7];
601 uint8_t cmpval = bios->data[condptr + 8];
604 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
605 "Shift: 0x%02X, FlagArray: 0x%04X, FAMask: 0x%02X, "
607 offset, crtcport, crtcindex, mask, shift, flagarray, flagarraymask, cmpval);
609 data = bios_idxprt_rd(bios, crtcport, crtcindex);
611 data = bios->data[flagarray + ((data & mask) >> shift)];
612 data &= flagarraymask;
614 BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n",
615 offset, data, cmpval);
617 return (data == cmpval);
621 bios_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
624 * The condition table entry has 4 bytes for the address of the
625 * register to check, 4 bytes for a mask to apply to the register and
626 * 4 for a test comparison value
629 uint16_t condptr = bios->condition_tbl_ptr + cond * CONDITION_SIZE;
630 uint32_t reg = ROM32(bios->data[condptr]);
631 uint32_t mask = ROM32(bios->data[condptr + 4]);
632 uint32_t cmpval = ROM32(bios->data[condptr + 8]);
635 BIOSLOG(bios, "0x%04X: Cond: 0x%02X, Reg: 0x%08X, Mask: 0x%08X\n",
636 offset, cond, reg, mask);
638 data = bios_rd32(bios, reg) & mask;
640 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n",
641 offset, data, cmpval);
643 return (data == cmpval);
647 io_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
650 * The IO condition entry has 2 bytes for the IO port address; 1 byte
651 * for the index to write to io_port; 1 byte for the mask to apply to
652 * the byte read from io_port+1; and 1 byte for the value to compare
653 * against the masked byte.
656 uint16_t condptr = bios->io_condition_tbl_ptr + cond * IO_CONDITION_SIZE;
657 uint16_t io_port = ROM16(bios->data[condptr]);
658 uint8_t port_index = bios->data[condptr + 2];
659 uint8_t mask = bios->data[condptr + 3];
660 uint8_t cmpval = bios->data[condptr + 4];
662 uint8_t data = bios_idxprt_rd(bios, io_port, port_index) & mask;
664 BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n",
665 offset, data, cmpval);
667 return (data == cmpval);
671 nv50_pll_set(struct drm_device *dev, uint32_t reg, uint32_t clk)
673 struct drm_nouveau_private *dev_priv = dev->dev_private;
674 uint32_t reg0 = nv_rd32(dev, reg + 0);
675 uint32_t reg1 = nv_rd32(dev, reg + 4);
676 struct nouveau_pll_vals pll;
677 struct pll_lims pll_limits;
680 ret = get_pll_limits(dev, reg, &pll_limits);
684 clk = nouveau_calc_pll_mnp(dev, &pll_limits, clk, &pll);
688 reg0 = (reg0 & 0xfff8ffff) | (pll.log2P << 16);
689 reg1 = (reg1 & 0xffff0000) | (pll.N1 << 8) | pll.M1;
691 if (dev_priv->VBIOS.execute) {
693 nv_wr32(dev, reg + 4, reg1);
694 nv_wr32(dev, reg + 0, reg0);
701 setPLL(struct nvbios *bios, uint32_t reg, uint32_t clk)
703 struct drm_device *dev = bios->dev;
704 struct drm_nouveau_private *dev_priv = dev->dev_private;
706 struct pll_lims pll_lim;
707 struct nouveau_pll_vals pllvals;
710 if (dev_priv->card_type >= NV_50)
711 return nv50_pll_set(dev, reg, clk);
713 /* high regs (such as in the mac g5 table) are not -= 4 */
714 ret = get_pll_limits(dev, reg > 0x405c ? reg : reg - 4, &pll_lim);
718 clk = nouveau_calc_pll_mnp(dev, &pll_lim, clk, &pllvals);
724 nouveau_hw_setpll(dev, reg, &pllvals);
730 static int dcb_entry_idx_from_crtchead(struct drm_device *dev)
732 struct drm_nouveau_private *dev_priv = dev->dev_private;
733 struct nvbios *bios = &dev_priv->VBIOS;
736 * For the results of this function to be correct, CR44 must have been
737 * set (using bios_idxprt_wr to set crtchead), CR58 set for CR57 = 0,
738 * and the DCB table parsed, before the script calling the function is
739 * run. run_digital_op_script is example of how to do such setup
742 uint8_t dcb_entry = NVReadVgaCrtc5758(dev, bios->state.crtchead, 0);
744 if (dcb_entry > bios->bdcb.dcb.entries) {
745 NV_ERROR(dev, "CR58 doesn't have a valid DCB entry currently "
746 "(%02X)\n", dcb_entry);
747 dcb_entry = 0x7f; /* unused / invalid marker */
753 static struct nouveau_i2c_chan *
754 init_i2c_device_find(struct drm_device *dev, int i2c_index)
756 struct drm_nouveau_private *dev_priv = dev->dev_private;
757 struct bios_parsed_dcb *bdcb = &dev_priv->VBIOS.bdcb;
759 if (i2c_index == 0xff) {
760 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */
761 int idx = dcb_entry_idx_from_crtchead(dev), shift = 0;
762 int default_indices = bdcb->i2c_default_indices;
764 if (idx != 0x7f && bdcb->dcb.entry[idx].i2c_upper_default)
767 i2c_index = (default_indices >> shift) & 0xf;
769 if (i2c_index == 0x80) /* g80+ */
770 i2c_index = bdcb->i2c_default_indices & 0xf;
772 return nouveau_i2c_find(dev, i2c_index);
775 static uint32_t get_tmds_index_reg(struct drm_device *dev, uint8_t mlv)
778 * For mlv < 0x80, it is an index into a table of TMDS base addresses.
779 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by
780 * CR58 for CR57 = 0 to index a table of offsets to the basic
782 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by
783 * CR58 for CR57 = 0 to index a table of offsets to the basic
784 * 0x6808b0 address, and then flip the offset by 8.
787 struct drm_nouveau_private *dev_priv = dev->dev_private;
788 const int pramdac_offset[13] = {
789 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 };
790 const uint32_t pramdac_table[4] = {
791 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 };
794 int dcb_entry, dacoffset;
796 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */
797 dcb_entry = dcb_entry_idx_from_crtchead(dev);
798 if (dcb_entry == 0x7f)
800 dacoffset = pramdac_offset[
801 dev_priv->VBIOS.bdcb.dcb.entry[dcb_entry].or];
804 return 0x6808b0 + dacoffset;
806 if (mlv > ARRAY_SIZE(pramdac_table)) {
807 NV_ERROR(dev, "Magic Lookup Value too big (%02X)\n",
811 return pramdac_table[mlv];
816 init_io_restrict_prog(struct nvbios *bios, uint16_t offset,
817 struct init_exec *iexec)
820 * INIT_IO_RESTRICT_PROG opcode: 0x32 ('2')
822 * offset (8 bit): opcode
823 * offset + 1 (16 bit): CRTC port
824 * offset + 3 (8 bit): CRTC index
825 * offset + 4 (8 bit): mask
826 * offset + 5 (8 bit): shift
827 * offset + 6 (8 bit): count
828 * offset + 7 (32 bit): register
829 * offset + 11 (32 bit): configuration 1
832 * Starting at offset + 11 there are "count" 32 bit values.
833 * To find out which value to use read index "CRTC index" on "CRTC
834 * port", AND this value with "mask" and then bit shift right "shift"
835 * bits. Read the appropriate value using this index and write to
839 uint16_t crtcport = ROM16(bios->data[offset + 1]);
840 uint8_t crtcindex = bios->data[offset + 3];
841 uint8_t mask = bios->data[offset + 4];
842 uint8_t shift = bios->data[offset + 5];
843 uint8_t count = bios->data[offset + 6];
844 uint32_t reg = ROM32(bios->data[offset + 7]);
847 int len = 11 + count * 4;
852 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
853 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
854 offset, crtcport, crtcindex, mask, shift, count, reg);
856 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
857 if (config > count) {
859 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
860 offset, config, count);
864 configval = ROM32(bios->data[offset + 11 + config * 4]);
866 BIOSLOG(bios, "0x%04X: Writing config %02X\n", offset, config);
868 bios_wr32(bios, reg, configval);
874 init_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
877 * INIT_REPEAT opcode: 0x33 ('3')
879 * offset (8 bit): opcode
880 * offset + 1 (8 bit): count
882 * Execute script following this opcode up to INIT_REPEAT_END
886 uint8_t count = bios->data[offset + 1];
889 /* no iexec->execute check by design */
891 BIOSLOG(bios, "0x%04X: Repeating following segment %d times\n",
894 iexec->repeat = true;
897 * count - 1, as the script block will execute once when we leave this
898 * opcode -- this is compatible with bios behaviour as:
899 * a) the block is always executed at least once, even if count == 0
900 * b) the bios interpreter skips to the op following INIT_END_REPEAT,
903 for (i = 0; i < count - 1; i++)
904 parse_init_table(bios, offset + 2, iexec);
906 iexec->repeat = false;
912 init_io_restrict_pll(struct nvbios *bios, uint16_t offset,
913 struct init_exec *iexec)
916 * INIT_IO_RESTRICT_PLL opcode: 0x34 ('4')
918 * offset (8 bit): opcode
919 * offset + 1 (16 bit): CRTC port
920 * offset + 3 (8 bit): CRTC index
921 * offset + 4 (8 bit): mask
922 * offset + 5 (8 bit): shift
923 * offset + 6 (8 bit): IO flag condition index
924 * offset + 7 (8 bit): count
925 * offset + 8 (32 bit): register
926 * offset + 12 (16 bit): frequency 1
929 * Starting at offset + 12 there are "count" 16 bit frequencies (10kHz).
930 * Set PLL register "register" to coefficients for frequency n,
931 * selected by reading index "CRTC index" of "CRTC port" ANDed with
932 * "mask" and shifted right by "shift".
934 * If "IO flag condition index" > 0, and condition met, double
935 * frequency before setting it.
938 uint16_t crtcport = ROM16(bios->data[offset + 1]);
939 uint8_t crtcindex = bios->data[offset + 3];
940 uint8_t mask = bios->data[offset + 4];
941 uint8_t shift = bios->data[offset + 5];
942 int8_t io_flag_condition_idx = bios->data[offset + 6];
943 uint8_t count = bios->data[offset + 7];
944 uint32_t reg = ROM32(bios->data[offset + 8]);
947 int len = 12 + count * 2;
952 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
953 "Shift: 0x%02X, IO Flag Condition: 0x%02X, "
954 "Count: 0x%02X, Reg: 0x%08X\n",
955 offset, crtcport, crtcindex, mask, shift,
956 io_flag_condition_idx, count, reg);
958 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
959 if (config > count) {
961 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
962 offset, config, count);
966 freq = ROM16(bios->data[offset + 12 + config * 2]);
968 if (io_flag_condition_idx > 0) {
969 if (io_flag_condition_met(bios, offset, io_flag_condition_idx)) {
970 BIOSLOG(bios, "0x%04X: Condition fulfilled -- "
971 "frequency doubled\n", offset);
974 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- "
975 "frequency unchanged\n", offset);
978 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %d0kHz\n",
979 offset, reg, config, freq);
981 setPLL(bios, reg, freq * 10);
987 init_end_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
990 * INIT_END_REPEAT opcode: 0x36 ('6')
992 * offset (8 bit): opcode
994 * Marks the end of the block for INIT_REPEAT to repeat
997 /* no iexec->execute check by design */
1000 * iexec->repeat flag necessary to go past INIT_END_REPEAT opcode when
1001 * we're not in repeat mode
1010 init_copy(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1013 * INIT_COPY opcode: 0x37 ('7')
1015 * offset (8 bit): opcode
1016 * offset + 1 (32 bit): register
1017 * offset + 5 (8 bit): shift
1018 * offset + 6 (8 bit): srcmask
1019 * offset + 7 (16 bit): CRTC port
1020 * offset + 9 (8 bit): CRTC index
1021 * offset + 10 (8 bit): mask
1023 * Read index "CRTC index" on "CRTC port", AND with "mask", OR with
1024 * (REGVAL("register") >> "shift" & "srcmask") and write-back to CRTC
1028 uint32_t reg = ROM32(bios->data[offset + 1]);
1029 uint8_t shift = bios->data[offset + 5];
1030 uint8_t srcmask = bios->data[offset + 6];
1031 uint16_t crtcport = ROM16(bios->data[offset + 7]);
1032 uint8_t crtcindex = bios->data[offset + 9];
1033 uint8_t mask = bios->data[offset + 10];
1037 if (!iexec->execute)
1040 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%02X, "
1041 "Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X\n",
1042 offset, reg, shift, srcmask, crtcport, crtcindex, mask);
1044 data = bios_rd32(bios, reg);
1049 data <<= (0x100 - shift);
1053 crtcdata = bios_idxprt_rd(bios, crtcport, crtcindex) & mask;
1054 crtcdata |= (uint8_t)data;
1055 bios_idxprt_wr(bios, crtcport, crtcindex, crtcdata);
1061 init_not(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1064 * INIT_NOT opcode: 0x38 ('8')
1066 * offset (8 bit): opcode
1068 * Invert the current execute / no-execute condition (i.e. "else")
1071 BIOSLOG(bios, "0x%04X: ------ Skipping following commands ------\n", offset);
1073 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", offset);
1075 iexec->execute = !iexec->execute;
1080 init_io_flag_condition(struct nvbios *bios, uint16_t offset,
1081 struct init_exec *iexec)
1084 * INIT_IO_FLAG_CONDITION opcode: 0x39 ('9')
1086 * offset (8 bit): opcode
1087 * offset + 1 (8 bit): condition number
1089 * Check condition "condition number" in the IO flag condition table.
1090 * If condition not met skip subsequent opcodes until condition is
1091 * inverted (INIT_NOT), or we hit INIT_RESUME
1094 uint8_t cond = bios->data[offset + 1];
1096 if (!iexec->execute)
1099 if (io_flag_condition_met(bios, offset, cond))
1100 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
1102 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
1103 iexec->execute = false;
1110 init_idx_addr_latched(struct nvbios *bios, uint16_t offset,
1111 struct init_exec *iexec)
1114 * INIT_INDEX_ADDRESS_LATCHED opcode: 0x49 ('I')
1116 * offset (8 bit): opcode
1117 * offset + 1 (32 bit): control register
1118 * offset + 5 (32 bit): data register
1119 * offset + 9 (32 bit): mask
1120 * offset + 13 (32 bit): data
1121 * offset + 17 (8 bit): count
1122 * offset + 18 (8 bit): address 1
1123 * offset + 19 (8 bit): data 1
1126 * For each of "count" address and data pairs, write "data n" to
1127 * "data register", read the current value of "control register",
1128 * and write it back once ANDed with "mask", ORed with "data",
1129 * and ORed with "address n"
1132 uint32_t controlreg = ROM32(bios->data[offset + 1]);
1133 uint32_t datareg = ROM32(bios->data[offset + 5]);
1134 uint32_t mask = ROM32(bios->data[offset + 9]);
1135 uint32_t data = ROM32(bios->data[offset + 13]);
1136 uint8_t count = bios->data[offset + 17];
1137 int len = 18 + count * 2;
1141 if (!iexec->execute)
1144 BIOSLOG(bios, "0x%04X: ControlReg: 0x%08X, DataReg: 0x%08X, "
1145 "Mask: 0x%08X, Data: 0x%08X, Count: 0x%02X\n",
1146 offset, controlreg, datareg, mask, data, count);
1148 for (i = 0; i < count; i++) {
1149 uint8_t instaddress = bios->data[offset + 18 + i * 2];
1150 uint8_t instdata = bios->data[offset + 19 + i * 2];
1152 BIOSLOG(bios, "0x%04X: Address: 0x%02X, Data: 0x%02X\n",
1153 offset, instaddress, instdata);
1155 bios_wr32(bios, datareg, instdata);
1156 value = bios_rd32(bios, controlreg) & mask;
1158 value |= instaddress;
1159 bios_wr32(bios, controlreg, value);
1166 init_io_restrict_pll2(struct nvbios *bios, uint16_t offset,
1167 struct init_exec *iexec)
1170 * INIT_IO_RESTRICT_PLL2 opcode: 0x4A ('J')
1172 * offset (8 bit): opcode
1173 * offset + 1 (16 bit): CRTC port
1174 * offset + 3 (8 bit): CRTC index
1175 * offset + 4 (8 bit): mask
1176 * offset + 5 (8 bit): shift
1177 * offset + 6 (8 bit): count
1178 * offset + 7 (32 bit): register
1179 * offset + 11 (32 bit): frequency 1
1182 * Starting at offset + 11 there are "count" 32 bit frequencies (kHz).
1183 * Set PLL register "register" to coefficients for frequency n,
1184 * selected by reading index "CRTC index" of "CRTC port" ANDed with
1185 * "mask" and shifted right by "shift".
1188 uint16_t crtcport = ROM16(bios->data[offset + 1]);
1189 uint8_t crtcindex = bios->data[offset + 3];
1190 uint8_t mask = bios->data[offset + 4];
1191 uint8_t shift = bios->data[offset + 5];
1192 uint8_t count = bios->data[offset + 6];
1193 uint32_t reg = ROM32(bios->data[offset + 7]);
1194 int len = 11 + count * 4;
1198 if (!iexec->execute)
1201 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
1202 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
1203 offset, crtcport, crtcindex, mask, shift, count, reg);
1208 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
1209 if (config > count) {
1211 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
1212 offset, config, count);
1216 freq = ROM32(bios->data[offset + 11 + config * 4]);
1218 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %dkHz\n",
1219 offset, reg, config, freq);
1221 setPLL(bios, reg, freq);
1227 init_pll2(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1230 * INIT_PLL2 opcode: 0x4B ('K')
1232 * offset (8 bit): opcode
1233 * offset + 1 (32 bit): register
1234 * offset + 5 (32 bit): freq
1236 * Set PLL register "register" to coefficients for frequency "freq"
1239 uint32_t reg = ROM32(bios->data[offset + 1]);
1240 uint32_t freq = ROM32(bios->data[offset + 5]);
1242 if (!iexec->execute)
1245 BIOSLOG(bios, "0x%04X: Reg: 0x%04X, Freq: %dkHz\n",
1248 setPLL(bios, reg, freq);
1253 init_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1256 * INIT_I2C_BYTE opcode: 0x4C ('L')
1258 * offset (8 bit): opcode
1259 * offset + 1 (8 bit): DCB I2C table entry index
1260 * offset + 2 (8 bit): I2C slave address
1261 * offset + 3 (8 bit): count
1262 * offset + 4 (8 bit): I2C register 1
1263 * offset + 5 (8 bit): mask 1
1264 * offset + 6 (8 bit): data 1
1267 * For each of "count" registers given by "I2C register n" on the device
1268 * addressed by "I2C slave address" on the I2C bus given by
1269 * "DCB I2C table entry index", read the register, AND the result with
1270 * "mask n" and OR it with "data n" before writing it back to the device
1273 uint8_t i2c_index = bios->data[offset + 1];
1274 uint8_t i2c_address = bios->data[offset + 2];
1275 uint8_t count = bios->data[offset + 3];
1276 int len = 4 + count * 3;
1277 struct nouveau_i2c_chan *chan;
1281 if (!iexec->execute)
1284 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1286 offset, i2c_index, i2c_address, count);
1288 chan = init_i2c_device_find(bios->dev, i2c_index);
1292 for (i = 0; i < count; i++) {
1293 uint8_t i2c_reg = bios->data[offset + 4 + i * 3];
1294 uint8_t mask = bios->data[offset + 5 + i * 3];
1295 uint8_t data = bios->data[offset + 6 + i * 3];
1298 msg.addr = i2c_address;
1299 msg.flags = I2C_M_RD;
1302 if (i2c_transfer(&chan->adapter, &msg, 1) != 1)
1305 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, "
1306 "Mask: 0x%02X, Data: 0x%02X\n",
1307 offset, i2c_reg, value, mask, data);
1309 value = (value & mask) | data;
1311 if (bios->execute) {
1312 msg.addr = i2c_address;
1316 if (i2c_transfer(&chan->adapter, &msg, 1) != 1)
1325 init_zm_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1328 * INIT_ZM_I2C_BYTE opcode: 0x4D ('M')
1330 * offset (8 bit): opcode
1331 * offset + 1 (8 bit): DCB I2C table entry index
1332 * offset + 2 (8 bit): I2C slave address
1333 * offset + 3 (8 bit): count
1334 * offset + 4 (8 bit): I2C register 1
1335 * offset + 5 (8 bit): data 1
1338 * For each of "count" registers given by "I2C register n" on the device
1339 * addressed by "I2C slave address" on the I2C bus given by
1340 * "DCB I2C table entry index", set the register to "data n"
1343 uint8_t i2c_index = bios->data[offset + 1];
1344 uint8_t i2c_address = bios->data[offset + 2];
1345 uint8_t count = bios->data[offset + 3];
1346 int len = 4 + count * 2;
1347 struct nouveau_i2c_chan *chan;
1351 if (!iexec->execute)
1354 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1356 offset, i2c_index, i2c_address, count);
1358 chan = init_i2c_device_find(bios->dev, i2c_index);
1362 for (i = 0; i < count; i++) {
1363 uint8_t i2c_reg = bios->data[offset + 4 + i * 2];
1364 uint8_t data = bios->data[offset + 5 + i * 2];
1366 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Data: 0x%02X\n",
1367 offset, i2c_reg, data);
1369 if (bios->execute) {
1370 msg.addr = i2c_address;
1374 if (i2c_transfer(&chan->adapter, &msg, 1) != 1)
1383 init_zm_i2c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1386 * INIT_ZM_I2C opcode: 0x4E ('N')
1388 * offset (8 bit): opcode
1389 * offset + 1 (8 bit): DCB I2C table entry index
1390 * offset + 2 (8 bit): I2C slave address
1391 * offset + 3 (8 bit): count
1392 * offset + 4 (8 bit): data 1
1395 * Send "count" bytes ("data n") to the device addressed by "I2C slave
1396 * address" on the I2C bus given by "DCB I2C table entry index"
1399 uint8_t i2c_index = bios->data[offset + 1];
1400 uint8_t i2c_address = bios->data[offset + 2];
1401 uint8_t count = bios->data[offset + 3];
1402 int len = 4 + count;
1403 struct nouveau_i2c_chan *chan;
1408 if (!iexec->execute)
1411 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1413 offset, i2c_index, i2c_address, count);
1415 chan = init_i2c_device_find(bios->dev, i2c_index);
1419 for (i = 0; i < count; i++) {
1420 data[i] = bios->data[offset + 4 + i];
1422 BIOSLOG(bios, "0x%04X: Data: 0x%02X\n", offset, data[i]);
1425 if (bios->execute) {
1426 msg.addr = i2c_address;
1430 if (i2c_transfer(&chan->adapter, &msg, 1) != 1)
1438 init_tmds(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1441 * INIT_TMDS opcode: 0x4F ('O') (non-canon name)
1443 * offset (8 bit): opcode
1444 * offset + 1 (8 bit): magic lookup value
1445 * offset + 2 (8 bit): TMDS address
1446 * offset + 3 (8 bit): mask
1447 * offset + 4 (8 bit): data
1449 * Read the data reg for TMDS address "TMDS address", AND it with mask
1450 * and OR it with data, then write it back
1451 * "magic lookup value" determines which TMDS base address register is
1452 * used -- see get_tmds_index_reg()
1455 uint8_t mlv = bios->data[offset + 1];
1456 uint32_t tmdsaddr = bios->data[offset + 2];
1457 uint8_t mask = bios->data[offset + 3];
1458 uint8_t data = bios->data[offset + 4];
1459 uint32_t reg, value;
1461 if (!iexec->execute)
1464 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, TMDSAddr: 0x%02X, "
1465 "Mask: 0x%02X, Data: 0x%02X\n",
1466 offset, mlv, tmdsaddr, mask, data);
1468 reg = get_tmds_index_reg(bios->dev, mlv);
1472 bios_wr32(bios, reg,
1473 tmdsaddr | NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE);
1474 value = (bios_rd32(bios, reg + 4) & mask) | data;
1475 bios_wr32(bios, reg + 4, value);
1476 bios_wr32(bios, reg, tmdsaddr);
1482 init_zm_tmds_group(struct nvbios *bios, uint16_t offset,
1483 struct init_exec *iexec)
1486 * INIT_ZM_TMDS_GROUP opcode: 0x50 ('P') (non-canon name)
1488 * offset (8 bit): opcode
1489 * offset + 1 (8 bit): magic lookup value
1490 * offset + 2 (8 bit): count
1491 * offset + 3 (8 bit): addr 1
1492 * offset + 4 (8 bit): data 1
1495 * For each of "count" TMDS address and data pairs write "data n" to
1496 * "addr n". "magic lookup value" determines which TMDS base address
1497 * register is used -- see get_tmds_index_reg()
1500 uint8_t mlv = bios->data[offset + 1];
1501 uint8_t count = bios->data[offset + 2];
1502 int len = 3 + count * 2;
1506 if (!iexec->execute)
1509 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, Count: 0x%02X\n",
1510 offset, mlv, count);
1512 reg = get_tmds_index_reg(bios->dev, mlv);
1516 for (i = 0; i < count; i++) {
1517 uint8_t tmdsaddr = bios->data[offset + 3 + i * 2];
1518 uint8_t tmdsdata = bios->data[offset + 4 + i * 2];
1520 bios_wr32(bios, reg + 4, tmdsdata);
1521 bios_wr32(bios, reg, tmdsaddr);
1528 init_cr_idx_adr_latch(struct nvbios *bios, uint16_t offset,
1529 struct init_exec *iexec)
1532 * INIT_CR_INDEX_ADDRESS_LATCHED opcode: 0x51 ('Q')
1534 * offset (8 bit): opcode
1535 * offset + 1 (8 bit): CRTC index1
1536 * offset + 2 (8 bit): CRTC index2
1537 * offset + 3 (8 bit): baseaddr
1538 * offset + 4 (8 bit): count
1539 * offset + 5 (8 bit): data 1
1542 * For each of "count" address and data pairs, write "baseaddr + n" to
1543 * "CRTC index1" and "data n" to "CRTC index2"
1544 * Once complete, restore initial value read from "CRTC index1"
1546 uint8_t crtcindex1 = bios->data[offset + 1];
1547 uint8_t crtcindex2 = bios->data[offset + 2];
1548 uint8_t baseaddr = bios->data[offset + 3];
1549 uint8_t count = bios->data[offset + 4];
1550 int len = 5 + count;
1551 uint8_t oldaddr, data;
1554 if (!iexec->execute)
1557 BIOSLOG(bios, "0x%04X: Index1: 0x%02X, Index2: 0x%02X, "
1558 "BaseAddr: 0x%02X, Count: 0x%02X\n",
1559 offset, crtcindex1, crtcindex2, baseaddr, count);
1561 oldaddr = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex1);
1563 for (i = 0; i < count; i++) {
1564 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1,
1566 data = bios->data[offset + 5 + i];
1567 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex2, data);
1570 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1, oldaddr);
1576 init_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1579 * INIT_CR opcode: 0x52 ('R')
1581 * offset (8 bit): opcode
1582 * offset + 1 (8 bit): CRTC index
1583 * offset + 2 (8 bit): mask
1584 * offset + 3 (8 bit): data
1586 * Assign the value of at "CRTC index" ANDed with mask and ORed with
1587 * data back to "CRTC index"
1590 uint8_t crtcindex = bios->data[offset + 1];
1591 uint8_t mask = bios->data[offset + 2];
1592 uint8_t data = bios->data[offset + 3];
1595 if (!iexec->execute)
1598 BIOSLOG(bios, "0x%04X: Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n",
1599 offset, crtcindex, mask, data);
1601 value = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex) & mask;
1603 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, value);
1609 init_zm_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1612 * INIT_ZM_CR opcode: 0x53 ('S')
1614 * offset (8 bit): opcode
1615 * offset + 1 (8 bit): CRTC index
1616 * offset + 2 (8 bit): value
1618 * Assign "value" to CRTC register with index "CRTC index".
1621 uint8_t crtcindex = ROM32(bios->data[offset + 1]);
1622 uint8_t data = bios->data[offset + 2];
1624 if (!iexec->execute)
1627 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, data);
1633 init_zm_cr_group(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1636 * INIT_ZM_CR_GROUP opcode: 0x54 ('T')
1638 * offset (8 bit): opcode
1639 * offset + 1 (8 bit): count
1640 * offset + 2 (8 bit): CRTC index 1
1641 * offset + 3 (8 bit): value 1
1644 * For "count", assign "value n" to CRTC register with index
1648 uint8_t count = bios->data[offset + 1];
1649 int len = 2 + count * 2;
1652 if (!iexec->execute)
1655 for (i = 0; i < count; i++)
1656 init_zm_cr(bios, offset + 2 + 2 * i - 1, iexec);
1662 init_condition_time(struct nvbios *bios, uint16_t offset,
1663 struct init_exec *iexec)
1666 * INIT_CONDITION_TIME opcode: 0x56 ('V')
1668 * offset (8 bit): opcode
1669 * offset + 1 (8 bit): condition number
1670 * offset + 2 (8 bit): retries / 50
1672 * Check condition "condition number" in the condition table.
1673 * Bios code then sleeps for 2ms if the condition is not met, and
1674 * repeats up to "retries" times, but on one C51 this has proved
1675 * insufficient. In mmiotraces the driver sleeps for 20ms, so we do
1676 * this, and bail after "retries" times, or 2s, whichever is less.
1677 * If still not met after retries, clear execution flag for this table.
1680 uint8_t cond = bios->data[offset + 1];
1681 uint16_t retries = bios->data[offset + 2] * 50;
1684 if (!iexec->execute)
1690 BIOSLOG(bios, "0x%04X: Condition: 0x%02X, Retries: 0x%02X\n",
1691 offset, cond, retries);
1693 if (!bios->execute) /* avoid 2s delays when "faking" execution */
1696 for (cnt = 0; cnt < retries; cnt++) {
1697 if (bios_condition_met(bios, offset, cond)) {
1698 BIOSLOG(bios, "0x%04X: Condition met, continuing\n",
1702 BIOSLOG(bios, "0x%04X: "
1703 "Condition not met, sleeping for 20ms\n",
1709 if (!bios_condition_met(bios, offset, cond)) {
1711 "0x%04X: Condition still not met after %dms, "
1712 "skipping following opcodes\n", offset, 20 * retries);
1713 iexec->execute = false;
1720 init_zm_reg_sequence(struct nvbios *bios, uint16_t offset,
1721 struct init_exec *iexec)
1724 * INIT_ZM_REG_SEQUENCE opcode: 0x58 ('X')
1726 * offset (8 bit): opcode
1727 * offset + 1 (32 bit): base register
1728 * offset + 5 (8 bit): count
1729 * offset + 6 (32 bit): value 1
1732 * Starting at offset + 6 there are "count" 32 bit values.
1733 * For "count" iterations set "base register" + 4 * current_iteration
1734 * to "value current_iteration"
1737 uint32_t basereg = ROM32(bios->data[offset + 1]);
1738 uint32_t count = bios->data[offset + 5];
1739 int len = 6 + count * 4;
1742 if (!iexec->execute)
1745 BIOSLOG(bios, "0x%04X: BaseReg: 0x%08X, Count: 0x%02X\n",
1746 offset, basereg, count);
1748 for (i = 0; i < count; i++) {
1749 uint32_t reg = basereg + i * 4;
1750 uint32_t data = ROM32(bios->data[offset + 6 + i * 4]);
1752 bios_wr32(bios, reg, data);
1759 init_sub_direct(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1762 * INIT_SUB_DIRECT opcode: 0x5B ('[')
1764 * offset (8 bit): opcode
1765 * offset + 1 (16 bit): subroutine offset (in bios)
1767 * Calls a subroutine that will execute commands until INIT_DONE
1771 uint16_t sub_offset = ROM16(bios->data[offset + 1]);
1773 if (!iexec->execute)
1776 BIOSLOG(bios, "0x%04X: Executing subroutine at 0x%04X\n",
1777 offset, sub_offset);
1779 parse_init_table(bios, sub_offset, iexec);
1781 BIOSLOG(bios, "0x%04X: End of 0x%04X subroutine\n", offset, sub_offset);
1787 init_copy_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1790 * INIT_COPY_NV_REG opcode: 0x5F ('_')
1792 * offset (8 bit): opcode
1793 * offset + 1 (32 bit): src reg
1794 * offset + 5 (8 bit): shift
1795 * offset + 6 (32 bit): src mask
1796 * offset + 10 (32 bit): xor
1797 * offset + 14 (32 bit): dst reg
1798 * offset + 18 (32 bit): dst mask
1800 * Shift REGVAL("src reg") right by (signed) "shift", AND result with
1801 * "src mask", then XOR with "xor". Write this OR'd with
1802 * (REGVAL("dst reg") AND'd with "dst mask") to "dst reg"
1805 uint32_t srcreg = *((uint32_t *)(&bios->data[offset + 1]));
1806 uint8_t shift = bios->data[offset + 5];
1807 uint32_t srcmask = *((uint32_t *)(&bios->data[offset + 6]));
1808 uint32_t xor = *((uint32_t *)(&bios->data[offset + 10]));
1809 uint32_t dstreg = *((uint32_t *)(&bios->data[offset + 14]));
1810 uint32_t dstmask = *((uint32_t *)(&bios->data[offset + 18]));
1811 uint32_t srcvalue, dstvalue;
1813 if (!iexec->execute)
1816 BIOSLOG(bios, "0x%04X: SrcReg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%08X, "
1817 "Xor: 0x%08X, DstReg: 0x%08X, DstMask: 0x%08X\n",
1818 offset, srcreg, shift, srcmask, xor, dstreg, dstmask);
1820 srcvalue = bios_rd32(bios, srcreg);
1825 srcvalue <<= (0x100 - shift);
1827 srcvalue = (srcvalue & srcmask) ^ xor;
1829 dstvalue = bios_rd32(bios, dstreg) & dstmask;
1831 bios_wr32(bios, dstreg, dstvalue | srcvalue);
1837 init_zm_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1840 * INIT_ZM_INDEX_IO opcode: 0x62 ('b')
1842 * offset (8 bit): opcode
1843 * offset + 1 (16 bit): CRTC port
1844 * offset + 3 (8 bit): CRTC index
1845 * offset + 4 (8 bit): data
1847 * Write "data" to index "CRTC index" of "CRTC port"
1849 uint16_t crtcport = ROM16(bios->data[offset + 1]);
1850 uint8_t crtcindex = bios->data[offset + 3];
1851 uint8_t data = bios->data[offset + 4];
1853 if (!iexec->execute)
1856 bios_idxprt_wr(bios, crtcport, crtcindex, data);
1862 init_compute_mem(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1865 * INIT_COMPUTE_MEM opcode: 0x63 ('c')
1867 * offset (8 bit): opcode
1869 * This opcode is meant to set NV_PFB_CFG0 (0x100200) appropriately so
1870 * that the hardware can correctly calculate how much VRAM it has
1871 * (and subsequently report that value in NV_PFB_CSTATUS (0x10020C))
1873 * The implementation of this opcode in general consists of two parts:
1874 * 1) determination of the memory bus width
1875 * 2) determination of how many of the card's RAM pads have ICs attached
1877 * 1) is done by a cunning combination of writes to offsets 0x1c and
1878 * 0x3c in the framebuffer, and seeing whether the written values are
1879 * read back correctly. This then affects bits 4-7 of NV_PFB_CFG0
1881 * 2) is done by a cunning combination of writes to an offset slightly
1882 * less than the maximum memory reported by NV_PFB_CSTATUS, then seeing
1883 * if the test pattern can be read back. This then affects bits 12-15 of
1886 * In this context a "cunning combination" may include multiple reads
1887 * and writes to varying locations, often alternating the test pattern
1888 * and 0, doubtless to make sure buffers are filled, residual charges
1889 * on tracks are removed etc.
1891 * Unfortunately, the "cunning combination"s mentioned above, and the
1892 * changes to the bits in NV_PFB_CFG0 differ with nearly every bios
1895 * Therefore, we cheat and assume the value of NV_PFB_CFG0 with which
1896 * we started was correct, and use that instead
1899 /* no iexec->execute check by design */
1902 * This appears to be a NOP on G8x chipsets, both io logs of the VBIOS
1903 * and kmmio traces of the binary driver POSTing the card show nothing
1904 * being done for this opcode. why is it still listed in the table?!
1907 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
1909 if (dev_priv->card_type >= NV_50)
1913 * On every card I've seen, this step gets done for us earlier in
1915 uint8_t crdata = bios_idxprt_rd(dev, NV_VIO_SRX, 0x01);
1916 bios_idxprt_wr(dev, NV_VIO_SRX, 0x01, crdata | 0x20);
1920 * This also has probably been done in the scripts, but an mmio trace of
1921 * s3 resume shows nvidia doing it anyway (unlike the NV_VIO_SRX write)
1923 bios_wr32(bios, NV_PFB_REFCTRL, NV_PFB_REFCTRL_VALID_1);
1925 /* write back the saved configuration value */
1926 bios_wr32(bios, NV_PFB_CFG0, bios->state.saved_nv_pfb_cfg0);
1932 init_reset(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1935 * INIT_RESET opcode: 0x65 ('e')
1937 * offset (8 bit): opcode
1938 * offset + 1 (32 bit): register
1939 * offset + 5 (32 bit): value1
1940 * offset + 9 (32 bit): value2
1942 * Assign "value1" to "register", then assign "value2" to "register"
1945 uint32_t reg = ROM32(bios->data[offset + 1]);
1946 uint32_t value1 = ROM32(bios->data[offset + 5]);
1947 uint32_t value2 = ROM32(bios->data[offset + 9]);
1948 uint32_t pci_nv_19, pci_nv_20;
1950 /* no iexec->execute check by design */
1952 pci_nv_19 = bios_rd32(bios, NV_PBUS_PCI_NV_19);
1953 bios_wr32(bios, NV_PBUS_PCI_NV_19, 0);
1954 bios_wr32(bios, reg, value1);
1958 bios_wr32(bios, reg, value2);
1959 bios_wr32(bios, NV_PBUS_PCI_NV_19, pci_nv_19);
1961 pci_nv_20 = bios_rd32(bios, NV_PBUS_PCI_NV_20);
1962 pci_nv_20 &= ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED; /* 0xfffffffe */
1963 bios_wr32(bios, NV_PBUS_PCI_NV_20, pci_nv_20);
1969 init_configure_mem(struct nvbios *bios, uint16_t offset,
1970 struct init_exec *iexec)
1973 * INIT_CONFIGURE_MEM opcode: 0x66 ('f')
1975 * offset (8 bit): opcode
1977 * Equivalent to INIT_DONE on bios version 3 or greater.
1978 * For early bios versions, sets up the memory registers, using values
1979 * taken from the memory init table
1982 /* no iexec->execute check by design */
1984 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4);
1985 uint16_t seqtbloffs = bios->legacy.sdr_seq_tbl_ptr, meminitdata = meminitoffs + 6;
1988 if (bios->major_version > 2)
1991 bios_idxprt_wr(bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX, bios_idxprt_rd(
1992 bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX) | 0x20);
1994 if (bios->data[meminitoffs] & 1)
1995 seqtbloffs = bios->legacy.ddr_seq_tbl_ptr;
1997 for (reg = ROM32(bios->data[seqtbloffs]);
1999 reg = ROM32(bios->data[seqtbloffs += 4])) {
2003 data = NV_PFB_PRE_CMD_PRECHARGE;
2006 data = NV_PFB_PAD_CKE_NORMAL;
2009 data = NV_PFB_REF_CMD_REFRESH;
2012 data = ROM32(bios->data[meminitdata]);
2014 if (data == 0xffffffff)
2018 bios_wr32(bios, reg, data);
2025 init_configure_clk(struct nvbios *bios, uint16_t offset,
2026 struct init_exec *iexec)
2029 * INIT_CONFIGURE_CLK opcode: 0x67 ('g')
2031 * offset (8 bit): opcode
2033 * Equivalent to INIT_DONE on bios version 3 or greater.
2034 * For early bios versions, sets up the NVClk and MClk PLLs, using
2035 * values taken from the memory init table
2038 /* no iexec->execute check by design */
2040 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4);
2043 if (bios->major_version > 2)
2046 clock = ROM16(bios->data[meminitoffs + 4]) * 10;
2047 setPLL(bios, NV_PRAMDAC_NVPLL_COEFF, clock);
2049 clock = ROM16(bios->data[meminitoffs + 2]) * 10;
2050 if (bios->data[meminitoffs] & 1) /* DDR */
2052 setPLL(bios, NV_PRAMDAC_MPLL_COEFF, clock);
2058 init_configure_preinit(struct nvbios *bios, uint16_t offset,
2059 struct init_exec *iexec)
2062 * INIT_CONFIGURE_PREINIT opcode: 0x68 ('h')
2064 * offset (8 bit): opcode
2066 * Equivalent to INIT_DONE on bios version 3 or greater.
2067 * For early bios versions, does early init, loading ram and crystal
2068 * configuration from straps into CR3C
2071 /* no iexec->execute check by design */
2073 uint32_t straps = bios_rd32(bios, NV_PEXTDEV_BOOT_0);
2074 uint8_t cr3c = ((straps << 2) & 0xf0) | (straps & (1 << 6));
2076 if (bios->major_version > 2)
2079 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR,
2080 NV_CIO_CRE_SCRATCH4__INDEX, cr3c);
2086 init_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2089 * INIT_IO opcode: 0x69 ('i')
2091 * offset (8 bit): opcode
2092 * offset + 1 (16 bit): CRTC port
2093 * offset + 3 (8 bit): mask
2094 * offset + 4 (8 bit): data
2096 * Assign ((IOVAL("crtc port") & "mask") | "data") to "crtc port"
2099 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
2100 uint16_t crtcport = ROM16(bios->data[offset + 1]);
2101 uint8_t mask = bios->data[offset + 3];
2102 uint8_t data = bios->data[offset + 4];
2104 if (!iexec->execute)
2107 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Mask: 0x%02X, Data: 0x%02X\n",
2108 offset, crtcport, mask, data);
2111 * I have no idea what this does, but NVIDIA do this magic sequence
2112 * in the places where this INIT_IO happens..
2114 if (dev_priv->card_type >= NV_50 && crtcport == 0x3c3 && data == 1) {
2117 bios_wr32(bios, 0x614100, (bios_rd32(
2118 bios, 0x614100) & 0x0fffffff) | 0x00800000);
2120 bios_wr32(bios, 0x00e18c, bios_rd32(
2121 bios, 0x00e18c) | 0x00020000);
2123 bios_wr32(bios, 0x614900, (bios_rd32(
2124 bios, 0x614900) & 0x0fffffff) | 0x00800000);
2126 bios_wr32(bios, 0x000200, bios_rd32(
2127 bios, 0x000200) & ~0x40000000);
2131 bios_wr32(bios, 0x00e18c, bios_rd32(
2132 bios, 0x00e18c) & ~0x00020000);
2134 bios_wr32(bios, 0x000200, bios_rd32(
2135 bios, 0x000200) | 0x40000000);
2137 bios_wr32(bios, 0x614100, 0x00800018);
2138 bios_wr32(bios, 0x614900, 0x00800018);
2142 bios_wr32(bios, 0x614100, 0x10000018);
2143 bios_wr32(bios, 0x614900, 0x10000018);
2145 for (i = 0; i < 3; i++)
2146 bios_wr32(bios, 0x614280 + (i*0x800), bios_rd32(
2147 bios, 0x614280 + (i*0x800)) & 0xf0f0f0f0);
2149 for (i = 0; i < 2; i++)
2150 bios_wr32(bios, 0x614300 + (i*0x800), bios_rd32(
2151 bios, 0x614300 + (i*0x800)) & 0xfffff0f0);
2153 for (i = 0; i < 3; i++)
2154 bios_wr32(bios, 0x614380 + (i*0x800), bios_rd32(
2155 bios, 0x614380 + (i*0x800)) & 0xfffff0f0);
2157 for (i = 0; i < 2; i++)
2158 bios_wr32(bios, 0x614200 + (i*0x800), bios_rd32(
2159 bios, 0x614200 + (i*0x800)) & 0xfffffff0);
2161 for (i = 0; i < 2; i++)
2162 bios_wr32(bios, 0x614108 + (i*0x800), bios_rd32(
2163 bios, 0x614108 + (i*0x800)) & 0x0fffffff);
2167 bios_port_wr(bios, crtcport, (bios_port_rd(bios, crtcport) & mask) |
2173 init_sub(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2176 * INIT_SUB opcode: 0x6B ('k')
2178 * offset (8 bit): opcode
2179 * offset + 1 (8 bit): script number
2181 * Execute script number "script number", as a subroutine
2184 uint8_t sub = bios->data[offset + 1];
2186 if (!iexec->execute)
2189 BIOSLOG(bios, "0x%04X: Calling script %d\n", offset, sub);
2191 parse_init_table(bios,
2192 ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]),
2195 BIOSLOG(bios, "0x%04X: End of script %d\n", offset, sub);
2201 init_ram_condition(struct nvbios *bios, uint16_t offset,
2202 struct init_exec *iexec)
2205 * INIT_RAM_CONDITION opcode: 0x6D ('m')
2207 * offset (8 bit): opcode
2208 * offset + 1 (8 bit): mask
2209 * offset + 2 (8 bit): cmpval
2211 * Test if (NV_PFB_BOOT_0 & "mask") equals "cmpval".
2212 * If condition not met skip subsequent opcodes until condition is
2213 * inverted (INIT_NOT), or we hit INIT_RESUME
2216 uint8_t mask = bios->data[offset + 1];
2217 uint8_t cmpval = bios->data[offset + 2];
2220 if (!iexec->execute)
2223 data = bios_rd32(bios, NV_PFB_BOOT_0) & mask;
2225 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n",
2226 offset, data, cmpval);
2229 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
2231 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
2232 iexec->execute = false;
2239 init_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2242 * INIT_NV_REG opcode: 0x6E ('n')
2244 * offset (8 bit): opcode
2245 * offset + 1 (32 bit): register
2246 * offset + 5 (32 bit): mask
2247 * offset + 9 (32 bit): data
2249 * Assign ((REGVAL("register") & "mask") | "data") to "register"
2252 uint32_t reg = ROM32(bios->data[offset + 1]);
2253 uint32_t mask = ROM32(bios->data[offset + 5]);
2254 uint32_t data = ROM32(bios->data[offset + 9]);
2256 if (!iexec->execute)
2259 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Mask: 0x%08X, Data: 0x%08X\n",
2260 offset, reg, mask, data);
2262 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | data);
2268 init_macro(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2271 * INIT_MACRO opcode: 0x6F ('o')
2273 * offset (8 bit): opcode
2274 * offset + 1 (8 bit): macro number
2276 * Look up macro index "macro number" in the macro index table.
2277 * The macro index table entry has 1 byte for the index in the macro
2278 * table, and 1 byte for the number of times to repeat the macro.
2279 * The macro table entry has 4 bytes for the register address and
2280 * 4 bytes for the value to write to that register
2283 uint8_t macro_index_tbl_idx = bios->data[offset + 1];
2284 uint16_t tmp = bios->macro_index_tbl_ptr + (macro_index_tbl_idx * MACRO_INDEX_SIZE);
2285 uint8_t macro_tbl_idx = bios->data[tmp];
2286 uint8_t count = bios->data[tmp + 1];
2290 if (!iexec->execute)
2293 BIOSLOG(bios, "0x%04X: Macro: 0x%02X, MacroTableIndex: 0x%02X, "
2295 offset, macro_index_tbl_idx, macro_tbl_idx, count);
2297 for (i = 0; i < count; i++) {
2298 uint16_t macroentryptr = bios->macro_tbl_ptr + (macro_tbl_idx + i) * MACRO_SIZE;
2300 reg = ROM32(bios->data[macroentryptr]);
2301 data = ROM32(bios->data[macroentryptr + 4]);
2303 bios_wr32(bios, reg, data);
2310 init_done(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2313 * INIT_DONE opcode: 0x71 ('q')
2315 * offset (8 bit): opcode
2317 * End the current script
2320 /* mild retval abuse to stop parsing this table */
2325 init_resume(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2328 * INIT_RESUME opcode: 0x72 ('r')
2330 * offset (8 bit): opcode
2332 * End the current execute / no-execute condition
2338 iexec->execute = true;
2339 BIOSLOG(bios, "0x%04X: ---- Executing following commands ----\n", offset);
2345 init_time(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2348 * INIT_TIME opcode: 0x74 ('t')
2350 * offset (8 bit): opcode
2351 * offset + 1 (16 bit): time
2353 * Sleep for "time" microseconds.
2356 unsigned time = ROM16(bios->data[offset + 1]);
2358 if (!iexec->execute)
2361 BIOSLOG(bios, "0x%04X: Sleeping for 0x%04X microseconds\n",
2367 msleep((time + 900) / 1000);
2373 init_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2376 * INIT_CONDITION opcode: 0x75 ('u')
2378 * offset (8 bit): opcode
2379 * offset + 1 (8 bit): condition number
2381 * Check condition "condition number" in the condition table.
2382 * If condition not met skip subsequent opcodes until condition is
2383 * inverted (INIT_NOT), or we hit INIT_RESUME
2386 uint8_t cond = bios->data[offset + 1];
2388 if (!iexec->execute)
2391 BIOSLOG(bios, "0x%04X: Condition: 0x%02X\n", offset, cond);
2393 if (bios_condition_met(bios, offset, cond))
2394 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
2396 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
2397 iexec->execute = false;
2404 init_io_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2407 * INIT_IO_CONDITION opcode: 0x76
2409 * offset (8 bit): opcode
2410 * offset + 1 (8 bit): condition number
2412 * Check condition "condition number" in the io condition table.
2413 * If condition not met skip subsequent opcodes until condition is
2414 * inverted (INIT_NOT), or we hit INIT_RESUME
2417 uint8_t cond = bios->data[offset + 1];
2419 if (!iexec->execute)
2422 BIOSLOG(bios, "0x%04X: IO condition: 0x%02X\n", offset, cond);
2424 if (io_condition_met(bios, offset, cond))
2425 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
2427 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
2428 iexec->execute = false;
2435 init_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2438 * INIT_INDEX_IO opcode: 0x78 ('x')
2440 * offset (8 bit): opcode
2441 * offset + 1 (16 bit): CRTC port
2442 * offset + 3 (8 bit): CRTC index
2443 * offset + 4 (8 bit): mask
2444 * offset + 5 (8 bit): data
2446 * Read value at index "CRTC index" on "CRTC port", AND with "mask",
2447 * OR with "data", write-back
2450 uint16_t crtcport = ROM16(bios->data[offset + 1]);
2451 uint8_t crtcindex = bios->data[offset + 3];
2452 uint8_t mask = bios->data[offset + 4];
2453 uint8_t data = bios->data[offset + 5];
2456 if (!iexec->execute)
2459 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
2461 offset, crtcport, crtcindex, mask, data);
2463 value = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) | data;
2464 bios_idxprt_wr(bios, crtcport, crtcindex, value);
2470 init_pll(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2473 * INIT_PLL opcode: 0x79 ('y')
2475 * offset (8 bit): opcode
2476 * offset + 1 (32 bit): register
2477 * offset + 5 (16 bit): freq
2479 * Set PLL register "register" to coefficients for frequency (10kHz)
2483 uint32_t reg = ROM32(bios->data[offset + 1]);
2484 uint16_t freq = ROM16(bios->data[offset + 5]);
2486 if (!iexec->execute)
2489 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Freq: %d0kHz\n", offset, reg, freq);
2491 setPLL(bios, reg, freq * 10);
2497 init_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2500 * INIT_ZM_REG opcode: 0x7A ('z')
2502 * offset (8 bit): opcode
2503 * offset + 1 (32 bit): register
2504 * offset + 5 (32 bit): value
2506 * Assign "value" to "register"
2509 uint32_t reg = ROM32(bios->data[offset + 1]);
2510 uint32_t value = ROM32(bios->data[offset + 5]);
2512 if (!iexec->execute)
2515 if (reg == 0x000200)
2518 bios_wr32(bios, reg, value);
2524 init_ram_restrict_pll(struct nvbios *bios, uint16_t offset,
2525 struct init_exec *iexec)
2528 * INIT_RAM_RESTRICT_PLL opcode: 0x87 ('')
2530 * offset (8 bit): opcode
2531 * offset + 1 (8 bit): PLL type
2532 * offset + 2 (32 bit): frequency 0
2534 * Uses the RAMCFG strap of PEXTDEV_BOOT as an index into the table at
2535 * ram_restrict_table_ptr. The value read from there is used to select
2536 * a frequency from the table starting at 'frequency 0' to be
2537 * programmed into the PLL corresponding to 'type'.
2539 * The PLL limits table on cards using this opcode has a mapping of
2540 * 'type' to the relevant registers.
2543 struct drm_device *dev = bios->dev;
2544 uint32_t strap = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) & 0x0000003c) >> 2;
2545 uint8_t index = bios->data[bios->ram_restrict_tbl_ptr + strap];
2546 uint8_t type = bios->data[offset + 1];
2547 uint32_t freq = ROM32(bios->data[offset + 2 + (index * 4)]);
2548 uint8_t *pll_limits = &bios->data[bios->pll_limit_tbl_ptr], *entry;
2549 int len = 2 + bios->ram_restrict_group_count * 4;
2552 if (!iexec->execute)
2555 if (!bios->pll_limit_tbl_ptr || (pll_limits[0] & 0xf0) != 0x30) {
2556 NV_ERROR(dev, "PLL limits table not version 3.x\n");
2557 return len; /* deliberate, allow default clocks to remain */
2560 entry = pll_limits + pll_limits[1];
2561 for (i = 0; i < pll_limits[3]; i++, entry += pll_limits[2]) {
2562 if (entry[0] == type) {
2563 uint32_t reg = ROM32(entry[3]);
2565 BIOSLOG(bios, "0x%04X: "
2566 "Type %02x Reg 0x%08x Freq %dKHz\n",
2567 offset, type, reg, freq);
2569 setPLL(bios, reg, freq);
2574 NV_ERROR(dev, "PLL type 0x%02x not found in PLL limits table", type);
2579 init_8c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2582 * INIT_8C opcode: 0x8C ('')
2592 init_8d(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2595 * INIT_8D opcode: 0x8D ('')
2605 init_gpio(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2608 * INIT_GPIO opcode: 0x8E ('')
2610 * offset (8 bit): opcode
2612 * Loop over all entries in the DCB GPIO table, and initialise
2613 * each GPIO according to various values listed in each entry
2616 const uint32_t nv50_gpio_reg[4] = { 0xe104, 0xe108, 0xe280, 0xe284 };
2617 const uint32_t nv50_gpio_ctl[2] = { 0xe100, 0xe28c };
2618 const uint8_t *gpio_table = &bios->data[bios->bdcb.gpio_table_ptr];
2619 const uint8_t *gpio_entry;
2622 if (!iexec->execute)
2625 if (bios->bdcb.version != 0x40) {
2626 NV_ERROR(bios->dev, "DCB table not version 4.0\n");
2630 if (!bios->bdcb.gpio_table_ptr) {
2631 NV_WARN(bios->dev, "Invalid pointer to INIT_8E table\n");
2635 gpio_entry = gpio_table + gpio_table[1];
2636 for (i = 0; i < gpio_table[2]; i++, gpio_entry += gpio_table[3]) {
2637 uint32_t entry = ROM32(gpio_entry[0]), r, s, v;
2638 int line = (entry & 0x0000001f);
2640 BIOSLOG(bios, "0x%04X: Entry: 0x%08X\n", offset, entry);
2642 if ((entry & 0x0000ff00) == 0x0000ff00)
2645 r = nv50_gpio_reg[line >> 3];
2646 s = (line & 0x07) << 2;
2647 v = bios_rd32(bios, r) & ~(0x00000003 << s);
2648 if (entry & 0x01000000)
2649 v |= (((entry & 0x60000000) >> 29) ^ 2) << s;
2651 v |= (((entry & 0x18000000) >> 27) ^ 2) << s;
2652 bios_wr32(bios, r, v);
2654 r = nv50_gpio_ctl[line >> 4];
2656 v = bios_rd32(bios, r) & ~(0x00010001 << s);
2657 switch ((entry & 0x06000000) >> 25) {
2659 v |= (0x00000001 << s);
2662 v |= (0x00010000 << s);
2667 bios_wr32(bios, r, v);
2674 init_ram_restrict_zm_reg_group(struct nvbios *bios, uint16_t offset,
2675 struct init_exec *iexec)
2678 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode: 0x8F ('')
2680 * offset (8 bit): opcode
2681 * offset + 1 (32 bit): reg
2682 * offset + 5 (8 bit): regincrement
2683 * offset + 6 (8 bit): count
2684 * offset + 7 (32 bit): value 1,1
2687 * Use the RAMCFG strap of PEXTDEV_BOOT as an index into the table at
2688 * ram_restrict_table_ptr. The value read from here is 'n', and
2689 * "value 1,n" gets written to "reg". This repeats "count" times and on
2690 * each iteration 'm', "reg" increases by "regincrement" and
2691 * "value m,n" is used. The extent of n is limited by a number read
2692 * from the 'M' BIT table, herein called "blocklen"
2695 uint32_t reg = ROM32(bios->data[offset + 1]);
2696 uint8_t regincrement = bios->data[offset + 5];
2697 uint8_t count = bios->data[offset + 6];
2698 uint32_t strap_ramcfg, data;
2699 /* previously set by 'M' BIT table */
2700 uint16_t blocklen = bios->ram_restrict_group_count * 4;
2701 int len = 7 + count * blocklen;
2706 if (!iexec->execute)
2711 "0x%04X: Zero block length - has the M table "
2712 "been parsed?\n", offset);
2716 strap_ramcfg = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 2) & 0xf;
2717 index = bios->data[bios->ram_restrict_tbl_ptr + strap_ramcfg];
2719 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, RegIncrement: 0x%02X, "
2720 "Count: 0x%02X, StrapRamCfg: 0x%02X, Index: 0x%02X\n",
2721 offset, reg, regincrement, count, strap_ramcfg, index);
2723 for (i = 0; i < count; i++) {
2724 data = ROM32(bios->data[offset + 7 + index * 4 + blocklen * i]);
2726 bios_wr32(bios, reg, data);
2728 reg += regincrement;
2735 init_copy_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2738 * INIT_COPY_ZM_REG opcode: 0x90 ('')
2740 * offset (8 bit): opcode
2741 * offset + 1 (32 bit): src reg
2742 * offset + 5 (32 bit): dst reg
2744 * Put contents of "src reg" into "dst reg"
2747 uint32_t srcreg = ROM32(bios->data[offset + 1]);
2748 uint32_t dstreg = ROM32(bios->data[offset + 5]);
2750 if (!iexec->execute)
2753 bios_wr32(bios, dstreg, bios_rd32(bios, srcreg));
2759 init_zm_reg_group_addr_latched(struct nvbios *bios, uint16_t offset,
2760 struct init_exec *iexec)
2763 * INIT_ZM_REG_GROUP_ADDRESS_LATCHED opcode: 0x91 ('')
2765 * offset (8 bit): opcode
2766 * offset + 1 (32 bit): dst reg
2767 * offset + 5 (8 bit): count
2768 * offset + 6 (32 bit): data 1
2771 * For each of "count" values write "data n" to "dst reg"
2774 uint32_t reg = ROM32(bios->data[offset + 1]);
2775 uint8_t count = bios->data[offset + 5];
2776 int len = 6 + count * 4;
2779 if (!iexec->execute)
2782 for (i = 0; i < count; i++) {
2783 uint32_t data = ROM32(bios->data[offset + 6 + 4 * i]);
2784 bios_wr32(bios, reg, data);
2791 init_reserved(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2794 * INIT_RESERVED opcode: 0x92 ('')
2796 * offset (8 bit): opcode
2798 * Seemingly does nothing
2805 init_96(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2808 * INIT_96 opcode: 0x96 ('')
2810 * offset (8 bit): opcode
2811 * offset + 1 (32 bit): sreg
2812 * offset + 5 (8 bit): sshift
2813 * offset + 6 (8 bit): smask
2814 * offset + 7 (8 bit): index
2815 * offset + 8 (32 bit): reg
2816 * offset + 12 (32 bit): mask
2817 * offset + 16 (8 bit): shift
2821 uint16_t xlatptr = bios->init96_tbl_ptr + (bios->data[offset + 7] * 2);
2822 uint32_t reg = ROM32(bios->data[offset + 8]);
2823 uint32_t mask = ROM32(bios->data[offset + 12]);
2826 val = bios_rd32(bios, ROM32(bios->data[offset + 1]));
2827 if (bios->data[offset + 5] < 0x80)
2828 val >>= bios->data[offset + 5];
2830 val <<= (0x100 - bios->data[offset + 5]);
2831 val &= bios->data[offset + 6];
2833 val = bios->data[ROM16(bios->data[xlatptr]) + val];
2834 val <<= bios->data[offset + 16];
2836 if (!iexec->execute)
2839 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | val);
2844 init_97(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2847 * INIT_97 opcode: 0x97 ('')
2849 * offset (8 bit): opcode
2850 * offset + 1 (32 bit): register
2851 * offset + 5 (32 bit): mask
2852 * offset + 9 (32 bit): value
2854 * Adds "value" to "register" preserving the fields specified
2858 uint32_t reg = ROM32(bios->data[offset + 1]);
2859 uint32_t mask = ROM32(bios->data[offset + 5]);
2860 uint32_t add = ROM32(bios->data[offset + 9]);
2863 val = bios_rd32(bios, reg);
2864 val = (val & mask) | ((val + add) & ~mask);
2866 if (!iexec->execute)
2869 bios_wr32(bios, reg, val);
2874 init_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2877 * INIT_AUXCH opcode: 0x98 ('')
2879 * offset (8 bit): opcode
2880 * offset + 1 (32 bit): address
2881 * offset + 5 (8 bit): count
2882 * offset + 6 (8 bit): mask 0
2883 * offset + 7 (8 bit): data 0
2888 struct drm_device *dev = bios->dev;
2889 struct nouveau_i2c_chan *auxch;
2890 uint32_t addr = ROM32(bios->data[offset + 1]);
2891 uint8_t count = bios->data[offset + 5];
2892 int len = 6 + count * 2;
2895 if (!bios->display.output) {
2896 NV_ERROR(dev, "INIT_AUXCH: no active output\n");
2900 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index);
2902 NV_ERROR(dev, "INIT_AUXCH: couldn't get auxch %d\n",
2903 bios->display.output->i2c_index);
2907 if (!iexec->execute)
2911 for (i = 0; i < count; i++, offset += 2) {
2914 ret = nouveau_dp_auxch(auxch, 9, addr, &data, 1);
2916 NV_ERROR(dev, "INIT_AUXCH: rd auxch fail %d\n", ret);
2920 data &= bios->data[offset + 0];
2921 data |= bios->data[offset + 1];
2923 ret = nouveau_dp_auxch(auxch, 8, addr, &data, 1);
2925 NV_ERROR(dev, "INIT_AUXCH: wr auxch fail %d\n", ret);
2934 init_zm_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2937 * INIT_ZM_AUXCH opcode: 0x99 ('')
2939 * offset (8 bit): opcode
2940 * offset + 1 (32 bit): address
2941 * offset + 5 (8 bit): count
2942 * offset + 6 (8 bit): data 0
2947 struct drm_device *dev = bios->dev;
2948 struct nouveau_i2c_chan *auxch;
2949 uint32_t addr = ROM32(bios->data[offset + 1]);
2950 uint8_t count = bios->data[offset + 5];
2951 int len = 6 + count;
2954 if (!bios->display.output) {
2955 NV_ERROR(dev, "INIT_ZM_AUXCH: no active output\n");
2959 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index);
2961 NV_ERROR(dev, "INIT_ZM_AUXCH: couldn't get auxch %d\n",
2962 bios->display.output->i2c_index);
2966 if (!iexec->execute)
2970 for (i = 0; i < count; i++, offset++) {
2971 ret = nouveau_dp_auxch(auxch, 8, addr, &bios->data[offset], 1);
2973 NV_ERROR(dev, "INIT_ZM_AUXCH: wr auxch fail %d\n", ret);
2981 static struct init_tbl_entry itbl_entry[] = {
2982 /* command name , id , length , offset , mult , command handler */
2983 /* INIT_PROG (0x31, 15, 10, 4) removed due to no example of use */
2984 { "INIT_IO_RESTRICT_PROG" , 0x32, init_io_restrict_prog },
2985 { "INIT_REPEAT" , 0x33, init_repeat },
2986 { "INIT_IO_RESTRICT_PLL" , 0x34, init_io_restrict_pll },
2987 { "INIT_END_REPEAT" , 0x36, init_end_repeat },
2988 { "INIT_COPY" , 0x37, init_copy },
2989 { "INIT_NOT" , 0x38, init_not },
2990 { "INIT_IO_FLAG_CONDITION" , 0x39, init_io_flag_condition },
2991 { "INIT_INDEX_ADDRESS_LATCHED" , 0x49, init_idx_addr_latched },
2992 { "INIT_IO_RESTRICT_PLL2" , 0x4A, init_io_restrict_pll2 },
2993 { "INIT_PLL2" , 0x4B, init_pll2 },
2994 { "INIT_I2C_BYTE" , 0x4C, init_i2c_byte },
2995 { "INIT_ZM_I2C_BYTE" , 0x4D, init_zm_i2c_byte },
2996 { "INIT_ZM_I2C" , 0x4E, init_zm_i2c },
2997 { "INIT_TMDS" , 0x4F, init_tmds },
2998 { "INIT_ZM_TMDS_GROUP" , 0x50, init_zm_tmds_group },
2999 { "INIT_CR_INDEX_ADDRESS_LATCHED" , 0x51, init_cr_idx_adr_latch },
3000 { "INIT_CR" , 0x52, init_cr },
3001 { "INIT_ZM_CR" , 0x53, init_zm_cr },
3002 { "INIT_ZM_CR_GROUP" , 0x54, init_zm_cr_group },
3003 { "INIT_CONDITION_TIME" , 0x56, init_condition_time },
3004 { "INIT_ZM_REG_SEQUENCE" , 0x58, init_zm_reg_sequence },
3005 /* INIT_INDIRECT_REG (0x5A, 7, 0, 0) removed due to no example of use */
3006 { "INIT_SUB_DIRECT" , 0x5B, init_sub_direct },
3007 { "INIT_COPY_NV_REG" , 0x5F, init_copy_nv_reg },
3008 { "INIT_ZM_INDEX_IO" , 0x62, init_zm_index_io },
3009 { "INIT_COMPUTE_MEM" , 0x63, init_compute_mem },
3010 { "INIT_RESET" , 0x65, init_reset },
3011 { "INIT_CONFIGURE_MEM" , 0x66, init_configure_mem },
3012 { "INIT_CONFIGURE_CLK" , 0x67, init_configure_clk },
3013 { "INIT_CONFIGURE_PREINIT" , 0x68, init_configure_preinit },
3014 { "INIT_IO" , 0x69, init_io },
3015 { "INIT_SUB" , 0x6B, init_sub },
3016 { "INIT_RAM_CONDITION" , 0x6D, init_ram_condition },
3017 { "INIT_NV_REG" , 0x6E, init_nv_reg },
3018 { "INIT_MACRO" , 0x6F, init_macro },
3019 { "INIT_DONE" , 0x71, init_done },
3020 { "INIT_RESUME" , 0x72, init_resume },
3021 /* INIT_RAM_CONDITION2 (0x73, 9, 0, 0) removed due to no example of use */
3022 { "INIT_TIME" , 0x74, init_time },
3023 { "INIT_CONDITION" , 0x75, init_condition },
3024 { "INIT_IO_CONDITION" , 0x76, init_io_condition },
3025 { "INIT_INDEX_IO" , 0x78, init_index_io },
3026 { "INIT_PLL" , 0x79, init_pll },
3027 { "INIT_ZM_REG" , 0x7A, init_zm_reg },
3028 { "INIT_RAM_RESTRICT_PLL" , 0x87, init_ram_restrict_pll },
3029 { "INIT_8C" , 0x8C, init_8c },
3030 { "INIT_8D" , 0x8D, init_8d },
3031 { "INIT_GPIO" , 0x8E, init_gpio },
3032 { "INIT_RAM_RESTRICT_ZM_REG_GROUP" , 0x8F, init_ram_restrict_zm_reg_group },
3033 { "INIT_COPY_ZM_REG" , 0x90, init_copy_zm_reg },
3034 { "INIT_ZM_REG_GROUP_ADDRESS_LATCHED" , 0x91, init_zm_reg_group_addr_latched },
3035 { "INIT_RESERVED" , 0x92, init_reserved },
3036 { "INIT_96" , 0x96, init_96 },
3037 { "INIT_97" , 0x97, init_97 },
3038 { "INIT_AUXCH" , 0x98, init_auxch },
3039 { "INIT_ZM_AUXCH" , 0x99, init_zm_auxch },
3043 #define MAX_TABLE_OPS 1000
3046 parse_init_table(struct nvbios *bios, unsigned int offset,
3047 struct init_exec *iexec)
3050 * Parses all commands in an init table.
3052 * We start out executing all commands found in the init table. Some
3053 * opcodes may change the status of iexec->execute to SKIP, which will
3054 * cause the following opcodes to perform no operation until the value
3055 * is changed back to EXECUTE.
3058 int count = 0, i, res;
3062 * Loop until INIT_DONE causes us to break out of the loop
3063 * (or until offset > bios length just in case... )
3064 * (and no more than MAX_TABLE_OPS iterations, just in case... )
3066 while ((offset < bios->length) && (count++ < MAX_TABLE_OPS)) {
3067 id = bios->data[offset];
3069 /* Find matching id in itbl_entry */
3070 for (i = 0; itbl_entry[i].name && (itbl_entry[i].id != id); i++)
3073 if (itbl_entry[i].name) {
3074 BIOSLOG(bios, "0x%04X: [ (0x%02X) - %s ]\n",
3075 offset, itbl_entry[i].id, itbl_entry[i].name);
3077 /* execute eventual command handler */
3078 res = (*itbl_entry[i].handler)(bios, offset, iexec);
3082 * Add the offset of the current command including all data
3083 * of that command. The offset will then be pointing on the
3089 "0x%04X: Init table command not found: "
3090 "0x%02X\n", offset, id);
3095 if (offset >= bios->length)
3097 "Offset 0x%04X greater than known bios image length. "
3098 "Corrupt image?\n", offset);
3099 if (count >= MAX_TABLE_OPS)
3101 "More than %d opcodes to a table is unlikely, "
3102 "is the bios image corrupt?\n", MAX_TABLE_OPS);
3108 parse_init_tables(struct nvbios *bios)
3110 /* Loops and calls parse_init_table() for each present table. */
3114 struct init_exec iexec = {true, false};
3116 if (bios->old_style_init) {
3117 if (bios->init_script_tbls_ptr)
3118 parse_init_table(bios, bios->init_script_tbls_ptr, &iexec);
3119 if (bios->extra_init_script_tbl_ptr)
3120 parse_init_table(bios, bios->extra_init_script_tbl_ptr, &iexec);
3125 while ((table = ROM16(bios->data[bios->init_script_tbls_ptr + i]))) {
3127 "Parsing VBIOS init table %d at offset 0x%04X\n",
3129 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", table);
3131 parse_init_table(bios, table, &iexec);
3136 static uint16_t clkcmptable(struct nvbios *bios, uint16_t clktable, int pxclk)
3138 int compare_record_len, i = 0;
3139 uint16_t compareclk, scriptptr = 0;
3141 if (bios->major_version < 5) /* pre BIT */
3142 compare_record_len = 3;
3144 compare_record_len = 4;
3147 compareclk = ROM16(bios->data[clktable + compare_record_len * i]);
3148 if (pxclk >= compareclk * 10) {
3149 if (bios->major_version < 5) {
3150 uint8_t tmdssub = bios->data[clktable + 2 + compare_record_len * i];
3151 scriptptr = ROM16(bios->data[bios->init_script_tbls_ptr + tmdssub * 2]);
3153 scriptptr = ROM16(bios->data[clktable + 2 + compare_record_len * i]);
3157 } while (compareclk);
3163 run_digital_op_script(struct drm_device *dev, uint16_t scriptptr,
3164 struct dcb_entry *dcbent, int head, bool dl)
3166 struct drm_nouveau_private *dev_priv = dev->dev_private;
3167 struct nvbios *bios = &dev_priv->VBIOS;
3168 struct init_exec iexec = {true, false};
3170 NV_TRACE(dev, "0x%04X: Parsing digital output script table\n",
3172 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_44,
3173 head ? NV_CIO_CRE_44_HEADB : NV_CIO_CRE_44_HEADA);
3174 /* note: if dcb entries have been merged, index may be misleading */
3175 NVWriteVgaCrtc5758(dev, head, 0, dcbent->index);
3176 parse_init_table(bios, scriptptr, &iexec);
3178 nv04_dfp_bind_head(dev, dcbent, head, dl);
3181 static int call_lvds_manufacturer_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script)
3183 struct drm_nouveau_private *dev_priv = dev->dev_private;
3184 struct nvbios *bios = &dev_priv->VBIOS;
3185 uint8_t sub = bios->data[bios->fp.xlated_entry + script] + (bios->fp.link_c_increment && dcbent->or & OUTPUT_C ? 1 : 0);
3186 uint16_t scriptofs = ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]);
3188 if (!bios->fp.xlated_entry || !sub || !scriptofs)
3191 run_digital_op_script(dev, scriptofs, dcbent, head, bios->fp.dual_link);
3193 if (script == LVDS_PANEL_OFF) {
3194 /* off-on delay in ms */
3195 msleep(ROM16(bios->data[bios->fp.xlated_entry + 7]));
3198 /* Powerbook specific quirks */
3199 if (script == LVDS_RESET && ((dev->pci_device & 0xffff) == 0x0179 || (dev->pci_device & 0xffff) == 0x0329))
3200 nv_write_tmds(dev, dcbent->or, 0, 0x02, 0x72);
3201 if ((dev->pci_device & 0xffff) == 0x0179 || (dev->pci_device & 0xffff) == 0x0189 || (dev->pci_device & 0xffff) == 0x0329) {
3202 if (script == LVDS_PANEL_ON) {
3203 bios_wr32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL, bios_rd32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL) | (1 << 31));
3204 bios_wr32(bios, NV_PCRTC_GPIO_EXT, bios_rd32(bios, NV_PCRTC_GPIO_EXT) | 1);
3206 if (script == LVDS_PANEL_OFF) {
3207 bios_wr32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL, bios_rd32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL) & ~(1 << 31));
3208 bios_wr32(bios, NV_PCRTC_GPIO_EXT, bios_rd32(bios, NV_PCRTC_GPIO_EXT) & ~3);
3216 static int run_lvds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk)
3219 * The BIT LVDS table's header has the information to setup the
3220 * necessary registers. Following the standard 4 byte header are:
3221 * A bitmask byte and a dual-link transition pxclk value for use in
3222 * selecting the init script when not using straps; 4 script pointers
3223 * for panel power, selected by output and on/off; and 8 table pointers
3224 * for panel init, the needed one determined by output, and bits in the
3225 * conf byte. These tables are similar to the TMDS tables, consisting
3226 * of a list of pxclks and script pointers.
3228 struct drm_nouveau_private *dev_priv = dev->dev_private;
3229 struct nvbios *bios = &dev_priv->VBIOS;
3230 unsigned int outputset = (dcbent->or == 4) ? 1 : 0;
3231 uint16_t scriptptr = 0, clktable;
3232 uint8_t clktableptr = 0;
3235 * For now we assume version 3.0 table - g80 support will need some
3242 case LVDS_BACKLIGHT_ON:
3244 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 7 + outputset * 2]);
3246 case LVDS_BACKLIGHT_OFF:
3247 case LVDS_PANEL_OFF:
3248 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 11 + outputset * 2]);
3251 if (dcbent->lvdsconf.use_straps_for_mode) {
3252 if (bios->fp.dual_link)
3254 if (bios->fp.BITbit1)
3258 uint8_t fallback = bios->data[bios->fp.lvdsmanufacturerpointer + 4];
3259 int fallbackcmpval = (dcbent->or == 4) ? 4 : 1;
3261 if (bios->fp.dual_link) {
3263 fallbackcmpval *= 2;
3265 if (fallbackcmpval & fallback)
3269 /* adding outputset * 8 may not be correct */
3270 clktable = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 15 + clktableptr * 2 + outputset * 8]);
3272 NV_ERROR(dev, "Pixel clock comparison table not found\n");
3275 scriptptr = clkcmptable(bios, clktable, pxclk);
3279 NV_ERROR(dev, "LVDS output init script not found\n");
3282 run_digital_op_script(dev, scriptptr, dcbent, head, bios->fp.dual_link);
3287 int call_lvds_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk)
3290 * LVDS operations are multiplexed in an effort to present a single API
3291 * which works with two vastly differing underlying structures.
3292 * This acts as the demux
3295 struct drm_nouveau_private *dev_priv = dev->dev_private;
3296 struct nvbios *bios = &dev_priv->VBIOS;
3297 uint8_t lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer];
3298 uint32_t sel_clk_binding, sel_clk;
3301 if (bios->fp.last_script_invoc == (script << 1 | head) || !lvds_ver ||
3302 (lvds_ver >= 0x30 && script == LVDS_INIT))
3305 if (!bios->fp.lvds_init_run) {
3306 bios->fp.lvds_init_run = true;
3307 call_lvds_script(dev, dcbent, head, LVDS_INIT, pxclk);
3310 if (script == LVDS_PANEL_ON && bios->fp.reset_after_pclk_change)
3311 call_lvds_script(dev, dcbent, head, LVDS_RESET, pxclk);
3312 if (script == LVDS_RESET && bios->fp.power_off_for_reset)
3313 call_lvds_script(dev, dcbent, head, LVDS_PANEL_OFF, pxclk);
3315 NV_TRACE(dev, "Calling LVDS script %d:\n", script);
3317 /* don't let script change pll->head binding */
3318 sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000;
3320 if (lvds_ver < 0x30)
3321 ret = call_lvds_manufacturer_script(dev, dcbent, head, script);
3323 ret = run_lvds_table(dev, dcbent, head, script, pxclk);
3325 bios->fp.last_script_invoc = (script << 1 | head);
3327 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000;
3328 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding);
3329 /* some scripts set a value in NV_PBUS_POWERCTRL_2 and break video overlay */
3330 nvWriteMC(dev, NV_PBUS_POWERCTRL_2, 0);
3335 struct lvdstableheader {
3336 uint8_t lvds_ver, headerlen, recordlen;
3339 static int parse_lvds_manufacturer_table_header(struct drm_device *dev, struct nvbios *bios, struct lvdstableheader *lth)
3342 * BMP version (0xa) LVDS table has a simple header of version and
3343 * record length. The BIT LVDS table has the typical BIT table header:
3344 * version byte, header length byte, record length byte, and a byte for
3345 * the maximum number of records that can be held in the table.
3348 uint8_t lvds_ver, headerlen, recordlen;
3350 memset(lth, 0, sizeof(struct lvdstableheader));
3352 if (bios->fp.lvdsmanufacturerpointer == 0x0) {
3353 NV_ERROR(dev, "Pointer to LVDS manufacturer table invalid\n");
3357 lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer];
3360 case 0x0a: /* pre NV40 */
3362 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
3364 case 0x30: /* NV4x */
3365 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
3366 if (headerlen < 0x1f) {
3367 NV_ERROR(dev, "LVDS table header not understood\n");
3370 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2];
3372 case 0x40: /* G80/G90 */
3373 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
3374 if (headerlen < 0x7) {
3375 NV_ERROR(dev, "LVDS table header not understood\n");
3378 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2];
3382 "LVDS table revision %d.%d not currently supported\n",
3383 lvds_ver >> 4, lvds_ver & 0xf);
3387 lth->lvds_ver = lvds_ver;
3388 lth->headerlen = headerlen;
3389 lth->recordlen = recordlen;
3395 get_fp_strap(struct drm_device *dev, struct nvbios *bios)
3397 struct drm_nouveau_private *dev_priv = dev->dev_private;
3400 * The fp strap is normally dictated by the "User Strap" in
3401 * PEXTDEV_BOOT_0[20:16], but on BMP cards when bit 2 of the
3402 * Internal_Flags struct at 0x48 is set, the user strap gets overriden
3403 * by the PCI subsystem ID during POST, but not before the previous user
3404 * strap has been committed to CR58 for CR57=0xf on head A, which may be
3405 * read and used instead
3408 if (bios->major_version < 5 && bios->data[0x48] & 0x4)
3409 return NVReadVgaCrtc5758(dev, 0, 0xf) & 0xf;
3411 if (dev_priv->card_type >= NV_50)
3412 return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 24) & 0xf;
3414 return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 16) & 0xf;
3417 static int parse_fp_mode_table(struct drm_device *dev, struct nvbios *bios)
3420 uint8_t fptable_ver, headerlen = 0, recordlen, fpentries = 0xf, fpindex;
3421 int ret, ofs, fpstrapping;
3422 struct lvdstableheader lth;
3424 if (bios->fp.fptablepointer == 0x0) {
3425 /* Apple cards don't have the fp table; the laptops use DDC */
3426 /* The table is also missing on some x86 IGPs */
3428 NV_ERROR(dev, "Pointer to flat panel table invalid\n");
3430 bios->pub.digital_min_front_porch = 0x4b;
3434 fptable = &bios->data[bios->fp.fptablepointer];
3435 fptable_ver = fptable[0];
3437 switch (fptable_ver) {
3439 * BMP version 0x5.0x11 BIOSen have version 1 like tables, but no
3440 * version field, and miss one of the spread spectrum/PWM bytes.
3441 * This could affect early GF2Go parts (not seen any appropriate ROMs
3442 * though). Here we assume that a version of 0x05 matches this case
3443 * (combining with a BMP version check would be better), as the
3444 * common case for the panel type field is 0x0005, and that is in
3445 * fact what we are reading the first byte of.
3447 case 0x05: /* some NV10, 11, 15, 16 */
3451 case 0x10: /* some NV15/16, and NV11+ */
3455 case 0x20: /* NV40+ */
3456 headerlen = fptable[1];
3457 recordlen = fptable[2];
3458 fpentries = fptable[3];
3460 * fptable[4] is the minimum
3461 * RAMDAC_FP_HCRTC -> RAMDAC_FP_HSYNC_START gap
3463 bios->pub.digital_min_front_porch = fptable[4];
3468 "FP table revision %d.%d not currently supported\n",
3469 fptable_ver >> 4, fptable_ver & 0xf);
3473 if (!bios->is_mobile) /* !mobile only needs digital_min_front_porch */
3476 ret = parse_lvds_manufacturer_table_header(dev, bios, <h);
3480 if (lth.lvds_ver == 0x30 || lth.lvds_ver == 0x40) {
3481 bios->fp.fpxlatetableptr = bios->fp.lvdsmanufacturerpointer +
3483 bios->fp.xlatwidth = lth.recordlen;
3485 if (bios->fp.fpxlatetableptr == 0x0) {
3486 NV_ERROR(dev, "Pointer to flat panel xlat table invalid\n");
3490 fpstrapping = get_fp_strap(dev, bios);
3492 fpindex = bios->data[bios->fp.fpxlatetableptr +
3493 fpstrapping * bios->fp.xlatwidth];
3495 if (fpindex > fpentries) {
3496 NV_ERROR(dev, "Bad flat panel table index\n");
3500 /* nv4x cards need both a strap value and fpindex of 0xf to use DDC */
3501 if (lth.lvds_ver > 0x10)
3502 bios->pub.fp_no_ddc = fpstrapping != 0xf || fpindex != 0xf;
3505 * If either the strap or xlated fpindex value are 0xf there is no
3506 * panel using a strap-derived bios mode present. this condition
3507 * includes, but is different from, the DDC panel indicator above
3509 if (fpstrapping == 0xf || fpindex == 0xf)
3512 bios->fp.mode_ptr = bios->fp.fptablepointer + headerlen +
3513 recordlen * fpindex + ofs;
3515 NV_TRACE(dev, "BIOS FP mode: %dx%d (%dkHz pixel clock)\n",
3516 ROM16(bios->data[bios->fp.mode_ptr + 11]) + 1,
3517 ROM16(bios->data[bios->fp.mode_ptr + 25]) + 1,
3518 ROM16(bios->data[bios->fp.mode_ptr + 7]) * 10);
3523 bool nouveau_bios_fp_mode(struct drm_device *dev, struct drm_display_mode *mode)
3525 struct drm_nouveau_private *dev_priv = dev->dev_private;
3526 struct nvbios *bios = &dev_priv->VBIOS;
3527 uint8_t *mode_entry = &bios->data[bios->fp.mode_ptr];
3529 if (!mode) /* just checking whether we can produce a mode */
3530 return bios->fp.mode_ptr;
3532 memset(mode, 0, sizeof(struct drm_display_mode));
3534 * For version 1.0 (version in byte 0):
3535 * bytes 1-2 are "panel type", including bits on whether Colour/mono,
3536 * single/dual link, and type (TFT etc.)
3537 * bytes 3-6 are bits per colour in RGBX
3539 mode->clock = ROM16(mode_entry[7]) * 10;
3540 /* bytes 9-10 is HActive */
3541 mode->hdisplay = ROM16(mode_entry[11]) + 1;
3543 * bytes 13-14 is HValid Start
3544 * bytes 15-16 is HValid End
3546 mode->hsync_start = ROM16(mode_entry[17]) + 1;
3547 mode->hsync_end = ROM16(mode_entry[19]) + 1;
3548 mode->htotal = ROM16(mode_entry[21]) + 1;
3549 /* bytes 23-24, 27-30 similarly, but vertical */
3550 mode->vdisplay = ROM16(mode_entry[25]) + 1;
3551 mode->vsync_start = ROM16(mode_entry[31]) + 1;
3552 mode->vsync_end = ROM16(mode_entry[33]) + 1;
3553 mode->vtotal = ROM16(mode_entry[35]) + 1;
3554 mode->flags |= (mode_entry[37] & 0x10) ?
3555 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
3556 mode->flags |= (mode_entry[37] & 0x1) ?
3557 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
3559 * bytes 38-39 relate to spread spectrum settings
3560 * bytes 40-43 are something to do with PWM
3563 mode->status = MODE_OK;
3564 mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
3565 drm_mode_set_name(mode);
3566 return bios->fp.mode_ptr;
3569 int nouveau_bios_parse_lvds_table(struct drm_device *dev, int pxclk, bool *dl, bool *if_is_24bit)
3572 * The LVDS table header is (mostly) described in
3573 * parse_lvds_manufacturer_table_header(): the BIT header additionally
3574 * contains the dual-link transition pxclk (in 10s kHz), at byte 5 - if
3575 * straps are not being used for the panel, this specifies the frequency
3576 * at which modes should be set up in the dual link style.
3578 * Following the header, the BMP (ver 0xa) table has several records,
3579 * indexed by a seperate xlat table, indexed in turn by the fp strap in
3580 * EXTDEV_BOOT. Each record had a config byte, followed by 6 script
3581 * numbers for use by INIT_SUB which controlled panel init and power,
3582 * and finally a dword of ms to sleep between power off and on
3585 * In the BIT versions, the table following the header serves as an
3586 * integrated config and xlat table: the records in the table are
3587 * indexed by the FP strap nibble in EXTDEV_BOOT, and each record has
3588 * two bytes - the first as a config byte, the second for indexing the
3589 * fp mode table pointed to by the BIT 'D' table
3591 * DDC is not used until after card init, so selecting the correct table
3592 * entry and setting the dual link flag for EDID equipped panels,
3593 * requiring tests against the native-mode pixel clock, cannot be done
3594 * until later, when this function should be called with non-zero pxclk
3596 struct drm_nouveau_private *dev_priv = dev->dev_private;
3597 struct nvbios *bios = &dev_priv->VBIOS;
3598 int fpstrapping = get_fp_strap(dev, bios), lvdsmanufacturerindex = 0;
3599 struct lvdstableheader lth;
3601 int ret, chip_version = bios->pub.chip_version;
3603 ret = parse_lvds_manufacturer_table_header(dev, bios, <h);
3607 switch (lth.lvds_ver) {
3608 case 0x0a: /* pre NV40 */
3609 lvdsmanufacturerindex = bios->data[
3610 bios->fp.fpxlatemanufacturertableptr +
3613 /* we're done if this isn't the EDID panel case */
3617 if (chip_version < 0x25) {
3620 * It seems the old style lvds script pointer is reused
3621 * to select 18/24 bit colour depth for EDID panels.
3623 lvdsmanufacturerindex =
3624 (bios->legacy.lvds_single_a_script_ptr & 1) ?
3626 if (pxclk >= bios->fp.duallink_transition_clk)
3627 lvdsmanufacturerindex++;
3628 } else if (chip_version < 0x30) {
3629 /* nv28 behaviour (off-chip encoder)
3631 * nv28 does a complex dance of first using byte 121 of
3632 * the EDID to choose the lvdsmanufacturerindex, then
3633 * later attempting to match the EDID manufacturer and
3634 * product IDs in a table (signature 'pidt' (panel id
3635 * table?)), setting an lvdsmanufacturerindex of 0 and
3636 * an fp strap of the match index (or 0xf if none)
3638 lvdsmanufacturerindex = 0;
3640 /* nv31, nv34 behaviour */
3641 lvdsmanufacturerindex = 0;
3642 if (pxclk >= bios->fp.duallink_transition_clk)
3643 lvdsmanufacturerindex = 2;
3644 if (pxclk >= 140000)
3645 lvdsmanufacturerindex = 3;
3649 * nvidia set the high nibble of (cr57=f, cr58) to
3650 * lvdsmanufacturerindex in this case; we don't
3653 case 0x30: /* NV4x */
3654 case 0x40: /* G80/G90 */
3655 lvdsmanufacturerindex = fpstrapping;
3658 NV_ERROR(dev, "LVDS table revision not currently supported\n");
3662 lvdsofs = bios->fp.xlated_entry = bios->fp.lvdsmanufacturerpointer + lth.headerlen + lth.recordlen * lvdsmanufacturerindex;
3663 switch (lth.lvds_ver) {
3665 bios->fp.power_off_for_reset = bios->data[lvdsofs] & 1;
3666 bios->fp.reset_after_pclk_change = bios->data[lvdsofs] & 2;
3667 bios->fp.dual_link = bios->data[lvdsofs] & 4;
3668 bios->fp.link_c_increment = bios->data[lvdsofs] & 8;
3669 *if_is_24bit = bios->data[lvdsofs] & 16;
3673 * My money would be on there being a 24 bit interface bit in
3674 * this table, but I have no example of a laptop bios with a
3675 * 24 bit panel to confirm that. Hence we shout loudly if any
3676 * bit other than bit 0 is set (I've not even seen bit 1)
3678 if (bios->data[lvdsofs] > 1)
3680 "You have a very unusual laptop display; please report it\n");
3682 * No sign of the "power off for reset" or "reset for panel
3683 * on" bits, but it's safer to assume we should
3685 bios->fp.power_off_for_reset = true;
3686 bios->fp.reset_after_pclk_change = true;
3688 * It's ok lvdsofs is wrong for nv4x edid case; dual_link is
3689 * over-written, and BITbit1 isn't used
3691 bios->fp.dual_link = bios->data[lvdsofs] & 1;
3692 bios->fp.BITbit1 = bios->data[lvdsofs] & 2;
3693 bios->fp.duallink_transition_clk = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 5]) * 10;
3696 bios->fp.dual_link = bios->data[lvdsofs] & 1;
3697 bios->fp.if_is_24bit = bios->data[lvdsofs] & 2;
3698 bios->fp.strapless_is_24bit = bios->data[bios->fp.lvdsmanufacturerpointer + 4];
3699 bios->fp.duallink_transition_clk = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 5]) * 10;
3703 /* set dual_link flag for EDID case */
3704 if (pxclk && (chip_version < 0x25 || chip_version > 0x28))
3705 bios->fp.dual_link = (pxclk >= bios->fp.duallink_transition_clk);
3707 *dl = bios->fp.dual_link;
3713 bios_output_config_match(struct drm_device *dev, struct dcb_entry *dcbent,
3714 uint16_t record, int record_len, int record_nr)
3716 struct drm_nouveau_private *dev_priv = dev->dev_private;
3717 struct nvbios *bios = &dev_priv->VBIOS;
3722 for (i = 0; i < record_nr; i++, record += record_len) {
3723 table = ROM16(bios->data[record]);
3726 entry = ROM32(bios->data[table]);
3728 v = (entry & 0x000f0000) >> 16;
3729 if (!(v & dcbent->or))
3732 v = (entry & 0x000000f0) >> 4;
3733 if (v != dcbent->location)
3736 v = (entry & 0x0000000f);
3737 if (v != dcbent->type)
3740 return &bios->data[table];
3747 nouveau_bios_dp_table(struct drm_device *dev, struct dcb_entry *dcbent,
3750 struct drm_nouveau_private *dev_priv = dev->dev_private;
3751 struct nvbios *bios = &dev_priv->VBIOS;
3754 if (!bios->display.dp_table_ptr) {
3755 NV_ERROR(dev, "No pointer to DisplayPort table\n");
3758 table = &bios->data[bios->display.dp_table_ptr];
3760 if (table[0] != 0x21) {
3761 NV_ERROR(dev, "DisplayPort table version 0x%02x unknown\n",
3767 return bios_output_config_match(dev, dcbent,
3768 bios->display.dp_table_ptr + table[1],
3769 table[2], table[3]);
3773 nouveau_bios_run_display_table(struct drm_device *dev, struct dcb_entry *dcbent,
3774 uint32_t sub, int pxclk)
3777 * The display script table is located by the BIT 'U' table.
3779 * It contains an array of pointers to various tables describing
3780 * a particular output type. The first 32-bits of the output
3781 * tables contains similar information to a DCB entry, and is
3782 * used to decide whether that particular table is suitable for
3783 * the output you want to access.
3785 * The "record header length" field here seems to indicate the
3786 * offset of the first configuration entry in the output tables.
3787 * This is 10 on most cards I've seen, but 12 has been witnessed
3788 * on DP cards, and there's another script pointer within the
3791 * offset + 0 ( 8 bits): version
3792 * offset + 1 ( 8 bits): header length
3793 * offset + 2 ( 8 bits): record length
3794 * offset + 3 ( 8 bits): number of records
3795 * offset + 4 ( 8 bits): record header length
3796 * offset + 5 (16 bits): pointer to first output script table
3799 struct drm_nouveau_private *dev_priv = dev->dev_private;
3800 struct init_exec iexec = {true, false};
3801 struct nvbios *bios = &dev_priv->VBIOS;
3802 uint8_t *table = &bios->data[bios->display.script_table_ptr];
3803 uint8_t *otable = NULL;
3807 if (!bios->display.script_table_ptr) {
3808 NV_ERROR(dev, "No pointer to output script table\n");
3813 * Nothing useful has been in any of the pre-2.0 tables I've seen,
3814 * so until they are, we really don't need to care.
3816 if (table[0] < 0x20)
3819 if (table[0] != 0x20 && table[0] != 0x21) {
3820 NV_ERROR(dev, "Output script table version 0x%02x unknown\n",
3826 * The output script tables describing a particular output type
3829 * offset + 0 (32 bits): output this table matches (hash of DCB)
3830 * offset + 4 ( 8 bits): unknown
3831 * offset + 5 ( 8 bits): number of configurations
3832 * offset + 6 (16 bits): pointer to some script
3833 * offset + 8 (16 bits): pointer to some script
3836 * offset + 10 : configuration 0
3839 * offset + 10 : pointer to some script
3840 * offset + 12 : configuration 0
3842 * Each config entry is as follows:
3844 * offset + 0 (16 bits): unknown, assumed to be a match value
3845 * offset + 2 (16 bits): pointer to script table (clock set?)
3846 * offset + 4 (16 bits): pointer to script table (reset?)
3848 * There doesn't appear to be a count value to say how many
3849 * entries exist in each script table, instead, a 0 value in
3850 * the first 16-bit word seems to indicate both the end of the
3851 * list and the default entry. The second 16-bit word in the
3852 * script tables is a pointer to the script to execute.
3855 NV_DEBUG_KMS(dev, "Searching for output entry for %d %d %d\n",
3856 dcbent->type, dcbent->location, dcbent->or);
3857 otable = bios_output_config_match(dev, dcbent, table[1] +
3858 bios->display.script_table_ptr,
3859 table[2], table[3]);
3861 NV_ERROR(dev, "Couldn't find matching output script table\n");
3865 if (pxclk < -2 || pxclk > 0) {
3866 /* Try to find matching script table entry */
3867 for (i = 0; i < otable[5]; i++) {
3868 if (ROM16(otable[table[4] + i*6]) == sub)
3872 if (i == otable[5]) {
3873 NV_ERROR(dev, "Table 0x%04x not found for %d/%d, "
3875 sub, dcbent->type, dcbent->or);
3880 bios->display.output = dcbent;
3883 script = ROM16(otable[6]);
3885 NV_DEBUG_KMS(dev, "output script 0 not found\n");
3889 NV_TRACE(dev, "0x%04X: parsing output script 0\n", script);
3890 parse_init_table(bios, script, &iexec);
3893 script = ROM16(otable[8]);
3895 NV_DEBUG_KMS(dev, "output script 1 not found\n");
3899 NV_TRACE(dev, "0x%04X: parsing output script 1\n", script);
3900 parse_init_table(bios, script, &iexec);
3904 script = ROM16(otable[10]);
3908 NV_DEBUG_KMS(dev, "output script 2 not found\n");
3912 NV_TRACE(dev, "0x%04X: parsing output script 2\n", script);
3913 parse_init_table(bios, script, &iexec);
3916 script = ROM16(otable[table[4] + i*6 + 2]);
3918 script = clkcmptable(bios, script, pxclk);
3920 NV_ERROR(dev, "clock script 0 not found\n");
3924 NV_TRACE(dev, "0x%04X: parsing clock script 0\n", script);
3925 parse_init_table(bios, script, &iexec);
3928 script = ROM16(otable[table[4] + i*6 + 4]);
3930 script = clkcmptable(bios, script, -pxclk);
3932 NV_DEBUG_KMS(dev, "clock script 1 not found\n");
3936 NV_TRACE(dev, "0x%04X: parsing clock script 1\n", script);
3937 parse_init_table(bios, script, &iexec);
3944 int run_tmds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, int pxclk)
3947 * the pxclk parameter is in kHz
3949 * This runs the TMDS regs setting code found on BIT bios cards
3951 * For ffs(or) == 1 use the first table, for ffs(or) == 2 and
3952 * ffs(or) == 3, use the second.
3955 struct drm_nouveau_private *dev_priv = dev->dev_private;
3956 struct nvbios *bios = &dev_priv->VBIOS;
3957 int cv = bios->pub.chip_version;
3958 uint16_t clktable = 0, scriptptr;
3959 uint32_t sel_clk_binding, sel_clk;
3961 /* pre-nv17 off-chip tmds uses scripts, post nv17 doesn't */
3962 if (cv >= 0x17 && cv != 0x1a && cv != 0x20 &&
3963 dcbent->location != DCB_LOC_ON_CHIP)
3966 switch (ffs(dcbent->or)) {
3968 clktable = bios->tmds.output0_script_ptr;
3972 clktable = bios->tmds.output1_script_ptr;
3977 NV_ERROR(dev, "Pixel clock comparison table not found\n");
3981 scriptptr = clkcmptable(bios, clktable, pxclk);
3984 NV_ERROR(dev, "TMDS output init script not found\n");
3988 /* don't let script change pll->head binding */
3989 sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000;
3990 run_digital_op_script(dev, scriptptr, dcbent, head, pxclk >= 165000);
3991 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000;
3992 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding);
3997 int get_pll_limits(struct drm_device *dev, uint32_t limit_match, struct pll_lims *pll_lim)
4002 * Version 0x10: NV30, NV31
4003 * One byte header (version), one record of 24 bytes
4004 * Version 0x11: NV36 - Not implemented
4005 * Seems to have same record style as 0x10, but 3 records rather than 1
4006 * Version 0x20: Found on Geforce 6 cards
4007 * Trivial 4 byte BIT header. 31 (0x1f) byte record length
4008 * Version 0x21: Found on Geforce 7, 8 and some Geforce 6 cards
4009 * 5 byte header, fifth byte of unknown purpose. 35 (0x23) byte record
4010 * length in general, some (integrated) have an extra configuration byte
4011 * Version 0x30: Found on Geforce 8, separates the register mapping
4012 * from the limits tables.
4015 struct drm_nouveau_private *dev_priv = dev->dev_private;
4016 struct nvbios *bios = &dev_priv->VBIOS;
4017 int cv = bios->pub.chip_version, pllindex = 0;
4018 uint8_t pll_lim_ver = 0, headerlen = 0, recordlen = 0, entries = 0;
4019 uint32_t crystal_strap_mask, crystal_straps;
4021 if (!bios->pll_limit_tbl_ptr) {
4022 if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 ||
4024 NV_ERROR(dev, "Pointer to PLL limits table invalid\n");
4028 pll_lim_ver = bios->data[bios->pll_limit_tbl_ptr];
4030 crystal_strap_mask = 1 << 6;
4031 /* open coded dev->twoHeads test */
4032 if (cv > 0x10 && cv != 0x15 && cv != 0x1a && cv != 0x20)
4033 crystal_strap_mask |= 1 << 22;
4034 crystal_straps = nvReadEXTDEV(dev, NV_PEXTDEV_BOOT_0) &
4037 switch (pll_lim_ver) {
4039 * We use version 0 to indicate a pre limit table bios (single stage
4040 * pll) and load the hard coded limits instead.
4047 * Strictly v0x11 has 3 entries, but the last two don't seem
4059 headerlen = bios->data[bios->pll_limit_tbl_ptr + 1];
4060 recordlen = bios->data[bios->pll_limit_tbl_ptr + 2];
4061 entries = bios->data[bios->pll_limit_tbl_ptr + 3];
4064 NV_ERROR(dev, "PLL limits table revision 0x%X not currently "
4065 "supported\n", pll_lim_ver);
4069 /* initialize all members to zero */
4070 memset(pll_lim, 0, sizeof(struct pll_lims));
4072 if (pll_lim_ver == 0x10 || pll_lim_ver == 0x11) {
4073 uint8_t *pll_rec = &bios->data[bios->pll_limit_tbl_ptr + headerlen + recordlen * pllindex];
4075 pll_lim->vco1.minfreq = ROM32(pll_rec[0]);
4076 pll_lim->vco1.maxfreq = ROM32(pll_rec[4]);
4077 pll_lim->vco2.minfreq = ROM32(pll_rec[8]);
4078 pll_lim->vco2.maxfreq = ROM32(pll_rec[12]);
4079 pll_lim->vco1.min_inputfreq = ROM32(pll_rec[16]);
4080 pll_lim->vco2.min_inputfreq = ROM32(pll_rec[20]);
4081 pll_lim->vco1.max_inputfreq = pll_lim->vco2.max_inputfreq = INT_MAX;
4083 /* these values taken from nv30/31/36 */
4084 pll_lim->vco1.min_n = 0x1;
4086 pll_lim->vco1.min_n = 0x5;
4087 pll_lim->vco1.max_n = 0xff;
4088 pll_lim->vco1.min_m = 0x1;
4089 pll_lim->vco1.max_m = 0xd;
4090 pll_lim->vco2.min_n = 0x4;
4092 * On nv30, 31, 36 (i.e. all cards with two stage PLLs with this
4093 * table version (apart from nv35)), N2 is compared to
4094 * maxN2 (0x46) and 10 * maxM2 (0x4), so set maxN2 to 0x28 and
4097 pll_lim->vco2.max_n = 0x28;
4098 if (cv == 0x30 || cv == 0x35)
4099 /* only 5 bits available for N2 on nv30/35 */
4100 pll_lim->vco2.max_n = 0x1f;
4101 pll_lim->vco2.min_m = 0x1;
4102 pll_lim->vco2.max_m = 0x4;
4103 pll_lim->max_log2p = 0x7;
4104 pll_lim->max_usable_log2p = 0x6;
4105 } else if (pll_lim_ver == 0x20 || pll_lim_ver == 0x21) {
4106 uint16_t plloffs = bios->pll_limit_tbl_ptr + headerlen;
4107 uint32_t reg = 0; /* default match */
4112 * First entry is default match, if nothing better. warn if
4115 if (ROM32(bios->data[plloffs]))
4116 NV_WARN(dev, "Default PLL limit entry has non-zero "
4117 "register field\n");
4119 if (limit_match > MAX_PLL_TYPES)
4120 /* we've been passed a reg as the match */
4122 else /* limit match is a pll type */
4123 for (i = 1; i < entries && !reg; i++) {
4124 uint32_t cmpreg = ROM32(bios->data[plloffs + recordlen * i]);
4126 if (limit_match == NVPLL &&
4127 (cmpreg == NV_PRAMDAC_NVPLL_COEFF || cmpreg == 0x4000))
4129 if (limit_match == MPLL &&
4130 (cmpreg == NV_PRAMDAC_MPLL_COEFF || cmpreg == 0x4020))
4132 if (limit_match == VPLL1 &&
4133 (cmpreg == NV_PRAMDAC_VPLL_COEFF || cmpreg == 0x4010))
4135 if (limit_match == VPLL2 &&
4136 (cmpreg == NV_RAMDAC_VPLL2 || cmpreg == 0x4018))
4140 for (i = 1; i < entries; i++)
4141 if (ROM32(bios->data[plloffs + recordlen * i]) == reg) {
4146 pll_rec = &bios->data[plloffs + recordlen * pllindex];
4148 BIOSLOG(bios, "Loading PLL limits for reg 0x%08x\n",
4149 pllindex ? reg : 0);
4152 * Frequencies are stored in tables in MHz, kHz are more
4153 * useful, so we convert.
4156 /* What output frequencies can each VCO generate? */
4157 pll_lim->vco1.minfreq = ROM16(pll_rec[4]) * 1000;
4158 pll_lim->vco1.maxfreq = ROM16(pll_rec[6]) * 1000;
4159 pll_lim->vco2.minfreq = ROM16(pll_rec[8]) * 1000;
4160 pll_lim->vco2.maxfreq = ROM16(pll_rec[10]) * 1000;
4162 /* What input frequencies they accept (past the m-divider)? */
4163 pll_lim->vco1.min_inputfreq = ROM16(pll_rec[12]) * 1000;
4164 pll_lim->vco2.min_inputfreq = ROM16(pll_rec[14]) * 1000;
4165 pll_lim->vco1.max_inputfreq = ROM16(pll_rec[16]) * 1000;
4166 pll_lim->vco2.max_inputfreq = ROM16(pll_rec[18]) * 1000;
4168 /* What values are accepted as multiplier and divider? */
4169 pll_lim->vco1.min_n = pll_rec[20];
4170 pll_lim->vco1.max_n = pll_rec[21];
4171 pll_lim->vco1.min_m = pll_rec[22];
4172 pll_lim->vco1.max_m = pll_rec[23];
4173 pll_lim->vco2.min_n = pll_rec[24];
4174 pll_lim->vco2.max_n = pll_rec[25];
4175 pll_lim->vco2.min_m = pll_rec[26];
4176 pll_lim->vco2.max_m = pll_rec[27];
4178 pll_lim->max_usable_log2p = pll_lim->max_log2p = pll_rec[29];
4179 if (pll_lim->max_log2p > 0x7)
4180 /* pll decoding in nv_hw.c assumes never > 7 */
4181 NV_WARN(dev, "Max log2 P value greater than 7 (%d)\n",
4182 pll_lim->max_log2p);
4184 pll_lim->max_usable_log2p = 0x6;
4185 pll_lim->log2p_bias = pll_rec[30];
4187 if (recordlen > 0x22)
4188 pll_lim->refclk = ROM32(pll_rec[31]);
4190 if (recordlen > 0x23 && pll_rec[35])
4192 "Bits set in PLL configuration byte (%x)\n",
4195 /* C51 special not seen elsewhere */
4196 if (cv == 0x51 && !pll_lim->refclk) {
4197 uint32_t sel_clk = bios_rd32(bios, NV_PRAMDAC_SEL_CLK);
4199 if (((limit_match == NV_PRAMDAC_VPLL_COEFF || limit_match == VPLL1) && sel_clk & 0x20) ||
4200 ((limit_match == NV_RAMDAC_VPLL2 || limit_match == VPLL2) && sel_clk & 0x80)) {
4201 if (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_CHIP_ID_INDEX) < 0xa3)
4202 pll_lim->refclk = 200000;
4204 pll_lim->refclk = 25000;
4207 } else if (pll_lim_ver == 0x30) { /* ver 0x30 */
4208 uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen];
4209 uint8_t *record = NULL;
4212 BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n",
4215 for (i = 0; i < entries; i++, entry += recordlen) {
4216 if (ROM32(entry[3]) == limit_match) {
4217 record = &bios->data[ROM16(entry[1])];
4223 NV_ERROR(dev, "Register 0x%08x not found in PLL "
4224 "limits table", limit_match);
4228 pll_lim->vco1.minfreq = ROM16(record[0]) * 1000;
4229 pll_lim->vco1.maxfreq = ROM16(record[2]) * 1000;
4230 pll_lim->vco2.minfreq = ROM16(record[4]) * 1000;
4231 pll_lim->vco2.maxfreq = ROM16(record[6]) * 1000;
4232 pll_lim->vco1.min_inputfreq = ROM16(record[8]) * 1000;
4233 pll_lim->vco2.min_inputfreq = ROM16(record[10]) * 1000;
4234 pll_lim->vco1.max_inputfreq = ROM16(record[12]) * 1000;
4235 pll_lim->vco2.max_inputfreq = ROM16(record[14]) * 1000;
4236 pll_lim->vco1.min_n = record[16];
4237 pll_lim->vco1.max_n = record[17];
4238 pll_lim->vco1.min_m = record[18];
4239 pll_lim->vco1.max_m = record[19];
4240 pll_lim->vco2.min_n = record[20];
4241 pll_lim->vco2.max_n = record[21];
4242 pll_lim->vco2.min_m = record[22];
4243 pll_lim->vco2.max_m = record[23];
4244 pll_lim->max_usable_log2p = pll_lim->max_log2p = record[25];
4245 pll_lim->log2p_bias = record[27];
4246 pll_lim->refclk = ROM32(record[28]);
4247 } else if (pll_lim_ver) { /* ver 0x40 */
4248 uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen];
4249 uint8_t *record = NULL;
4252 BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n",
4255 for (i = 0; i < entries; i++, entry += recordlen) {
4256 if (ROM32(entry[3]) == limit_match) {
4257 record = &bios->data[ROM16(entry[1])];
4263 NV_ERROR(dev, "Register 0x%08x not found in PLL "
4264 "limits table", limit_match);
4268 pll_lim->vco1.minfreq = ROM16(record[0]) * 1000;
4269 pll_lim->vco1.maxfreq = ROM16(record[2]) * 1000;
4270 pll_lim->vco1.min_inputfreq = ROM16(record[4]) * 1000;
4271 pll_lim->vco1.max_inputfreq = ROM16(record[6]) * 1000;
4272 pll_lim->vco1.min_m = record[8];
4273 pll_lim->vco1.max_m = record[9];
4274 pll_lim->vco1.min_n = record[10];
4275 pll_lim->vco1.max_n = record[11];
4276 pll_lim->min_p = record[12];
4277 pll_lim->max_p = record[13];
4278 /* where did this go to?? */
4279 if (limit_match == 0x00614100 || limit_match == 0x00614900)
4280 pll_lim->refclk = 27000;
4282 pll_lim->refclk = 100000;
4286 * By now any valid limit table ought to have set a max frequency for
4287 * vco1, so if it's zero it's either a pre limit table bios, or one
4288 * with an empty limit table (seen on nv18)
4290 if (!pll_lim->vco1.maxfreq) {
4291 pll_lim->vco1.minfreq = bios->fminvco;
4292 pll_lim->vco1.maxfreq = bios->fmaxvco;
4293 pll_lim->vco1.min_inputfreq = 0;
4294 pll_lim->vco1.max_inputfreq = INT_MAX;
4295 pll_lim->vco1.min_n = 0x1;
4296 pll_lim->vco1.max_n = 0xff;
4297 pll_lim->vco1.min_m = 0x1;
4298 if (crystal_straps == 0) {
4299 /* nv05 does this, nv11 doesn't, nv10 unknown */
4301 pll_lim->vco1.min_m = 0x7;
4302 pll_lim->vco1.max_m = 0xd;
4305 pll_lim->vco1.min_m = 0x8;
4306 pll_lim->vco1.max_m = 0xe;
4308 if (cv < 0x17 || cv == 0x1a || cv == 0x20)
4309 pll_lim->max_log2p = 4;
4311 pll_lim->max_log2p = 5;
4312 pll_lim->max_usable_log2p = pll_lim->max_log2p;
4315 if (!pll_lim->refclk)
4316 switch (crystal_straps) {
4318 pll_lim->refclk = 13500;
4321 pll_lim->refclk = 14318;
4324 pll_lim->refclk = 27000;
4326 case (1 << 22 | 1 << 6):
4327 pll_lim->refclk = 25000;
4331 #if 0 /* for easy debugging */
4332 ErrorF("pll.vco1.minfreq: %d\n", pll_lim->vco1.minfreq);
4333 ErrorF("pll.vco1.maxfreq: %d\n", pll_lim->vco1.maxfreq);
4334 ErrorF("pll.vco2.minfreq: %d\n", pll_lim->vco2.minfreq);
4335 ErrorF("pll.vco2.maxfreq: %d\n", pll_lim->vco2.maxfreq);
4337 ErrorF("pll.vco1.min_inputfreq: %d\n", pll_lim->vco1.min_inputfreq);
4338 ErrorF("pll.vco1.max_inputfreq: %d\n", pll_lim->vco1.max_inputfreq);
4339 ErrorF("pll.vco2.min_inputfreq: %d\n", pll_lim->vco2.min_inputfreq);
4340 ErrorF("pll.vco2.max_inputfreq: %d\n", pll_lim->vco2.max_inputfreq);
4342 ErrorF("pll.vco1.min_n: %d\n", pll_lim->vco1.min_n);
4343 ErrorF("pll.vco1.max_n: %d\n", pll_lim->vco1.max_n);
4344 ErrorF("pll.vco1.min_m: %d\n", pll_lim->vco1.min_m);
4345 ErrorF("pll.vco1.max_m: %d\n", pll_lim->vco1.max_m);
4346 ErrorF("pll.vco2.min_n: %d\n", pll_lim->vco2.min_n);
4347 ErrorF("pll.vco2.max_n: %d\n", pll_lim->vco2.max_n);
4348 ErrorF("pll.vco2.min_m: %d\n", pll_lim->vco2.min_m);
4349 ErrorF("pll.vco2.max_m: %d\n", pll_lim->vco2.max_m);
4351 ErrorF("pll.max_log2p: %d\n", pll_lim->max_log2p);
4352 ErrorF("pll.log2p_bias: %d\n", pll_lim->log2p_bias);
4354 ErrorF("pll.refclk: %d\n", pll_lim->refclk);
4360 static void parse_bios_version(struct drm_device *dev, struct nvbios *bios, uint16_t offset)
4363 * offset + 0 (8 bits): Micro version
4364 * offset + 1 (8 bits): Minor version
4365 * offset + 2 (8 bits): Chip version
4366 * offset + 3 (8 bits): Major version
4369 bios->major_version = bios->data[offset + 3];
4370 bios->pub.chip_version = bios->data[offset + 2];
4371 NV_TRACE(dev, "Bios version %02x.%02x.%02x.%02x\n",
4372 bios->data[offset + 3], bios->data[offset + 2],
4373 bios->data[offset + 1], bios->data[offset]);
4376 static void parse_script_table_pointers(struct nvbios *bios, uint16_t offset)
4379 * Parses the init table segment for pointers used in script execution.
4381 * offset + 0 (16 bits): init script tables pointer
4382 * offset + 2 (16 bits): macro index table pointer
4383 * offset + 4 (16 bits): macro table pointer
4384 * offset + 6 (16 bits): condition table pointer
4385 * offset + 8 (16 bits): io condition table pointer
4386 * offset + 10 (16 bits): io flag condition table pointer
4387 * offset + 12 (16 bits): init function table pointer
4390 bios->init_script_tbls_ptr = ROM16(bios->data[offset]);
4391 bios->macro_index_tbl_ptr = ROM16(bios->data[offset + 2]);
4392 bios->macro_tbl_ptr = ROM16(bios->data[offset + 4]);
4393 bios->condition_tbl_ptr = ROM16(bios->data[offset + 6]);
4394 bios->io_condition_tbl_ptr = ROM16(bios->data[offset + 8]);
4395 bios->io_flag_condition_tbl_ptr = ROM16(bios->data[offset + 10]);
4396 bios->init_function_tbl_ptr = ROM16(bios->data[offset + 12]);
4399 static int parse_bit_A_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4402 * Parses the load detect values for g80 cards.
4404 * offset + 0 (16 bits): loadval table pointer
4407 uint16_t load_table_ptr;
4408 uint8_t version, headerlen, entrylen, num_entries;
4410 if (bitentry->length != 3) {
4411 NV_ERROR(dev, "Do not understand BIT A table\n");
4415 load_table_ptr = ROM16(bios->data[bitentry->offset]);
4417 if (load_table_ptr == 0x0) {
4418 NV_ERROR(dev, "Pointer to BIT loadval table invalid\n");
4422 version = bios->data[load_table_ptr];
4424 if (version != 0x10) {
4425 NV_ERROR(dev, "BIT loadval table version %d.%d not supported\n",
4426 version >> 4, version & 0xF);
4430 headerlen = bios->data[load_table_ptr + 1];
4431 entrylen = bios->data[load_table_ptr + 2];
4432 num_entries = bios->data[load_table_ptr + 3];
4434 if (headerlen != 4 || entrylen != 4 || num_entries != 2) {
4435 NV_ERROR(dev, "Do not understand BIT loadval table\n");
4439 /* First entry is normal dac, 2nd tv-out perhaps? */
4440 bios->pub.dactestval = ROM32(bios->data[load_table_ptr + headerlen]) & 0x3ff;
4445 static int parse_bit_C_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4448 * offset + 8 (16 bits): PLL limits table pointer
4450 * There's more in here, but that's unknown.
4453 if (bitentry->length < 10) {
4454 NV_ERROR(dev, "Do not understand BIT C table\n");
4458 bios->pll_limit_tbl_ptr = ROM16(bios->data[bitentry->offset + 8]);
4463 static int parse_bit_display_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4466 * Parses the flat panel table segment that the bit entry points to.
4467 * Starting at bitentry->offset:
4469 * offset + 0 (16 bits): ??? table pointer - seems to have 18 byte
4470 * records beginning with a freq.
4471 * offset + 2 (16 bits): mode table pointer
4474 if (bitentry->length != 4) {
4475 NV_ERROR(dev, "Do not understand BIT display table\n");
4479 bios->fp.fptablepointer = ROM16(bios->data[bitentry->offset + 2]);
4484 static int parse_bit_init_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4487 * Parses the init table segment that the bit entry points to.
4489 * See parse_script_table_pointers for layout
4492 if (bitentry->length < 14) {
4493 NV_ERROR(dev, "Do not understand init table\n");
4497 parse_script_table_pointers(bios, bitentry->offset);
4499 if (bitentry->length >= 16)
4500 bios->some_script_ptr = ROM16(bios->data[bitentry->offset + 14]);
4501 if (bitentry->length >= 18)
4502 bios->init96_tbl_ptr = ROM16(bios->data[bitentry->offset + 16]);
4507 static int parse_bit_i_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4510 * BIT 'i' (info?) table
4512 * offset + 0 (32 bits): BIOS version dword (as in B table)
4513 * offset + 5 (8 bits): BIOS feature byte (same as for BMP?)
4514 * offset + 13 (16 bits): pointer to table containing DAC load
4515 * detection comparison values
4517 * There's other things in the table, purpose unknown
4520 uint16_t daccmpoffset;
4521 uint8_t dacver, dacheaderlen;
4523 if (bitentry->length < 6) {
4524 NV_ERROR(dev, "BIT i table too short for needed information\n");
4528 parse_bios_version(dev, bios, bitentry->offset);
4531 * bit 4 seems to indicate a mobile bios (doesn't suffer from BMP's
4532 * Quadro identity crisis), other bits possibly as for BMP feature byte
4534 bios->feature_byte = bios->data[bitentry->offset + 5];
4535 bios->is_mobile = bios->feature_byte & FEATURE_MOBILE;
4537 if (bitentry->length < 15) {
4538 NV_WARN(dev, "BIT i table not long enough for DAC load "
4539 "detection comparison table\n");
4543 daccmpoffset = ROM16(bios->data[bitentry->offset + 13]);
4545 /* doesn't exist on g80 */
4550 * The first value in the table, following the header, is the
4551 * comparison value, the second entry is a comparison value for
4552 * TV load detection.
4555 dacver = bios->data[daccmpoffset];
4556 dacheaderlen = bios->data[daccmpoffset + 1];
4558 if (dacver != 0x00 && dacver != 0x10) {
4559 NV_WARN(dev, "DAC load detection comparison table version "
4560 "%d.%d not known\n", dacver >> 4, dacver & 0xf);
4564 bios->pub.dactestval = ROM32(bios->data[daccmpoffset + dacheaderlen]);
4565 bios->pub.tvdactestval = ROM32(bios->data[daccmpoffset + dacheaderlen + 4]);
4570 static int parse_bit_lvds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4573 * Parses the LVDS table segment that the bit entry points to.
4574 * Starting at bitentry->offset:
4576 * offset + 0 (16 bits): LVDS strap xlate table pointer
4579 if (bitentry->length != 2) {
4580 NV_ERROR(dev, "Do not understand BIT LVDS table\n");
4585 * No idea if it's still called the LVDS manufacturer table, but
4586 * the concept's close enough.
4588 bios->fp.lvdsmanufacturerpointer = ROM16(bios->data[bitentry->offset]);
4594 parse_bit_M_tbl_entry(struct drm_device *dev, struct nvbios *bios,
4595 struct bit_entry *bitentry)
4598 * offset + 2 (8 bits): number of options in an
4599 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode option set
4600 * offset + 3 (16 bits): pointer to strap xlate table for RAM
4601 * restrict option selection
4603 * There's a bunch of bits in this table other than the RAM restrict
4604 * stuff that we don't use - their use currently unknown
4608 * Older bios versions don't have a sufficiently long table for
4611 if (bitentry->length < 0x5)
4614 if (bitentry->id[1] < 2) {
4615 bios->ram_restrict_group_count = bios->data[bitentry->offset + 2];
4616 bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 3]);
4618 bios->ram_restrict_group_count = bios->data[bitentry->offset + 0];
4619 bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 1]);
4625 static int parse_bit_tmds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4628 * Parses the pointer to the TMDS table
4630 * Starting at bitentry->offset:
4632 * offset + 0 (16 bits): TMDS table pointer
4634 * The TMDS table is typically found just before the DCB table, with a
4635 * characteristic signature of 0x11,0x13 (1.1 being version, 0x13 being
4638 * At offset +7 is a pointer to a script, which I don't know how to
4640 * At offset +9 is a pointer to another script, likewise
4641 * Offset +11 has a pointer to a table where the first word is a pxclk
4642 * frequency and the second word a pointer to a script, which should be
4643 * run if the comparison pxclk frequency is less than the pxclk desired.
4644 * This repeats for decreasing comparison frequencies
4645 * Offset +13 has a pointer to a similar table
4646 * The selection of table (and possibly +7/+9 script) is dictated by
4647 * "or" from the DCB.
4650 uint16_t tmdstableptr, script1, script2;
4652 if (bitentry->length != 2) {
4653 NV_ERROR(dev, "Do not understand BIT TMDS table\n");
4657 tmdstableptr = ROM16(bios->data[bitentry->offset]);
4659 if (tmdstableptr == 0x0) {
4660 NV_ERROR(dev, "Pointer to TMDS table invalid\n");
4664 /* nv50+ has v2.0, but we don't parse it atm */
4665 if (bios->data[tmdstableptr] != 0x11) {
4667 "TMDS table revision %d.%d not currently supported\n",
4668 bios->data[tmdstableptr] >> 4, bios->data[tmdstableptr] & 0xf);
4673 * These two scripts are odd: they don't seem to get run even when
4674 * they are not stubbed.
4676 script1 = ROM16(bios->data[tmdstableptr + 7]);
4677 script2 = ROM16(bios->data[tmdstableptr + 9]);
4678 if (bios->data[script1] != 'q' || bios->data[script2] != 'q')
4679 NV_WARN(dev, "TMDS table script pointers not stubbed\n");
4681 bios->tmds.output0_script_ptr = ROM16(bios->data[tmdstableptr + 11]);
4682 bios->tmds.output1_script_ptr = ROM16(bios->data[tmdstableptr + 13]);
4688 parse_bit_U_tbl_entry(struct drm_device *dev, struct nvbios *bios,
4689 struct bit_entry *bitentry)
4692 * Parses the pointer to the G80 output script tables
4694 * Starting at bitentry->offset:
4696 * offset + 0 (16 bits): output script table pointer
4699 uint16_t outputscripttableptr;
4701 if (bitentry->length != 3) {
4702 NV_ERROR(dev, "Do not understand BIT U table\n");
4706 outputscripttableptr = ROM16(bios->data[bitentry->offset]);
4707 bios->display.script_table_ptr = outputscripttableptr;
4712 parse_bit_displayport_tbl_entry(struct drm_device *dev, struct nvbios *bios,
4713 struct bit_entry *bitentry)
4715 bios->display.dp_table_ptr = ROM16(bios->data[bitentry->offset]);
4721 int (* const parse_fn)(struct drm_device *, struct nvbios *, struct bit_entry *);
4724 #define BIT_TABLE(id, funcid) ((struct bit_table){ id, parse_bit_##funcid##_tbl_entry })
4727 parse_bit_table(struct nvbios *bios, const uint16_t bitoffset,
4728 struct bit_table *table)
4730 struct drm_device *dev = bios->dev;
4731 uint8_t maxentries = bios->data[bitoffset + 4];
4733 struct bit_entry bitentry;
4735 for (i = 0, offset = bitoffset + 6; i < maxentries; i++, offset += 6) {
4736 bitentry.id[0] = bios->data[offset];
4738 if (bitentry.id[0] != table->id)
4741 bitentry.id[1] = bios->data[offset + 1];
4742 bitentry.length = ROM16(bios->data[offset + 2]);
4743 bitentry.offset = ROM16(bios->data[offset + 4]);
4745 return table->parse_fn(dev, bios, &bitentry);
4748 NV_INFO(dev, "BIT table '%c' not found\n", table->id);
4753 parse_bit_structure(struct nvbios *bios, const uint16_t bitoffset)
4758 * The only restriction on parsing order currently is having 'i' first
4759 * for use of bios->*_version or bios->feature_byte while parsing;
4760 * functions shouldn't be actually *doing* anything apart from pulling
4761 * data from the image into the bios struct, thus no interdependencies
4763 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('i', i));
4764 if (ret) /* info? */
4766 if (bios->major_version >= 0x60) /* g80+ */
4767 parse_bit_table(bios, bitoffset, &BIT_TABLE('A', A));
4768 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('C', C));
4771 parse_bit_table(bios, bitoffset, &BIT_TABLE('D', display));
4772 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('I', init));
4775 parse_bit_table(bios, bitoffset, &BIT_TABLE('M', M)); /* memory? */
4776 parse_bit_table(bios, bitoffset, &BIT_TABLE('L', lvds));
4777 parse_bit_table(bios, bitoffset, &BIT_TABLE('T', tmds));
4778 parse_bit_table(bios, bitoffset, &BIT_TABLE('U', U));
4779 parse_bit_table(bios, bitoffset, &BIT_TABLE('d', displayport));
4784 static int parse_bmp_structure(struct drm_device *dev, struct nvbios *bios, unsigned int offset)
4787 * Parses the BMP structure for useful things, but does not act on them
4789 * offset + 5: BMP major version
4790 * offset + 6: BMP minor version
4791 * offset + 9: BMP feature byte
4792 * offset + 10: BCD encoded BIOS version
4794 * offset + 18: init script table pointer (for bios versions < 5.10h)
4795 * offset + 20: extra init script table pointer (for bios
4798 * offset + 24: memory init table pointer (used on early bios versions)
4799 * offset + 26: SDR memory sequencing setup data table
4800 * offset + 28: DDR memory sequencing setup data table
4802 * offset + 54: index of I2C CRTC pair to use for CRT output
4803 * offset + 55: index of I2C CRTC pair to use for TV output
4804 * offset + 56: index of I2C CRTC pair to use for flat panel output
4805 * offset + 58: write CRTC index for I2C pair 0
4806 * offset + 59: read CRTC index for I2C pair 0
4807 * offset + 60: write CRTC index for I2C pair 1
4808 * offset + 61: read CRTC index for I2C pair 1
4810 * offset + 67: maximum internal PLL frequency (single stage PLL)
4811 * offset + 71: minimum internal PLL frequency (single stage PLL)
4813 * offset + 75: script table pointers, as described in
4814 * parse_script_table_pointers
4816 * offset + 89: TMDS single link output A table pointer
4817 * offset + 91: TMDS single link output B table pointer
4818 * offset + 95: LVDS single link output A table pointer
4819 * offset + 105: flat panel timings table pointer
4820 * offset + 107: flat panel strapping translation table pointer
4821 * offset + 117: LVDS manufacturer panel config table pointer
4822 * offset + 119: LVDS manufacturer strapping translation table pointer
4824 * offset + 142: PLL limits table pointer
4826 * offset + 156: minimum pixel clock for LVDS dual link
4829 uint8_t *bmp = &bios->data[offset], bmp_version_major, bmp_version_minor;
4831 uint16_t legacy_scripts_offset, legacy_i2c_offset;
4833 /* load needed defaults in case we can't parse this info */
4834 bios->bdcb.dcb.i2c[0].write = NV_CIO_CRE_DDC_WR__INDEX;
4835 bios->bdcb.dcb.i2c[0].read = NV_CIO_CRE_DDC_STATUS__INDEX;
4836 bios->bdcb.dcb.i2c[1].write = NV_CIO_CRE_DDC0_WR__INDEX;
4837 bios->bdcb.dcb.i2c[1].read = NV_CIO_CRE_DDC0_STATUS__INDEX;
4838 bios->pub.digital_min_front_porch = 0x4b;
4839 bios->fmaxvco = 256000;
4840 bios->fminvco = 128000;
4841 bios->fp.duallink_transition_clk = 90000;
4843 bmp_version_major = bmp[5];
4844 bmp_version_minor = bmp[6];
4846 NV_TRACE(dev, "BMP version %d.%d\n",
4847 bmp_version_major, bmp_version_minor);
4850 * Make sure that 0x36 is blank and can't be mistaken for a DCB
4851 * pointer on early versions
4853 if (bmp_version_major < 5)
4854 *(uint16_t *)&bios->data[0x36] = 0;
4857 * Seems that the minor version was 1 for all major versions prior
4858 * to 5. Version 6 could theoretically exist, but I suspect BIT
4861 if ((bmp_version_major < 5 && bmp_version_minor != 1) || bmp_version_major > 5) {
4862 NV_ERROR(dev, "You have an unsupported BMP version. "
4863 "Please send in your bios\n");
4867 if (bmp_version_major == 0)
4868 /* nothing that's currently useful in this version */
4870 else if (bmp_version_major == 1)
4871 bmplength = 44; /* exact for 1.01 */
4872 else if (bmp_version_major == 2)
4873 bmplength = 48; /* exact for 2.01 */
4874 else if (bmp_version_major == 3)
4876 /* guessed - mem init tables added in this version */
4877 else if (bmp_version_major == 4 || bmp_version_minor < 0x1)
4878 /* don't know if 5.0 exists... */
4880 /* guessed - BMP I2C indices added in version 4*/
4881 else if (bmp_version_minor < 0x6)
4882 bmplength = 67; /* exact for 5.01 */
4883 else if (bmp_version_minor < 0x10)
4884 bmplength = 75; /* exact for 5.06 */
4885 else if (bmp_version_minor == 0x10)
4886 bmplength = 89; /* exact for 5.10h */
4887 else if (bmp_version_minor < 0x14)
4888 bmplength = 118; /* exact for 5.11h */
4889 else if (bmp_version_minor < 0x24)
4891 * Not sure of version where pll limits came in;
4892 * certainly exist by 0x24 though.
4894 /* length not exact: this is long enough to get lvds members */
4896 else if (bmp_version_minor < 0x27)
4898 * Length not exact: this is long enough to get pll limit
4904 * Length not exact: this is long enough to get dual link
4910 if (nv_cksum(bmp, 8)) {
4911 NV_ERROR(dev, "Bad BMP checksum\n");
4916 * Bit 4 seems to indicate either a mobile bios or a quadro card --
4917 * mobile behaviour consistent (nv11+), quadro only seen nv18gl-nv36gl
4918 * (not nv10gl), bit 5 that the flat panel tables are present, and
4921 bios->feature_byte = bmp[9];
4923 parse_bios_version(dev, bios, offset + 10);
4925 if (bmp_version_major < 5 || bmp_version_minor < 0x10)
4926 bios->old_style_init = true;
4927 legacy_scripts_offset = 18;
4928 if (bmp_version_major < 2)
4929 legacy_scripts_offset -= 4;
4930 bios->init_script_tbls_ptr = ROM16(bmp[legacy_scripts_offset]);
4931 bios->extra_init_script_tbl_ptr = ROM16(bmp[legacy_scripts_offset + 2]);
4933 if (bmp_version_major > 2) { /* appears in BMP 3 */
4934 bios->legacy.mem_init_tbl_ptr = ROM16(bmp[24]);
4935 bios->legacy.sdr_seq_tbl_ptr = ROM16(bmp[26]);
4936 bios->legacy.ddr_seq_tbl_ptr = ROM16(bmp[28]);
4939 legacy_i2c_offset = 0x48; /* BMP version 2 & 3 */
4941 legacy_i2c_offset = offset + 54;
4942 bios->legacy.i2c_indices.crt = bios->data[legacy_i2c_offset];
4943 bios->legacy.i2c_indices.tv = bios->data[legacy_i2c_offset + 1];
4944 bios->legacy.i2c_indices.panel = bios->data[legacy_i2c_offset + 2];
4945 bios->bdcb.dcb.i2c[0].write = bios->data[legacy_i2c_offset + 4];
4946 bios->bdcb.dcb.i2c[0].read = bios->data[legacy_i2c_offset + 5];
4947 bios->bdcb.dcb.i2c[1].write = bios->data[legacy_i2c_offset + 6];
4948 bios->bdcb.dcb.i2c[1].read = bios->data[legacy_i2c_offset + 7];
4950 if (bmplength > 74) {
4951 bios->fmaxvco = ROM32(bmp[67]);
4952 bios->fminvco = ROM32(bmp[71]);
4955 parse_script_table_pointers(bios, offset + 75);
4956 if (bmplength > 94) {
4957 bios->tmds.output0_script_ptr = ROM16(bmp[89]);
4958 bios->tmds.output1_script_ptr = ROM16(bmp[91]);
4960 * Never observed in use with lvds scripts, but is reused for
4961 * 18/24 bit panel interface default for EDID equipped panels
4962 * (if_is_24bit not set directly to avoid any oscillation).
4964 bios->legacy.lvds_single_a_script_ptr = ROM16(bmp[95]);
4966 if (bmplength > 108) {
4967 bios->fp.fptablepointer = ROM16(bmp[105]);
4968 bios->fp.fpxlatetableptr = ROM16(bmp[107]);
4969 bios->fp.xlatwidth = 1;
4971 if (bmplength > 120) {
4972 bios->fp.lvdsmanufacturerpointer = ROM16(bmp[117]);
4973 bios->fp.fpxlatemanufacturertableptr = ROM16(bmp[119]);
4975 if (bmplength > 143)
4976 bios->pll_limit_tbl_ptr = ROM16(bmp[142]);
4978 if (bmplength > 157)
4979 bios->fp.duallink_transition_clk = ROM16(bmp[156]) * 10;
4984 static uint16_t findstr(uint8_t *data, int n, const uint8_t *str, int len)
4988 for (i = 0; i <= (n - len); i++) {
4989 for (j = 0; j < len; j++)
4990 if (data[i + j] != str[j])
5000 read_dcb_i2c_entry(struct drm_device *dev, int dcb_version, uint8_t *i2ctable, int index, struct dcb_i2c_entry *i2c)
5002 uint8_t dcb_i2c_ver = dcb_version, headerlen = 0, entry_len = 4;
5003 int i2c_entries = DCB_MAX_NUM_I2C_ENTRIES;
5004 int recordoffset = 0, rdofs = 1, wrofs = 0;
5005 uint8_t port_type = 0;
5010 if (dcb_version >= 0x30) {
5011 if (i2ctable[0] != dcb_version) /* necessary? */
5013 "DCB I2C table version mismatch (%02X vs %02X)\n",
5014 i2ctable[0], dcb_version);
5015 dcb_i2c_ver = i2ctable[0];
5016 headerlen = i2ctable[1];
5017 if (i2ctable[2] <= DCB_MAX_NUM_I2C_ENTRIES)
5018 i2c_entries = i2ctable[2];
5021 "DCB I2C table has more entries than indexable "
5022 "(%d entries, max index 15)\n", i2ctable[2]);
5023 entry_len = i2ctable[3];
5024 /* [4] is i2c_default_indices, read in parse_dcb_table() */
5027 * It's your own fault if you call this function on a DCB 1.1 BIOS --
5028 * the test below is for DCB 1.2
5030 if (dcb_version < 0x14) {
5038 if (index > i2c_entries) {
5039 NV_ERROR(dev, "DCB I2C index too big (%d > %d)\n",
5040 index, i2ctable[2]);
5043 if (i2ctable[headerlen + entry_len * index + 3] == 0xff) {
5044 NV_ERROR(dev, "DCB I2C entry invalid\n");
5048 if (dcb_i2c_ver >= 0x30) {
5049 port_type = i2ctable[headerlen + recordoffset + 3 + entry_len * index];
5052 * Fixup for chips using same address offset for read and
5055 if (port_type == 4) /* seen on C51 */
5057 if (port_type >= 5) /* G80+ */
5061 if (dcb_i2c_ver >= 0x40 && port_type != 5 && port_type != 6)
5062 NV_WARN(dev, "DCB I2C table has port type %d\n", port_type);
5064 i2c->port_type = port_type;
5065 i2c->read = i2ctable[headerlen + recordoffset + rdofs + entry_len * index];
5066 i2c->write = i2ctable[headerlen + recordoffset + wrofs + entry_len * index];
5071 static struct dcb_gpio_entry *
5072 new_gpio_entry(struct nvbios *bios)
5074 struct parsed_dcb_gpio *gpio = &bios->bdcb.gpio;
5076 return &gpio->entry[gpio->entries++];
5079 struct dcb_gpio_entry *
5080 nouveau_bios_gpio_entry(struct drm_device *dev, enum dcb_gpio_tag tag)
5082 struct drm_nouveau_private *dev_priv = dev->dev_private;
5083 struct nvbios *bios = &dev_priv->VBIOS;
5086 for (i = 0; i < bios->bdcb.gpio.entries; i++) {
5087 if (bios->bdcb.gpio.entry[i].tag != tag)
5090 return &bios->bdcb.gpio.entry[i];
5097 parse_dcb30_gpio_entry(struct nvbios *bios, uint16_t offset)
5099 struct dcb_gpio_entry *gpio;
5100 uint16_t ent = ROM16(bios->data[offset]);
5101 uint8_t line = ent & 0x1f,
5102 tag = ent >> 5 & 0x3f,
5103 flags = ent >> 11 & 0x1f;
5108 gpio = new_gpio_entry(bios);
5112 gpio->invert = flags != 4;
5116 parse_dcb40_gpio_entry(struct nvbios *bios, uint16_t offset)
5118 struct dcb_gpio_entry *gpio;
5119 uint32_t ent = ROM32(bios->data[offset]);
5120 uint8_t line = ent & 0x1f,
5121 tag = ent >> 8 & 0xff;
5126 gpio = new_gpio_entry(bios);
5128 /* Currently unused, we may need more fields parsed at some
5135 parse_dcb_gpio_table(struct nvbios *bios)
5137 struct drm_device *dev = bios->dev;
5138 uint16_t gpio_table_ptr = bios->bdcb.gpio_table_ptr;
5139 uint8_t *gpio_table = &bios->data[gpio_table_ptr];
5140 int header_len = gpio_table[1],
5141 entries = gpio_table[2],
5142 entry_len = gpio_table[3];
5143 void (*parse_entry)(struct nvbios *, uint16_t) = NULL;
5146 if (bios->bdcb.version >= 0x40) {
5147 if (gpio_table_ptr && entry_len != 4) {
5148 NV_WARN(dev, "Invalid DCB GPIO table entry length.\n");
5152 parse_entry = parse_dcb40_gpio_entry;
5154 } else if (bios->bdcb.version >= 0x30) {
5155 if (gpio_table_ptr && entry_len != 2) {
5156 NV_WARN(dev, "Invalid DCB GPIO table entry length.\n");
5160 parse_entry = parse_dcb30_gpio_entry;
5162 } else if (bios->bdcb.version >= 0x22) {
5164 * DCBs older than v3.0 don't really have a GPIO
5165 * table, instead they keep some GPIO info at fixed
5168 uint16_t dcbptr = ROM16(bios->data[0x36]);
5169 uint8_t *tvdac_gpio = &bios->data[dcbptr - 5];
5171 if (tvdac_gpio[0] & 1) {
5172 struct dcb_gpio_entry *gpio = new_gpio_entry(bios);
5174 gpio->tag = DCB_GPIO_TVDAC0;
5175 gpio->line = tvdac_gpio[1] >> 4;
5176 gpio->invert = tvdac_gpio[0] & 2;
5180 if (!gpio_table_ptr)
5183 if (entries > DCB_MAX_NUM_GPIO_ENTRIES) {
5184 NV_WARN(dev, "Too many entries in the DCB GPIO table.\n");
5185 entries = DCB_MAX_NUM_GPIO_ENTRIES;
5188 for (i = 0; i < entries; i++)
5189 parse_entry(bios, gpio_table_ptr + header_len + entry_len * i);
5192 struct dcb_connector_table_entry *
5193 nouveau_bios_connector_entry(struct drm_device *dev, int index)
5195 struct drm_nouveau_private *dev_priv = dev->dev_private;
5196 struct nvbios *bios = &dev_priv->VBIOS;
5197 struct dcb_connector_table_entry *cte;
5199 if (index >= bios->bdcb.connector.entries)
5202 cte = &bios->bdcb.connector.entry[index];
5203 if (cte->type == 0xff)
5210 parse_dcb_connector_table(struct nvbios *bios)
5212 struct drm_device *dev = bios->dev;
5213 struct dcb_connector_table *ct = &bios->bdcb.connector;
5214 struct dcb_connector_table_entry *cte;
5215 uint8_t *conntab = &bios->data[bios->bdcb.connector_table_ptr];
5219 if (!bios->bdcb.connector_table_ptr) {
5220 NV_DEBUG_KMS(dev, "No DCB connector table present\n");
5224 NV_INFO(dev, "DCB connector table: VHER 0x%02x %d %d %d\n",
5225 conntab[0], conntab[1], conntab[2], conntab[3]);
5226 if ((conntab[0] != 0x30 && conntab[0] != 0x40) ||
5227 (conntab[3] != 2 && conntab[3] != 4)) {
5228 NV_ERROR(dev, " Unknown! Please report.\n");
5232 ct->entries = conntab[2];
5234 entry = conntab + conntab[1];
5235 cte = &ct->entry[0];
5236 for (i = 0; i < conntab[2]; i++, entry += conntab[3], cte++) {
5237 if (conntab[3] == 2)
5238 cte->entry = ROM16(entry[0]);
5240 cte->entry = ROM32(entry[0]);
5241 cte->type = (cte->entry & 0x000000ff) >> 0;
5242 cte->index = (cte->entry & 0x00000f00) >> 8;
5243 switch (cte->entry & 0x00033000) {
5245 cte->gpio_tag = 0x07;
5248 cte->gpio_tag = 0x08;
5251 cte->gpio_tag = 0x51;
5254 cte->gpio_tag = 0x52;
5257 cte->gpio_tag = 0xff;
5261 if (cte->type == 0xff)
5264 NV_INFO(dev, " %d: 0x%08x: type 0x%02x idx %d tag 0x%02x\n",
5265 i, cte->entry, cte->type, cte->index, cte->gpio_tag);
5269 static struct dcb_entry *new_dcb_entry(struct parsed_dcb *dcb)
5271 struct dcb_entry *entry = &dcb->entry[dcb->entries];
5273 memset(entry, 0, sizeof(struct dcb_entry));
5274 entry->index = dcb->entries++;
5279 static void fabricate_vga_output(struct parsed_dcb *dcb, int i2c, int heads)
5281 struct dcb_entry *entry = new_dcb_entry(dcb);
5284 entry->i2c_index = i2c;
5285 entry->heads = heads;
5286 entry->location = DCB_LOC_ON_CHIP;
5287 /* "or" mostly unused in early gen crt modesetting, 0 is fine */
5290 static void fabricate_dvi_i_output(struct parsed_dcb *dcb, bool twoHeads)
5292 struct dcb_entry *entry = new_dcb_entry(dcb);
5295 entry->i2c_index = LEGACY_I2C_PANEL;
5296 entry->heads = twoHeads ? 3 : 1;
5297 entry->location = !DCB_LOC_ON_CHIP; /* ie OFF CHIP */
5298 entry->or = 1; /* means |0x10 gets set on CRE_LCD__INDEX */
5299 entry->duallink_possible = false; /* SiI164 and co. are single link */
5303 * For dvi-a either crtc probably works, but my card appears to only
5304 * support dvi-d. "nvidia" still attempts to program it for dvi-a,
5305 * doing the full fp output setup (program 0x6808.. fp dimension regs,
5306 * setting 0x680848 to 0x10000111 to enable, maybe setting 0x680880);
5307 * the monitor picks up the mode res ok and lights up, but no pixel
5308 * data appears, so the board manufacturer probably connected up the
5309 * sync lines, but missed the video traces / components
5311 * with this introduction, dvi-a left as an exercise for the reader.
5313 fabricate_vga_output(dcb, LEGACY_I2C_PANEL, entry->heads);
5317 static void fabricate_tv_output(struct parsed_dcb *dcb, bool twoHeads)
5319 struct dcb_entry *entry = new_dcb_entry(dcb);
5322 entry->i2c_index = LEGACY_I2C_TV;
5323 entry->heads = twoHeads ? 3 : 1;
5324 entry->location = !DCB_LOC_ON_CHIP; /* ie OFF CHIP */
5328 parse_dcb20_entry(struct drm_device *dev, struct bios_parsed_dcb *bdcb,
5329 uint32_t conn, uint32_t conf, struct dcb_entry *entry)
5331 entry->type = conn & 0xf;
5332 entry->i2c_index = (conn >> 4) & 0xf;
5333 entry->heads = (conn >> 8) & 0xf;
5334 if (bdcb->version >= 0x40)
5335 entry->connector = (conn >> 12) & 0xf;
5336 entry->bus = (conn >> 16) & 0xf;
5337 entry->location = (conn >> 20) & 0x3;
5338 entry->or = (conn >> 24) & 0xf;
5340 * Normal entries consist of a single bit, but dual link has the
5341 * next most significant bit set too
5343 entry->duallink_possible =
5344 ((1 << (ffs(entry->or) - 1)) * 3 == entry->or);
5346 switch (entry->type) {
5349 * Although the rest of a CRT conf dword is usually
5350 * zeros, mac biosen have stuff there so we must mask
5352 entry->crtconf.maxfreq = (bdcb->version < 0x30) ?
5353 (conf & 0xffff) * 10 :
5354 (conf & 0xff) * 10000;
5360 entry->lvdsconf.use_straps_for_mode = true;
5361 if (bdcb->version < 0x22) {
5364 * The laptop in bug 14567 lies and claims to not use
5365 * straps when it does, so assume all DCB 2.0 laptops
5366 * use straps, until a broken EDID using one is produced
5368 entry->lvdsconf.use_straps_for_mode = true;
5370 * Both 0x4 and 0x8 show up in v2.0 tables; assume they
5371 * mean the same thing (probably wrong, but might work)
5373 if (conf & 0x4 || conf & 0x8)
5374 entry->lvdsconf.use_power_scripts = true;
5378 entry->lvdsconf.use_power_scripts = true;
5382 * Until we even try to use these on G8x, it's
5383 * useless reporting unknown bits. They all are.
5385 if (bdcb->version >= 0x40)
5388 NV_ERROR(dev, "Unknown LVDS configuration bits, "
5395 if (bdcb->version >= 0x30)
5396 entry->tvconf.has_component_output = conf & (0x8 << 4);
5398 entry->tvconf.has_component_output = false;
5403 entry->dpconf.sor.link = (conf & 0x00000030) >> 4;
5404 entry->dpconf.link_bw = (conf & 0x00e00000) >> 21;
5405 switch ((conf & 0x0f000000) >> 24) {
5407 entry->dpconf.link_nr = 4;
5410 entry->dpconf.link_nr = 2;
5413 entry->dpconf.link_nr = 1;
5418 entry->tmdsconf.sor.link = (conf & 0x00000030) >> 4;
5421 /* weird g80 mobile type that "nv" treats as a terminator */
5422 bdcb->dcb.entries--;
5426 /* unsure what DCB version introduces this, 3.0? */
5427 if (conf & 0x100000)
5428 entry->i2c_upper_default = true;
5434 parse_dcb15_entry(struct drm_device *dev, struct parsed_dcb *dcb,
5435 uint32_t conn, uint32_t conf, struct dcb_entry *entry)
5437 if (conn != 0xf0003f00 && conn != 0xf2247f10 && conn != 0xf2204001 &&
5438 conn != 0xf2204301 && conn != 0xf2204311 && conn != 0xf2208001 &&
5439 conn != 0xf2244001 && conn != 0xf2244301 && conn != 0xf2244311 &&
5440 conn != 0xf4204011 && conn != 0xf4208011 && conn != 0xf4248011 &&
5441 conn != 0xf2045ff2 && conn != 0xf2045f14 && conn != 0xf207df14 &&
5442 conn != 0xf2205004 && conn != 0xf2209004) {
5443 NV_ERROR(dev, "Unknown DCB 1.5 entry, please report\n");
5445 /* cause output setting to fail for !TV, so message is seen */
5446 if ((conn & 0xf) != 0x1)
5451 /* most of the below is a "best guess" atm */
5452 entry->type = conn & 0xf;
5453 if (entry->type == 2)
5454 /* another way of specifying straps based lvds... */
5455 entry->type = OUTPUT_LVDS;
5456 if (entry->type == 4) { /* digital */
5458 entry->type = OUTPUT_LVDS;
5460 entry->type = OUTPUT_TMDS;
5462 /* what's in bits 5-13? could be some encoder maker thing, in tv case */
5463 entry->i2c_index = (conn >> 14) & 0xf;
5464 /* raw heads field is in range 0-1, so move to 1-2 */
5465 entry->heads = ((conn >> 18) & 0x7) + 1;
5466 entry->location = (conn >> 21) & 0xf;
5467 /* unused: entry->bus = (conn >> 25) & 0x7; */
5468 /* set or to be same as heads -- hopefully safe enough */
5469 entry->or = entry->heads;
5470 entry->duallink_possible = false;
5472 switch (entry->type) {
5474 entry->crtconf.maxfreq = (conf & 0xffff) * 10;
5478 * This is probably buried in conn's unknown bits.
5479 * This will upset EDID-ful models, if they exist
5481 entry->lvdsconf.use_straps_for_mode = true;
5482 entry->lvdsconf.use_power_scripts = true;
5486 * Invent a DVI-A output, by copying the fields of the DVI-D
5487 * output; reported to work by math_b on an NV20(!).
5489 fabricate_vga_output(dcb, entry->i2c_index, entry->heads);
5492 entry->tvconf.has_component_output = false;
5499 static bool parse_dcb_entry(struct drm_device *dev, struct bios_parsed_dcb *bdcb,
5500 uint32_t conn, uint32_t conf)
5502 struct dcb_entry *entry = new_dcb_entry(&bdcb->dcb);
5505 if (bdcb->version >= 0x20)
5506 ret = parse_dcb20_entry(dev, bdcb, conn, conf, entry);
5508 ret = parse_dcb15_entry(dev, &bdcb->dcb, conn, conf, entry);
5512 read_dcb_i2c_entry(dev, bdcb->version, bdcb->i2c_table,
5513 entry->i2c_index, &bdcb->dcb.i2c[entry->i2c_index]);
5519 void merge_like_dcb_entries(struct drm_device *dev, struct parsed_dcb *dcb)
5522 * DCB v2.0 lists each output combination separately.
5523 * Here we merge compatible entries to have fewer outputs, with
5527 int i, newentries = 0;
5529 for (i = 0; i < dcb->entries; i++) {
5530 struct dcb_entry *ient = &dcb->entry[i];
5533 for (j = i + 1; j < dcb->entries; j++) {
5534 struct dcb_entry *jent = &dcb->entry[j];
5536 if (jent->type == 100) /* already merged entry */
5539 /* merge heads field when all other fields the same */
5540 if (jent->i2c_index == ient->i2c_index &&
5541 jent->type == ient->type &&
5542 jent->location == ient->location &&
5543 jent->or == ient->or) {
5544 NV_TRACE(dev, "Merging DCB entries %d and %d\n",
5546 ient->heads |= jent->heads;
5547 jent->type = 100; /* dummy value */
5552 /* Compact entries merged into others out of dcb */
5553 for (i = 0; i < dcb->entries; i++) {
5554 if (dcb->entry[i].type == 100)
5557 if (newentries != i) {
5558 dcb->entry[newentries] = dcb->entry[i];
5559 dcb->entry[newentries].index = newentries;
5564 dcb->entries = newentries;
5567 static int parse_dcb_table(struct drm_device *dev, struct nvbios *bios, bool twoHeads)
5569 struct bios_parsed_dcb *bdcb = &bios->bdcb;
5570 struct parsed_dcb *dcb;
5571 uint16_t dcbptr, i2ctabptr = 0;
5573 uint8_t headerlen = 0x4, entries = DCB_MAX_NUM_ENTRIES;
5574 bool configblock = true;
5575 int recordlength = 8, confofs = 4;
5578 dcb = bios->pub.dcb = &bdcb->dcb;
5581 /* get the offset from 0x36 */
5582 dcbptr = ROM16(bios->data[0x36]);
5584 if (dcbptr == 0x0) {
5585 NV_WARN(dev, "No output data (DCB) found in BIOS, "
5586 "assuming a CRT output exists\n");
5587 /* this situation likely means a really old card, pre DCB */
5588 fabricate_vga_output(dcb, LEGACY_I2C_CRT, 1);
5590 if (nv04_tv_identify(dev,
5591 bios->legacy.i2c_indices.tv) >= 0)
5592 fabricate_tv_output(dcb, twoHeads);
5597 dcbtable = &bios->data[dcbptr];
5599 /* get DCB version */
5600 bdcb->version = dcbtable[0];
5601 NV_TRACE(dev, "Found Display Configuration Block version %d.%d\n",
5602 bdcb->version >> 4, bdcb->version & 0xf);
5604 if (bdcb->version >= 0x20) { /* NV17+ */
5607 if (bdcb->version >= 0x30) { /* NV40+ */
5608 headerlen = dcbtable[1];
5609 entries = dcbtable[2];
5610 recordlength = dcbtable[3];
5611 i2ctabptr = ROM16(dcbtable[4]);
5612 sig = ROM32(dcbtable[6]);
5613 bdcb->gpio_table_ptr = ROM16(dcbtable[10]);
5614 bdcb->connector_table_ptr = ROM16(dcbtable[20]);
5616 i2ctabptr = ROM16(dcbtable[2]);
5617 sig = ROM32(dcbtable[4]);
5621 if (sig != 0x4edcbdcb) {
5622 NV_ERROR(dev, "Bad Display Configuration Block "
5623 "signature (%08X)\n", sig);
5626 } else if (bdcb->version >= 0x15) { /* some NV11 and NV20 */
5627 char sig[8] = { 0 };
5629 strncpy(sig, (char *)&dcbtable[-7], 7);
5630 i2ctabptr = ROM16(dcbtable[2]);
5634 if (strcmp(sig, "DEV_REC")) {
5635 NV_ERROR(dev, "Bad Display Configuration Block "
5636 "signature (%s)\n", sig);
5641 * v1.4 (some NV15/16, NV11+) seems the same as v1.5, but always
5642 * has the same single (crt) entry, even when tv-out present, so
5643 * the conclusion is this version cannot really be used.
5644 * v1.2 tables (some NV6/10, and NV15+) normally have the same
5645 * 5 entries, which are not specific to the card and so no use.
5646 * v1.2 does have an I2C table that read_dcb_i2c_table can
5647 * handle, but cards exist (nv11 in #14821) with a bad i2c table
5648 * pointer, so use the indices parsed in parse_bmp_structure.
5649 * v1.1 (NV5+, maybe some NV4) is entirely unhelpful
5651 NV_TRACEWARN(dev, "No useful information in BIOS output table; "
5652 "adding all possible outputs\n");
5653 fabricate_vga_output(dcb, LEGACY_I2C_CRT, 1);
5656 * Attempt to detect TV before DVI because the test
5657 * for the former is more accurate and it rules the
5660 if (nv04_tv_identify(dev,
5661 bios->legacy.i2c_indices.tv) >= 0)
5662 fabricate_tv_output(dcb, twoHeads);
5664 else if (bios->tmds.output0_script_ptr ||
5665 bios->tmds.output1_script_ptr)
5666 fabricate_dvi_i_output(dcb, twoHeads);
5672 NV_WARN(dev, "No pointer to DCB I2C port table\n");
5674 bdcb->i2c_table = &bios->data[i2ctabptr];
5675 if (bdcb->version >= 0x30)
5676 bdcb->i2c_default_indices = bdcb->i2c_table[4];
5679 parse_dcb_gpio_table(bios);
5680 parse_dcb_connector_table(bios);
5682 if (entries > DCB_MAX_NUM_ENTRIES)
5683 entries = DCB_MAX_NUM_ENTRIES;
5685 for (i = 0; i < entries; i++) {
5686 uint32_t connection, config = 0;
5688 connection = ROM32(dcbtable[headerlen + recordlength * i]);
5690 config = ROM32(dcbtable[headerlen + confofs + recordlength * i]);
5692 /* seen on an NV11 with DCB v1.5 */
5693 if (connection == 0x00000000)
5696 /* seen on an NV17 with DCB v2.0 */
5697 if (connection == 0xffffffff)
5700 if ((connection & 0x0000000f) == 0x0000000f)
5703 NV_TRACEWARN(dev, "Raw DCB entry %d: %08x %08x\n",
5704 dcb->entries, connection, config);
5706 if (!parse_dcb_entry(dev, bdcb, connection, config))
5711 * apart for v2.1+ not being known for requiring merging, this
5712 * guarantees dcbent->index is the index of the entry in the rom image
5714 if (bdcb->version < 0x21)
5715 merge_like_dcb_entries(dev, dcb);
5717 return dcb->entries ? 0 : -ENXIO;
5721 fixup_legacy_connector(struct nvbios *bios)
5723 struct bios_parsed_dcb *bdcb = &bios->bdcb;
5724 struct parsed_dcb *dcb = &bdcb->dcb;
5728 * DCB 3.0 also has the table in most cases, but there are some cards
5729 * where the table is filled with stub entries, and the DCB entriy
5730 * indices are all 0. We don't need the connector indices on pre-G80
5731 * chips (yet?) so limit the use to DCB 4.0 and above.
5733 if (bdcb->version >= 0x40)
5737 * No known connector info before v3.0, so make it up. the rule here
5738 * is: anything on the same i2c bus is considered to be on the same
5739 * connector. any output without an associated i2c bus is assigned
5740 * its own unique connector index.
5742 for (i = 0; i < dcb->entries; i++) {
5743 if (dcb->entry[i].i2c_index == 0xf)
5747 * Ignore the I2C index for on-chip TV-out, as there
5748 * are cards with bogus values (nv31m in bug 23212),
5749 * and it's otherwise useless.
5751 if (dcb->entry[i].type == OUTPUT_TV &&
5752 dcb->entry[i].location == DCB_LOC_ON_CHIP) {
5753 dcb->entry[i].i2c_index = 0xf;
5757 dcb->entry[i].connector = dcb->entry[i].i2c_index;
5758 if (dcb->entry[i].connector > high)
5759 high = dcb->entry[i].connector;
5762 for (i = 0; i < dcb->entries; i++) {
5763 if (dcb->entry[i].i2c_index != 0xf)
5766 dcb->entry[i].connector = ++high;
5771 fixup_legacy_i2c(struct nvbios *bios)
5773 struct parsed_dcb *dcb = &bios->bdcb.dcb;
5776 for (i = 0; i < dcb->entries; i++) {
5777 if (dcb->entry[i].i2c_index == LEGACY_I2C_CRT)
5778 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.crt;
5779 if (dcb->entry[i].i2c_index == LEGACY_I2C_PANEL)
5780 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.panel;
5781 if (dcb->entry[i].i2c_index == LEGACY_I2C_TV)
5782 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.tv;
5786 static int load_nv17_hwsq_ucode_entry(struct drm_device *dev, struct nvbios *bios, uint16_t hwsq_offset, int entry)
5789 * The header following the "HWSQ" signature has the number of entries,
5790 * and the entry size
5792 * An entry consists of a dword to write to the sequencer control reg
5793 * (0x00001304), followed by the ucode bytes, written sequentially,
5794 * starting at reg 0x00001400
5797 uint8_t bytes_to_write;
5798 uint16_t hwsq_entry_offset;
5801 if (bios->data[hwsq_offset] <= entry) {
5802 NV_ERROR(dev, "Too few entries in HW sequencer table for "
5803 "requested entry\n");
5807 bytes_to_write = bios->data[hwsq_offset + 1];
5809 if (bytes_to_write != 36) {
5810 NV_ERROR(dev, "Unknown HW sequencer entry size\n");
5814 NV_TRACE(dev, "Loading NV17 power sequencing microcode\n");
5816 hwsq_entry_offset = hwsq_offset + 2 + entry * bytes_to_write;
5818 /* set sequencer control */
5819 bios_wr32(bios, 0x00001304, ROM32(bios->data[hwsq_entry_offset]));
5820 bytes_to_write -= 4;
5823 for (i = 0; i < bytes_to_write; i += 4)
5824 bios_wr32(bios, 0x00001400 + i, ROM32(bios->data[hwsq_entry_offset + i + 4]));
5826 /* twiddle NV_PBUS_DEBUG_4 */
5827 bios_wr32(bios, NV_PBUS_DEBUG_4, bios_rd32(bios, NV_PBUS_DEBUG_4) | 0x18);
5832 static int load_nv17_hw_sequencer_ucode(struct drm_device *dev,
5833 struct nvbios *bios)
5836 * BMP based cards, from NV17, need a microcode loading to correctly
5837 * control the GPIO etc for LVDS panels
5839 * BIT based cards seem to do this directly in the init scripts
5841 * The microcode entries are found by the "HWSQ" signature.
5844 const uint8_t hwsq_signature[] = { 'H', 'W', 'S', 'Q' };
5845 const int sz = sizeof(hwsq_signature);
5848 hwsq_offset = findstr(bios->data, bios->length, hwsq_signature, sz);
5852 /* always use entry 0? */
5853 return load_nv17_hwsq_ucode_entry(dev, bios, hwsq_offset + sz, 0);
5856 uint8_t *nouveau_bios_embedded_edid(struct drm_device *dev)
5858 struct drm_nouveau_private *dev_priv = dev->dev_private;
5859 struct nvbios *bios = &dev_priv->VBIOS;
5860 const uint8_t edid_sig[] = {
5861 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 };
5862 uint16_t offset = 0;
5864 int searchlen = NV_PROM_SIZE;
5867 return bios->fp.edid;
5870 newoffset = findstr(&bios->data[offset], searchlen,
5874 offset += newoffset;
5875 if (!nv_cksum(&bios->data[offset], EDID1_LEN))
5878 searchlen -= offset;
5882 NV_TRACE(dev, "Found EDID in BIOS\n");
5884 return bios->fp.edid = &bios->data[offset];
5888 nouveau_bios_run_init_table(struct drm_device *dev, uint16_t table,
5889 struct dcb_entry *dcbent)
5891 struct drm_nouveau_private *dev_priv = dev->dev_private;
5892 struct nvbios *bios = &dev_priv->VBIOS;
5893 struct init_exec iexec = { true, false };
5895 bios->display.output = dcbent;
5896 parse_init_table(bios, table, &iexec);
5897 bios->display.output = NULL;
5900 static bool NVInitVBIOS(struct drm_device *dev)
5902 struct drm_nouveau_private *dev_priv = dev->dev_private;
5903 struct nvbios *bios = &dev_priv->VBIOS;
5905 memset(bios, 0, sizeof(struct nvbios));
5908 if (!NVShadowVBIOS(dev, bios->data))
5911 bios->length = NV_PROM_SIZE;
5915 static int nouveau_parse_vbios_struct(struct drm_device *dev)
5917 struct drm_nouveau_private *dev_priv = dev->dev_private;
5918 struct nvbios *bios = &dev_priv->VBIOS;
5919 const uint8_t bit_signature[] = { 0xff, 0xb8, 'B', 'I', 'T' };
5920 const uint8_t bmp_signature[] = { 0xff, 0x7f, 'N', 'V', 0x0 };
5923 offset = findstr(bios->data, bios->length,
5924 bit_signature, sizeof(bit_signature));
5926 NV_TRACE(dev, "BIT BIOS found\n");
5927 return parse_bit_structure(bios, offset + 6);
5930 offset = findstr(bios->data, bios->length,
5931 bmp_signature, sizeof(bmp_signature));
5933 NV_TRACE(dev, "BMP BIOS found\n");
5934 return parse_bmp_structure(dev, bios, offset);
5937 NV_ERROR(dev, "No known BIOS signature found\n");
5942 nouveau_run_vbios_init(struct drm_device *dev)
5944 struct drm_nouveau_private *dev_priv = dev->dev_private;
5945 struct nvbios *bios = &dev_priv->VBIOS;
5948 NVLockVgaCrtcs(dev, false);
5949 if (nv_two_heads(dev))
5950 NVSetOwner(dev, bios->state.crtchead);
5952 if (bios->major_version < 5) /* BMP only */
5953 load_nv17_hw_sequencer_ucode(dev, bios);
5955 if (bios->execute) {
5956 bios->fp.last_script_invoc = 0;
5957 bios->fp.lvds_init_run = false;
5960 parse_init_tables(bios);
5963 * Runs some additional script seen on G8x VBIOSen. The VBIOS'
5964 * parser will run this right after the init tables, the binary
5965 * driver appears to run it at some point later.
5967 if (bios->some_script_ptr) {
5968 struct init_exec iexec = {true, false};
5970 NV_INFO(dev, "Parsing VBIOS init table at offset 0x%04X\n",
5971 bios->some_script_ptr);
5972 parse_init_table(bios, bios->some_script_ptr, &iexec);
5975 if (dev_priv->card_type >= NV_50) {
5976 for (i = 0; i < bios->bdcb.dcb.entries; i++) {
5977 nouveau_bios_run_display_table(dev,
5978 &bios->bdcb.dcb.entry[i],
5983 NVLockVgaCrtcs(dev, true);
5989 nouveau_bios_i2c_devices_takedown(struct drm_device *dev)
5991 struct drm_nouveau_private *dev_priv = dev->dev_private;
5992 struct nvbios *bios = &dev_priv->VBIOS;
5993 struct dcb_i2c_entry *entry;
5996 entry = &bios->bdcb.dcb.i2c[0];
5997 for (i = 0; i < DCB_MAX_NUM_I2C_ENTRIES; i++, entry++)
5998 nouveau_i2c_fini(dev, entry);
6002 nouveau_bios_init(struct drm_device *dev)
6004 struct drm_nouveau_private *dev_priv = dev->dev_private;
6005 struct nvbios *bios = &dev_priv->VBIOS;
6006 uint32_t saved_nv_pextdev_boot_0;
6010 dev_priv->vbios = &bios->pub;
6012 if (!NVInitVBIOS(dev))
6015 ret = nouveau_parse_vbios_struct(dev);
6019 ret = parse_dcb_table(dev, bios, nv_two_heads(dev));
6023 fixup_legacy_i2c(bios);
6024 fixup_legacy_connector(bios);
6026 if (!bios->major_version) /* we don't run version 0 bios */
6029 /* these will need remembering across a suspend */
6030 saved_nv_pextdev_boot_0 = bios_rd32(bios, NV_PEXTDEV_BOOT_0);
6031 bios->state.saved_nv_pfb_cfg0 = bios_rd32(bios, NV_PFB_CFG0);
6033 /* init script execution disabled */
6034 bios->execute = false;
6036 /* ... unless card isn't POSTed already */
6037 if (dev_priv->card_type >= NV_10 &&
6038 NVReadVgaCrtc(dev, 0, 0x00) == 0 &&
6039 NVReadVgaCrtc(dev, 0, 0x1a) == 0) {
6040 NV_INFO(dev, "Adaptor not initialised\n");
6041 if (dev_priv->card_type < NV_50) {
6042 NV_ERROR(dev, "Unable to POST this chipset\n");
6046 NV_INFO(dev, "Running VBIOS init tables\n");
6047 bios->execute = true;
6050 bios_wr32(bios, NV_PEXTDEV_BOOT_0, saved_nv_pextdev_boot_0);
6052 ret = nouveau_run_vbios_init(dev);
6054 dev_priv->vbios = NULL;
6058 /* feature_byte on BMP is poor, but init always sets CR4B */
6059 was_locked = NVLockVgaCrtcs(dev, false);
6060 if (bios->major_version < 5)
6061 bios->is_mobile = NVReadVgaCrtc(dev, 0, NV_CIO_CRE_4B) & 0x40;
6063 /* all BIT systems need p_f_m_t for digital_min_front_porch */
6064 if (bios->is_mobile || bios->major_version >= 5)
6065 ret = parse_fp_mode_table(dev, bios);
6066 NVLockVgaCrtcs(dev, was_locked);
6068 /* allow subsequent scripts to execute */
6069 bios->execute = true;
6075 nouveau_bios_takedown(struct drm_device *dev)
6077 nouveau_bios_i2c_devices_takedown(dev);