drivers/gpu/drm/nouveau/include/nvrm/535.54.03/nvidia/kernel/inc/vgpu/rpc_global_enums.h

   1 #ifndef __src_nvidia_kernel_inc_vgpu_rpc_global_enums_h__
   2 #define __src_nvidia_kernel_inc_vgpu_rpc_global_enums_h__
   3
   4 /* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.54.03 */
   5
   6 #ifndef X
   7 #    define X(UNIT, RPC) NV_VGPU_MSG_FUNCTION_##RPC,
   8 #    define DEFINING_X_IN_RPC_GLOBAL_ENUMS_H
   9 enum {
  10 #endif
  11     X(RM, NOP)                             // 0
  12     X(RM, SET_GUEST_SYSTEM_INFO)           // 1
  13     X(RM, ALLOC_ROOT)                      // 2
  14     X(RM, ALLOC_DEVICE)                    // 3 deprecated
  15     X(RM, ALLOC_MEMORY)                    // 4
  16     X(RM, ALLOC_CTX_DMA)                   // 5
  17     X(RM, ALLOC_CHANNEL_DMA)               // 6
  18     X(RM, MAP_MEMORY)                      // 7
  19     X(RM, BIND_CTX_DMA)                    // 8 deprecated
  20     X(RM, ALLOC_OBJECT)                    // 9
  21     X(RM, FREE)                            //10
  22     X(RM, LOG)                             //11
  23     X(RM, ALLOC_VIDMEM)                    //12
  24     X(RM, UNMAP_MEMORY)                    //13
  25     X(RM, MAP_MEMORY_DMA)                  //14
  26     X(RM, UNMAP_MEMORY_DMA)                //15
  27     X(RM, GET_EDID)                        //16
  28     X(RM, ALLOC_DISP_CHANNEL)              //17
  29     X(RM, ALLOC_DISP_OBJECT)               //18
  30     X(RM, ALLOC_SUBDEVICE)                 //19
  31     X(RM, ALLOC_DYNAMIC_MEMORY)            //20
  32     X(RM, DUP_OBJECT)                      //21
  33     X(RM, IDLE_CHANNELS)                   //22
  34     X(RM, ALLOC_EVENT)                     //23
  35     X(RM, SEND_EVENT)                      //24
  36     X(RM, REMAPPER_CONTROL)                //25 deprecated
  37     X(RM, DMA_CONTROL)                     //26
  38     X(RM, DMA_FILL_PTE_MEM)                //27
  39     X(RM, MANAGE_HW_RESOURCE)              //28
  40     X(RM, BIND_ARBITRARY_CTX_DMA)          //29 deprecated
  41     X(RM, CREATE_FB_SEGMENT)               //30
  42     X(RM, DESTROY_FB_SEGMENT)              //31
  43     X(RM, ALLOC_SHARE_DEVICE)              //32
  44     X(RM, DEFERRED_API_CONTROL)            //33
  45     X(RM, REMOVE_DEFERRED_API)             //34
  46     X(RM, SIM_ESCAPE_READ)                 //35
  47     X(RM, SIM_ESCAPE_WRITE)                //36
  48     X(RM, SIM_MANAGE_DISPLAY_CONTEXT_DMA)  //37
  49     X(RM, FREE_VIDMEM_VIRT)                //38
  50     X(RM, PERF_GET_PSTATE_INFO)            //39  deprecated for vGPU, used by GSP
  51     X(RM, PERF_GET_PERFMON_SAMPLE)         //40
  52     X(RM, PERF_GET_VIRTUAL_PSTATE_INFO)    //41  deprecated
  53     X(RM, PERF_GET_LEVEL_INFO)             //42
  54     X(RM, MAP_SEMA_MEMORY)                 //43
  55     X(RM, UNMAP_SEMA_MEMORY)               //44
  56     X(RM, SET_SURFACE_PROPERTIES)          //45
  57     X(RM, CLEANUP_SURFACE)                 //46
  58     X(RM, UNLOADING_GUEST_DRIVER)          //47
  59     X(RM, TDR_SET_TIMEOUT_STATE)           //48
  60     X(RM, SWITCH_TO_VGA)                   //49
  61     X(RM, GPU_EXEC_REG_OPS)                //50
  62     X(RM, GET_STATIC_INFO)                 //51
  63     X(RM, ALLOC_VIRTMEM)                   //52
  64     X(RM, UPDATE_PDE_2)                    //53
  65     X(RM, SET_PAGE_DIRECTORY)              //54
  66     X(RM, GET_STATIC_PSTATE_INFO)          //55
  67     X(RM, TRANSLATE_GUEST_GPU_PTES)        //56
  68     X(RM, RESERVED_57)                     //57
  69     X(RM, RESET_CURRENT_GR_CONTEXT)        //58
  70     X(RM, SET_SEMA_MEM_VALIDATION_STATE)   //59
  71     X(RM, GET_ENGINE_UTILIZATION)          //60
  72     X(RM, UPDATE_GPU_PDES)                 //61
  73     X(RM, GET_ENCODER_CAPACITY)            //62
  74     X(RM, VGPU_PF_REG_READ32)              //63
  75     X(RM, SET_GUEST_SYSTEM_INFO_EXT)       //64
  76     X(GSP, GET_GSP_STATIC_INFO)            //65
  77     X(RM, RMFS_INIT)                       //66
  78     X(RM, RMFS_CLOSE_QUEUE)                //67
  79     X(RM, RMFS_CLEANUP)                    //68
  80     X(RM, RMFS_TEST)                       //69
  81     X(RM, UPDATE_BAR_PDE)                  //70
  82     X(RM, CONTINUATION_RECORD)             //71
  83     X(RM, GSP_SET_SYSTEM_INFO)             //72
  84     X(RM, SET_REGISTRY)                    //73
  85     X(GSP, GSP_INIT_POST_OBJGPU)           //74 deprecated
  86     X(RM, SUBDEV_EVENT_SET_NOTIFICATION)   //75 deprecated
  87     X(GSP, GSP_RM_CONTROL)                 //76
  88     X(RM, GET_STATIC_INFO2)                //77
  89     X(RM, DUMP_PROTOBUF_COMPONENT)         //78
  90     X(RM, UNSET_PAGE_DIRECTORY)            //79
  91     X(RM, GET_CONSOLIDATED_STATIC_INFO)    //80
  92     X(RM, GMMU_REGISTER_FAULT_BUFFER)      //81 deprecated
  93     X(RM, GMMU_UNREGISTER_FAULT_BUFFER)    //82 deprecated
  94     X(RM, GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER)   //83 deprecated
  95     X(RM, GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER) //84 deprecated
  96     X(RM, CTRL_SET_VGPU_FB_USAGE)          //85
  97     X(RM, CTRL_NVFBC_SW_SESSION_UPDATE_INFO)    //86
  98     X(RM, CTRL_NVENC_SW_SESSION_UPDATE_INFO)    //87
  99     X(RM, CTRL_RESET_CHANNEL)                   //88
 100     X(RM, CTRL_RESET_ISOLATED_CHANNEL)          //89
 101     X(RM, CTRL_GPU_HANDLE_VF_PRI_FAULT)         //90
 102     X(RM, CTRL_CLK_GET_EXTENDED_INFO)           //91
 103     X(RM, CTRL_PERF_BOOST)                      //92
 104     X(RM, CTRL_PERF_VPSTATES_GET_CONTROL)       //93
 105     X(RM, CTRL_GET_ZBC_CLEAR_TABLE)             //94
 106     X(RM, CTRL_SET_ZBC_COLOR_CLEAR)             //95
 107     X(RM, CTRL_SET_ZBC_DEPTH_CLEAR)             //96
 108     X(RM, CTRL_GPFIFO_SCHEDULE)                 //97
 109     X(RM, CTRL_SET_TIMESLICE)                   //98
 110     X(RM, CTRL_PREEMPT)                         //99
 111     X(RM, CTRL_FIFO_DISABLE_CHANNELS)           //100
 112     X(RM, CTRL_SET_TSG_INTERLEAVE_LEVEL)        //101
 113     X(RM, CTRL_SET_CHANNEL_INTERLEAVE_LEVEL)    //102
 114     X(GSP, GSP_RM_ALLOC)                        //103
 115     X(RM, CTRL_GET_P2P_CAPS_V2)                 //104
 116     X(RM, CTRL_CIPHER_AES_ENCRYPT)              //105
 117     X(RM, CTRL_CIPHER_SESSION_KEY)              //106
 118     X(RM, CTRL_CIPHER_SESSION_KEY_STATUS)       //107
 119     X(RM, CTRL_DBG_CLEAR_ALL_SM_ERROR_STATES)   //108
 120     X(RM, CTRL_DBG_READ_ALL_SM_ERROR_STATES)    //109
 121     X(RM, CTRL_DBG_SET_EXCEPTION_MASK)          //110
 122     X(RM, CTRL_GPU_PROMOTE_CTX)                 //111
 123     X(RM, CTRL_GR_CTXSW_PREEMPTION_BIND)        //112
 124     X(RM, CTRL_GR_SET_CTXSW_PREEMPTION_MODE)    //113
 125     X(RM, CTRL_GR_CTXSW_ZCULL_BIND)             //114
 126     X(RM, CTRL_GPU_INITIALIZE_CTX)              //115
 127     X(RM, CTRL_VASPACE_COPY_SERVER_RESERVED_PDES)    //116
 128     X(RM, CTRL_FIFO_CLEAR_FAULTED_BIT)          //117
 129     X(RM, CTRL_GET_LATEST_ECC_ADDRESSES)        //118
 130     X(RM, CTRL_MC_SERVICE_INTERRUPTS)           //119
 131     X(RM, CTRL_DMA_SET_DEFAULT_VASPACE)         //120
 132     X(RM, CTRL_GET_CE_PCE_MASK)                 //121
 133     X(RM, CTRL_GET_ZBC_CLEAR_TABLE_ENTRY)       //122
 134     X(RM, CTRL_GET_NVLINK_PEER_ID_MASK)         //123
 135     X(RM, CTRL_GET_NVLINK_STATUS)               //124
 136     X(RM, CTRL_GET_P2P_CAPS)                    //125
 137     X(RM, CTRL_GET_P2P_CAPS_MATRIX)             //126
 138     X(RM, RESERVED_0)                           //127
 139     X(RM, CTRL_RESERVE_PM_AREA_SMPC)            //128
 140     X(RM, CTRL_RESERVE_HWPM_LEGACY)             //129
 141     X(RM, CTRL_B0CC_EXEC_REG_OPS)               //130
 142     X(RM, CTRL_BIND_PM_RESOURCES)               //131
 143     X(RM, CTRL_DBG_SUSPEND_CONTEXT)             //132
 144     X(RM, CTRL_DBG_RESUME_CONTEXT)              //133
 145     X(RM, CTRL_DBG_EXEC_REG_OPS)                //134
 146     X(RM, CTRL_DBG_SET_MODE_MMU_DEBUG)          //135
 147     X(RM, CTRL_DBG_READ_SINGLE_SM_ERROR_STATE)  //136
 148     X(RM, CTRL_DBG_CLEAR_SINGLE_SM_ERROR_STATE) //137
 149     X(RM, CTRL_DBG_SET_MODE_ERRBAR_DEBUG)       //138
 150     X(RM, CTRL_DBG_SET_NEXT_STOP_TRIGGER_TYPE)  //139
 151     X(RM, CTRL_ALLOC_PMA_STREAM)                //140
 152     X(RM, CTRL_PMA_STREAM_UPDATE_GET_PUT)       //141
 153     X(RM, CTRL_FB_GET_INFO_V2)                  //142
 154     X(RM, CTRL_FIFO_SET_CHANNEL_PROPERTIES)     //143
 155     X(RM, CTRL_GR_GET_CTX_BUFFER_INFO)          //144
 156     X(RM, CTRL_KGR_GET_CTX_BUFFER_PTES)         //145
 157     X(RM, CTRL_GPU_EVICT_CTX)                   //146
 158     X(RM, CTRL_FB_GET_FS_INFO)                  //147
 159     X(RM, CTRL_GRMGR_GET_GR_FS_INFO)            //148
 160     X(RM, CTRL_STOP_CHANNEL)                    //149
 161     X(RM, CTRL_GR_PC_SAMPLING_MODE)             //150
 162     X(RM, CTRL_PERF_RATED_TDP_GET_STATUS)       //151
 163     X(RM, CTRL_PERF_RATED_TDP_SET_CONTROL)      //152
 164     X(RM, CTRL_FREE_PMA_STREAM)                 //153
 165     X(RM, CTRL_TIMER_SET_GR_TICK_FREQ)          //154
 166     X(RM, CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB) //155
 167     X(RM, GET_CONSOLIDATED_GR_STATIC_INFO)      //156
 168     X(RM, CTRL_DBG_SET_SINGLE_SM_SINGLE_STEP)   //157
 169     X(RM, CTRL_GR_GET_TPC_PARTITION_MODE)       //158
 170     X(RM, CTRL_GR_SET_TPC_PARTITION_MODE)       //159
 171     X(UVM, UVM_PAGING_CHANNEL_ALLOCATE)         //160
 172     X(UVM, UVM_PAGING_CHANNEL_DESTROY)          //161
 173     X(UVM, UVM_PAGING_CHANNEL_MAP)              //162
 174     X(UVM, UVM_PAGING_CHANNEL_UNMAP)            //163
 175     X(UVM, UVM_PAGING_CHANNEL_PUSH_STREAM)      //164
 176     X(UVM, UVM_PAGING_CHANNEL_SET_HANDLES)      //165
 177     X(UVM, UVM_METHOD_STREAM_GUEST_PAGES_OPERATION)  //166
 178     X(RM, CTRL_INTERNAL_QUIESCE_PMA_CHANNEL)    //167
 179     X(RM, DCE_RM_INIT)                          //168
 180     X(RM, REGISTER_VIRTUAL_EVENT_BUFFER)        //169
 181     X(RM, CTRL_EVENT_BUFFER_UPDATE_GET)         //170
 182     X(RM, GET_PLCABLE_ADDRESS_KIND)             //171
 183     X(RM, CTRL_PERF_LIMITS_SET_STATUS_V2)       //172
 184     X(RM, CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM)    //173
 185     X(RM, CTRL_GET_MMU_DEBUG_MODE)              //174
 186     X(RM, CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS) //175
 187     X(RM, CTRL_FLCN_GET_CTX_BUFFER_SIZE)        //176
 188     X(RM, CTRL_FLCN_GET_CTX_BUFFER_INFO)        //177
 189     X(RM, DISABLE_CHANNELS)                     //178
 190     X(RM, CTRL_FABRIC_MEMORY_DESCRIBE)          //179
 191     X(RM, CTRL_FABRIC_MEM_STATS)                //180
 192     X(RM, SAVE_HIBERNATION_DATA)                //181
 193     X(RM, RESTORE_HIBERNATION_DATA)             //182
 194     X(RM, CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED) //183
 195     X(RM, CTRL_EXEC_PARTITIONS_CREATE)          //184
 196     X(RM, CTRL_EXEC_PARTITIONS_DELETE)          //185
 197     X(RM, CTRL_GPFIFO_GET_WORK_SUBMIT_TOKEN)    //186
 198     X(RM, CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX) //187
 199     X(RM, PMA_SCRUBBER_SHARED_BUFFER_GUEST_PAGES_OPERATION)  //188
 200     X(RM, CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK)    //189
 201     X(RM, SET_SYSMEM_DIRTY_PAGE_TRACKING_BUFFER)  //190
 202     X(RM, CTRL_SUBDEVICE_GET_P2P_CAPS)          // 191
 203     X(RM, CTRL_BUS_SET_P2P_MAPPING)             // 192
 204     X(RM, CTRL_BUS_UNSET_P2P_MAPPING)           // 193
 205     X(RM, CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK)    // 194
 206     X(RM, CTRL_GPU_MIGRATABLE_OPS)              // 195
 207     X(RM, CTRL_GET_TOTAL_HS_CREDITS)            // 196
 208     X(RM, CTRL_GET_HS_CREDITS)                  // 197
 209     X(RM, CTRL_SET_HS_CREDITS)                  // 198
 210     X(RM, CTRL_PM_AREA_PC_SAMPLER)              // 199
 211     X(RM, INVALIDATE_TLB)                       // 200
 212     X(RM, NUM_FUNCTIONS)                        //END
 213 #ifdef DEFINING_X_IN_RPC_GLOBAL_ENUMS_H
 214 };
 215 #   undef X
 216 #   undef DEFINING_X_IN_RPC_GLOBAL_ENUMS_H
 217 #endif
 218
 219 #ifndef E
 220 #    define E(RPC) NV_VGPU_MSG_EVENT_##RPC,
 221 #    define DEFINING_E_IN_RPC_GLOBAL_ENUMS_H
 222 enum {
 223 #endif
 224     E(FIRST_EVENT = 0x1000)                      // 0x1000
 225     E(GSP_INIT_DONE)                             // 0x1001
 226     E(GSP_RUN_CPU_SEQUENCER)                     // 0x1002
 227     E(POST_EVENT)                                // 0x1003
 228     E(RC_TRIGGERED)                              // 0x1004
 229     E(MMU_FAULT_QUEUED)                          // 0x1005
 230     E(OS_ERROR_LOG)                              // 0x1006
 231     E(RG_LINE_INTR)                              // 0x1007
 232     E(GPUACCT_PERFMON_UTIL_SAMPLES)              // 0x1008
 233     E(SIM_READ)                                  // 0x1009
 234     E(SIM_WRITE)                                 // 0x100a
 235     E(SEMAPHORE_SCHEDULE_CALLBACK)               // 0x100b
 236     E(UCODE_LIBOS_PRINT)                         // 0x100c
 237     E(VGPU_GSP_PLUGIN_TRIGGERED)                 // 0x100d
 238     E(PERF_GPU_BOOST_SYNC_LIMITS_CALLBACK)       // 0x100e
 239     E(PERF_BRIDGELESS_INFO_UPDATE)               // 0x100f
 240     E(VGPU_CONFIG)                               // 0x1010
 241     E(DISPLAY_MODESET)                           // 0x1011
 242     E(EXTDEV_INTR_SERVICE)                       // 0x1012
 243     E(NVLINK_INBAND_RECEIVED_DATA_256)           // 0x1013
 244     E(NVLINK_INBAND_RECEIVED_DATA_512)           // 0x1014
 245     E(NVLINK_INBAND_RECEIVED_DATA_1024)          // 0x1015
 246     E(NVLINK_INBAND_RECEIVED_DATA_2048)          // 0x1016
 247     E(NVLINK_INBAND_RECEIVED_DATA_4096)          // 0x1017
 248     E(TIMED_SEMAPHORE_RELEASE)                   // 0x1018
 249     E(NVLINK_IS_GPU_DEGRADED)                    // 0x1019
 250     E(PFM_REQ_HNDLR_STATE_SYNC_CALLBACK)         // 0x101a
 251     E(GSP_SEND_USER_SHARED_DATA)                 // 0x101b
 252     E(NVLINK_FAULT_UP)                           // 0x101c
 253     E(GSP_LOCKDOWN_NOTICE)                       // 0x101d
 254     E(MIG_CI_CONFIG_UPDATE)                      // 0x101e
 255     E(NUM_EVENTS)                                // END
 256 #ifdef DEFINING_E_IN_RPC_GLOBAL_ENUMS_H
 257 };
 258 #   undef E
 259 #   undef DEFINING_E_IN_RPC_GLOBAL_ENUMS_H
 260 #endif
 261
 262 #endif