1 #ifndef __src_common_shared_msgq_inc_msgq_msgq_priv_h__
2 #define __src_common_shared_msgq_inc_msgq_msgq_priv_h__
4 /* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.54.03 */
7 * SPDX-FileCopyrightText: Copyright (c) 2018-2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
8 * SPDX-License-Identifier: MIT
10 * Permission is hereby granted, free of charge, to any person obtaining a
11 * copy of this software and associated documentation files (the "Software"),
12 * to deal in the Software without restriction, including without limitation
13 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
14 * and/or sell copies of the Software, and to permit persons to whom the
15 * Software is furnished to do so, subject to the following conditions:
17 * The above copyright notice and this permission notice shall be included in
18 * all copies or substantial portions of the Software.
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
24 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
25 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26 * DEALINGS IN THE SOFTWARE.
31 NvU32 version; // queue version
32 NvU32 size; // bytes, page aligned
33 NvU32 msgSize; // entry size, bytes, must be power-of-2, 16 is minimum
34 NvU32 msgCount; // number of entries in queue
35 NvU32 writePtr; // message id of next slot
36 NvU32 flags; // if set it means "i want to swap RX"
37 NvU32 rxHdrOff; // Offset of msgqRxHeader from start of backing store.
38 NvU32 entryOff; // Offset of entries from start of backing store.
43 NvU32 readPtr; // message id of last message read