drivers/gpu/drm/nouveau/dispnv50/disp.c

   1 /*
   2  * Copyright 2011 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "disp.h"
  25 #include "atom.h"
  26 #include "core.h"
  27 #include "head.h"
  28 #include "wndw.h"
  29
  30 #include <linux/dma-mapping.h>
  31 #include <linux/hdmi.h>
  32
  33 #include <drm/drmP.h>
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_crtc_helper.h>
  36 #include <drm/drm_dp_helper.h>
  37 #include <drm/drm_fb_helper.h>
  38 #include <drm/drm_plane_helper.h>
  39 #include <drm/drm_edid.h>
  40
  41 #include <nvif/class.h>
  42 #include <nvif/cl0002.h>
  43 #include <nvif/cl5070.h>
  44 #include <nvif/cl507d.h>
  45 #include <nvif/event.h>
  46
  47 #include "nouveau_drv.h"
  48 #include "nouveau_dma.h"
  49 #include "nouveau_gem.h"
  50 #include "nouveau_connector.h"
  51 #include "nouveau_encoder.h"
  52 #include "nouveau_fence.h"
  53 #include "nouveau_fbcon.h"
  54
  55 #include <subdev/bios/dp.h>
  56
  57 /******************************************************************************
  58  * Atomic state
  59  *****************************************************************************/
  60
  61 struct nv50_outp_atom {
  62         struct list_head head;
  63
  64         struct drm_encoder *encoder;
  65         bool flush_disable;
  66
  67         union nv50_outp_atom_mask {
  68                 struct {
  69                         bool ctrl:1;
  70                 };
  71                 u8 mask;
  72         } set, clr;
  73 };
  74
  75 /******************************************************************************
  76  * EVO channel
  77  *****************************************************************************/
  78
  79 static int
  80 nv50_chan_create(struct nvif_device *device, struct nvif_object *disp,
  81                  const s32 *oclass, u8 head, void *data, u32 size,
  82                  struct nv50_chan *chan)
  83 {
  84         struct nvif_sclass *sclass;
  85         int ret, i, n;
  86
  87         chan->device = device;
  88
  89         ret = n = nvif_object_sclass_get(disp, &sclass);
  90         if (ret < 0)
  91                 return ret;
  92
  93         while (oclass[0]) {
  94                 for (i = 0; i < n; i++) {
  95                         if (sclass[i].oclass == oclass[0]) {
  96                                 ret = nvif_object_init(disp, 0, oclass[0],
  97                                                        data, size, &chan->user);
  98                                 if (ret == 0)
  99                                         nvif_object_map(&chan->user, NULL, 0);
 100                                 nvif_object_sclass_put(&sclass);
 101                                 return ret;
 102                         }
 103                 }
 104                 oclass++;
 105         }
 106
 107         nvif_object_sclass_put(&sclass);
 108         return -ENOSYS;
 109 }
 110
 111 static void
 112 nv50_chan_destroy(struct nv50_chan *chan)
 113 {
 114         nvif_object_fini(&chan->user);
 115 }
 116
 117 /******************************************************************************
 118  * DMA EVO channel
 119  *****************************************************************************/
 120
 121 void
 122 nv50_dmac_destroy(struct nv50_dmac *dmac)
 123 {
 124         nvif_object_fini(&dmac->vram);
 125         nvif_object_fini(&dmac->sync);
 126
 127         nv50_chan_destroy(&dmac->base);
 128
 129         nvif_mem_fini(&dmac->push);
 130 }
 131
 132 int
 133 nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp,
 134                  const s32 *oclass, u8 head, void *data, u32 size, u64 syncbuf,
 135                  struct nv50_dmac *dmac)
 136 {
 137         struct nouveau_cli *cli = (void *)device->object.client;
 138         struct nv50_disp_core_channel_dma_v0 *args = data;
 139         int ret;
 140
 141         mutex_init(&dmac->lock);
 142
 143         ret = nvif_mem_init_map(&cli->mmu, NVIF_MEM_COHERENT, 0x1000,
 144                                 &dmac->push);
 145         if (ret)
 146                 return ret;
 147
 148         dmac->ptr = dmac->push.object.map.ptr;
 149
 150         args->pushbuf = nvif_handle(&dmac->push.object);
 151
 152         ret = nv50_chan_create(device, disp, oclass, head, data, size,
 153                                &dmac->base);
 154         if (ret)
 155                 return ret;
 156
 157         ret = nvif_object_init(&dmac->base.user, 0xf0000000, NV_DMA_IN_MEMORY,
 158                                &(struct nv_dma_v0) {
 159                                         .target = NV_DMA_V0_TARGET_VRAM,
 160                                         .access = NV_DMA_V0_ACCESS_RDWR,
 161                                         .start = syncbuf + 0x0000,
 162                                         .limit = syncbuf + 0x0fff,
 163                                }, sizeof(struct nv_dma_v0),
 164                                &dmac->sync);
 165         if (ret)
 166                 return ret;
 167
 168         ret = nvif_object_init(&dmac->base.user, 0xf0000001, NV_DMA_IN_MEMORY,
 169                                &(struct nv_dma_v0) {
 170                                         .target = NV_DMA_V0_TARGET_VRAM,
 171                                         .access = NV_DMA_V0_ACCESS_RDWR,
 172                                         .start = 0,
 173                                         .limit = device->info.ram_user - 1,
 174                                }, sizeof(struct nv_dma_v0),
 175                                &dmac->vram);
 176         if (ret)
 177                 return ret;
 178
 179         return ret;
 180 }
 181
 182 /******************************************************************************
 183  * EVO channel helpers
 184  *****************************************************************************/
 185 u32 *
 186 evo_wait(struct nv50_dmac *evoc, int nr)
 187 {
 188         struct nv50_dmac *dmac = evoc;
 189         struct nvif_device *device = dmac->base.device;
 190         u32 put = nvif_rd32(&dmac->base.user, 0x0000) / 4;
 191
 192         mutex_lock(&dmac->lock);
 193         if (put + nr >= (PAGE_SIZE / 4) - 8) {
 194                 dmac->ptr[put] = 0x20000000;
 195
 196                 nvif_wr32(&dmac->base.user, 0x0000, 0x00000000);
 197                 if (nvif_msec(device, 2000,
 198                         if (!nvif_rd32(&dmac->base.user, 0x0004))
 199                                 break;
 200                 ) < 0) {
 201                         mutex_unlock(&dmac->lock);
 202                         pr_err("nouveau: evo channel stalled\n");
 203                         return NULL;
 204                 }
 205
 206                 put = 0;
 207         }
 208
 209         return dmac->ptr + put;
 210 }
 211
 212 void
 213 evo_kick(u32 *push, struct nv50_dmac *evoc)
 214 {
 215         struct nv50_dmac *dmac = evoc;
 216         nvif_wr32(&dmac->base.user, 0x0000, (push - dmac->ptr) << 2);
 217         mutex_unlock(&dmac->lock);
 218 }
 219
 220 /******************************************************************************
 221  * Output path helpers
 222  *****************************************************************************/
 223 static void
 224 nv50_outp_release(struct nouveau_encoder *nv_encoder)
 225 {
 226         struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev);
 227         struct {
 228                 struct nv50_disp_mthd_v1 base;
 229         } args = {
 230                 .base.version = 1,
 231                 .base.method = NV50_DISP_MTHD_V1_RELEASE,
 232                 .base.hasht  = nv_encoder->dcb->hasht,
 233                 .base.hashm  = nv_encoder->dcb->hashm,
 234         };
 235
 236         nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 237         nv_encoder->or = -1;
 238         nv_encoder->link = 0;
 239 }
 240
 241 static int
 242 nv50_outp_acquire(struct nouveau_encoder *nv_encoder)
 243 {
 244         struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev);
 245         struct nv50_disp *disp = nv50_disp(drm->dev);
 246         struct {
 247                 struct nv50_disp_mthd_v1 base;
 248                 struct nv50_disp_acquire_v0 info;
 249         } args = {
 250                 .base.version = 1,
 251                 .base.method = NV50_DISP_MTHD_V1_ACQUIRE,
 252                 .base.hasht  = nv_encoder->dcb->hasht,
 253                 .base.hashm  = nv_encoder->dcb->hashm,
 254         };
 255         int ret;
 256
 257         ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 258         if (ret) {
 259                 NV_ERROR(drm, "error acquiring output path: %d\n", ret);
 260                 return ret;
 261         }
 262
 263         nv_encoder->or = args.info.or;
 264         nv_encoder->link = args.info.link;
 265         return 0;
 266 }
 267
 268 static int
 269 nv50_outp_atomic_check_view(struct drm_encoder *encoder,
 270                             struct drm_crtc_state *crtc_state,
 271                             struct drm_connector_state *conn_state,
 272                             struct drm_display_mode *native_mode)
 273 {
 274         struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
 275         struct drm_display_mode *mode = &crtc_state->mode;
 276         struct drm_connector *connector = conn_state->connector;
 277         struct nouveau_conn_atom *asyc = nouveau_conn_atom(conn_state);
 278         struct nouveau_drm *drm = nouveau_drm(encoder->dev);
 279
 280         NV_ATOMIC(drm, "%s atomic_check\n", encoder->name);
 281         asyc->scaler.full = false;
 282         if (!native_mode)
 283                 return 0;
 284
 285         if (asyc->scaler.mode == DRM_MODE_SCALE_NONE) {
 286                 switch (connector->connector_type) {
 287                 case DRM_MODE_CONNECTOR_LVDS:
 288                 case DRM_MODE_CONNECTOR_eDP:
 289                         /* Force use of scaler for non-EDID modes. */
 290                         if (adjusted_mode->type & DRM_MODE_TYPE_DRIVER)
 291                                 break;
 292                         mode = native_mode;
 293                         asyc->scaler.full = true;
 294                         break;
 295                 default:
 296                         break;
 297                 }
 298         } else {
 299                 mode = native_mode;
 300         }
 301
 302         if (!drm_mode_equal(adjusted_mode, mode)) {
 303                 drm_mode_copy(adjusted_mode, mode);
 304                 crtc_state->mode_changed = true;
 305         }
 306
 307         return 0;
 308 }
 309
 310 static int
 311 nv50_outp_atomic_check(struct drm_encoder *encoder,
 312                        struct drm_crtc_state *crtc_state,
 313                        struct drm_connector_state *conn_state)
 314 {
 315         struct nouveau_connector *nv_connector =
 316                 nouveau_connector(conn_state->connector);
 317         return nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
 318                                            nv_connector->native_mode);
 319 }
 320
 321 /******************************************************************************
 322  * DAC
 323  *****************************************************************************/
 324 static void
 325 nv50_dac_disable(struct drm_encoder *encoder)
 326 {
 327         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 328         struct nv50_core *core = nv50_disp(encoder->dev)->core;
 329         if (nv_encoder->crtc)
 330                 core->func->dac->ctrl(core, nv_encoder->or, 0x00000000, NULL);
 331         nv_encoder->crtc = NULL;
 332         nv50_outp_release(nv_encoder);
 333 }
 334
 335 static void
 336 nv50_dac_enable(struct drm_encoder *encoder)
 337 {
 338         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 339         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 340         struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
 341         struct nv50_core *core = nv50_disp(encoder->dev)->core;
 342
 343         nv50_outp_acquire(nv_encoder);
 344
 345         core->func->dac->ctrl(core, nv_encoder->or, 1 << nv_crtc->index, asyh);
 346         asyh->or.depth = 0;
 347
 348         nv_encoder->crtc = encoder->crtc;
 349 }
 350
 351 static enum drm_connector_status
 352 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
 353 {
 354         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 355         struct nv50_disp *disp = nv50_disp(encoder->dev);
 356         struct {
 357                 struct nv50_disp_mthd_v1 base;
 358                 struct nv50_disp_dac_load_v0 load;
 359         } args = {
 360                 .base.version = 1,
 361                 .base.method = NV50_DISP_MTHD_V1_DAC_LOAD,
 362                 .base.hasht  = nv_encoder->dcb->hasht,
 363                 .base.hashm  = nv_encoder->dcb->hashm,
 364         };
 365         int ret;
 366
 367         args.load.data = nouveau_drm(encoder->dev)->vbios.dactestval;
 368         if (args.load.data == 0)
 369                 args.load.data = 340;
 370
 371         ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 372         if (ret || !args.load.load)
 373                 return connector_status_disconnected;
 374
 375         return connector_status_connected;
 376 }
 377
 378 static const struct drm_encoder_helper_funcs
 379 nv50_dac_help = {
 380         .atomic_check = nv50_outp_atomic_check,
 381         .enable = nv50_dac_enable,
 382         .disable = nv50_dac_disable,
 383         .detect = nv50_dac_detect
 384 };
 385
 386 static void
 387 nv50_dac_destroy(struct drm_encoder *encoder)
 388 {
 389         drm_encoder_cleanup(encoder);
 390         kfree(encoder);
 391 }
 392
 393 static const struct drm_encoder_funcs
 394 nv50_dac_func = {
 395         .destroy = nv50_dac_destroy,
 396 };
 397
 398 static int
 399 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe)
 400 {
 401         struct nouveau_drm *drm = nouveau_drm(connector->dev);
 402         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
 403         struct nvkm_i2c_bus *bus;
 404         struct nouveau_encoder *nv_encoder;
 405         struct drm_encoder *encoder;
 406         int type = DRM_MODE_ENCODER_DAC;
 407
 408         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
 409         if (!nv_encoder)
 410                 return -ENOMEM;
 411         nv_encoder->dcb = dcbe;
 412
 413         bus = nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
 414         if (bus)
 415                 nv_encoder->i2c = &bus->i2c;
 416
 417         encoder = to_drm_encoder(nv_encoder);
 418         encoder->possible_crtcs = dcbe->heads;
 419         encoder->possible_clones = 0;
 420         drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type,
 421                          "dac-%04x-%04x", dcbe->hasht, dcbe->hashm);
 422         drm_encoder_helper_add(encoder, &nv50_dac_help);
 423
 424         drm_mode_connector_attach_encoder(connector, encoder);
 425         return 0;
 426 }
 427
 428 /******************************************************************************
 429  * Audio
 430  *****************************************************************************/
 431 static void
 432 nv50_audio_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
 433 {
 434         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 435         struct nv50_disp *disp = nv50_disp(encoder->dev);
 436         struct {
 437                 struct nv50_disp_mthd_v1 base;
 438                 struct nv50_disp_sor_hda_eld_v0 eld;
 439         } args = {
 440                 .base.version = 1,
 441                 .base.method  = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
 442                 .base.hasht   = nv_encoder->dcb->hasht,
 443                 .base.hashm   = (0xf0ff & nv_encoder->dcb->hashm) |
 444                                 (0x0100 << nv_crtc->index),
 445         };
 446
 447         nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 448 }
 449
 450 static void
 451 nv50_audio_enable(struct drm_encoder *encoder, struct drm_display_mode *mode)
 452 {
 453         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 454         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 455         struct nouveau_connector *nv_connector;
 456         struct nv50_disp *disp = nv50_disp(encoder->dev);
 457         struct __packed {
 458                 struct {
 459                         struct nv50_disp_mthd_v1 mthd;
 460                         struct nv50_disp_sor_hda_eld_v0 eld;
 461                 } base;
 462                 u8 data[sizeof(nv_connector->base.eld)];
 463         } args = {
 464                 .base.mthd.version = 1,
 465                 .base.mthd.method  = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
 466                 .base.mthd.hasht   = nv_encoder->dcb->hasht,
 467                 .base.mthd.hashm   = (0xf0ff & nv_encoder->dcb->hashm) |
 468                                      (0x0100 << nv_crtc->index),
 469         };
 470
 471         nv_connector = nouveau_encoder_connector_get(nv_encoder);
 472         if (!drm_detect_monitor_audio(nv_connector->edid))
 473                 return;
 474
 475         memcpy(args.data, nv_connector->base.eld, sizeof(args.data));
 476
 477         nvif_mthd(&disp->disp->object, 0, &args,
 478                   sizeof(args.base) + drm_eld_size(args.data));
 479 }
 480
 481 /******************************************************************************
 482  * HDMI
 483  *****************************************************************************/
 484 static void
 485 nv50_hdmi_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
 486 {
 487         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 488         struct nv50_disp *disp = nv50_disp(encoder->dev);
 489         struct {
 490                 struct nv50_disp_mthd_v1 base;
 491                 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
 492         } args = {
 493                 .base.version = 1,
 494                 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
 495                 .base.hasht  = nv_encoder->dcb->hasht,
 496                 .base.hashm  = (0xf0ff & nv_encoder->dcb->hashm) |
 497                                (0x0100 << nv_crtc->index),
 498         };
 499
 500         nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 501 }
 502
 503 static void
 504 nv50_hdmi_enable(struct drm_encoder *encoder, struct drm_display_mode *mode)
 505 {
 506         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 507         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 508         struct nv50_disp *disp = nv50_disp(encoder->dev);
 509         struct {
 510                 struct nv50_disp_mthd_v1 base;
 511                 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
 512                 u8 infoframes[2 * 17]; /* two frames, up to 17 bytes each */
 513         } args = {
 514                 .base.version = 1,
 515                 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
 516                 .base.hasht  = nv_encoder->dcb->hasht,
 517                 .base.hashm  = (0xf0ff & nv_encoder->dcb->hashm) |
 518                                (0x0100 << nv_crtc->index),
 519                 .pwr.state = 1,
 520                 .pwr.rekey = 56, /* binary driver, and tegra, constant */
 521         };
 522         struct nouveau_connector *nv_connector;
 523         u32 max_ac_packet;
 524         union hdmi_infoframe avi_frame;
 525         union hdmi_infoframe vendor_frame;
 526         int ret;
 527         int size;
 528
 529         nv_connector = nouveau_encoder_connector_get(nv_encoder);
 530         if (!drm_detect_hdmi_monitor(nv_connector->edid))
 531                 return;
 532
 533         ret = drm_hdmi_avi_infoframe_from_display_mode(&avi_frame.avi, mode,
 534                                                        false);
 535         if (!ret) {
 536                 /* We have an AVI InfoFrame, populate it to the display */
 537                 args.pwr.avi_infoframe_length
 538                         = hdmi_infoframe_pack(&avi_frame, args.infoframes, 17);
 539         }
 540
 541         ret = drm_hdmi_vendor_infoframe_from_display_mode(&vendor_frame.vendor.hdmi,
 542                                                           &nv_connector->base, mode);
 543         if (!ret) {
 544                 /* We have a Vendor InfoFrame, populate it to the display */
 545                 args.pwr.vendor_infoframe_length
 546                         = hdmi_infoframe_pack(&vendor_frame,
 547                                               args.infoframes
 548                                               + args.pwr.avi_infoframe_length,
 549                                               17);
 550         }
 551
 552         max_ac_packet  = mode->htotal - mode->hdisplay;
 553         max_ac_packet -= args.pwr.rekey;
 554         max_ac_packet -= 18; /* constant from tegra */
 555         args.pwr.max_ac_packet = max_ac_packet / 32;
 556
 557         size = sizeof(args.base)
 558                 + sizeof(args.pwr)
 559                 + args.pwr.avi_infoframe_length
 560                 + args.pwr.vendor_infoframe_length;
 561         nvif_mthd(&disp->disp->object, 0, &args, size);
 562         nv50_audio_enable(encoder, mode);
 563 }
 564
 565 /******************************************************************************
 566  * MST
 567  *****************************************************************************/
 568 #define nv50_mstm(p) container_of((p), struct nv50_mstm, mgr)
 569 #define nv50_mstc(p) container_of((p), struct nv50_mstc, connector)
 570 #define nv50_msto(p) container_of((p), struct nv50_msto, encoder)
 571
 572 struct nv50_mstm {
 573         struct nouveau_encoder *outp;
 574
 575         struct drm_dp_mst_topology_mgr mgr;
 576         struct nv50_msto *msto[4];
 577
 578         bool modified;
 579         bool disabled;
 580         int links;
 581 };
 582
 583 struct nv50_mstc {
 584         struct nv50_mstm *mstm;
 585         struct drm_dp_mst_port *port;
 586         struct drm_connector connector;
 587
 588         struct drm_display_mode *native;
 589         struct edid *edid;
 590
 591         int pbn;
 592 };
 593
 594 struct nv50_msto {
 595         struct drm_encoder encoder;
 596
 597         struct nv50_head *head;
 598         struct nv50_mstc *mstc;
 599         bool disabled;
 600 };
 601
 602 static struct drm_dp_payload *
 603 nv50_msto_payload(struct nv50_msto *msto)
 604 {
 605         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
 606         struct nv50_mstc *mstc = msto->mstc;
 607         struct nv50_mstm *mstm = mstc->mstm;
 608         int vcpi = mstc->port->vcpi.vcpi, i;
 609
 610         NV_ATOMIC(drm, "%s: vcpi %d\n", msto->encoder.name, vcpi);
 611         for (i = 0; i < mstm->mgr.max_payloads; i++) {
 612                 struct drm_dp_payload *payload = &mstm->mgr.payloads[i];
 613                 NV_ATOMIC(drm, "%s: %d: vcpi %d start 0x%02x slots 0x%02x\n",
 614                           mstm->outp->base.base.name, i, payload->vcpi,
 615                           payload->start_slot, payload->num_slots);
 616         }
 617
 618         for (i = 0; i < mstm->mgr.max_payloads; i++) {
 619                 struct drm_dp_payload *payload = &mstm->mgr.payloads[i];
 620                 if (payload->vcpi == vcpi)
 621                         return payload;
 622         }
 623
 624         return NULL;
 625 }
 626
 627 static void
 628 nv50_msto_cleanup(struct nv50_msto *msto)
 629 {
 630         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
 631         struct nv50_mstc *mstc = msto->mstc;
 632         struct nv50_mstm *mstm = mstc->mstm;
 633
 634         NV_ATOMIC(drm, "%s: msto cleanup\n", msto->encoder.name);
 635         if (mstc->port && mstc->port->vcpi.vcpi > 0 && !nv50_msto_payload(msto))
 636                 drm_dp_mst_deallocate_vcpi(&mstm->mgr, mstc->port);
 637         if (msto->disabled) {
 638                 msto->mstc = NULL;
 639                 msto->head = NULL;
 640                 msto->disabled = false;
 641         }
 642 }
 643
 644 static void
 645 nv50_msto_prepare(struct nv50_msto *msto)
 646 {
 647         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
 648         struct nv50_mstc *mstc = msto->mstc;
 649         struct nv50_mstm *mstm = mstc->mstm;
 650         struct {
 651                 struct nv50_disp_mthd_v1 base;
 652                 struct nv50_disp_sor_dp_mst_vcpi_v0 vcpi;
 653         } args = {
 654                 .base.version = 1,
 655                 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_VCPI,
 656                 .base.hasht  = mstm->outp->dcb->hasht,
 657                 .base.hashm  = (0xf0ff & mstm->outp->dcb->hashm) |
 658                                (0x0100 << msto->head->base.index),
 659         };
 660
 661         NV_ATOMIC(drm, "%s: msto prepare\n", msto->encoder.name);
 662         if (mstc->port && mstc->port->vcpi.vcpi > 0) {
 663                 struct drm_dp_payload *payload = nv50_msto_payload(msto);
 664                 if (payload) {
 665                         args.vcpi.start_slot = payload->start_slot;
 666                         args.vcpi.num_slots = payload->num_slots;
 667                         args.vcpi.pbn = mstc->port->vcpi.pbn;
 668                         args.vcpi.aligned_pbn = mstc->port->vcpi.aligned_pbn;
 669                 }
 670         }
 671
 672         NV_ATOMIC(drm, "%s: %s: %02x %02x %04x %04x\n",
 673                   msto->encoder.name, msto->head->base.base.name,
 674                   args.vcpi.start_slot, args.vcpi.num_slots,
 675                   args.vcpi.pbn, args.vcpi.aligned_pbn);
 676         nvif_mthd(&drm->display->disp.object, 0, &args, sizeof(args));
 677 }
 678
 679 static int
 680 nv50_msto_atomic_check(struct drm_encoder *encoder,
 681                        struct drm_crtc_state *crtc_state,
 682                        struct drm_connector_state *conn_state)
 683 {
 684         struct nv50_mstc *mstc = nv50_mstc(conn_state->connector);
 685         struct nv50_mstm *mstm = mstc->mstm;
 686         int bpp = conn_state->connector->display_info.bpc * 3;
 687         int slots;
 688
 689         mstc->pbn = drm_dp_calc_pbn_mode(crtc_state->adjusted_mode.clock, bpp);
 690
 691         slots = drm_dp_find_vcpi_slots(&mstm->mgr, mstc->pbn);
 692         if (slots < 0)
 693                 return slots;
 694
 695         return nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
 696                                            mstc->native);
 697 }
 698
 699 static void
 700 nv50_msto_enable(struct drm_encoder *encoder)
 701 {
 702         struct nv50_head *head = nv50_head(encoder->crtc);
 703         struct nv50_msto *msto = nv50_msto(encoder);
 704         struct nv50_mstc *mstc = NULL;
 705         struct nv50_mstm *mstm = NULL;
 706         struct drm_connector *connector;
 707         struct drm_connector_list_iter conn_iter;
 708         u8 proto, depth;
 709         int slots;
 710         bool r;
 711
 712         drm_connector_list_iter_begin(encoder->dev, &conn_iter);
 713         drm_for_each_connector_iter(connector, &conn_iter) {
 714                 if (connector->state->best_encoder == &msto->encoder) {
 715                         mstc = nv50_mstc(connector);
 716                         mstm = mstc->mstm;
 717                         break;
 718                 }
 719         }
 720         drm_connector_list_iter_end(&conn_iter);
 721
 722         if (WARN_ON(!mstc))
 723                 return;
 724
 725         slots = drm_dp_find_vcpi_slots(&mstm->mgr, mstc->pbn);
 726         r = drm_dp_mst_allocate_vcpi(&mstm->mgr, mstc->port, mstc->pbn, slots);
 727         WARN_ON(!r);
 728
 729         if (!mstm->links++)
 730                 nv50_outp_acquire(mstm->outp);
 731
 732         if (mstm->outp->link & 1)
 733                 proto = 0x8;
 734         else
 735                 proto = 0x9;
 736
 737         switch (mstc->connector.display_info.bpc) {
 738         case  6: depth = 0x2; break;
 739         case  8: depth = 0x5; break;
 740         case 10:
 741         default: depth = 0x6; break;
 742         }
 743
 744         mstm->outp->update(mstm->outp, head->base.index,
 745                            nv50_head_atom(head->base.base.state), proto, depth);
 746
 747         msto->head = head;
 748         msto->mstc = mstc;
 749         mstm->modified = true;
 750 }
 751
 752 static void
 753 nv50_msto_disable(struct drm_encoder *encoder)
 754 {
 755         struct nv50_msto *msto = nv50_msto(encoder);
 756         struct nv50_mstc *mstc = msto->mstc;
 757         struct nv50_mstm *mstm = mstc->mstm;
 758
 759         if (mstc->port)
 760                 drm_dp_mst_reset_vcpi_slots(&mstm->mgr, mstc->port);
 761
 762         mstm->outp->update(mstm->outp, msto->head->base.index, NULL, 0, 0);
 763         mstm->modified = true;
 764         if (!--mstm->links)
 765                 mstm->disabled = true;
 766         msto->disabled = true;
 767 }
 768
 769 static const struct drm_encoder_helper_funcs
 770 nv50_msto_help = {
 771         .disable = nv50_msto_disable,
 772         .enable = nv50_msto_enable,
 773         .atomic_check = nv50_msto_atomic_check,
 774 };
 775
 776 static void
 777 nv50_msto_destroy(struct drm_encoder *encoder)
 778 {
 779         struct nv50_msto *msto = nv50_msto(encoder);
 780         drm_encoder_cleanup(&msto->encoder);
 781         kfree(msto);
 782 }
 783
 784 static const struct drm_encoder_funcs
 785 nv50_msto = {
 786         .destroy = nv50_msto_destroy,
 787 };
 788
 789 static int
 790 nv50_msto_new(struct drm_device *dev, u32 heads, const char *name, int id,
 791               struct nv50_msto **pmsto)
 792 {
 793         struct nv50_msto *msto;
 794         int ret;
 795
 796         if (!(msto = *pmsto = kzalloc(sizeof(*msto), GFP_KERNEL)))
 797                 return -ENOMEM;
 798
 799         ret = drm_encoder_init(dev, &msto->encoder, &nv50_msto,
 800                                DRM_MODE_ENCODER_DPMST, "%s-mst-%d", name, id);
 801         if (ret) {
 802                 kfree(*pmsto);
 803                 *pmsto = NULL;
 804                 return ret;
 805         }
 806
 807         drm_encoder_helper_add(&msto->encoder, &nv50_msto_help);
 808         msto->encoder.possible_crtcs = heads;
 809         return 0;
 810 }
 811
 812 static struct drm_encoder *
 813 nv50_mstc_atomic_best_encoder(struct drm_connector *connector,
 814                               struct drm_connector_state *connector_state)
 815 {
 816         struct nv50_head *head = nv50_head(connector_state->crtc);
 817         struct nv50_mstc *mstc = nv50_mstc(connector);
 818         if (mstc->port) {
 819                 struct nv50_mstm *mstm = mstc->mstm;
 820                 return &mstm->msto[head->base.index]->encoder;
 821         }
 822         return NULL;
 823 }
 824
 825 static struct drm_encoder *
 826 nv50_mstc_best_encoder(struct drm_connector *connector)
 827 {
 828         struct nv50_mstc *mstc = nv50_mstc(connector);
 829         if (mstc->port) {
 830                 struct nv50_mstm *mstm = mstc->mstm;
 831                 return &mstm->msto[0]->encoder;
 832         }
 833         return NULL;
 834 }
 835
 836 static enum drm_mode_status
 837 nv50_mstc_mode_valid(struct drm_connector *connector,
 838                      struct drm_display_mode *mode)
 839 {
 840         return MODE_OK;
 841 }
 842
 843 static int
 844 nv50_mstc_get_modes(struct drm_connector *connector)
 845 {
 846         struct nv50_mstc *mstc = nv50_mstc(connector);
 847         int ret = 0;
 848
 849         mstc->edid = drm_dp_mst_get_edid(&mstc->connector, mstc->port->mgr, mstc->port);
 850         drm_mode_connector_update_edid_property(&mstc->connector, mstc->edid);
 851         if (mstc->edid)
 852                 ret = drm_add_edid_modes(&mstc->connector, mstc->edid);
 853
 854         if (!mstc->connector.display_info.bpc)
 855                 mstc->connector.display_info.bpc = 8;
 856
 857         if (mstc->native)
 858                 drm_mode_destroy(mstc->connector.dev, mstc->native);
 859         mstc->native = nouveau_conn_native_mode(&mstc->connector);
 860         return ret;
 861 }
 862
 863 static const struct drm_connector_helper_funcs
 864 nv50_mstc_help = {
 865         .get_modes = nv50_mstc_get_modes,
 866         .mode_valid = nv50_mstc_mode_valid,
 867         .best_encoder = nv50_mstc_best_encoder,
 868         .atomic_best_encoder = nv50_mstc_atomic_best_encoder,
 869 };
 870
 871 static enum drm_connector_status
 872 nv50_mstc_detect(struct drm_connector *connector, bool force)
 873 {
 874         struct nv50_mstc *mstc = nv50_mstc(connector);
 875         if (!mstc->port)
 876                 return connector_status_disconnected;
 877         return drm_dp_mst_detect_port(connector, mstc->port->mgr, mstc->port);
 878 }
 879
 880 static void
 881 nv50_mstc_destroy(struct drm_connector *connector)
 882 {
 883         struct nv50_mstc *mstc = nv50_mstc(connector);
 884         drm_connector_cleanup(&mstc->connector);
 885         kfree(mstc);
 886 }
 887
 888 static const struct drm_connector_funcs
 889 nv50_mstc = {
 890         .reset = nouveau_conn_reset,
 891         .detect = nv50_mstc_detect,
 892         .fill_modes = drm_helper_probe_single_connector_modes,
 893         .destroy = nv50_mstc_destroy,
 894         .atomic_duplicate_state = nouveau_conn_atomic_duplicate_state,
 895         .atomic_destroy_state = nouveau_conn_atomic_destroy_state,
 896         .atomic_set_property = nouveau_conn_atomic_set_property,
 897         .atomic_get_property = nouveau_conn_atomic_get_property,
 898 };
 899
 900 static int
 901 nv50_mstc_new(struct nv50_mstm *mstm, struct drm_dp_mst_port *port,
 902               const char *path, struct nv50_mstc **pmstc)
 903 {
 904         struct drm_device *dev = mstm->outp->base.base.dev;
 905         struct nv50_mstc *mstc;
 906         int ret, i;
 907
 908         if (!(mstc = *pmstc = kzalloc(sizeof(*mstc), GFP_KERNEL)))
 909                 return -ENOMEM;
 910         mstc->mstm = mstm;
 911         mstc->port = port;
 912
 913         ret = drm_connector_init(dev, &mstc->connector, &nv50_mstc,
 914                                  DRM_MODE_CONNECTOR_DisplayPort);
 915         if (ret) {
 916                 kfree(*pmstc);
 917                 *pmstc = NULL;
 918                 return ret;
 919         }
 920
 921         drm_connector_helper_add(&mstc->connector, &nv50_mstc_help);
 922
 923         mstc->connector.funcs->reset(&mstc->connector);
 924         nouveau_conn_attach_properties(&mstc->connector);
 925
 926         for (i = 0; i < ARRAY_SIZE(mstm->msto) && mstm->msto[i]; i++)
 927                 drm_mode_connector_attach_encoder(&mstc->connector, &mstm->msto[i]->encoder);
 928
 929         drm_object_attach_property(&mstc->connector.base, dev->mode_config.path_property, 0);
 930         drm_object_attach_property(&mstc->connector.base, dev->mode_config.tile_property, 0);
 931         drm_mode_connector_set_path_property(&mstc->connector, path);
 932         return 0;
 933 }
 934
 935 static void
 936 nv50_mstm_cleanup(struct nv50_mstm *mstm)
 937 {
 938         struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
 939         struct drm_encoder *encoder;
 940         int ret;
 941
 942         NV_ATOMIC(drm, "%s: mstm cleanup\n", mstm->outp->base.base.name);
 943         ret = drm_dp_check_act_status(&mstm->mgr);
 944
 945         ret = drm_dp_update_payload_part2(&mstm->mgr);
 946
 947         drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
 948                 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
 949                         struct nv50_msto *msto = nv50_msto(encoder);
 950                         struct nv50_mstc *mstc = msto->mstc;
 951                         if (mstc && mstc->mstm == mstm)
 952                                 nv50_msto_cleanup(msto);
 953                 }
 954         }
 955
 956         mstm->modified = false;
 957 }
 958
 959 static void
 960 nv50_mstm_prepare(struct nv50_mstm *mstm)
 961 {
 962         struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
 963         struct drm_encoder *encoder;
 964         int ret;
 965
 966         NV_ATOMIC(drm, "%s: mstm prepare\n", mstm->outp->base.base.name);
 967         ret = drm_dp_update_payload_part1(&mstm->mgr);
 968
 969         drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
 970                 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
 971                         struct nv50_msto *msto = nv50_msto(encoder);
 972                         struct nv50_mstc *mstc = msto->mstc;
 973                         if (mstc && mstc->mstm == mstm)
 974                                 nv50_msto_prepare(msto);
 975                 }
 976         }
 977
 978         if (mstm->disabled) {
 979                 if (!mstm->links)
 980                         nv50_outp_release(mstm->outp);
 981                 mstm->disabled = false;
 982         }
 983 }
 984
 985 static void
 986 nv50_mstm_hotplug(struct drm_dp_mst_topology_mgr *mgr)
 987 {
 988         struct nv50_mstm *mstm = nv50_mstm(mgr);
 989         drm_kms_helper_hotplug_event(mstm->outp->base.base.dev);
 990 }
 991
 992 static void
 993 nv50_mstm_destroy_connector(struct drm_dp_mst_topology_mgr *mgr,
 994                             struct drm_connector *connector)
 995 {
 996         struct nouveau_drm *drm = nouveau_drm(connector->dev);
 997         struct nv50_mstc *mstc = nv50_mstc(connector);
 998
 999         drm_connector_unregister(&mstc->connector);
1000
1001         drm_fb_helper_remove_one_connector(&drm->fbcon->helper, &mstc->connector);
1002
1003         drm_modeset_lock(&drm->dev->mode_config.connection_mutex, NULL);
1004         mstc->port = NULL;
1005         drm_modeset_unlock(&drm->dev->mode_config.connection_mutex);
1006
1007         drm_connector_unreference(&mstc->connector);
1008 }
1009
1010 static void
1011 nv50_mstm_register_connector(struct drm_connector *connector)
1012 {
1013         struct nouveau_drm *drm = nouveau_drm(connector->dev);
1014
1015         drm_fb_helper_add_one_connector(&drm->fbcon->helper, connector);
1016
1017         drm_connector_register(connector);
1018 }
1019
1020 static struct drm_connector *
1021 nv50_mstm_add_connector(struct drm_dp_mst_topology_mgr *mgr,
1022                         struct drm_dp_mst_port *port, const char *path)
1023 {
1024         struct nv50_mstm *mstm = nv50_mstm(mgr);
1025         struct nv50_mstc *mstc;
1026         int ret;
1027
1028         ret = nv50_mstc_new(mstm, port, path, &mstc);
1029         if (ret) {
1030                 if (mstc)
1031                         mstc->connector.funcs->destroy(&mstc->connector);
1032                 return NULL;
1033         }
1034
1035         return &mstc->connector;
1036 }
1037
1038 static const struct drm_dp_mst_topology_cbs
1039 nv50_mstm = {
1040         .add_connector = nv50_mstm_add_connector,
1041         .register_connector = nv50_mstm_register_connector,
1042         .destroy_connector = nv50_mstm_destroy_connector,
1043         .hotplug = nv50_mstm_hotplug,
1044 };
1045
1046 void
1047 nv50_mstm_service(struct nv50_mstm *mstm)
1048 {
1049         struct drm_dp_aux *aux = mstm ? mstm->mgr.aux : NULL;
1050         bool handled = true;
1051         int ret;
1052         u8 esi[8] = {};
1053
1054         if (!aux)
1055                 return;
1056
1057         while (handled) {
1058                 ret = drm_dp_dpcd_read(aux, DP_SINK_COUNT_ESI, esi, 8);
1059                 if (ret != 8) {
1060                         drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1061                         return;
1062                 }
1063
1064                 drm_dp_mst_hpd_irq(&mstm->mgr, esi, &handled);
1065                 if (!handled)
1066                         break;
1067
1068                 drm_dp_dpcd_write(aux, DP_SINK_COUNT_ESI + 1, &esi[1], 3);
1069         }
1070 }
1071
1072 void
1073 nv50_mstm_remove(struct nv50_mstm *mstm)
1074 {
1075         if (mstm)
1076                 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1077 }
1078
1079 static int
1080 nv50_mstm_enable(struct nv50_mstm *mstm, u8 dpcd, int state)
1081 {
1082         struct nouveau_encoder *outp = mstm->outp;
1083         struct {
1084                 struct nv50_disp_mthd_v1 base;
1085                 struct nv50_disp_sor_dp_mst_link_v0 mst;
1086         } args = {
1087                 .base.version = 1,
1088                 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_LINK,
1089                 .base.hasht = outp->dcb->hasht,
1090                 .base.hashm = outp->dcb->hashm,
1091                 .mst.state = state,
1092         };
1093         struct nouveau_drm *drm = nouveau_drm(outp->base.base.dev);
1094         struct nvif_object *disp = &drm->display->disp.object;
1095         int ret;
1096
1097         if (dpcd >= 0x12) {
1098                 ret = drm_dp_dpcd_readb(mstm->mgr.aux, DP_MSTM_CTRL, &dpcd);
1099                 if (ret < 0)
1100                         return ret;
1101
1102                 dpcd &= ~DP_MST_EN;
1103                 if (state)
1104                         dpcd |= DP_MST_EN;
1105
1106                 ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL, dpcd);
1107                 if (ret < 0)
1108                         return ret;
1109         }
1110
1111         return nvif_mthd(disp, 0, &args, sizeof(args));
1112 }
1113
1114 int
1115 nv50_mstm_detect(struct nv50_mstm *mstm, u8 dpcd[8], int allow)
1116 {
1117         int ret, state = 0;
1118
1119         if (!mstm)
1120                 return 0;
1121
1122         if (dpcd[0] >= 0x12) {
1123                 ret = drm_dp_dpcd_readb(mstm->mgr.aux, DP_MSTM_CAP, &dpcd[1]);
1124                 if (ret < 0)
1125                         return ret;
1126
1127                 if (!(dpcd[1] & DP_MST_CAP))
1128                         dpcd[0] = 0x11;
1129                 else
1130                         state = allow;
1131         }
1132
1133         ret = nv50_mstm_enable(mstm, dpcd[0], state);
1134         if (ret)
1135                 return ret;
1136
1137         ret = drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, state);
1138         if (ret)
1139                 return nv50_mstm_enable(mstm, dpcd[0], 0);
1140
1141         return mstm->mgr.mst_state;
1142 }
1143
1144 static void
1145 nv50_mstm_fini(struct nv50_mstm *mstm)
1146 {
1147         if (mstm && mstm->mgr.mst_state)
1148                 drm_dp_mst_topology_mgr_suspend(&mstm->mgr);
1149 }
1150
1151 static void
1152 nv50_mstm_init(struct nv50_mstm *mstm)
1153 {
1154         if (mstm && mstm->mgr.mst_state)
1155                 drm_dp_mst_topology_mgr_resume(&mstm->mgr);
1156 }
1157
1158 static void
1159 nv50_mstm_del(struct nv50_mstm **pmstm)
1160 {
1161         struct nv50_mstm *mstm = *pmstm;
1162         if (mstm) {
1163                 kfree(*pmstm);
1164                 *pmstm = NULL;
1165         }
1166 }
1167
1168 static int
1169 nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max,
1170               int conn_base_id, struct nv50_mstm **pmstm)
1171 {
1172         const int max_payloads = hweight8(outp->dcb->heads);
1173         struct drm_device *dev = outp->base.base.dev;
1174         struct nv50_mstm *mstm;
1175         int ret, i;
1176         u8 dpcd;
1177
1178         /* This is a workaround for some monitors not functioning
1179          * correctly in MST mode on initial module load.  I think
1180          * some bad interaction with the VBIOS may be responsible.
1181          *
1182          * A good ol' off and on again seems to work here ;)
1183          */
1184         ret = drm_dp_dpcd_readb(aux, DP_DPCD_REV, &dpcd);
1185         if (ret >= 0 && dpcd >= 0x12)
1186                 drm_dp_dpcd_writeb(aux, DP_MSTM_CTRL, 0);
1187
1188         if (!(mstm = *pmstm = kzalloc(sizeof(*mstm), GFP_KERNEL)))
1189                 return -ENOMEM;
1190         mstm->outp = outp;
1191         mstm->mgr.cbs = &nv50_mstm;
1192
1193         ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max,
1194                                            max_payloads, conn_base_id);
1195         if (ret)
1196                 return ret;
1197
1198         for (i = 0; i < max_payloads; i++) {
1199                 ret = nv50_msto_new(dev, outp->dcb->heads, outp->base.base.name,
1200                                     i, &mstm->msto[i]);
1201                 if (ret)
1202                         return ret;
1203         }
1204
1205         return 0;
1206 }
1207
1208 /******************************************************************************
1209  * SOR
1210  *****************************************************************************/
1211 static void
1212 nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head,
1213                 struct nv50_head_atom *asyh, u8 proto, u8 depth)
1214 {
1215         struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev);
1216         struct nv50_core *core = disp->core;
1217
1218         if (!asyh) {
1219                 nv_encoder->ctrl &= ~BIT(head);
1220                 if (!(nv_encoder->ctrl & 0x0000000f))
1221                         nv_encoder->ctrl = 0;
1222         } else {
1223                 nv_encoder->ctrl |= proto << 8;
1224                 nv_encoder->ctrl |= BIT(head);
1225                 asyh->or.depth = depth;
1226         }
1227
1228         core->func->sor->ctrl(core, nv_encoder->or, nv_encoder->ctrl, asyh);
1229 }
1230
1231 static void
1232 nv50_sor_disable(struct drm_encoder *encoder)
1233 {
1234         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1235         struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
1236
1237         nv_encoder->crtc = NULL;
1238
1239         if (nv_crtc) {
1240                 struct nvkm_i2c_aux *aux = nv_encoder->aux;
1241                 u8 pwr;
1242
1243                 if (aux) {
1244                         int ret = nvkm_rdaux(aux, DP_SET_POWER, &pwr, 1);
1245                         if (ret == 0) {
1246                                 pwr &= ~DP_SET_POWER_MASK;
1247                                 pwr |=  DP_SET_POWER_D3;
1248                                 nvkm_wraux(aux, DP_SET_POWER, &pwr, 1);
1249                         }
1250                 }
1251
1252                 nv_encoder->update(nv_encoder, nv_crtc->index, NULL, 0, 0);
1253                 nv50_audio_disable(encoder, nv_crtc);
1254                 nv50_hdmi_disable(&nv_encoder->base.base, nv_crtc);
1255                 nv50_outp_release(nv_encoder);
1256         }
1257 }
1258
1259 static void
1260 nv50_sor_enable(struct drm_encoder *encoder)
1261 {
1262         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1263         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1264         struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
1265         struct drm_display_mode *mode = &asyh->state.adjusted_mode;
1266         struct {
1267                 struct nv50_disp_mthd_v1 base;
1268                 struct nv50_disp_sor_lvds_script_v0 lvds;
1269         } lvds = {
1270                 .base.version = 1,
1271                 .base.method  = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT,
1272                 .base.hasht   = nv_encoder->dcb->hasht,
1273                 .base.hashm   = nv_encoder->dcb->hashm,
1274         };
1275         struct nv50_disp *disp = nv50_disp(encoder->dev);
1276         struct drm_device *dev = encoder->dev;
1277         struct nouveau_drm *drm = nouveau_drm(dev);
1278         struct nouveau_connector *nv_connector;
1279         struct nvbios *bios = &drm->vbios;
1280         u8 proto = 0xf;
1281         u8 depth = 0x0;
1282
1283         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1284         nv_encoder->crtc = encoder->crtc;
1285         nv50_outp_acquire(nv_encoder);
1286
1287         switch (nv_encoder->dcb->type) {
1288         case DCB_OUTPUT_TMDS:
1289                 if (nv_encoder->link & 1) {
1290                         proto = 0x1;
1291                         /* Only enable dual-link if:
1292                          *  - Need to (i.e. rate > 165MHz)
1293                          *  - DCB says we can
1294                          *  - Not an HDMI monitor, since there's no dual-link
1295                          *    on HDMI.
1296                          */
1297                         if (mode->clock >= 165000 &&
1298                             nv_encoder->dcb->duallink_possible &&
1299                             !drm_detect_hdmi_monitor(nv_connector->edid))
1300                                 proto |= 0x4;
1301                 } else {
1302                         proto = 0x2;
1303                 }
1304
1305                 nv50_hdmi_enable(&nv_encoder->base.base, mode);
1306                 break;
1307         case DCB_OUTPUT_LVDS:
1308                 proto = 0x0;
1309
1310                 if (bios->fp_no_ddc) {
1311                         if (bios->fp.dual_link)
1312                                 lvds.lvds.script |= 0x0100;
1313                         if (bios->fp.if_is_24bit)
1314                                 lvds.lvds.script |= 0x0200;
1315                 } else {
1316                         if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
1317                                 if (((u8 *)nv_connector->edid)[121] == 2)
1318                                         lvds.lvds.script |= 0x0100;
1319                         } else
1320                         if (mode->clock >= bios->fp.duallink_transition_clk) {
1321                                 lvds.lvds.script |= 0x0100;
1322                         }
1323
1324                         if (lvds.lvds.script & 0x0100) {
1325                                 if (bios->fp.strapless_is_24bit & 2)
1326                                         lvds.lvds.script |= 0x0200;
1327                         } else {
1328                                 if (bios->fp.strapless_is_24bit & 1)
1329                                         lvds.lvds.script |= 0x0200;
1330                         }
1331
1332                         if (nv_connector->base.display_info.bpc == 8)
1333                                 lvds.lvds.script |= 0x0200;
1334                 }
1335
1336                 nvif_mthd(&disp->disp->object, 0, &lvds, sizeof(lvds));
1337                 break;
1338         case DCB_OUTPUT_DP:
1339                 if (nv_connector->base.display_info.bpc == 6)
1340                         depth = 0x2;
1341                 else
1342                 if (nv_connector->base.display_info.bpc == 8)
1343                         depth = 0x5;
1344                 else
1345                         depth = 0x6;
1346
1347                 if (nv_encoder->link & 1)
1348                         proto = 0x8;
1349                 else
1350                         proto = 0x9;
1351
1352                 nv50_audio_enable(encoder, mode);
1353                 break;
1354         default:
1355                 BUG();
1356                 break;
1357         }
1358
1359         nv_encoder->update(nv_encoder, nv_crtc->index, asyh, proto, depth);
1360 }
1361
1362 static const struct drm_encoder_helper_funcs
1363 nv50_sor_help = {
1364         .atomic_check = nv50_outp_atomic_check,
1365         .enable = nv50_sor_enable,
1366         .disable = nv50_sor_disable,
1367 };
1368
1369 static void
1370 nv50_sor_destroy(struct drm_encoder *encoder)
1371 {
1372         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1373         nv50_mstm_del(&nv_encoder->dp.mstm);
1374         drm_encoder_cleanup(encoder);
1375         kfree(encoder);
1376 }
1377
1378 static const struct drm_encoder_funcs
1379 nv50_sor_func = {
1380         .destroy = nv50_sor_destroy,
1381 };
1382
1383 static int
1384 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe)
1385 {
1386         struct nouveau_connector *nv_connector = nouveau_connector(connector);
1387         struct nouveau_drm *drm = nouveau_drm(connector->dev);
1388         struct nvkm_bios *bios = nvxx_bios(&drm->client.device);
1389         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
1390         struct nouveau_encoder *nv_encoder;
1391         struct drm_encoder *encoder;
1392         u8 ver, hdr, cnt, len;
1393         u32 data;
1394         int type, ret;
1395
1396         switch (dcbe->type) {
1397         case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break;
1398         case DCB_OUTPUT_TMDS:
1399         case DCB_OUTPUT_DP:
1400         default:
1401                 type = DRM_MODE_ENCODER_TMDS;
1402                 break;
1403         }
1404
1405         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1406         if (!nv_encoder)
1407                 return -ENOMEM;
1408         nv_encoder->dcb = dcbe;
1409         nv_encoder->update = nv50_sor_update;
1410
1411         encoder = to_drm_encoder(nv_encoder);
1412         encoder->possible_crtcs = dcbe->heads;
1413         encoder->possible_clones = 0;
1414         drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type,
1415                          "sor-%04x-%04x", dcbe->hasht, dcbe->hashm);
1416         drm_encoder_helper_add(encoder, &nv50_sor_help);
1417
1418         drm_mode_connector_attach_encoder(connector, encoder);
1419
1420         if (dcbe->type == DCB_OUTPUT_DP) {
1421                 struct nv50_disp *disp = nv50_disp(encoder->dev);
1422                 struct nvkm_i2c_aux *aux =
1423                         nvkm_i2c_aux_find(i2c, dcbe->i2c_index);
1424                 if (aux) {
1425                         if (disp->disp->object.oclass < GF110_DISP) {
1426                                 /* HW has no support for address-only
1427                                  * transactions, so we're required to
1428                                  * use custom I2C-over-AUX code.
1429                                  */
1430                                 nv_encoder->i2c = &aux->i2c;
1431                         } else {
1432                                 nv_encoder->i2c = &nv_connector->aux.ddc;
1433                         }
1434                         nv_encoder->aux = aux;
1435                 }
1436
1437                 if ((data = nvbios_dp_table(bios, &ver, &hdr, &cnt, &len)) &&
1438                     ver >= 0x40 && (nvbios_rd08(bios, data + 0x08) & 0x04)) {
1439                         ret = nv50_mstm_new(nv_encoder, &nv_connector->aux, 16,
1440                                             nv_connector->base.base.id,
1441                                             &nv_encoder->dp.mstm);
1442                         if (ret)
1443                                 return ret;
1444                 }
1445         } else {
1446                 struct nvkm_i2c_bus *bus =
1447                         nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
1448                 if (bus)
1449                         nv_encoder->i2c = &bus->i2c;
1450         }
1451
1452         return 0;
1453 }
1454
1455 /******************************************************************************
1456  * PIOR
1457  *****************************************************************************/
1458 static int
1459 nv50_pior_atomic_check(struct drm_encoder *encoder,
1460                        struct drm_crtc_state *crtc_state,
1461                        struct drm_connector_state *conn_state)
1462 {
1463         int ret = nv50_outp_atomic_check(encoder, crtc_state, conn_state);
1464         if (ret)
1465                 return ret;
1466         crtc_state->adjusted_mode.clock *= 2;
1467         return 0;
1468 }
1469
1470 static void
1471 nv50_pior_disable(struct drm_encoder *encoder)
1472 {
1473         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1474         struct nv50_core *core = nv50_disp(encoder->dev)->core;
1475         if (nv_encoder->crtc)
1476                 core->func->pior->ctrl(core, nv_encoder->or, 0x00000000, NULL);
1477         nv_encoder->crtc = NULL;
1478         nv50_outp_release(nv_encoder);
1479 }
1480
1481 static void
1482 nv50_pior_enable(struct drm_encoder *encoder)
1483 {
1484         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1485         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1486         struct nouveau_connector *nv_connector;
1487         struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
1488         struct nv50_core *core = nv50_disp(encoder->dev)->core;
1489         u8 owner = 1 << nv_crtc->index;
1490         u8 proto;
1491
1492         nv50_outp_acquire(nv_encoder);
1493
1494         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1495         switch (nv_connector->base.display_info.bpc) {
1496         case 10: asyh->or.depth = 0x6; break;
1497         case  8: asyh->or.depth = 0x5; break;
1498         case  6: asyh->or.depth = 0x2; break;
1499         default: asyh->or.depth = 0x0; break;
1500         }
1501
1502         switch (nv_encoder->dcb->type) {
1503         case DCB_OUTPUT_TMDS:
1504         case DCB_OUTPUT_DP:
1505                 proto = 0x0;
1506                 break;
1507         default:
1508                 BUG();
1509                 break;
1510         }
1511
1512         core->func->pior->ctrl(core, nv_encoder->or, (proto << 8) | owner, asyh);
1513         nv_encoder->crtc = encoder->crtc;
1514 }
1515
1516 static const struct drm_encoder_helper_funcs
1517 nv50_pior_help = {
1518         .atomic_check = nv50_pior_atomic_check,
1519         .enable = nv50_pior_enable,
1520         .disable = nv50_pior_disable,
1521 };
1522
1523 static void
1524 nv50_pior_destroy(struct drm_encoder *encoder)
1525 {
1526         drm_encoder_cleanup(encoder);
1527         kfree(encoder);
1528 }
1529
1530 static const struct drm_encoder_funcs
1531 nv50_pior_func = {
1532         .destroy = nv50_pior_destroy,
1533 };
1534
1535 static int
1536 nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe)
1537 {
1538         struct nouveau_drm *drm = nouveau_drm(connector->dev);
1539         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
1540         struct nvkm_i2c_bus *bus = NULL;
1541         struct nvkm_i2c_aux *aux = NULL;
1542         struct i2c_adapter *ddc;
1543         struct nouveau_encoder *nv_encoder;
1544         struct drm_encoder *encoder;
1545         int type;
1546
1547         switch (dcbe->type) {
1548         case DCB_OUTPUT_TMDS:
1549                 bus  = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_EXT(dcbe->extdev));
1550                 ddc  = bus ? &bus->i2c : NULL;
1551                 type = DRM_MODE_ENCODER_TMDS;
1552                 break;
1553         case DCB_OUTPUT_DP:
1554                 aux  = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbe->extdev));
1555                 ddc  = aux ? &aux->i2c : NULL;
1556                 type = DRM_MODE_ENCODER_TMDS;
1557                 break;
1558         default:
1559                 return -ENODEV;
1560         }
1561
1562         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1563         if (!nv_encoder)
1564                 return -ENOMEM;
1565         nv_encoder->dcb = dcbe;
1566         nv_encoder->i2c = ddc;
1567         nv_encoder->aux = aux;
1568
1569         encoder = to_drm_encoder(nv_encoder);
1570         encoder->possible_crtcs = dcbe->heads;
1571         encoder->possible_clones = 0;
1572         drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type,
1573                          "pior-%04x-%04x", dcbe->hasht, dcbe->hashm);
1574         drm_encoder_helper_add(encoder, &nv50_pior_help);
1575
1576         drm_mode_connector_attach_encoder(connector, encoder);
1577         return 0;
1578 }
1579
1580 /******************************************************************************
1581  * Atomic
1582  *****************************************************************************/
1583
1584 static void
1585 nv50_disp_atomic_commit_core(struct nouveau_drm *drm, u32 *interlock)
1586 {
1587         struct nv50_disp *disp = nv50_disp(drm->dev);
1588         struct nv50_core *core = disp->core;
1589         struct nv50_mstm *mstm;
1590         struct drm_encoder *encoder;
1591
1592         NV_ATOMIC(drm, "commit core %08x\n", interlock[NV50_DISP_INTERLOCK_BASE]);
1593
1594         drm_for_each_encoder(encoder, drm->dev) {
1595                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
1596                         mstm = nouveau_encoder(encoder)->dp.mstm;
1597                         if (mstm && mstm->modified)
1598                                 nv50_mstm_prepare(mstm);
1599                 }
1600         }
1601
1602         core->func->ntfy_init(disp->sync, NV50_DISP_CORE_NTFY);
1603         core->func->update(core, interlock, true);
1604         if (core->func->ntfy_wait_done(disp->sync, NV50_DISP_CORE_NTFY,
1605                                        disp->core->chan.base.device))
1606                 NV_ERROR(drm, "core notifier timeout\n");
1607
1608         drm_for_each_encoder(encoder, drm->dev) {
1609                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
1610                         mstm = nouveau_encoder(encoder)->dp.mstm;
1611                         if (mstm && mstm->modified)
1612                                 nv50_mstm_cleanup(mstm);
1613                 }
1614         }
1615 }
1616
1617 static void
1618 nv50_disp_atomic_commit_tail(struct drm_atomic_state *state)
1619 {
1620         struct drm_device *dev = state->dev;
1621         struct drm_crtc_state *new_crtc_state, *old_crtc_state;
1622         struct drm_crtc *crtc;
1623         struct drm_plane_state *new_plane_state;
1624         struct drm_plane *plane;
1625         struct nouveau_drm *drm = nouveau_drm(dev);
1626         struct nv50_disp *disp = nv50_disp(dev);
1627         struct nv50_atom *atom = nv50_atom(state);
1628         struct nv50_outp_atom *outp, *outt;
1629         u32 interlock[NV50_DISP_INTERLOCK__SIZE] = {};
1630         int i;
1631
1632         NV_ATOMIC(drm, "commit %d %d\n", atom->lock_core, atom->flush_disable);
1633         drm_atomic_helper_wait_for_fences(dev, state, false);
1634         drm_atomic_helper_wait_for_dependencies(state);
1635         drm_atomic_helper_update_legacy_modeset_state(dev, state);
1636
1637         if (atom->lock_core)
1638                 mutex_lock(&disp->mutex);
1639
1640         /* Disable head(s). */
1641         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
1642                 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
1643                 struct nv50_head *head = nv50_head(crtc);
1644
1645                 NV_ATOMIC(drm, "%s: clr %04x (set %04x)\n", crtc->name,
1646                           asyh->clr.mask, asyh->set.mask);
1647                 if (old_crtc_state->active && !new_crtc_state->active)
1648                         drm_crtc_vblank_off(crtc);
1649
1650                 if (asyh->clr.mask) {
1651                         nv50_head_flush_clr(head, asyh, atom->flush_disable);
1652                         interlock[NV50_DISP_INTERLOCK_CORE] |= 1;
1653                 }
1654         }
1655
1656         /* Disable plane(s). */
1657         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1658                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
1659                 struct nv50_wndw *wndw = nv50_wndw(plane);
1660
1661                 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", plane->name,
1662                           asyw->clr.mask, asyw->set.mask);
1663                 if (!asyw->clr.mask)
1664                         continue;
1665
1666                 nv50_wndw_flush_clr(wndw, interlock, atom->flush_disable, asyw);
1667         }
1668
1669         /* Disable output path(s). */
1670         list_for_each_entry(outp, &atom->outp, head) {
1671                 const struct drm_encoder_helper_funcs *help;
1672                 struct drm_encoder *encoder;
1673
1674                 encoder = outp->encoder;
1675                 help = encoder->helper_private;
1676
1677                 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", encoder->name,
1678                           outp->clr.mask, outp->set.mask);
1679
1680                 if (outp->clr.mask) {
1681                         help->disable(encoder);
1682                         interlock[NV50_DISP_INTERLOCK_CORE] |= 1;
1683                         if (outp->flush_disable) {
1684                                 nv50_disp_atomic_commit_core(drm, interlock);
1685                                 memset(interlock, 0x00, sizeof(interlock));
1686                         }
1687                 }
1688         }
1689
1690         /* Flush disable. */
1691         if (interlock[NV50_DISP_INTERLOCK_CORE]) {
1692                 if (atom->flush_disable) {
1693                         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1694                                 struct nv50_wndw *wndw = nv50_wndw(plane);
1695                                 if (interlock[wndw->interlock.type] & wndw->interlock.data) {
1696                                         if (wndw->func->update)
1697                                                 wndw->func->update(wndw, interlock);
1698                                 }
1699                         }
1700
1701                         nv50_disp_atomic_commit_core(drm, interlock);
1702                         memset(interlock, 0x00, sizeof(interlock));
1703                 }
1704         }
1705
1706         /* Update output path(s). */
1707         list_for_each_entry_safe(outp, outt, &atom->outp, head) {
1708                 const struct drm_encoder_helper_funcs *help;
1709                 struct drm_encoder *encoder;
1710
1711                 encoder = outp->encoder;
1712                 help = encoder->helper_private;
1713
1714                 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", encoder->name,
1715                           outp->set.mask, outp->clr.mask);
1716
1717                 if (outp->set.mask) {
1718                         help->enable(encoder);
1719                         interlock[NV50_DISP_INTERLOCK_CORE] = 1;
1720                 }
1721
1722                 list_del(&outp->head);
1723                 kfree(outp);
1724         }
1725
1726         /* Update head(s). */
1727         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
1728                 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
1729                 struct nv50_head *head = nv50_head(crtc);
1730
1731                 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name,
1732                           asyh->set.mask, asyh->clr.mask);
1733
1734                 if (asyh->set.mask) {
1735                         nv50_head_flush_set(head, asyh);
1736                         interlock[NV50_DISP_INTERLOCK_CORE] = 1;
1737                 }
1738
1739                 if (new_crtc_state->active) {
1740                         if (!old_crtc_state->active)
1741                                 drm_crtc_vblank_on(crtc);
1742                         if (new_crtc_state->event)
1743                                 drm_crtc_vblank_get(crtc);
1744                 }
1745         }
1746
1747         /* Update plane(s). */
1748         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1749                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
1750                 struct nv50_wndw *wndw = nv50_wndw(plane);
1751
1752                 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", plane->name,
1753                           asyw->set.mask, asyw->clr.mask);
1754                 if ( !asyw->set.mask &&
1755                     (!asyw->clr.mask || atom->flush_disable))
1756                         continue;
1757
1758                 nv50_wndw_flush_set(wndw, interlock, asyw);
1759         }
1760
1761         /* Flush update. */
1762         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1763                 struct nv50_wndw *wndw = nv50_wndw(plane);
1764                 if (interlock[wndw->interlock.type] & wndw->interlock.data) {
1765                         if (wndw->func->update)
1766                                 wndw->func->update(wndw, interlock);
1767                 }
1768         }
1769
1770         if (interlock[NV50_DISP_INTERLOCK_CORE]) {
1771                 if (interlock[NV50_DISP_INTERLOCK_BASE] ||
1772                     !atom->state.legacy_cursor_update)
1773                         nv50_disp_atomic_commit_core(drm, interlock);
1774                 else
1775                         disp->core->func->update(disp->core, interlock, false);
1776         }
1777
1778         if (atom->lock_core)
1779                 mutex_unlock(&disp->mutex);
1780
1781         /* Wait for HW to signal completion. */
1782         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1783                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
1784                 struct nv50_wndw *wndw = nv50_wndw(plane);
1785                 int ret = nv50_wndw_wait_armed(wndw, asyw);
1786                 if (ret)
1787                         NV_ERROR(drm, "%s: timeout\n", plane->name);
1788         }
1789
1790         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
1791                 if (new_crtc_state->event) {
1792                         unsigned long flags;
1793                         /* Get correct count/ts if racing with vblank irq */
1794                         if (new_crtc_state->active)
1795                                 drm_crtc_accurate_vblank_count(crtc);
1796                         spin_lock_irqsave(&crtc->dev->event_lock, flags);
1797                         drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
1798                         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
1799
1800                         new_crtc_state->event = NULL;
1801                         if (new_crtc_state->active)
1802                                 drm_crtc_vblank_put(crtc);
1803                 }
1804         }
1805
1806         drm_atomic_helper_commit_hw_done(state);
1807         drm_atomic_helper_cleanup_planes(dev, state);
1808         drm_atomic_helper_commit_cleanup_done(state);
1809         drm_atomic_state_put(state);
1810 }
1811
1812 static void
1813 nv50_disp_atomic_commit_work(struct work_struct *work)
1814 {
1815         struct drm_atomic_state *state =
1816                 container_of(work, typeof(*state), commit_work);
1817         nv50_disp_atomic_commit_tail(state);
1818 }
1819
1820 static int
1821 nv50_disp_atomic_commit(struct drm_device *dev,
1822                         struct drm_atomic_state *state, bool nonblock)
1823 {
1824         struct nouveau_drm *drm = nouveau_drm(dev);
1825         struct drm_plane_state *new_plane_state;
1826         struct drm_plane *plane;
1827         struct drm_crtc *crtc;
1828         bool active = false;
1829         int ret, i;
1830
1831         ret = pm_runtime_get_sync(dev->dev);
1832         if (ret < 0 && ret != -EACCES)
1833                 return ret;
1834
1835         ret = drm_atomic_helper_setup_commit(state, nonblock);
1836         if (ret)
1837                 goto done;
1838
1839         INIT_WORK(&state->commit_work, nv50_disp_atomic_commit_work);
1840
1841         ret = drm_atomic_helper_prepare_planes(dev, state);
1842         if (ret)
1843                 goto done;
1844
1845         if (!nonblock) {
1846                 ret = drm_atomic_helper_wait_for_fences(dev, state, true);
1847                 if (ret)
1848                         goto err_cleanup;
1849         }
1850
1851         ret = drm_atomic_helper_swap_state(state, true);
1852         if (ret)
1853                 goto err_cleanup;
1854
1855         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1856                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
1857                 struct nv50_wndw *wndw = nv50_wndw(plane);
1858
1859                 if (asyw->set.image)
1860                         nv50_wndw_ntfy_enable(wndw, asyw);
1861         }
1862
1863         drm_atomic_state_get(state);
1864
1865         if (nonblock)
1866                 queue_work(system_unbound_wq, &state->commit_work);
1867         else
1868                 nv50_disp_atomic_commit_tail(state);
1869
1870         drm_for_each_crtc(crtc, dev) {
1871                 if (crtc->state->enable) {
1872                         if (!drm->have_disp_power_ref) {
1873                                 drm->have_disp_power_ref = true;
1874                                 return 0;
1875                         }
1876                         active = true;
1877                         break;
1878                 }
1879         }
1880
1881         if (!active && drm->have_disp_power_ref) {
1882                 pm_runtime_put_autosuspend(dev->dev);
1883                 drm->have_disp_power_ref = false;
1884         }
1885
1886 err_cleanup:
1887         if (ret)
1888                 drm_atomic_helper_cleanup_planes(dev, state);
1889 done:
1890         pm_runtime_put_autosuspend(dev->dev);
1891         return ret;
1892 }
1893
1894 static struct nv50_outp_atom *
1895 nv50_disp_outp_atomic_add(struct nv50_atom *atom, struct drm_encoder *encoder)
1896 {
1897         struct nv50_outp_atom *outp;
1898
1899         list_for_each_entry(outp, &atom->outp, head) {
1900                 if (outp->encoder == encoder)
1901                         return outp;
1902         }
1903
1904         outp = kzalloc(sizeof(*outp), GFP_KERNEL);
1905         if (!outp)
1906                 return ERR_PTR(-ENOMEM);
1907
1908         list_add(&outp->head, &atom->outp);
1909         outp->encoder = encoder;
1910         return outp;
1911 }
1912
1913 static int
1914 nv50_disp_outp_atomic_check_clr(struct nv50_atom *atom,
1915                                 struct drm_connector_state *old_connector_state)
1916 {
1917         struct drm_encoder *encoder = old_connector_state->best_encoder;
1918         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
1919         struct drm_crtc *crtc;
1920         struct nv50_outp_atom *outp;
1921
1922         if (!(crtc = old_connector_state->crtc))
1923                 return 0;
1924
1925         old_crtc_state = drm_atomic_get_old_crtc_state(&atom->state, crtc);
1926         new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
1927         if (old_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
1928                 outp = nv50_disp_outp_atomic_add(atom, encoder);
1929                 if (IS_ERR(outp))
1930                         return PTR_ERR(outp);
1931
1932                 if (outp->encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
1933                         outp->flush_disable = true;
1934                         atom->flush_disable = true;
1935                 }
1936                 outp->clr.ctrl = true;
1937                 atom->lock_core = true;
1938         }
1939
1940         return 0;
1941 }
1942
1943 static int
1944 nv50_disp_outp_atomic_check_set(struct nv50_atom *atom,
1945                                 struct drm_connector_state *connector_state)
1946 {
1947         struct drm_encoder *encoder = connector_state->best_encoder;
1948         struct drm_crtc_state *new_crtc_state;
1949         struct drm_crtc *crtc;
1950         struct nv50_outp_atom *outp;
1951
1952         if (!(crtc = connector_state->crtc))
1953                 return 0;
1954
1955         new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
1956         if (new_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
1957                 outp = nv50_disp_outp_atomic_add(atom, encoder);
1958                 if (IS_ERR(outp))
1959                         return PTR_ERR(outp);
1960
1961                 outp->set.ctrl = true;
1962                 atom->lock_core = true;
1963         }
1964
1965         return 0;
1966 }
1967
1968 static int
1969 nv50_disp_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
1970 {
1971         struct nv50_atom *atom = nv50_atom(state);
1972         struct drm_connector_state *old_connector_state, *new_connector_state;
1973         struct drm_connector *connector;
1974         int ret, i;
1975
1976         ret = drm_atomic_helper_check(dev, state);
1977         if (ret)
1978                 return ret;
1979
1980         for_each_oldnew_connector_in_state(state, connector, old_connector_state, new_connector_state, i) {
1981                 ret = nv50_disp_outp_atomic_check_clr(atom, old_connector_state);
1982                 if (ret)
1983                         return ret;
1984
1985                 ret = nv50_disp_outp_atomic_check_set(atom, new_connector_state);
1986                 if (ret)
1987                         return ret;
1988         }
1989
1990         return 0;
1991 }
1992
1993 static void
1994 nv50_disp_atomic_state_clear(struct drm_atomic_state *state)
1995 {
1996         struct nv50_atom *atom = nv50_atom(state);
1997         struct nv50_outp_atom *outp, *outt;
1998
1999         list_for_each_entry_safe(outp, outt, &atom->outp, head) {
2000                 list_del(&outp->head);
2001                 kfree(outp);
2002         }
2003
2004         drm_atomic_state_default_clear(state);
2005 }
2006
2007 static void
2008 nv50_disp_atomic_state_free(struct drm_atomic_state *state)
2009 {
2010         struct nv50_atom *atom = nv50_atom(state);
2011         drm_atomic_state_default_release(&atom->state);
2012         kfree(atom);
2013 }
2014
2015 static struct drm_atomic_state *
2016 nv50_disp_atomic_state_alloc(struct drm_device *dev)
2017 {
2018         struct nv50_atom *atom;
2019         if (!(atom = kzalloc(sizeof(*atom), GFP_KERNEL)) ||
2020             drm_atomic_state_init(dev, &atom->state) < 0) {
2021                 kfree(atom);
2022                 return NULL;
2023         }
2024         INIT_LIST_HEAD(&atom->outp);
2025         return &atom->state;
2026 }
2027
2028 static const struct drm_mode_config_funcs
2029 nv50_disp_func = {
2030         .fb_create = nouveau_user_framebuffer_create,
2031         .output_poll_changed = drm_fb_helper_output_poll_changed,
2032         .atomic_check = nv50_disp_atomic_check,
2033         .atomic_commit = nv50_disp_atomic_commit,
2034         .atomic_state_alloc = nv50_disp_atomic_state_alloc,
2035         .atomic_state_clear = nv50_disp_atomic_state_clear,
2036         .atomic_state_free = nv50_disp_atomic_state_free,
2037 };
2038
2039 /******************************************************************************
2040  * Init
2041  *****************************************************************************/
2042
2043 void
2044 nv50_display_fini(struct drm_device *dev)
2045 {
2046         struct nouveau_encoder *nv_encoder;
2047         struct drm_encoder *encoder;
2048         struct drm_plane *plane;
2049
2050         drm_for_each_plane(plane, dev) {
2051                 struct nv50_wndw *wndw = nv50_wndw(plane);
2052                 if (plane->funcs != &nv50_wndw)
2053                         continue;
2054                 nv50_wndw_fini(wndw);
2055         }
2056
2057         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2058                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2059                         nv_encoder = nouveau_encoder(encoder);
2060                         nv50_mstm_fini(nv_encoder->dp.mstm);
2061                 }
2062         }
2063 }
2064
2065 int
2066 nv50_display_init(struct drm_device *dev)
2067 {
2068         struct nv50_core *core = nv50_disp(dev)->core;
2069         struct drm_encoder *encoder;
2070         struct drm_plane *plane;
2071
2072         core->func->init(core);
2073
2074         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2075                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2076                         struct nouveau_encoder *nv_encoder =
2077                                 nouveau_encoder(encoder);
2078                         nv50_mstm_init(nv_encoder->dp.mstm);
2079                 }
2080         }
2081
2082         drm_for_each_plane(plane, dev) {
2083                 struct nv50_wndw *wndw = nv50_wndw(plane);
2084                 if (plane->funcs != &nv50_wndw)
2085                         continue;
2086                 nv50_wndw_init(wndw);
2087         }
2088
2089         return 0;
2090 }
2091
2092 void
2093 nv50_display_destroy(struct drm_device *dev)
2094 {
2095         struct nv50_disp *disp = nv50_disp(dev);
2096
2097         nv50_core_del(&disp->core);
2098
2099         nouveau_bo_unmap(disp->sync);
2100         if (disp->sync)
2101                 nouveau_bo_unpin(disp->sync);
2102         nouveau_bo_ref(NULL, &disp->sync);
2103
2104         nouveau_display(dev)->priv = NULL;
2105         kfree(disp);
2106 }
2107
2108 MODULE_PARM_DESC(atomic, "Expose atomic ioctl (default: disabled)");
2109 static int nouveau_atomic = 0;
2110 module_param_named(atomic, nouveau_atomic, int, 0400);
2111
2112 int
2113 nv50_display_create(struct drm_device *dev)
2114 {
2115         struct nvif_device *device = &nouveau_drm(dev)->client.device;
2116         struct nouveau_drm *drm = nouveau_drm(dev);
2117         struct dcb_table *dcb = &drm->vbios.dcb;
2118         struct drm_connector *connector, *tmp;
2119         struct nv50_disp *disp;
2120         struct dcb_output *dcbe;
2121         int crtcs, ret, i;
2122
2123         disp = kzalloc(sizeof(*disp), GFP_KERNEL);
2124         if (!disp)
2125                 return -ENOMEM;
2126
2127         mutex_init(&disp->mutex);
2128
2129         nouveau_display(dev)->priv = disp;
2130         nouveau_display(dev)->dtor = nv50_display_destroy;
2131         nouveau_display(dev)->init = nv50_display_init;
2132         nouveau_display(dev)->fini = nv50_display_fini;
2133         disp->disp = &nouveau_display(dev)->disp;
2134         dev->mode_config.funcs = &nv50_disp_func;
2135         dev->driver->driver_features |= DRIVER_PREFER_XBGR_30BPP;
2136         if (nouveau_atomic)
2137                 dev->driver->driver_features |= DRIVER_ATOMIC;
2138
2139         /* small shared memory area we use for notifiers and semaphores */
2140         ret = nouveau_bo_new(&drm->client, 4096, 0x1000, TTM_PL_FLAG_VRAM,
2141                              0, 0x0000, NULL, NULL, &disp->sync);
2142         if (!ret) {
2143                 ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM, true);
2144                 if (!ret) {
2145                         ret = nouveau_bo_map(disp->sync);
2146                         if (ret)
2147                                 nouveau_bo_unpin(disp->sync);
2148                 }
2149                 if (ret)
2150                         nouveau_bo_ref(NULL, &disp->sync);
2151         }
2152
2153         if (ret)
2154                 goto out;
2155
2156         /* allocate master evo channel */
2157         ret = nv50_core_new(drm, &disp->core);
2158         if (ret)
2159                 goto out;
2160
2161         /* create crtc objects to represent the hw heads */
2162         if (disp->disp->object.oclass >= GF110_DISP)
2163                 crtcs = nvif_rd32(&device->object, 0x612004) & 0xf;
2164         else
2165                 crtcs = 0x3;
2166
2167         for (i = 0; i < fls(crtcs); i++) {
2168                 if (!(crtcs & (1 << i)))
2169                         continue;
2170                 ret = nv50_head_create(dev, i);
2171                 if (ret)
2172                         goto out;
2173         }
2174
2175         /* create encoder/connector objects based on VBIOS DCB table */
2176         for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
2177                 connector = nouveau_connector_create(dev, dcbe->connector);
2178                 if (IS_ERR(connector))
2179                         continue;
2180
2181                 if (dcbe->location == DCB_LOC_ON_CHIP) {
2182                         switch (dcbe->type) {
2183                         case DCB_OUTPUT_TMDS:
2184                         case DCB_OUTPUT_LVDS:
2185                         case DCB_OUTPUT_DP:
2186                                 ret = nv50_sor_create(connector, dcbe);
2187                                 break;
2188                         case DCB_OUTPUT_ANALOG:
2189                                 ret = nv50_dac_create(connector, dcbe);
2190                                 break;
2191                         default:
2192                                 ret = -ENODEV;
2193                                 break;
2194                         }
2195                 } else {
2196                         ret = nv50_pior_create(connector, dcbe);
2197                 }
2198
2199                 if (ret) {
2200                         NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n",
2201                                      dcbe->location, dcbe->type,
2202                                      ffs(dcbe->or) - 1, ret);
2203                         ret = 0;
2204                 }
2205         }
2206
2207         /* cull any connectors we created that don't have an encoder */
2208         list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
2209                 if (connector->encoder_ids[0])
2210                         continue;
2211
2212                 NV_WARN(drm, "%s has no encoders, removing\n",
2213                         connector->name);
2214                 connector->funcs->destroy(connector);
2215         }
2216
2217 out:
2218         if (ret)
2219                 nv50_display_destroy(dev);
2220         return ret;
2221 }