drivers/gpu/drm/nouveau/dispnv50/disp.c

   1 /*
   2  * Copyright 2011 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "disp.h"
  25 #include "atom.h"
  26 #include "core.h"
  27 #include "head.h"
  28 #include "wndw.h"
  29
  30 #include <linux/dma-mapping.h>
  31 #include <linux/hdmi.h>
  32
  33 #include <drm/drmP.h>
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_crtc_helper.h>
  36 #include <drm/drm_dp_helper.h>
  37 #include <drm/drm_fb_helper.h>
  38 #include <drm/drm_plane_helper.h>
  39 #include <drm/drm_scdc_helper.h>
  40 #include <drm/drm_edid.h>
  41
  42 #include <nvif/class.h>
  43 #include <nvif/cl0002.h>
  44 #include <nvif/cl5070.h>
  45 #include <nvif/cl507d.h>
  46 #include <nvif/event.h>
  47
  48 #include "nouveau_drv.h"
  49 #include "nouveau_dma.h"
  50 #include "nouveau_gem.h"
  51 #include "nouveau_connector.h"
  52 #include "nouveau_encoder.h"
  53 #include "nouveau_fence.h"
  54 #include "nouveau_fbcon.h"
  55
  56 #include <subdev/bios/dp.h>
  57
  58 /******************************************************************************
  59  * Atomic state
  60  *****************************************************************************/
  61
  62 struct nv50_outp_atom {
  63         struct list_head head;
  64
  65         struct drm_encoder *encoder;
  66         bool flush_disable;
  67
  68         union nv50_outp_atom_mask {
  69                 struct {
  70                         bool ctrl:1;
  71                 };
  72                 u8 mask;
  73         } set, clr;
  74 };
  75
  76 /******************************************************************************
  77  * EVO channel
  78  *****************************************************************************/
  79
  80 static int
  81 nv50_chan_create(struct nvif_device *device, struct nvif_object *disp,
  82                  const s32 *oclass, u8 head, void *data, u32 size,
  83                  struct nv50_chan *chan)
  84 {
  85         struct nvif_sclass *sclass;
  86         int ret, i, n;
  87
  88         chan->device = device;
  89
  90         ret = n = nvif_object_sclass_get(disp, &sclass);
  91         if (ret < 0)
  92                 return ret;
  93
  94         while (oclass[0]) {
  95                 for (i = 0; i < n; i++) {
  96                         if (sclass[i].oclass == oclass[0]) {
  97                                 ret = nvif_object_init(disp, 0, oclass[0],
  98                                                        data, size, &chan->user);
  99                                 if (ret == 0)
 100                                         nvif_object_map(&chan->user, NULL, 0);
 101                                 nvif_object_sclass_put(&sclass);
 102                                 return ret;
 103                         }
 104                 }
 105                 oclass++;
 106         }
 107
 108         nvif_object_sclass_put(&sclass);
 109         return -ENOSYS;
 110 }
 111
 112 static void
 113 nv50_chan_destroy(struct nv50_chan *chan)
 114 {
 115         nvif_object_fini(&chan->user);
 116 }
 117
 118 /******************************************************************************
 119  * DMA EVO channel
 120  *****************************************************************************/
 121
 122 void
 123 nv50_dmac_destroy(struct nv50_dmac *dmac)
 124 {
 125         nvif_object_fini(&dmac->vram);
 126         nvif_object_fini(&dmac->sync);
 127
 128         nv50_chan_destroy(&dmac->base);
 129
 130         nvif_mem_fini(&dmac->push);
 131 }
 132
 133 int
 134 nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp,
 135                  const s32 *oclass, u8 head, void *data, u32 size, u64 syncbuf,
 136                  struct nv50_dmac *dmac)
 137 {
 138         struct nouveau_cli *cli = (void *)device->object.client;
 139         struct nv50_disp_core_channel_dma_v0 *args = data;
 140         u8 type = NVIF_MEM_COHERENT;
 141         int ret;
 142
 143         mutex_init(&dmac->lock);
 144
 145         /* Pascal added support for 47-bit physical addresses, but some
 146          * parts of EVO still only accept 40-bit PAs.
 147          *
 148          * To avoid issues on systems with large amounts of RAM, and on
 149          * systems where an IOMMU maps pages at a high address, we need
 150          * to allocate push buffers in VRAM instead.
 151          *
 152          * This appears to match NVIDIA's behaviour on Pascal.
 153          */
 154         if (device->info.family == NV_DEVICE_INFO_V0_PASCAL)
 155                 type |= NVIF_MEM_VRAM;
 156
 157         ret = nvif_mem_init_map(&cli->mmu, type, 0x1000, &dmac->push);
 158         if (ret)
 159                 return ret;
 160
 161         dmac->ptr = dmac->push.object.map.ptr;
 162
 163         args->pushbuf = nvif_handle(&dmac->push.object);
 164
 165         ret = nv50_chan_create(device, disp, oclass, head, data, size,
 166                                &dmac->base);
 167         if (ret)
 168                 return ret;
 169
 170         if (!syncbuf)
 171                 return 0;
 172
 173         ret = nvif_object_init(&dmac->base.user, 0xf0000000, NV_DMA_IN_MEMORY,
 174                                &(struct nv_dma_v0) {
 175                                         .target = NV_DMA_V0_TARGET_VRAM,
 176                                         .access = NV_DMA_V0_ACCESS_RDWR,
 177                                         .start = syncbuf + 0x0000,
 178                                         .limit = syncbuf + 0x0fff,
 179                                }, sizeof(struct nv_dma_v0),
 180                                &dmac->sync);
 181         if (ret)
 182                 return ret;
 183
 184         ret = nvif_object_init(&dmac->base.user, 0xf0000001, NV_DMA_IN_MEMORY,
 185                                &(struct nv_dma_v0) {
 186                                         .target = NV_DMA_V0_TARGET_VRAM,
 187                                         .access = NV_DMA_V0_ACCESS_RDWR,
 188                                         .start = 0,
 189                                         .limit = device->info.ram_user - 1,
 190                                }, sizeof(struct nv_dma_v0),
 191                                &dmac->vram);
 192         if (ret)
 193                 return ret;
 194
 195         return ret;
 196 }
 197
 198 /******************************************************************************
 199  * EVO channel helpers
 200  *****************************************************************************/
 201 static void
 202 evo_flush(struct nv50_dmac *dmac)
 203 {
 204         /* Push buffer fetches are not coherent with BAR1, we need to ensure
 205          * writes have been flushed right through to VRAM before writing PUT.
 206          */
 207         if (dmac->push.type & NVIF_MEM_VRAM) {
 208                 struct nvif_device *device = dmac->base.device;
 209                 nvif_wr32(&device->object, 0x070000, 0x00000001);
 210                 nvif_msec(device, 2000,
 211                         if (!(nvif_rd32(&device->object, 0x070000) & 0x00000002))
 212                                 break;
 213                 );
 214         }
 215 }
 216
 217 u32 *
 218 evo_wait(struct nv50_dmac *evoc, int nr)
 219 {
 220         struct nv50_dmac *dmac = evoc;
 221         struct nvif_device *device = dmac->base.device;
 222         u32 put = nvif_rd32(&dmac->base.user, 0x0000) / 4;
 223
 224         mutex_lock(&dmac->lock);
 225         if (put + nr >= (PAGE_SIZE / 4) - 8) {
 226                 dmac->ptr[put] = 0x20000000;
 227                 evo_flush(dmac);
 228
 229                 nvif_wr32(&dmac->base.user, 0x0000, 0x00000000);
 230                 if (nvif_msec(device, 2000,
 231                         if (!nvif_rd32(&dmac->base.user, 0x0004))
 232                                 break;
 233                 ) < 0) {
 234                         mutex_unlock(&dmac->lock);
 235                         pr_err("nouveau: evo channel stalled\n");
 236                         return NULL;
 237                 }
 238
 239                 put = 0;
 240         }
 241
 242         return dmac->ptr + put;
 243 }
 244
 245 void
 246 evo_kick(u32 *push, struct nv50_dmac *evoc)
 247 {
 248         struct nv50_dmac *dmac = evoc;
 249
 250         evo_flush(dmac);
 251
 252         nvif_wr32(&dmac->base.user, 0x0000, (push - dmac->ptr) << 2);
 253         mutex_unlock(&dmac->lock);
 254 }
 255
 256 /******************************************************************************
 257  * Output path helpers
 258  *****************************************************************************/
 259 static void
 260 nv50_outp_release(struct nouveau_encoder *nv_encoder)
 261 {
 262         struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev);
 263         struct {
 264                 struct nv50_disp_mthd_v1 base;
 265         } args = {
 266                 .base.version = 1,
 267                 .base.method = NV50_DISP_MTHD_V1_RELEASE,
 268                 .base.hasht  = nv_encoder->dcb->hasht,
 269                 .base.hashm  = nv_encoder->dcb->hashm,
 270         };
 271
 272         nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 273         nv_encoder->or = -1;
 274         nv_encoder->link = 0;
 275 }
 276
 277 static int
 278 nv50_outp_acquire(struct nouveau_encoder *nv_encoder)
 279 {
 280         struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev);
 281         struct nv50_disp *disp = nv50_disp(drm->dev);
 282         struct {
 283                 struct nv50_disp_mthd_v1 base;
 284                 struct nv50_disp_acquire_v0 info;
 285         } args = {
 286                 .base.version = 1,
 287                 .base.method = NV50_DISP_MTHD_V1_ACQUIRE,
 288                 .base.hasht  = nv_encoder->dcb->hasht,
 289                 .base.hashm  = nv_encoder->dcb->hashm,
 290         };
 291         int ret;
 292
 293         ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 294         if (ret) {
 295                 NV_ERROR(drm, "error acquiring output path: %d\n", ret);
 296                 return ret;
 297         }
 298
 299         nv_encoder->or = args.info.or;
 300         nv_encoder->link = args.info.link;
 301         return 0;
 302 }
 303
 304 static int
 305 nv50_outp_atomic_check_view(struct drm_encoder *encoder,
 306                             struct drm_crtc_state *crtc_state,
 307                             struct drm_connector_state *conn_state,
 308                             struct drm_display_mode *native_mode)
 309 {
 310         struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
 311         struct drm_display_mode *mode = &crtc_state->mode;
 312         struct drm_connector *connector = conn_state->connector;
 313         struct nouveau_conn_atom *asyc = nouveau_conn_atom(conn_state);
 314         struct nouveau_drm *drm = nouveau_drm(encoder->dev);
 315
 316         NV_ATOMIC(drm, "%s atomic_check\n", encoder->name);
 317         asyc->scaler.full = false;
 318         if (!native_mode)
 319                 return 0;
 320
 321         if (asyc->scaler.mode == DRM_MODE_SCALE_NONE) {
 322                 switch (connector->connector_type) {
 323                 case DRM_MODE_CONNECTOR_LVDS:
 324                 case DRM_MODE_CONNECTOR_eDP:
 325                         /* Force use of scaler for non-EDID modes. */
 326                         if (adjusted_mode->type & DRM_MODE_TYPE_DRIVER)
 327                                 break;
 328                         mode = native_mode;
 329                         asyc->scaler.full = true;
 330                         break;
 331                 default:
 332                         break;
 333                 }
 334         } else {
 335                 mode = native_mode;
 336         }
 337
 338         if (!drm_mode_equal(adjusted_mode, mode)) {
 339                 drm_mode_copy(adjusted_mode, mode);
 340                 crtc_state->mode_changed = true;
 341         }
 342
 343         return 0;
 344 }
 345
 346 static int
 347 nv50_outp_atomic_check(struct drm_encoder *encoder,
 348                        struct drm_crtc_state *crtc_state,
 349                        struct drm_connector_state *conn_state)
 350 {
 351         struct nouveau_connector *nv_connector =
 352                 nouveau_connector(conn_state->connector);
 353         return nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
 354                                            nv_connector->native_mode);
 355 }
 356
 357 /******************************************************************************
 358  * DAC
 359  *****************************************************************************/
 360 static void
 361 nv50_dac_disable(struct drm_encoder *encoder)
 362 {
 363         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 364         struct nv50_core *core = nv50_disp(encoder->dev)->core;
 365         if (nv_encoder->crtc)
 366                 core->func->dac->ctrl(core, nv_encoder->or, 0x00000000, NULL);
 367         nv_encoder->crtc = NULL;
 368         nv50_outp_release(nv_encoder);
 369 }
 370
 371 static void
 372 nv50_dac_enable(struct drm_encoder *encoder)
 373 {
 374         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 375         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 376         struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
 377         struct nv50_core *core = nv50_disp(encoder->dev)->core;
 378
 379         nv50_outp_acquire(nv_encoder);
 380
 381         core->func->dac->ctrl(core, nv_encoder->or, 1 << nv_crtc->index, asyh);
 382         asyh->or.depth = 0;
 383
 384         nv_encoder->crtc = encoder->crtc;
 385 }
 386
 387 static enum drm_connector_status
 388 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
 389 {
 390         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 391         struct nv50_disp *disp = nv50_disp(encoder->dev);
 392         struct {
 393                 struct nv50_disp_mthd_v1 base;
 394                 struct nv50_disp_dac_load_v0 load;
 395         } args = {
 396                 .base.version = 1,
 397                 .base.method = NV50_DISP_MTHD_V1_DAC_LOAD,
 398                 .base.hasht  = nv_encoder->dcb->hasht,
 399                 .base.hashm  = nv_encoder->dcb->hashm,
 400         };
 401         int ret;
 402
 403         args.load.data = nouveau_drm(encoder->dev)->vbios.dactestval;
 404         if (args.load.data == 0)
 405                 args.load.data = 340;
 406
 407         ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 408         if (ret || !args.load.load)
 409                 return connector_status_disconnected;
 410
 411         return connector_status_connected;
 412 }
 413
 414 static const struct drm_encoder_helper_funcs
 415 nv50_dac_help = {
 416         .atomic_check = nv50_outp_atomic_check,
 417         .enable = nv50_dac_enable,
 418         .disable = nv50_dac_disable,
 419         .detect = nv50_dac_detect
 420 };
 421
 422 static void
 423 nv50_dac_destroy(struct drm_encoder *encoder)
 424 {
 425         drm_encoder_cleanup(encoder);
 426         kfree(encoder);
 427 }
 428
 429 static const struct drm_encoder_funcs
 430 nv50_dac_func = {
 431         .destroy = nv50_dac_destroy,
 432 };
 433
 434 static int
 435 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe)
 436 {
 437         struct nouveau_drm *drm = nouveau_drm(connector->dev);
 438         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
 439         struct nvkm_i2c_bus *bus;
 440         struct nouveau_encoder *nv_encoder;
 441         struct drm_encoder *encoder;
 442         int type = DRM_MODE_ENCODER_DAC;
 443
 444         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
 445         if (!nv_encoder)
 446                 return -ENOMEM;
 447         nv_encoder->dcb = dcbe;
 448
 449         bus = nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
 450         if (bus)
 451                 nv_encoder->i2c = &bus->i2c;
 452
 453         encoder = to_drm_encoder(nv_encoder);
 454         encoder->possible_crtcs = dcbe->heads;
 455         encoder->possible_clones = 0;
 456         drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type,
 457                          "dac-%04x-%04x", dcbe->hasht, dcbe->hashm);
 458         drm_encoder_helper_add(encoder, &nv50_dac_help);
 459
 460         drm_connector_attach_encoder(connector, encoder);
 461         return 0;
 462 }
 463
 464 /******************************************************************************
 465  * Audio
 466  *****************************************************************************/
 467 static void
 468 nv50_audio_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
 469 {
 470         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 471         struct nv50_disp *disp = nv50_disp(encoder->dev);
 472         struct {
 473                 struct nv50_disp_mthd_v1 base;
 474                 struct nv50_disp_sor_hda_eld_v0 eld;
 475         } args = {
 476                 .base.version = 1,
 477                 .base.method  = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
 478                 .base.hasht   = nv_encoder->dcb->hasht,
 479                 .base.hashm   = (0xf0ff & nv_encoder->dcb->hashm) |
 480                                 (0x0100 << nv_crtc->index),
 481         };
 482
 483         nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 484 }
 485
 486 static void
 487 nv50_audio_enable(struct drm_encoder *encoder, struct drm_display_mode *mode)
 488 {
 489         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 490         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 491         struct nouveau_connector *nv_connector;
 492         struct nv50_disp *disp = nv50_disp(encoder->dev);
 493         struct __packed {
 494                 struct {
 495                         struct nv50_disp_mthd_v1 mthd;
 496                         struct nv50_disp_sor_hda_eld_v0 eld;
 497                 } base;
 498                 u8 data[sizeof(nv_connector->base.eld)];
 499         } args = {
 500                 .base.mthd.version = 1,
 501                 .base.mthd.method  = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
 502                 .base.mthd.hasht   = nv_encoder->dcb->hasht,
 503                 .base.mthd.hashm   = (0xf0ff & nv_encoder->dcb->hashm) |
 504                                      (0x0100 << nv_crtc->index),
 505         };
 506
 507         nv_connector = nouveau_encoder_connector_get(nv_encoder);
 508         if (!drm_detect_monitor_audio(nv_connector->edid))
 509                 return;
 510
 511         memcpy(args.data, nv_connector->base.eld, sizeof(args.data));
 512
 513         nvif_mthd(&disp->disp->object, 0, &args,
 514                   sizeof(args.base) + drm_eld_size(args.data));
 515 }
 516
 517 /******************************************************************************
 518  * HDMI
 519  *****************************************************************************/
 520 static void
 521 nv50_hdmi_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
 522 {
 523         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 524         struct nv50_disp *disp = nv50_disp(encoder->dev);
 525         struct {
 526                 struct nv50_disp_mthd_v1 base;
 527                 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
 528         } args = {
 529                 .base.version = 1,
 530                 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
 531                 .base.hasht  = nv_encoder->dcb->hasht,
 532                 .base.hashm  = (0xf0ff & nv_encoder->dcb->hashm) |
 533                                (0x0100 << nv_crtc->index),
 534         };
 535
 536         nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 537 }
 538
 539 static void
 540 nv50_hdmi_enable(struct drm_encoder *encoder, struct drm_display_mode *mode)
 541 {
 542         struct nouveau_drm *drm = nouveau_drm(encoder->dev);
 543         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 544         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 545         struct nv50_disp *disp = nv50_disp(encoder->dev);
 546         struct {
 547                 struct nv50_disp_mthd_v1 base;
 548                 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
 549                 u8 infoframes[2 * 17]; /* two frames, up to 17 bytes each */
 550         } args = {
 551                 .base.version = 1,
 552                 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
 553                 .base.hasht  = nv_encoder->dcb->hasht,
 554                 .base.hashm  = (0xf0ff & nv_encoder->dcb->hashm) |
 555                                (0x0100 << nv_crtc->index),
 556                 .pwr.state = 1,
 557                 .pwr.rekey = 56, /* binary driver, and tegra, constant */
 558         };
 559         struct nouveau_connector *nv_connector;
 560         struct drm_hdmi_info *hdmi;
 561         u32 max_ac_packet;
 562         union hdmi_infoframe avi_frame;
 563         union hdmi_infoframe vendor_frame;
 564         bool high_tmds_clock_ratio = false, scrambling = false;
 565         u8 config;
 566         int ret;
 567         int size;
 568
 569         nv_connector = nouveau_encoder_connector_get(nv_encoder);
 570         if (!drm_detect_hdmi_monitor(nv_connector->edid))
 571                 return;
 572
 573         hdmi = &nv_connector->base.display_info.hdmi;
 574
 575         ret = drm_hdmi_avi_infoframe_from_display_mode(&avi_frame.avi,
 576                                                        &nv_connector->base, mode);
 577         if (!ret) {
 578                 /* We have an AVI InfoFrame, populate it to the display */
 579                 args.pwr.avi_infoframe_length
 580                         = hdmi_infoframe_pack(&avi_frame, args.infoframes, 17);
 581         }
 582
 583         ret = drm_hdmi_vendor_infoframe_from_display_mode(&vendor_frame.vendor.hdmi,
 584                                                           &nv_connector->base, mode);
 585         if (!ret) {
 586                 /* We have a Vendor InfoFrame, populate it to the display */
 587                 args.pwr.vendor_infoframe_length
 588                         = hdmi_infoframe_pack(&vendor_frame,
 589                                               args.infoframes
 590                                               + args.pwr.avi_infoframe_length,
 591                                               17);
 592         }
 593
 594         max_ac_packet  = mode->htotal - mode->hdisplay;
 595         max_ac_packet -= args.pwr.rekey;
 596         max_ac_packet -= 18; /* constant from tegra */
 597         args.pwr.max_ac_packet = max_ac_packet / 32;
 598
 599         if (hdmi->scdc.scrambling.supported) {
 600                 high_tmds_clock_ratio = mode->clock > 340000;
 601                 scrambling = high_tmds_clock_ratio ||
 602                         hdmi->scdc.scrambling.low_rates;
 603         }
 604
 605         args.pwr.scdc =
 606                 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_SCRAMBLE * scrambling |
 607                 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_DIV_BY_4 * high_tmds_clock_ratio;
 608
 609         size = sizeof(args.base)
 610                 + sizeof(args.pwr)
 611                 + args.pwr.avi_infoframe_length
 612                 + args.pwr.vendor_infoframe_length;
 613         nvif_mthd(&disp->disp->object, 0, &args, size);
 614
 615         nv50_audio_enable(encoder, mode);
 616
 617         /* If SCDC is supported by the downstream monitor, update
 618          * divider / scrambling settings to what we programmed above.
 619          */
 620         if (!hdmi->scdc.scrambling.supported)
 621                 return;
 622
 623         ret = drm_scdc_readb(nv_encoder->i2c, SCDC_TMDS_CONFIG, &config);
 624         if (ret < 0) {
 625                 NV_ERROR(drm, "Failure to read SCDC_TMDS_CONFIG: %d\n", ret);
 626                 return;
 627         }
 628         config &= ~(SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 | SCDC_SCRAMBLING_ENABLE);
 629         config |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 * high_tmds_clock_ratio;
 630         config |= SCDC_SCRAMBLING_ENABLE * scrambling;
 631         ret = drm_scdc_writeb(nv_encoder->i2c, SCDC_TMDS_CONFIG, config);
 632         if (ret < 0)
 633                 NV_ERROR(drm, "Failure to write SCDC_TMDS_CONFIG = 0x%02x: %d\n",
 634                          config, ret);
 635 }
 636
 637 /******************************************************************************
 638  * MST
 639  *****************************************************************************/
 640 #define nv50_mstm(p) container_of((p), struct nv50_mstm, mgr)
 641 #define nv50_mstc(p) container_of((p), struct nv50_mstc, connector)
 642 #define nv50_msto(p) container_of((p), struct nv50_msto, encoder)
 643
 644 struct nv50_mstm {
 645         struct nouveau_encoder *outp;
 646
 647         struct drm_dp_mst_topology_mgr mgr;
 648         struct nv50_msto *msto[4];
 649
 650         bool modified;
 651         bool disabled;
 652         int links;
 653 };
 654
 655 struct nv50_mstc {
 656         struct nv50_mstm *mstm;
 657         struct drm_dp_mst_port *port;
 658         struct drm_connector connector;
 659
 660         struct drm_display_mode *native;
 661         struct edid *edid;
 662
 663         int pbn;
 664 };
 665
 666 struct nv50_msto {
 667         struct drm_encoder encoder;
 668
 669         struct nv50_head *head;
 670         struct nv50_mstc *mstc;
 671         bool disabled;
 672 };
 673
 674 static struct drm_dp_payload *
 675 nv50_msto_payload(struct nv50_msto *msto)
 676 {
 677         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
 678         struct nv50_mstc *mstc = msto->mstc;
 679         struct nv50_mstm *mstm = mstc->mstm;
 680         int vcpi = mstc->port->vcpi.vcpi, i;
 681
 682         WARN_ON(!mutex_is_locked(&mstm->mgr.payload_lock));
 683
 684         NV_ATOMIC(drm, "%s: vcpi %d\n", msto->encoder.name, vcpi);
 685         for (i = 0; i < mstm->mgr.max_payloads; i++) {
 686                 struct drm_dp_payload *payload = &mstm->mgr.payloads[i];
 687                 NV_ATOMIC(drm, "%s: %d: vcpi %d start 0x%02x slots 0x%02x\n",
 688                           mstm->outp->base.base.name, i, payload->vcpi,
 689                           payload->start_slot, payload->num_slots);
 690         }
 691
 692         for (i = 0; i < mstm->mgr.max_payloads; i++) {
 693                 struct drm_dp_payload *payload = &mstm->mgr.payloads[i];
 694                 if (payload->vcpi == vcpi)
 695                         return payload;
 696         }
 697
 698         return NULL;
 699 }
 700
 701 static void
 702 nv50_msto_cleanup(struct nv50_msto *msto)
 703 {
 704         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
 705         struct nv50_mstc *mstc = msto->mstc;
 706         struct nv50_mstm *mstm = mstc->mstm;
 707
 708         if (!msto->disabled)
 709                 return;
 710
 711         NV_ATOMIC(drm, "%s: msto cleanup\n", msto->encoder.name);
 712
 713         drm_dp_mst_deallocate_vcpi(&mstm->mgr, mstc->port);
 714
 715         msto->mstc = NULL;
 716         msto->head = NULL;
 717         msto->disabled = false;
 718 }
 719
 720 static void
 721 nv50_msto_prepare(struct nv50_msto *msto)
 722 {
 723         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
 724         struct nv50_mstc *mstc = msto->mstc;
 725         struct nv50_mstm *mstm = mstc->mstm;
 726         struct {
 727                 struct nv50_disp_mthd_v1 base;
 728                 struct nv50_disp_sor_dp_mst_vcpi_v0 vcpi;
 729         } args = {
 730                 .base.version = 1,
 731                 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_VCPI,
 732                 .base.hasht  = mstm->outp->dcb->hasht,
 733                 .base.hashm  = (0xf0ff & mstm->outp->dcb->hashm) |
 734                                (0x0100 << msto->head->base.index),
 735         };
 736
 737         mutex_lock(&mstm->mgr.payload_lock);
 738
 739         NV_ATOMIC(drm, "%s: msto prepare\n", msto->encoder.name);
 740         if (mstc->port->vcpi.vcpi > 0) {
 741                 struct drm_dp_payload *payload = nv50_msto_payload(msto);
 742                 if (payload) {
 743                         args.vcpi.start_slot = payload->start_slot;
 744                         args.vcpi.num_slots = payload->num_slots;
 745                         args.vcpi.pbn = mstc->port->vcpi.pbn;
 746                         args.vcpi.aligned_pbn = mstc->port->vcpi.aligned_pbn;
 747                 }
 748         }
 749
 750         NV_ATOMIC(drm, "%s: %s: %02x %02x %04x %04x\n",
 751                   msto->encoder.name, msto->head->base.base.name,
 752                   args.vcpi.start_slot, args.vcpi.num_slots,
 753                   args.vcpi.pbn, args.vcpi.aligned_pbn);
 754
 755         nvif_mthd(&drm->display->disp.object, 0, &args, sizeof(args));
 756         mutex_unlock(&mstm->mgr.payload_lock);
 757 }
 758
 759 static int
 760 nv50_msto_atomic_check(struct drm_encoder *encoder,
 761                        struct drm_crtc_state *crtc_state,
 762                        struct drm_connector_state *conn_state)
 763 {
 764         struct drm_atomic_state *state = crtc_state->state;
 765         struct drm_connector *connector = conn_state->connector;
 766         struct nv50_mstc *mstc = nv50_mstc(connector);
 767         struct nv50_mstm *mstm = mstc->mstm;
 768         int bpp = connector->display_info.bpc * 3;
 769         int slots;
 770
 771         mstc->pbn = drm_dp_calc_pbn_mode(crtc_state->adjusted_mode.clock,
 772                                          bpp);
 773
 774         if (drm_atomic_crtc_needs_modeset(crtc_state) &&
 775             !drm_connector_is_unregistered(connector)) {
 776                 slots = drm_dp_atomic_find_vcpi_slots(state, &mstm->mgr,
 777                                                       mstc->port, mstc->pbn);
 778                 if (slots < 0)
 779                         return slots;
 780         }
 781
 782         return nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
 783                                            mstc->native);
 784 }
 785
 786 static void
 787 nv50_msto_enable(struct drm_encoder *encoder)
 788 {
 789         struct nv50_head *head = nv50_head(encoder->crtc);
 790         struct nv50_msto *msto = nv50_msto(encoder);
 791         struct nv50_mstc *mstc = NULL;
 792         struct nv50_mstm *mstm = NULL;
 793         struct drm_connector *connector;
 794         struct drm_connector_list_iter conn_iter;
 795         u8 proto, depth;
 796         int slots;
 797         bool r;
 798
 799         drm_connector_list_iter_begin(encoder->dev, &conn_iter);
 800         drm_for_each_connector_iter(connector, &conn_iter) {
 801                 if (connector->state->best_encoder == &msto->encoder) {
 802                         mstc = nv50_mstc(connector);
 803                         mstm = mstc->mstm;
 804                         break;
 805                 }
 806         }
 807         drm_connector_list_iter_end(&conn_iter);
 808
 809         if (WARN_ON(!mstc))
 810                 return;
 811
 812         slots = drm_dp_find_vcpi_slots(&mstm->mgr, mstc->pbn);
 813         r = drm_dp_mst_allocate_vcpi(&mstm->mgr, mstc->port, mstc->pbn, slots);
 814         WARN_ON(!r);
 815
 816         if (!mstm->links++)
 817                 nv50_outp_acquire(mstm->outp);
 818
 819         if (mstm->outp->link & 1)
 820                 proto = 0x8;
 821         else
 822                 proto = 0x9;
 823
 824         switch (mstc->connector.display_info.bpc) {
 825         case  6: depth = 0x2; break;
 826         case  8: depth = 0x5; break;
 827         case 10:
 828         default: depth = 0x6; break;
 829         }
 830
 831         mstm->outp->update(mstm->outp, head->base.index,
 832                            nv50_head_atom(head->base.base.state), proto, depth);
 833
 834         msto->head = head;
 835         msto->mstc = mstc;
 836         mstm->modified = true;
 837 }
 838
 839 static void
 840 nv50_msto_disable(struct drm_encoder *encoder)
 841 {
 842         struct nv50_msto *msto = nv50_msto(encoder);
 843         struct nv50_mstc *mstc = msto->mstc;
 844         struct nv50_mstm *mstm = mstc->mstm;
 845
 846         drm_dp_mst_reset_vcpi_slots(&mstm->mgr, mstc->port);
 847
 848         mstm->outp->update(mstm->outp, msto->head->base.index, NULL, 0, 0);
 849         mstm->modified = true;
 850         if (!--mstm->links)
 851                 mstm->disabled = true;
 852         msto->disabled = true;
 853 }
 854
 855 static const struct drm_encoder_helper_funcs
 856 nv50_msto_help = {
 857         .disable = nv50_msto_disable,
 858         .enable = nv50_msto_enable,
 859         .atomic_check = nv50_msto_atomic_check,
 860 };
 861
 862 static void
 863 nv50_msto_destroy(struct drm_encoder *encoder)
 864 {
 865         struct nv50_msto *msto = nv50_msto(encoder);
 866         drm_encoder_cleanup(&msto->encoder);
 867         kfree(msto);
 868 }
 869
 870 static const struct drm_encoder_funcs
 871 nv50_msto = {
 872         .destroy = nv50_msto_destroy,
 873 };
 874
 875 static int
 876 nv50_msto_new(struct drm_device *dev, u32 heads, const char *name, int id,
 877               struct nv50_msto **pmsto)
 878 {
 879         struct nv50_msto *msto;
 880         int ret;
 881
 882         if (!(msto = *pmsto = kzalloc(sizeof(*msto), GFP_KERNEL)))
 883                 return -ENOMEM;
 884
 885         ret = drm_encoder_init(dev, &msto->encoder, &nv50_msto,
 886                                DRM_MODE_ENCODER_DPMST, "%s-mst-%d", name, id);
 887         if (ret) {
 888                 kfree(*pmsto);
 889                 *pmsto = NULL;
 890                 return ret;
 891         }
 892
 893         drm_encoder_helper_add(&msto->encoder, &nv50_msto_help);
 894         msto->encoder.possible_crtcs = heads;
 895         return 0;
 896 }
 897
 898 static struct drm_encoder *
 899 nv50_mstc_atomic_best_encoder(struct drm_connector *connector,
 900                               struct drm_connector_state *connector_state)
 901 {
 902         struct nv50_head *head = nv50_head(connector_state->crtc);
 903         struct nv50_mstc *mstc = nv50_mstc(connector);
 904
 905         return &mstc->mstm->msto[head->base.index]->encoder;
 906 }
 907
 908 static struct drm_encoder *
 909 nv50_mstc_best_encoder(struct drm_connector *connector)
 910 {
 911         struct nv50_mstc *mstc = nv50_mstc(connector);
 912
 913         return &mstc->mstm->msto[0]->encoder;
 914 }
 915
 916 static enum drm_mode_status
 917 nv50_mstc_mode_valid(struct drm_connector *connector,
 918                      struct drm_display_mode *mode)
 919 {
 920         return MODE_OK;
 921 }
 922
 923 static int
 924 nv50_mstc_get_modes(struct drm_connector *connector)
 925 {
 926         struct nv50_mstc *mstc = nv50_mstc(connector);
 927         int ret = 0;
 928
 929         mstc->edid = drm_dp_mst_get_edid(&mstc->connector, mstc->port->mgr, mstc->port);
 930         drm_connector_update_edid_property(&mstc->connector, mstc->edid);
 931         if (mstc->edid)
 932                 ret = drm_add_edid_modes(&mstc->connector, mstc->edid);
 933
 934         if (!mstc->connector.display_info.bpc)
 935                 mstc->connector.display_info.bpc = 8;
 936
 937         if (mstc->native)
 938                 drm_mode_destroy(mstc->connector.dev, mstc->native);
 939         mstc->native = nouveau_conn_native_mode(&mstc->connector);
 940         return ret;
 941 }
 942
 943 static int
 944 nv50_mstc_atomic_check(struct drm_connector *connector,
 945                        struct drm_connector_state *new_conn_state)
 946 {
 947         struct drm_atomic_state *state = new_conn_state->state;
 948         struct nv50_mstc *mstc = nv50_mstc(connector);
 949         struct drm_dp_mst_topology_mgr *mgr = &mstc->mstm->mgr;
 950         struct drm_connector_state *old_conn_state =
 951                 drm_atomic_get_old_connector_state(state, connector);
 952         struct drm_crtc_state *crtc_state;
 953         struct drm_crtc *new_crtc = new_conn_state->crtc;
 954
 955         if (!old_conn_state->crtc)
 956                 return 0;
 957
 958         /* We only want to free VCPI if this state disables the CRTC on this
 959          * connector
 960          */
 961         if (new_crtc) {
 962                 crtc_state = drm_atomic_get_new_crtc_state(state, new_crtc);
 963
 964                 if (!crtc_state ||
 965                     !drm_atomic_crtc_needs_modeset(crtc_state) ||
 966                     crtc_state->enable)
 967                         return 0;
 968         }
 969
 970         return drm_dp_atomic_release_vcpi_slots(state, mgr, mstc->port);
 971 }
 972
 973 static const struct drm_connector_helper_funcs
 974 nv50_mstc_help = {
 975         .get_modes = nv50_mstc_get_modes,
 976         .mode_valid = nv50_mstc_mode_valid,
 977         .best_encoder = nv50_mstc_best_encoder,
 978         .atomic_best_encoder = nv50_mstc_atomic_best_encoder,
 979         .atomic_check = nv50_mstc_atomic_check,
 980 };
 981
 982 static enum drm_connector_status
 983 nv50_mstc_detect(struct drm_connector *connector, bool force)
 984 {
 985         struct nv50_mstc *mstc = nv50_mstc(connector);
 986         enum drm_connector_status conn_status;
 987         int ret;
 988
 989         if (drm_connector_is_unregistered(connector))
 990                 return connector_status_disconnected;
 991
 992         ret = pm_runtime_get_sync(connector->dev->dev);
 993         if (ret < 0 && ret != -EACCES)
 994                 return connector_status_disconnected;
 995
 996         conn_status = drm_dp_mst_detect_port(connector, mstc->port->mgr,
 997                                              mstc->port);
 998
 999         pm_runtime_mark_last_busy(connector->dev->dev);
1000         pm_runtime_put_autosuspend(connector->dev->dev);
1001         return conn_status;
1002 }
1003
1004 static void
1005 nv50_mstc_destroy(struct drm_connector *connector)
1006 {
1007         struct nv50_mstc *mstc = nv50_mstc(connector);
1008
1009         drm_connector_cleanup(&mstc->connector);
1010         drm_dp_mst_put_port_malloc(mstc->port);
1011
1012         kfree(mstc);
1013 }
1014
1015 static const struct drm_connector_funcs
1016 nv50_mstc = {
1017         .reset = nouveau_conn_reset,
1018         .detect = nv50_mstc_detect,
1019         .fill_modes = drm_helper_probe_single_connector_modes,
1020         .destroy = nv50_mstc_destroy,
1021         .atomic_duplicate_state = nouveau_conn_atomic_duplicate_state,
1022         .atomic_destroy_state = nouveau_conn_atomic_destroy_state,
1023         .atomic_set_property = nouveau_conn_atomic_set_property,
1024         .atomic_get_property = nouveau_conn_atomic_get_property,
1025 };
1026
1027 static int
1028 nv50_mstc_new(struct nv50_mstm *mstm, struct drm_dp_mst_port *port,
1029               const char *path, struct nv50_mstc **pmstc)
1030 {
1031         struct drm_device *dev = mstm->outp->base.base.dev;
1032         struct nv50_mstc *mstc;
1033         int ret, i;
1034
1035         if (!(mstc = *pmstc = kzalloc(sizeof(*mstc), GFP_KERNEL)))
1036                 return -ENOMEM;
1037         mstc->mstm = mstm;
1038         mstc->port = port;
1039
1040         ret = drm_connector_init(dev, &mstc->connector, &nv50_mstc,
1041                                  DRM_MODE_CONNECTOR_DisplayPort);
1042         if (ret) {
1043                 kfree(*pmstc);
1044                 *pmstc = NULL;
1045                 return ret;
1046         }
1047
1048         drm_connector_helper_add(&mstc->connector, &nv50_mstc_help);
1049
1050         mstc->connector.funcs->reset(&mstc->connector);
1051         nouveau_conn_attach_properties(&mstc->connector);
1052
1053         for (i = 0; i < ARRAY_SIZE(mstm->msto) && mstm->msto[i]; i++)
1054                 drm_connector_attach_encoder(&mstc->connector, &mstm->msto[i]->encoder);
1055
1056         drm_object_attach_property(&mstc->connector.base, dev->mode_config.path_property, 0);
1057         drm_object_attach_property(&mstc->connector.base, dev->mode_config.tile_property, 0);
1058         drm_connector_set_path_property(&mstc->connector, path);
1059         drm_dp_mst_get_port_malloc(port);
1060         return 0;
1061 }
1062
1063 static void
1064 nv50_mstm_cleanup(struct nv50_mstm *mstm)
1065 {
1066         struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
1067         struct drm_encoder *encoder;
1068         int ret;
1069
1070         NV_ATOMIC(drm, "%s: mstm cleanup\n", mstm->outp->base.base.name);
1071         ret = drm_dp_check_act_status(&mstm->mgr);
1072
1073         ret = drm_dp_update_payload_part2(&mstm->mgr);
1074
1075         drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
1076                 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
1077                         struct nv50_msto *msto = nv50_msto(encoder);
1078                         struct nv50_mstc *mstc = msto->mstc;
1079                         if (mstc && mstc->mstm == mstm)
1080                                 nv50_msto_cleanup(msto);
1081                 }
1082         }
1083
1084         mstm->modified = false;
1085 }
1086
1087 static void
1088 nv50_mstm_prepare(struct nv50_mstm *mstm)
1089 {
1090         struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
1091         struct drm_encoder *encoder;
1092         int ret;
1093
1094         NV_ATOMIC(drm, "%s: mstm prepare\n", mstm->outp->base.base.name);
1095         ret = drm_dp_update_payload_part1(&mstm->mgr);
1096
1097         drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
1098                 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
1099                         struct nv50_msto *msto = nv50_msto(encoder);
1100                         struct nv50_mstc *mstc = msto->mstc;
1101                         if (mstc && mstc->mstm == mstm)
1102                                 nv50_msto_prepare(msto);
1103                 }
1104         }
1105
1106         if (mstm->disabled) {
1107                 if (!mstm->links)
1108                         nv50_outp_release(mstm->outp);
1109                 mstm->disabled = false;
1110         }
1111 }
1112
1113 static void
1114 nv50_mstm_destroy_connector(struct drm_dp_mst_topology_mgr *mgr,
1115                             struct drm_connector *connector)
1116 {
1117         struct nouveau_drm *drm = nouveau_drm(connector->dev);
1118         struct nv50_mstc *mstc = nv50_mstc(connector);
1119
1120         drm_connector_unregister(&mstc->connector);
1121
1122         drm_fb_helper_remove_one_connector(&drm->fbcon->helper, &mstc->connector);
1123
1124         drm_connector_put(&mstc->connector);
1125 }
1126
1127 static void
1128 nv50_mstm_register_connector(struct drm_connector *connector)
1129 {
1130         struct nouveau_drm *drm = nouveau_drm(connector->dev);
1131
1132         drm_fb_helper_add_one_connector(&drm->fbcon->helper, connector);
1133
1134         drm_connector_register(connector);
1135 }
1136
1137 static struct drm_connector *
1138 nv50_mstm_add_connector(struct drm_dp_mst_topology_mgr *mgr,
1139                         struct drm_dp_mst_port *port, const char *path)
1140 {
1141         struct nv50_mstm *mstm = nv50_mstm(mgr);
1142         struct nv50_mstc *mstc;
1143         int ret;
1144
1145         ret = nv50_mstc_new(mstm, port, path, &mstc);
1146         if (ret)
1147                 return NULL;
1148
1149         return &mstc->connector;
1150 }
1151
1152 static const struct drm_dp_mst_topology_cbs
1153 nv50_mstm = {
1154         .add_connector = nv50_mstm_add_connector,
1155         .register_connector = nv50_mstm_register_connector,
1156         .destroy_connector = nv50_mstm_destroy_connector,
1157 };
1158
1159 void
1160 nv50_mstm_service(struct nv50_mstm *mstm)
1161 {
1162         struct drm_dp_aux *aux = mstm ? mstm->mgr.aux : NULL;
1163         bool handled = true;
1164         int ret;
1165         u8 esi[8] = {};
1166
1167         if (!aux)
1168                 return;
1169
1170         while (handled) {
1171                 ret = drm_dp_dpcd_read(aux, DP_SINK_COUNT_ESI, esi, 8);
1172                 if (ret != 8) {
1173                         drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1174                         return;
1175                 }
1176
1177                 drm_dp_mst_hpd_irq(&mstm->mgr, esi, &handled);
1178                 if (!handled)
1179                         break;
1180
1181                 drm_dp_dpcd_write(aux, DP_SINK_COUNT_ESI + 1, &esi[1], 3);
1182         }
1183 }
1184
1185 void
1186 nv50_mstm_remove(struct nv50_mstm *mstm)
1187 {
1188         if (mstm)
1189                 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1190 }
1191
1192 static int
1193 nv50_mstm_enable(struct nv50_mstm *mstm, u8 dpcd, int state)
1194 {
1195         struct nouveau_encoder *outp = mstm->outp;
1196         struct {
1197                 struct nv50_disp_mthd_v1 base;
1198                 struct nv50_disp_sor_dp_mst_link_v0 mst;
1199         } args = {
1200                 .base.version = 1,
1201                 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_LINK,
1202                 .base.hasht = outp->dcb->hasht,
1203                 .base.hashm = outp->dcb->hashm,
1204                 .mst.state = state,
1205         };
1206         struct nouveau_drm *drm = nouveau_drm(outp->base.base.dev);
1207         struct nvif_object *disp = &drm->display->disp.object;
1208         int ret;
1209
1210         if (dpcd >= 0x12) {
1211                 /* Even if we're enabling MST, start with disabling the
1212                  * branching unit to clear any sink-side MST topology state
1213                  * that wasn't set by us
1214                  */
1215                 ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL, 0);
1216                 if (ret < 0)
1217                         return ret;
1218
1219                 if (state) {
1220                         /* Now, start initializing */
1221                         ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL,
1222                                                  DP_MST_EN);
1223                         if (ret < 0)
1224                                 return ret;
1225                 }
1226         }
1227
1228         return nvif_mthd(disp, 0, &args, sizeof(args));
1229 }
1230
1231 int
1232 nv50_mstm_detect(struct nv50_mstm *mstm, u8 dpcd[8], int allow)
1233 {
1234         struct drm_dp_aux *aux;
1235         int ret;
1236         bool old_state, new_state;
1237         u8 mstm_ctrl;
1238
1239         if (!mstm)
1240                 return 0;
1241
1242         mutex_lock(&mstm->mgr.lock);
1243
1244         old_state = mstm->mgr.mst_state;
1245         new_state = old_state;
1246         aux = mstm->mgr.aux;
1247
1248         if (old_state) {
1249                 /* Just check that the MST hub is still as we expect it */
1250                 ret = drm_dp_dpcd_readb(aux, DP_MSTM_CTRL, &mstm_ctrl);
1251                 if (ret < 0 || !(mstm_ctrl & DP_MST_EN)) {
1252                         DRM_DEBUG_KMS("Hub gone, disabling MST topology\n");
1253                         new_state = false;
1254                 }
1255         } else if (dpcd[0] >= 0x12) {
1256                 ret = drm_dp_dpcd_readb(aux, DP_MSTM_CAP, &dpcd[1]);
1257                 if (ret < 0)
1258                         goto probe_error;
1259
1260                 if (!(dpcd[1] & DP_MST_CAP))
1261                         dpcd[0] = 0x11;
1262                 else
1263                         new_state = allow;
1264         }
1265
1266         if (new_state == old_state) {
1267                 mutex_unlock(&mstm->mgr.lock);
1268                 return new_state;
1269         }
1270
1271         ret = nv50_mstm_enable(mstm, dpcd[0], new_state);
1272         if (ret)
1273                 goto probe_error;
1274
1275         mutex_unlock(&mstm->mgr.lock);
1276
1277         ret = drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, new_state);
1278         if (ret)
1279                 return nv50_mstm_enable(mstm, dpcd[0], 0);
1280
1281         return new_state;
1282
1283 probe_error:
1284         mutex_unlock(&mstm->mgr.lock);
1285         return ret;
1286 }
1287
1288 static void
1289 nv50_mstm_fini(struct nv50_mstm *mstm)
1290 {
1291         if (mstm && mstm->mgr.mst_state)
1292                 drm_dp_mst_topology_mgr_suspend(&mstm->mgr);
1293 }
1294
1295 static void
1296 nv50_mstm_init(struct nv50_mstm *mstm)
1297 {
1298         int ret;
1299
1300         if (!mstm || !mstm->mgr.mst_state)
1301                 return;
1302
1303         ret = drm_dp_mst_topology_mgr_resume(&mstm->mgr);
1304         if (ret == -1) {
1305                 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1306                 drm_kms_helper_hotplug_event(mstm->mgr.dev);
1307         }
1308 }
1309
1310 static void
1311 nv50_mstm_del(struct nv50_mstm **pmstm)
1312 {
1313         struct nv50_mstm *mstm = *pmstm;
1314         if (mstm) {
1315                 drm_dp_mst_topology_mgr_destroy(&mstm->mgr);
1316                 kfree(*pmstm);
1317                 *pmstm = NULL;
1318         }
1319 }
1320
1321 static int
1322 nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max,
1323               int conn_base_id, struct nv50_mstm **pmstm)
1324 {
1325         const int max_payloads = hweight8(outp->dcb->heads);
1326         struct drm_device *dev = outp->base.base.dev;
1327         struct nv50_mstm *mstm;
1328         int ret, i;
1329         u8 dpcd;
1330
1331         /* This is a workaround for some monitors not functioning
1332          * correctly in MST mode on initial module load.  I think
1333          * some bad interaction with the VBIOS may be responsible.
1334          *
1335          * A good ol' off and on again seems to work here ;)
1336          */
1337         ret = drm_dp_dpcd_readb(aux, DP_DPCD_REV, &dpcd);
1338         if (ret >= 0 && dpcd >= 0x12)
1339                 drm_dp_dpcd_writeb(aux, DP_MSTM_CTRL, 0);
1340
1341         if (!(mstm = *pmstm = kzalloc(sizeof(*mstm), GFP_KERNEL)))
1342                 return -ENOMEM;
1343         mstm->outp = outp;
1344         mstm->mgr.cbs = &nv50_mstm;
1345
1346         ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max,
1347                                            max_payloads, conn_base_id);
1348         if (ret)
1349                 return ret;
1350
1351         for (i = 0; i < max_payloads; i++) {
1352                 ret = nv50_msto_new(dev, outp->dcb->heads, outp->base.base.name,
1353                                     i, &mstm->msto[i]);
1354                 if (ret)
1355                         return ret;
1356         }
1357
1358         return 0;
1359 }
1360
1361 /******************************************************************************
1362  * SOR
1363  *****************************************************************************/
1364 static void
1365 nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head,
1366                 struct nv50_head_atom *asyh, u8 proto, u8 depth)
1367 {
1368         struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev);
1369         struct nv50_core *core = disp->core;
1370
1371         if (!asyh) {
1372                 nv_encoder->ctrl &= ~BIT(head);
1373                 if (!(nv_encoder->ctrl & 0x0000000f))
1374                         nv_encoder->ctrl = 0;
1375         } else {
1376                 nv_encoder->ctrl |= proto << 8;
1377                 nv_encoder->ctrl |= BIT(head);
1378                 asyh->or.depth = depth;
1379         }
1380
1381         core->func->sor->ctrl(core, nv_encoder->or, nv_encoder->ctrl, asyh);
1382 }
1383
1384 static void
1385 nv50_sor_disable(struct drm_encoder *encoder)
1386 {
1387         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1388         struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
1389
1390         nv_encoder->crtc = NULL;
1391
1392         if (nv_crtc) {
1393                 struct nvkm_i2c_aux *aux = nv_encoder->aux;
1394                 u8 pwr;
1395
1396                 if (aux) {
1397                         int ret = nvkm_rdaux(aux, DP_SET_POWER, &pwr, 1);
1398                         if (ret == 0) {
1399                                 pwr &= ~DP_SET_POWER_MASK;
1400                                 pwr |=  DP_SET_POWER_D3;
1401                                 nvkm_wraux(aux, DP_SET_POWER, &pwr, 1);
1402                         }
1403                 }
1404
1405                 nv_encoder->update(nv_encoder, nv_crtc->index, NULL, 0, 0);
1406                 nv50_audio_disable(encoder, nv_crtc);
1407                 nv50_hdmi_disable(&nv_encoder->base.base, nv_crtc);
1408                 nv50_outp_release(nv_encoder);
1409         }
1410 }
1411
1412 static void
1413 nv50_sor_enable(struct drm_encoder *encoder)
1414 {
1415         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1416         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1417         struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
1418         struct drm_display_mode *mode = &asyh->state.adjusted_mode;
1419         struct {
1420                 struct nv50_disp_mthd_v1 base;
1421                 struct nv50_disp_sor_lvds_script_v0 lvds;
1422         } lvds = {
1423                 .base.version = 1,
1424                 .base.method  = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT,
1425                 .base.hasht   = nv_encoder->dcb->hasht,
1426                 .base.hashm   = nv_encoder->dcb->hashm,
1427         };
1428         struct nv50_disp *disp = nv50_disp(encoder->dev);
1429         struct drm_device *dev = encoder->dev;
1430         struct nouveau_drm *drm = nouveau_drm(dev);
1431         struct nouveau_connector *nv_connector;
1432         struct nvbios *bios = &drm->vbios;
1433         u8 proto = 0xf;
1434         u8 depth = 0x0;
1435
1436         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1437         nv_encoder->crtc = encoder->crtc;
1438         nv50_outp_acquire(nv_encoder);
1439
1440         switch (nv_encoder->dcb->type) {
1441         case DCB_OUTPUT_TMDS:
1442                 if (nv_encoder->link & 1) {
1443                         proto = 0x1;
1444                         /* Only enable dual-link if:
1445                          *  - Need to (i.e. rate > 165MHz)
1446                          *  - DCB says we can
1447                          *  - Not an HDMI monitor, since there's no dual-link
1448                          *    on HDMI.
1449                          */
1450                         if (mode->clock >= 165000 &&
1451                             nv_encoder->dcb->duallink_possible &&
1452                             !drm_detect_hdmi_monitor(nv_connector->edid))
1453                                 proto |= 0x4;
1454                 } else {
1455                         proto = 0x2;
1456                 }
1457
1458                 nv50_hdmi_enable(&nv_encoder->base.base, mode);
1459                 break;
1460         case DCB_OUTPUT_LVDS:
1461                 proto = 0x0;
1462
1463                 if (bios->fp_no_ddc) {
1464                         if (bios->fp.dual_link)
1465                                 lvds.lvds.script |= 0x0100;
1466                         if (bios->fp.if_is_24bit)
1467                                 lvds.lvds.script |= 0x0200;
1468                 } else {
1469                         if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
1470                                 if (((u8 *)nv_connector->edid)[121] == 2)
1471                                         lvds.lvds.script |= 0x0100;
1472                         } else
1473                         if (mode->clock >= bios->fp.duallink_transition_clk) {
1474                                 lvds.lvds.script |= 0x0100;
1475                         }
1476
1477                         if (lvds.lvds.script & 0x0100) {
1478                                 if (bios->fp.strapless_is_24bit & 2)
1479                                         lvds.lvds.script |= 0x0200;
1480                         } else {
1481                                 if (bios->fp.strapless_is_24bit & 1)
1482                                         lvds.lvds.script |= 0x0200;
1483                         }
1484
1485                         if (nv_connector->base.display_info.bpc == 8)
1486                                 lvds.lvds.script |= 0x0200;
1487                 }
1488
1489                 nvif_mthd(&disp->disp->object, 0, &lvds, sizeof(lvds));
1490                 break;
1491         case DCB_OUTPUT_DP:
1492                 if (nv_connector->base.display_info.bpc == 6)
1493                         depth = 0x2;
1494                 else
1495                 if (nv_connector->base.display_info.bpc == 8)
1496                         depth = 0x5;
1497                 else
1498                         depth = 0x6;
1499
1500                 if (nv_encoder->link & 1)
1501                         proto = 0x8;
1502                 else
1503                         proto = 0x9;
1504
1505                 nv50_audio_enable(encoder, mode);
1506                 break;
1507         default:
1508                 BUG();
1509                 break;
1510         }
1511
1512         nv_encoder->update(nv_encoder, nv_crtc->index, asyh, proto, depth);
1513 }
1514
1515 static const struct drm_encoder_helper_funcs
1516 nv50_sor_help = {
1517         .atomic_check = nv50_outp_atomic_check,
1518         .enable = nv50_sor_enable,
1519         .disable = nv50_sor_disable,
1520 };
1521
1522 static void
1523 nv50_sor_destroy(struct drm_encoder *encoder)
1524 {
1525         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1526         nv50_mstm_del(&nv_encoder->dp.mstm);
1527         drm_encoder_cleanup(encoder);
1528         kfree(encoder);
1529 }
1530
1531 static const struct drm_encoder_funcs
1532 nv50_sor_func = {
1533         .destroy = nv50_sor_destroy,
1534 };
1535
1536 static int
1537 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe)
1538 {
1539         struct nouveau_connector *nv_connector = nouveau_connector(connector);
1540         struct nouveau_drm *drm = nouveau_drm(connector->dev);
1541         struct nvkm_bios *bios = nvxx_bios(&drm->client.device);
1542         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
1543         struct nouveau_encoder *nv_encoder;
1544         struct drm_encoder *encoder;
1545         u8 ver, hdr, cnt, len;
1546         u32 data;
1547         int type, ret;
1548
1549         switch (dcbe->type) {
1550         case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break;
1551         case DCB_OUTPUT_TMDS:
1552         case DCB_OUTPUT_DP:
1553         default:
1554                 type = DRM_MODE_ENCODER_TMDS;
1555                 break;
1556         }
1557
1558         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1559         if (!nv_encoder)
1560                 return -ENOMEM;
1561         nv_encoder->dcb = dcbe;
1562         nv_encoder->update = nv50_sor_update;
1563
1564         encoder = to_drm_encoder(nv_encoder);
1565         encoder->possible_crtcs = dcbe->heads;
1566         encoder->possible_clones = 0;
1567         drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type,
1568                          "sor-%04x-%04x", dcbe->hasht, dcbe->hashm);
1569         drm_encoder_helper_add(encoder, &nv50_sor_help);
1570
1571         drm_connector_attach_encoder(connector, encoder);
1572
1573         if (dcbe->type == DCB_OUTPUT_DP) {
1574                 struct nv50_disp *disp = nv50_disp(encoder->dev);
1575                 struct nvkm_i2c_aux *aux =
1576                         nvkm_i2c_aux_find(i2c, dcbe->i2c_index);
1577                 if (aux) {
1578                         if (disp->disp->object.oclass < GF110_DISP) {
1579                                 /* HW has no support for address-only
1580                                  * transactions, so we're required to
1581                                  * use custom I2C-over-AUX code.
1582                                  */
1583                                 nv_encoder->i2c = &aux->i2c;
1584                         } else {
1585                                 nv_encoder->i2c = &nv_connector->aux.ddc;
1586                         }
1587                         nv_encoder->aux = aux;
1588                 }
1589
1590                 if ((data = nvbios_dp_table(bios, &ver, &hdr, &cnt, &len)) &&
1591                     ver >= 0x40 && (nvbios_rd08(bios, data + 0x08) & 0x04)) {
1592                         ret = nv50_mstm_new(nv_encoder, &nv_connector->aux, 16,
1593                                             nv_connector->base.base.id,
1594                                             &nv_encoder->dp.mstm);
1595                         if (ret)
1596                                 return ret;
1597                 }
1598         } else {
1599                 struct nvkm_i2c_bus *bus =
1600                         nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
1601                 if (bus)
1602                         nv_encoder->i2c = &bus->i2c;
1603         }
1604
1605         return 0;
1606 }
1607
1608 /******************************************************************************
1609  * PIOR
1610  *****************************************************************************/
1611 static int
1612 nv50_pior_atomic_check(struct drm_encoder *encoder,
1613                        struct drm_crtc_state *crtc_state,
1614                        struct drm_connector_state *conn_state)
1615 {
1616         int ret = nv50_outp_atomic_check(encoder, crtc_state, conn_state);
1617         if (ret)
1618                 return ret;
1619         crtc_state->adjusted_mode.clock *= 2;
1620         return 0;
1621 }
1622
1623 static void
1624 nv50_pior_disable(struct drm_encoder *encoder)
1625 {
1626         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1627         struct nv50_core *core = nv50_disp(encoder->dev)->core;
1628         if (nv_encoder->crtc)
1629                 core->func->pior->ctrl(core, nv_encoder->or, 0x00000000, NULL);
1630         nv_encoder->crtc = NULL;
1631         nv50_outp_release(nv_encoder);
1632 }
1633
1634 static void
1635 nv50_pior_enable(struct drm_encoder *encoder)
1636 {
1637         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1638         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1639         struct nouveau_connector *nv_connector;
1640         struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
1641         struct nv50_core *core = nv50_disp(encoder->dev)->core;
1642         u8 owner = 1 << nv_crtc->index;
1643         u8 proto;
1644
1645         nv50_outp_acquire(nv_encoder);
1646
1647         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1648         switch (nv_connector->base.display_info.bpc) {
1649         case 10: asyh->or.depth = 0x6; break;
1650         case  8: asyh->or.depth = 0x5; break;
1651         case  6: asyh->or.depth = 0x2; break;
1652         default: asyh->or.depth = 0x0; break;
1653         }
1654
1655         switch (nv_encoder->dcb->type) {
1656         case DCB_OUTPUT_TMDS:
1657         case DCB_OUTPUT_DP:
1658                 proto = 0x0;
1659                 break;
1660         default:
1661                 BUG();
1662                 break;
1663         }
1664
1665         core->func->pior->ctrl(core, nv_encoder->or, (proto << 8) | owner, asyh);
1666         nv_encoder->crtc = encoder->crtc;
1667 }
1668
1669 static const struct drm_encoder_helper_funcs
1670 nv50_pior_help = {
1671         .atomic_check = nv50_pior_atomic_check,
1672         .enable = nv50_pior_enable,
1673         .disable = nv50_pior_disable,
1674 };
1675
1676 static void
1677 nv50_pior_destroy(struct drm_encoder *encoder)
1678 {
1679         drm_encoder_cleanup(encoder);
1680         kfree(encoder);
1681 }
1682
1683 static const struct drm_encoder_funcs
1684 nv50_pior_func = {
1685         .destroy = nv50_pior_destroy,
1686 };
1687
1688 static int
1689 nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe)
1690 {
1691         struct nouveau_drm *drm = nouveau_drm(connector->dev);
1692         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
1693         struct nvkm_i2c_bus *bus = NULL;
1694         struct nvkm_i2c_aux *aux = NULL;
1695         struct i2c_adapter *ddc;
1696         struct nouveau_encoder *nv_encoder;
1697         struct drm_encoder *encoder;
1698         int type;
1699
1700         switch (dcbe->type) {
1701         case DCB_OUTPUT_TMDS:
1702                 bus  = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_EXT(dcbe->extdev));
1703                 ddc  = bus ? &bus->i2c : NULL;
1704                 type = DRM_MODE_ENCODER_TMDS;
1705                 break;
1706         case DCB_OUTPUT_DP:
1707                 aux  = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbe->extdev));
1708                 ddc  = aux ? &aux->i2c : NULL;
1709                 type = DRM_MODE_ENCODER_TMDS;
1710                 break;
1711         default:
1712                 return -ENODEV;
1713         }
1714
1715         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1716         if (!nv_encoder)
1717                 return -ENOMEM;
1718         nv_encoder->dcb = dcbe;
1719         nv_encoder->i2c = ddc;
1720         nv_encoder->aux = aux;
1721
1722         encoder = to_drm_encoder(nv_encoder);
1723         encoder->possible_crtcs = dcbe->heads;
1724         encoder->possible_clones = 0;
1725         drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type,
1726                          "pior-%04x-%04x", dcbe->hasht, dcbe->hashm);
1727         drm_encoder_helper_add(encoder, &nv50_pior_help);
1728
1729         drm_connector_attach_encoder(connector, encoder);
1730         return 0;
1731 }
1732
1733 /******************************************************************************
1734  * Atomic
1735  *****************************************************************************/
1736
1737 static void
1738 nv50_disp_atomic_commit_core(struct drm_atomic_state *state, u32 *interlock)
1739 {
1740         struct nouveau_drm *drm = nouveau_drm(state->dev);
1741         struct nv50_disp *disp = nv50_disp(drm->dev);
1742         struct nv50_core *core = disp->core;
1743         struct nv50_mstm *mstm;
1744         struct drm_encoder *encoder;
1745
1746         NV_ATOMIC(drm, "commit core %08x\n", interlock[NV50_DISP_INTERLOCK_BASE]);
1747
1748         drm_for_each_encoder(encoder, drm->dev) {
1749                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
1750                         mstm = nouveau_encoder(encoder)->dp.mstm;
1751                         if (mstm && mstm->modified)
1752                                 nv50_mstm_prepare(mstm);
1753                 }
1754         }
1755
1756         core->func->ntfy_init(disp->sync, NV50_DISP_CORE_NTFY);
1757         core->func->update(core, interlock, true);
1758         if (core->func->ntfy_wait_done(disp->sync, NV50_DISP_CORE_NTFY,
1759                                        disp->core->chan.base.device))
1760                 NV_ERROR(drm, "core notifier timeout\n");
1761
1762         drm_for_each_encoder(encoder, drm->dev) {
1763                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
1764                         mstm = nouveau_encoder(encoder)->dp.mstm;
1765                         if (mstm && mstm->modified)
1766                                 nv50_mstm_cleanup(mstm);
1767                 }
1768         }
1769 }
1770
1771 static void
1772 nv50_disp_atomic_commit_wndw(struct drm_atomic_state *state, u32 *interlock)
1773 {
1774         struct drm_plane_state *new_plane_state;
1775         struct drm_plane *plane;
1776         int i;
1777
1778         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1779                 struct nv50_wndw *wndw = nv50_wndw(plane);
1780                 if (interlock[wndw->interlock.type] & wndw->interlock.data) {
1781                         if (wndw->func->update)
1782                                 wndw->func->update(wndw, interlock);
1783                 }
1784         }
1785 }
1786
1787 static void
1788 nv50_disp_atomic_commit_tail(struct drm_atomic_state *state)
1789 {
1790         struct drm_device *dev = state->dev;
1791         struct drm_crtc_state *new_crtc_state, *old_crtc_state;
1792         struct drm_crtc *crtc;
1793         struct drm_plane_state *new_plane_state;
1794         struct drm_plane *plane;
1795         struct nouveau_drm *drm = nouveau_drm(dev);
1796         struct nv50_disp *disp = nv50_disp(dev);
1797         struct nv50_atom *atom = nv50_atom(state);
1798         struct nv50_outp_atom *outp, *outt;
1799         u32 interlock[NV50_DISP_INTERLOCK__SIZE] = {};
1800         int i;
1801
1802         NV_ATOMIC(drm, "commit %d %d\n", atom->lock_core, atom->flush_disable);
1803         drm_atomic_helper_wait_for_fences(dev, state, false);
1804         drm_atomic_helper_wait_for_dependencies(state);
1805         drm_atomic_helper_update_legacy_modeset_state(dev, state);
1806
1807         if (atom->lock_core)
1808                 mutex_lock(&disp->mutex);
1809
1810         /* Disable head(s). */
1811         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
1812                 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
1813                 struct nv50_head *head = nv50_head(crtc);
1814
1815                 NV_ATOMIC(drm, "%s: clr %04x (set %04x)\n", crtc->name,
1816                           asyh->clr.mask, asyh->set.mask);
1817                 if (old_crtc_state->active && !new_crtc_state->active)
1818                         drm_crtc_vblank_off(crtc);
1819
1820                 if (asyh->clr.mask) {
1821                         nv50_head_flush_clr(head, asyh, atom->flush_disable);
1822                         interlock[NV50_DISP_INTERLOCK_CORE] |= 1;
1823                 }
1824         }
1825
1826         /* Disable plane(s). */
1827         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1828                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
1829                 struct nv50_wndw *wndw = nv50_wndw(plane);
1830
1831                 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", plane->name,
1832                           asyw->clr.mask, asyw->set.mask);
1833                 if (!asyw->clr.mask)
1834                         continue;
1835
1836                 nv50_wndw_flush_clr(wndw, interlock, atom->flush_disable, asyw);
1837         }
1838
1839         /* Disable output path(s). */
1840         list_for_each_entry(outp, &atom->outp, head) {
1841                 const struct drm_encoder_helper_funcs *help;
1842                 struct drm_encoder *encoder;
1843
1844                 encoder = outp->encoder;
1845                 help = encoder->helper_private;
1846
1847                 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", encoder->name,
1848                           outp->clr.mask, outp->set.mask);
1849
1850                 if (outp->clr.mask) {
1851                         help->disable(encoder);
1852                         interlock[NV50_DISP_INTERLOCK_CORE] |= 1;
1853                         if (outp->flush_disable) {
1854                                 nv50_disp_atomic_commit_wndw(state, interlock);
1855                                 nv50_disp_atomic_commit_core(state, interlock);
1856                                 memset(interlock, 0x00, sizeof(interlock));
1857                         }
1858                 }
1859         }
1860
1861         /* Flush disable. */
1862         if (interlock[NV50_DISP_INTERLOCK_CORE]) {
1863                 if (atom->flush_disable) {
1864                         nv50_disp_atomic_commit_wndw(state, interlock);
1865                         nv50_disp_atomic_commit_core(state, interlock);
1866                         memset(interlock, 0x00, sizeof(interlock));
1867                 }
1868         }
1869
1870         /* Update output path(s). */
1871         list_for_each_entry_safe(outp, outt, &atom->outp, head) {
1872                 const struct drm_encoder_helper_funcs *help;
1873                 struct drm_encoder *encoder;
1874
1875                 encoder = outp->encoder;
1876                 help = encoder->helper_private;
1877
1878                 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", encoder->name,
1879                           outp->set.mask, outp->clr.mask);
1880
1881                 if (outp->set.mask) {
1882                         help->enable(encoder);
1883                         interlock[NV50_DISP_INTERLOCK_CORE] = 1;
1884                 }
1885
1886                 list_del(&outp->head);
1887                 kfree(outp);
1888         }
1889
1890         /* Update head(s). */
1891         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
1892                 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
1893                 struct nv50_head *head = nv50_head(crtc);
1894
1895                 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name,
1896                           asyh->set.mask, asyh->clr.mask);
1897
1898                 if (asyh->set.mask) {
1899                         nv50_head_flush_set(head, asyh);
1900                         interlock[NV50_DISP_INTERLOCK_CORE] = 1;
1901                 }
1902
1903                 if (new_crtc_state->active) {
1904                         if (!old_crtc_state->active)
1905                                 drm_crtc_vblank_on(crtc);
1906                         if (new_crtc_state->event)
1907                                 drm_crtc_vblank_get(crtc);
1908                 }
1909         }
1910
1911         /* Update plane(s). */
1912         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1913                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
1914                 struct nv50_wndw *wndw = nv50_wndw(plane);
1915
1916                 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", plane->name,
1917                           asyw->set.mask, asyw->clr.mask);
1918                 if ( !asyw->set.mask &&
1919                     (!asyw->clr.mask || atom->flush_disable))
1920                         continue;
1921
1922                 nv50_wndw_flush_set(wndw, interlock, asyw);
1923         }
1924
1925         /* Flush update. */
1926         nv50_disp_atomic_commit_wndw(state, interlock);
1927
1928         if (interlock[NV50_DISP_INTERLOCK_CORE]) {
1929                 if (interlock[NV50_DISP_INTERLOCK_BASE] ||
1930                     interlock[NV50_DISP_INTERLOCK_OVLY] ||
1931                     interlock[NV50_DISP_INTERLOCK_WNDW] ||
1932                     !atom->state.legacy_cursor_update)
1933                         nv50_disp_atomic_commit_core(state, interlock);
1934                 else
1935                         disp->core->func->update(disp->core, interlock, false);
1936         }
1937
1938         if (atom->lock_core)
1939                 mutex_unlock(&disp->mutex);
1940
1941         /* Wait for HW to signal completion. */
1942         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1943                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
1944                 struct nv50_wndw *wndw = nv50_wndw(plane);
1945                 int ret = nv50_wndw_wait_armed(wndw, asyw);
1946                 if (ret)
1947                         NV_ERROR(drm, "%s: timeout\n", plane->name);
1948         }
1949
1950         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
1951                 if (new_crtc_state->event) {
1952                         unsigned long flags;
1953                         /* Get correct count/ts if racing with vblank irq */
1954                         if (new_crtc_state->active)
1955                                 drm_crtc_accurate_vblank_count(crtc);
1956                         spin_lock_irqsave(&crtc->dev->event_lock, flags);
1957                         drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
1958                         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
1959
1960                         new_crtc_state->event = NULL;
1961                         if (new_crtc_state->active)
1962                                 drm_crtc_vblank_put(crtc);
1963                 }
1964         }
1965
1966         drm_atomic_helper_commit_hw_done(state);
1967         drm_atomic_helper_cleanup_planes(dev, state);
1968         drm_atomic_helper_commit_cleanup_done(state);
1969         drm_atomic_state_put(state);
1970 }
1971
1972 static void
1973 nv50_disp_atomic_commit_work(struct work_struct *work)
1974 {
1975         struct drm_atomic_state *state =
1976                 container_of(work, typeof(*state), commit_work);
1977         nv50_disp_atomic_commit_tail(state);
1978 }
1979
1980 static int
1981 nv50_disp_atomic_commit(struct drm_device *dev,
1982                         struct drm_atomic_state *state, bool nonblock)
1983 {
1984         struct nouveau_drm *drm = nouveau_drm(dev);
1985         struct drm_plane_state *new_plane_state;
1986         struct drm_plane *plane;
1987         struct drm_crtc *crtc;
1988         bool active = false;
1989         int ret, i;
1990
1991         ret = pm_runtime_get_sync(dev->dev);
1992         if (ret < 0 && ret != -EACCES)
1993                 return ret;
1994
1995         ret = drm_atomic_helper_setup_commit(state, nonblock);
1996         if (ret)
1997                 goto done;
1998
1999         INIT_WORK(&state->commit_work, nv50_disp_atomic_commit_work);
2000
2001         ret = drm_atomic_helper_prepare_planes(dev, state);
2002         if (ret)
2003                 goto done;
2004
2005         if (!nonblock) {
2006                 ret = drm_atomic_helper_wait_for_fences(dev, state, true);
2007                 if (ret)
2008                         goto err_cleanup;
2009         }
2010
2011         ret = drm_atomic_helper_swap_state(state, true);
2012         if (ret)
2013                 goto err_cleanup;
2014
2015         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2016                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
2017                 struct nv50_wndw *wndw = nv50_wndw(plane);
2018
2019                 if (asyw->set.image)
2020                         nv50_wndw_ntfy_enable(wndw, asyw);
2021         }
2022
2023         drm_atomic_state_get(state);
2024
2025         if (nonblock)
2026                 queue_work(system_unbound_wq, &state->commit_work);
2027         else
2028                 nv50_disp_atomic_commit_tail(state);
2029
2030         drm_for_each_crtc(crtc, dev) {
2031                 if (crtc->state->active) {
2032                         if (!drm->have_disp_power_ref) {
2033                                 drm->have_disp_power_ref = true;
2034                                 return 0;
2035                         }
2036                         active = true;
2037                         break;
2038                 }
2039         }
2040
2041         if (!active && drm->have_disp_power_ref) {
2042                 pm_runtime_put_autosuspend(dev->dev);
2043                 drm->have_disp_power_ref = false;
2044         }
2045
2046 err_cleanup:
2047         if (ret)
2048                 drm_atomic_helper_cleanup_planes(dev, state);
2049 done:
2050         pm_runtime_put_autosuspend(dev->dev);
2051         return ret;
2052 }
2053
2054 static struct nv50_outp_atom *
2055 nv50_disp_outp_atomic_add(struct nv50_atom *atom, struct drm_encoder *encoder)
2056 {
2057         struct nv50_outp_atom *outp;
2058
2059         list_for_each_entry(outp, &atom->outp, head) {
2060                 if (outp->encoder == encoder)
2061                         return outp;
2062         }
2063
2064         outp = kzalloc(sizeof(*outp), GFP_KERNEL);
2065         if (!outp)
2066                 return ERR_PTR(-ENOMEM);
2067
2068         list_add(&outp->head, &atom->outp);
2069         outp->encoder = encoder;
2070         return outp;
2071 }
2072
2073 static int
2074 nv50_disp_outp_atomic_check_clr(struct nv50_atom *atom,
2075                                 struct drm_connector_state *old_connector_state)
2076 {
2077         struct drm_encoder *encoder = old_connector_state->best_encoder;
2078         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
2079         struct drm_crtc *crtc;
2080         struct nv50_outp_atom *outp;
2081
2082         if (!(crtc = old_connector_state->crtc))
2083                 return 0;
2084
2085         old_crtc_state = drm_atomic_get_old_crtc_state(&atom->state, crtc);
2086         new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
2087         if (old_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
2088                 outp = nv50_disp_outp_atomic_add(atom, encoder);
2089                 if (IS_ERR(outp))
2090                         return PTR_ERR(outp);
2091
2092                 if (outp->encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
2093                         outp->flush_disable = true;
2094                         atom->flush_disable = true;
2095                 }
2096                 outp->clr.ctrl = true;
2097                 atom->lock_core = true;
2098         }
2099
2100         return 0;
2101 }
2102
2103 static int
2104 nv50_disp_outp_atomic_check_set(struct nv50_atom *atom,
2105                                 struct drm_connector_state *connector_state)
2106 {
2107         struct drm_encoder *encoder = connector_state->best_encoder;
2108         struct drm_crtc_state *new_crtc_state;
2109         struct drm_crtc *crtc;
2110         struct nv50_outp_atom *outp;
2111
2112         if (!(crtc = connector_state->crtc))
2113                 return 0;
2114
2115         new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
2116         if (new_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
2117                 outp = nv50_disp_outp_atomic_add(atom, encoder);
2118                 if (IS_ERR(outp))
2119                         return PTR_ERR(outp);
2120
2121                 outp->set.ctrl = true;
2122                 atom->lock_core = true;
2123         }
2124
2125         return 0;
2126 }
2127
2128 static int
2129 nv50_disp_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
2130 {
2131         struct nv50_atom *atom = nv50_atom(state);
2132         struct drm_connector_state *old_connector_state, *new_connector_state;
2133         struct drm_connector *connector;
2134         struct drm_crtc_state *new_crtc_state;
2135         struct drm_crtc *crtc;
2136         int ret, i;
2137
2138         /* We need to handle colour management on a per-plane basis. */
2139         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
2140                 if (new_crtc_state->color_mgmt_changed) {
2141                         ret = drm_atomic_add_affected_planes(state, crtc);
2142                         if (ret)
2143                                 return ret;
2144                 }
2145         }
2146
2147         ret = drm_atomic_helper_check(dev, state);
2148         if (ret)
2149                 return ret;
2150
2151         for_each_oldnew_connector_in_state(state, connector, old_connector_state, new_connector_state, i) {
2152                 ret = nv50_disp_outp_atomic_check_clr(atom, old_connector_state);
2153                 if (ret)
2154                         return ret;
2155
2156                 ret = nv50_disp_outp_atomic_check_set(atom, new_connector_state);
2157                 if (ret)
2158                         return ret;
2159         }
2160
2161         ret = drm_dp_mst_atomic_check(state);
2162         if (ret)
2163                 return ret;
2164
2165         return 0;
2166 }
2167
2168 static void
2169 nv50_disp_atomic_state_clear(struct drm_atomic_state *state)
2170 {
2171         struct nv50_atom *atom = nv50_atom(state);
2172         struct nv50_outp_atom *outp, *outt;
2173
2174         list_for_each_entry_safe(outp, outt, &atom->outp, head) {
2175                 list_del(&outp->head);
2176                 kfree(outp);
2177         }
2178
2179         drm_atomic_state_default_clear(state);
2180 }
2181
2182 static void
2183 nv50_disp_atomic_state_free(struct drm_atomic_state *state)
2184 {
2185         struct nv50_atom *atom = nv50_atom(state);
2186         drm_atomic_state_default_release(&atom->state);
2187         kfree(atom);
2188 }
2189
2190 static struct drm_atomic_state *
2191 nv50_disp_atomic_state_alloc(struct drm_device *dev)
2192 {
2193         struct nv50_atom *atom;
2194         if (!(atom = kzalloc(sizeof(*atom), GFP_KERNEL)) ||
2195             drm_atomic_state_init(dev, &atom->state) < 0) {
2196                 kfree(atom);
2197                 return NULL;
2198         }
2199         INIT_LIST_HEAD(&atom->outp);
2200         return &atom->state;
2201 }
2202
2203 static const struct drm_mode_config_funcs
2204 nv50_disp_func = {
2205         .fb_create = nouveau_user_framebuffer_create,
2206         .output_poll_changed = nouveau_fbcon_output_poll_changed,
2207         .atomic_check = nv50_disp_atomic_check,
2208         .atomic_commit = nv50_disp_atomic_commit,
2209         .atomic_state_alloc = nv50_disp_atomic_state_alloc,
2210         .atomic_state_clear = nv50_disp_atomic_state_clear,
2211         .atomic_state_free = nv50_disp_atomic_state_free,
2212 };
2213
2214 /******************************************************************************
2215  * Init
2216  *****************************************************************************/
2217
2218 void
2219 nv50_display_fini(struct drm_device *dev)
2220 {
2221         struct nouveau_encoder *nv_encoder;
2222         struct drm_encoder *encoder;
2223         struct drm_plane *plane;
2224
2225         drm_for_each_plane(plane, dev) {
2226                 struct nv50_wndw *wndw = nv50_wndw(plane);
2227                 if (plane->funcs != &nv50_wndw)
2228                         continue;
2229                 nv50_wndw_fini(wndw);
2230         }
2231
2232         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2233                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2234                         nv_encoder = nouveau_encoder(encoder);
2235                         nv50_mstm_fini(nv_encoder->dp.mstm);
2236                 }
2237         }
2238 }
2239
2240 int
2241 nv50_display_init(struct drm_device *dev)
2242 {
2243         struct nv50_core *core = nv50_disp(dev)->core;
2244         struct drm_encoder *encoder;
2245         struct drm_plane *plane;
2246
2247         core->func->init(core);
2248
2249         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2250                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2251                         struct nouveau_encoder *nv_encoder =
2252                                 nouveau_encoder(encoder);
2253                         nv50_mstm_init(nv_encoder->dp.mstm);
2254                 }
2255         }
2256
2257         drm_for_each_plane(plane, dev) {
2258                 struct nv50_wndw *wndw = nv50_wndw(plane);
2259                 if (plane->funcs != &nv50_wndw)
2260                         continue;
2261                 nv50_wndw_init(wndw);
2262         }
2263
2264         return 0;
2265 }
2266
2267 void
2268 nv50_display_destroy(struct drm_device *dev)
2269 {
2270         struct nv50_disp *disp = nv50_disp(dev);
2271
2272         nv50_core_del(&disp->core);
2273
2274         nouveau_bo_unmap(disp->sync);
2275         if (disp->sync)
2276                 nouveau_bo_unpin(disp->sync);
2277         nouveau_bo_ref(NULL, &disp->sync);
2278
2279         nouveau_display(dev)->priv = NULL;
2280         kfree(disp);
2281 }
2282
2283 int
2284 nv50_display_create(struct drm_device *dev)
2285 {
2286         struct nvif_device *device = &nouveau_drm(dev)->client.device;
2287         struct nouveau_drm *drm = nouveau_drm(dev);
2288         struct dcb_table *dcb = &drm->vbios.dcb;
2289         struct drm_connector *connector, *tmp;
2290         struct nv50_disp *disp;
2291         struct dcb_output *dcbe;
2292         int crtcs, ret, i;
2293
2294         disp = kzalloc(sizeof(*disp), GFP_KERNEL);
2295         if (!disp)
2296                 return -ENOMEM;
2297
2298         mutex_init(&disp->mutex);
2299
2300         nouveau_display(dev)->priv = disp;
2301         nouveau_display(dev)->dtor = nv50_display_destroy;
2302         nouveau_display(dev)->init = nv50_display_init;
2303         nouveau_display(dev)->fini = nv50_display_fini;
2304         disp->disp = &nouveau_display(dev)->disp;
2305         dev->mode_config.funcs = &nv50_disp_func;
2306         dev->mode_config.quirk_addfb_prefer_xbgr_30bpp = true;
2307
2308         /* small shared memory area we use for notifiers and semaphores */
2309         ret = nouveau_bo_new(&drm->client, 4096, 0x1000, TTM_PL_FLAG_VRAM,
2310                              0, 0x0000, NULL, NULL, &disp->sync);
2311         if (!ret) {
2312                 ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM, true);
2313                 if (!ret) {
2314                         ret = nouveau_bo_map(disp->sync);
2315                         if (ret)
2316                                 nouveau_bo_unpin(disp->sync);
2317                 }
2318                 if (ret)
2319                         nouveau_bo_ref(NULL, &disp->sync);
2320         }
2321
2322         if (ret)
2323                 goto out;
2324
2325         /* allocate master evo channel */
2326         ret = nv50_core_new(drm, &disp->core);
2327         if (ret)
2328                 goto out;
2329
2330         /* create crtc objects to represent the hw heads */
2331         if (disp->disp->object.oclass >= GV100_DISP)
2332                 crtcs = nvif_rd32(&device->object, 0x610060) & 0xff;
2333         else
2334         if (disp->disp->object.oclass >= GF110_DISP)
2335                 crtcs = nvif_rd32(&device->object, 0x612004) & 0xf;
2336         else
2337                 crtcs = 0x3;
2338
2339         for (i = 0; i < fls(crtcs); i++) {
2340                 if (!(crtcs & (1 << i)))
2341                         continue;
2342                 ret = nv50_head_create(dev, i);
2343                 if (ret)
2344                         goto out;
2345         }
2346
2347         /* create encoder/connector objects based on VBIOS DCB table */
2348         for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
2349                 connector = nouveau_connector_create(dev, dcbe);
2350                 if (IS_ERR(connector))
2351                         continue;
2352
2353                 if (dcbe->location == DCB_LOC_ON_CHIP) {
2354                         switch (dcbe->type) {
2355                         case DCB_OUTPUT_TMDS:
2356                         case DCB_OUTPUT_LVDS:
2357                         case DCB_OUTPUT_DP:
2358                                 ret = nv50_sor_create(connector, dcbe);
2359                                 break;
2360                         case DCB_OUTPUT_ANALOG:
2361                                 ret = nv50_dac_create(connector, dcbe);
2362                                 break;
2363                         default:
2364                                 ret = -ENODEV;
2365                                 break;
2366                         }
2367                 } else {
2368                         ret = nv50_pior_create(connector, dcbe);
2369                 }
2370
2371                 if (ret) {
2372                         NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n",
2373                                      dcbe->location, dcbe->type,
2374                                      ffs(dcbe->or) - 1, ret);
2375                         ret = 0;
2376                 }
2377         }
2378
2379         /* cull any connectors we created that don't have an encoder */
2380         list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
2381                 if (connector->encoder_ids[0])
2382                         continue;
2383
2384                 NV_WARN(drm, "%s has no encoders, removing\n",
2385                         connector->name);
2386                 connector->funcs->destroy(connector);
2387         }
2388
2389         /* Disable vblank irqs aggressively for power-saving, safe on nv50+ */
2390         dev->vblank_disable_immediate = true;
2391
2392 out:
2393         if (ret)
2394                 nv50_display_destroy(dev);
2395         return ret;
2396 }