2 * Copyright 1993-2003 NVIDIA, Corporation
3 * Copyright 2006 Dave Airlie
4 * Copyright 2007 Maarten Maathuis
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
25 #include <linux/pm_runtime.h>
28 #include <drm/drm_crtc_helper.h>
29 #include <drm/drm_plane_helper.h>
31 #include "nouveau_drv.h"
32 #include "nouveau_reg.h"
33 #include "nouveau_ttm.h"
34 #include "nouveau_bo.h"
35 #include "nouveau_gem.h"
36 #include "nouveau_encoder.h"
37 #include "nouveau_connector.h"
38 #include "nouveau_crtc.h"
41 #include "nouveau_fbcon.h"
44 #include <subdev/bios/pll.h>
45 #include <subdev/clk.h>
48 nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
49 struct drm_framebuffer *old_fb);
52 crtc_wr_cio_state(struct drm_crtc *crtc, struct nv04_crtc_reg *crtcstate, int index)
54 NVWriteVgaCrtc(crtc->dev, nouveau_crtc(crtc)->index, index,
55 crtcstate->CRTC[index]);
58 static void nv_crtc_set_digital_vibrance(struct drm_crtc *crtc, int level)
60 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
61 struct drm_device *dev = crtc->dev;
62 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
64 regp->CRTC[NV_CIO_CRE_CSB] = nv_crtc->saturation = level;
65 if (nv_crtc->saturation && nv_gf4_disp_arch(crtc->dev)) {
66 regp->CRTC[NV_CIO_CRE_CSB] = 0x80;
67 regp->CRTC[NV_CIO_CRE_5B] = nv_crtc->saturation << 2;
68 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_5B);
70 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_CSB);
73 static void nv_crtc_set_image_sharpening(struct drm_crtc *crtc, int level)
75 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
76 struct drm_device *dev = crtc->dev;
77 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
79 nv_crtc->sharpness = level;
80 if (level < 0) /* blur is in hw range 0x3f -> 0x20 */
82 regp->ramdac_634 = level;
83 NVWriteRAMDAC(crtc->dev, nv_crtc->index, NV_PRAMDAC_634, regp->ramdac_634);
86 #define PLLSEL_VPLL1_MASK \
87 (NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_VPLL \
88 | NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO_DB2)
89 #define PLLSEL_VPLL2_MASK \
90 (NV_PRAMDAC_PLL_COEFF_SELECT_PLL_SOURCE_VPLL2 \
91 | NV_PRAMDAC_PLL_COEFF_SELECT_VCLK2_RATIO_DB2)
92 #define PLLSEL_TV_MASK \
93 (NV_PRAMDAC_PLL_COEFF_SELECT_TV_VSCLK1 \
94 | NV_PRAMDAC_PLL_COEFF_SELECT_TV_PCLK1 \
95 | NV_PRAMDAC_PLL_COEFF_SELECT_TV_VSCLK2 \
96 | NV_PRAMDAC_PLL_COEFF_SELECT_TV_PCLK2)
98 /* NV4x 0x40.. pll notes:
99 * gpu pll: 0x4000 + 0x4004
100 * ?gpu? pll: 0x4008 + 0x400c
101 * vpll1: 0x4010 + 0x4014
102 * vpll2: 0x4018 + 0x401c
103 * mpll: 0x4020 + 0x4024
104 * mpll: 0x4038 + 0x403c
106 * the first register of each pair has some unknown details:
107 * bits 0-7: redirected values from elsewhere? (similar to PLL_SETUP_CONTROL?)
108 * bits 20-23: (mpll) something to do with post divider?
109 * bits 28-31: related to single stage mode? (bit 8/12)
112 static void nv_crtc_calc_state_ext(struct drm_crtc *crtc, struct drm_display_mode * mode, int dot_clock)
114 struct drm_device *dev = crtc->dev;
115 struct nouveau_drm *drm = nouveau_drm(dev);
116 struct nvkm_bios *bios = nvxx_bios(&drm->device);
117 struct nvkm_clk *clk = nvxx_clk(&drm->device);
118 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
119 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg;
120 struct nv04_crtc_reg *regp = &state->crtc_reg[nv_crtc->index];
121 struct nvkm_pll_vals *pv = ®p->pllvals;
122 struct nvbios_pll pll_lim;
124 if (nvbios_pll_parse(bios, nv_crtc->index ? PLL_VPLL1 : PLL_VPLL0,
128 /* NM2 == 0 is used to determine single stage mode on two stage plls */
131 /* for newer nv4x the blob uses only the first stage of the vpll below a
132 * certain clock. for a certain nv4b this is 150MHz. since the max
133 * output frequency of the first stage for this card is 300MHz, it is
134 * assumed the threshold is given by vco1 maxfreq/2
136 /* for early nv4x, specifically nv40 and *some* nv43 (devids 0 and 6,
137 * not 8, others unknown), the blob always uses both plls. no problem
138 * has yet been observed in allowing the use a single stage pll on all
139 * nv43 however. the behaviour of single stage use is untested on nv40
141 if (drm->device.info.chipset > 0x40 && dot_clock <= (pll_lim.vco1.max_freq / 2))
142 memset(&pll_lim.vco2, 0, sizeof(pll_lim.vco2));
145 if (!clk->pll_calc(clk, &pll_lim, dot_clock, pv))
148 state->pllsel &= PLLSEL_VPLL1_MASK | PLLSEL_VPLL2_MASK | PLLSEL_TV_MASK;
150 /* The blob uses this always, so let's do the same */
151 if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE)
152 state->pllsel |= NV_PRAMDAC_PLL_COEFF_SELECT_USE_VPLL2_TRUE;
153 /* again nv40 and some nv43 act more like nv3x as described above */
154 if (drm->device.info.chipset < 0x41)
155 state->pllsel |= NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_MPLL |
156 NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_NVPLL;
157 state->pllsel |= nv_crtc->index ? PLLSEL_VPLL2_MASK : PLLSEL_VPLL1_MASK;
160 NV_DEBUG(drm, "vpll: n1 %d n2 %d m1 %d m2 %d log2p %d\n",
161 pv->N1, pv->N2, pv->M1, pv->M2, pv->log2P);
163 NV_DEBUG(drm, "vpll: n %d m %d log2p %d\n",
164 pv->N1, pv->M1, pv->log2P);
166 nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset);
170 nv_crtc_dpms(struct drm_crtc *crtc, int mode)
172 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
173 struct drm_device *dev = crtc->dev;
174 struct nouveau_drm *drm = nouveau_drm(dev);
175 unsigned char seq1 = 0, crtc17 = 0;
176 unsigned char crtc1A;
178 NV_DEBUG(drm, "Setting dpms mode %d on CRTC %d\n", mode,
181 if (nv_crtc->last_dpms == mode) /* Don't do unnecessary mode changes. */
184 nv_crtc->last_dpms = mode;
186 if (nv_two_heads(dev))
187 NVSetOwner(dev, nv_crtc->index);
189 /* nv4ref indicates these two RPC1 bits inhibit h/v sync */
190 crtc1A = NVReadVgaCrtc(dev, nv_crtc->index,
191 NV_CIO_CRE_RPC1_INDEX) & ~0xC0;
193 case DRM_MODE_DPMS_STANDBY:
194 /* Screen: Off; HSync: Off, VSync: On -- Not Supported */
199 case DRM_MODE_DPMS_SUSPEND:
200 /* Screen: Off; HSync: On, VSync: Off -- Not Supported */
205 case DRM_MODE_DPMS_OFF:
206 /* Screen: Off; HSync: Off, VSync: Off */
211 case DRM_MODE_DPMS_ON:
213 /* Screen: On; HSync: On, VSync: On */
219 NVVgaSeqReset(dev, nv_crtc->index, true);
220 /* Each head has it's own sequencer, so we can turn it off when we want */
221 seq1 |= (NVReadVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX) & ~0x20);
222 NVWriteVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX, seq1);
223 crtc17 |= (NVReadVgaCrtc(dev, nv_crtc->index, NV_CIO_CR_MODE_INDEX) & ~0x80);
225 NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CR_MODE_INDEX, crtc17);
226 NVVgaSeqReset(dev, nv_crtc->index, false);
228 NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RPC1_INDEX, crtc1A);
232 nv_crtc_mode_set_vga(struct drm_crtc *crtc, struct drm_display_mode *mode)
234 struct drm_device *dev = crtc->dev;
235 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
236 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
237 struct drm_framebuffer *fb = crtc->primary->fb;
239 /* Calculate our timings */
240 int horizDisplay = (mode->crtc_hdisplay >> 3) - 1;
241 int horizStart = (mode->crtc_hsync_start >> 3) + 1;
242 int horizEnd = (mode->crtc_hsync_end >> 3) + 1;
243 int horizTotal = (mode->crtc_htotal >> 3) - 5;
244 int horizBlankStart = (mode->crtc_hdisplay >> 3) - 1;
245 int horizBlankEnd = (mode->crtc_htotal >> 3) - 1;
246 int vertDisplay = mode->crtc_vdisplay - 1;
247 int vertStart = mode->crtc_vsync_start - 1;
248 int vertEnd = mode->crtc_vsync_end - 1;
249 int vertTotal = mode->crtc_vtotal - 2;
250 int vertBlankStart = mode->crtc_vdisplay - 1;
251 int vertBlankEnd = mode->crtc_vtotal - 1;
253 struct drm_encoder *encoder;
254 bool fp_output = false;
256 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
257 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
259 if (encoder->crtc == crtc &&
260 (nv_encoder->dcb->type == DCB_OUTPUT_LVDS ||
261 nv_encoder->dcb->type == DCB_OUTPUT_TMDS))
266 vertStart = vertTotal - 3;
267 vertEnd = vertTotal - 2;
268 vertBlankStart = vertStart;
269 horizStart = horizTotal - 5;
270 horizEnd = horizTotal - 2;
271 horizBlankEnd = horizTotal + 4;
273 if (dev->overlayAdaptor && drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS)
274 /* This reportedly works around some video overlay bandwidth problems */
279 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
283 ErrorF("horizDisplay: 0x%X \n", horizDisplay);
284 ErrorF("horizStart: 0x%X \n", horizStart);
285 ErrorF("horizEnd: 0x%X \n", horizEnd);
286 ErrorF("horizTotal: 0x%X \n", horizTotal);
287 ErrorF("horizBlankStart: 0x%X \n", horizBlankStart);
288 ErrorF("horizBlankEnd: 0x%X \n", horizBlankEnd);
289 ErrorF("vertDisplay: 0x%X \n", vertDisplay);
290 ErrorF("vertStart: 0x%X \n", vertStart);
291 ErrorF("vertEnd: 0x%X \n", vertEnd);
292 ErrorF("vertTotal: 0x%X \n", vertTotal);
293 ErrorF("vertBlankStart: 0x%X \n", vertBlankStart);
294 ErrorF("vertBlankEnd: 0x%X \n", vertBlankEnd);
298 * compute correct Hsync & Vsync polarity
300 if ((mode->flags & (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))
301 && (mode->flags & (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) {
303 regp->MiscOutReg = 0x23;
304 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
305 regp->MiscOutReg |= 0x40;
306 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
307 regp->MiscOutReg |= 0x80;
309 int vdisplay = mode->vdisplay;
310 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
313 vdisplay *= mode->vscan;
315 regp->MiscOutReg = 0xA3; /* +hsync -vsync */
316 else if (vdisplay < 480)
317 regp->MiscOutReg = 0x63; /* -hsync +vsync */
318 else if (vdisplay < 768)
319 regp->MiscOutReg = 0xE3; /* -hsync -vsync */
321 regp->MiscOutReg = 0x23; /* +hsync +vsync */
327 regp->Sequencer[NV_VIO_SR_RESET_INDEX] = 0x00;
328 /* 0x20 disables the sequencer */
329 if (mode->flags & DRM_MODE_FLAG_CLKDIV2)
330 regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x29;
332 regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x21;
333 regp->Sequencer[NV_VIO_SR_PLANE_MASK_INDEX] = 0x0F;
334 regp->Sequencer[NV_VIO_SR_CHAR_MAP_INDEX] = 0x00;
335 regp->Sequencer[NV_VIO_SR_MEM_MODE_INDEX] = 0x0E;
340 regp->CRTC[NV_CIO_CR_HDT_INDEX] = horizTotal;
341 regp->CRTC[NV_CIO_CR_HDE_INDEX] = horizDisplay;
342 regp->CRTC[NV_CIO_CR_HBS_INDEX] = horizBlankStart;
343 regp->CRTC[NV_CIO_CR_HBE_INDEX] = (1 << 7) |
344 XLATE(horizBlankEnd, 0, NV_CIO_CR_HBE_4_0);
345 regp->CRTC[NV_CIO_CR_HRS_INDEX] = horizStart;
346 regp->CRTC[NV_CIO_CR_HRE_INDEX] = XLATE(horizBlankEnd, 5, NV_CIO_CR_HRE_HBE_5) |
347 XLATE(horizEnd, 0, NV_CIO_CR_HRE_4_0);
348 regp->CRTC[NV_CIO_CR_VDT_INDEX] = vertTotal;
349 regp->CRTC[NV_CIO_CR_OVL_INDEX] = XLATE(vertStart, 9, NV_CIO_CR_OVL_VRS_9) |
350 XLATE(vertDisplay, 9, NV_CIO_CR_OVL_VDE_9) |
351 XLATE(vertTotal, 9, NV_CIO_CR_OVL_VDT_9) |
353 XLATE(vertBlankStart, 8, NV_CIO_CR_OVL_VBS_8) |
354 XLATE(vertStart, 8, NV_CIO_CR_OVL_VRS_8) |
355 XLATE(vertDisplay, 8, NV_CIO_CR_OVL_VDE_8) |
356 XLATE(vertTotal, 8, NV_CIO_CR_OVL_VDT_8);
357 regp->CRTC[NV_CIO_CR_RSAL_INDEX] = 0x00;
358 regp->CRTC[NV_CIO_CR_CELL_HT_INDEX] = ((mode->flags & DRM_MODE_FLAG_DBLSCAN) ? MASK(NV_CIO_CR_CELL_HT_SCANDBL) : 0) |
360 XLATE(vertBlankStart, 9, NV_CIO_CR_CELL_HT_VBS_9);
361 regp->CRTC[NV_CIO_CR_CURS_ST_INDEX] = 0x00;
362 regp->CRTC[NV_CIO_CR_CURS_END_INDEX] = 0x00;
363 regp->CRTC[NV_CIO_CR_SA_HI_INDEX] = 0x00;
364 regp->CRTC[NV_CIO_CR_SA_LO_INDEX] = 0x00;
365 regp->CRTC[NV_CIO_CR_TCOFF_HI_INDEX] = 0x00;
366 regp->CRTC[NV_CIO_CR_TCOFF_LO_INDEX] = 0x00;
367 regp->CRTC[NV_CIO_CR_VRS_INDEX] = vertStart;
368 regp->CRTC[NV_CIO_CR_VRE_INDEX] = 1 << 5 | XLATE(vertEnd, 0, NV_CIO_CR_VRE_3_0);
369 regp->CRTC[NV_CIO_CR_VDE_INDEX] = vertDisplay;
370 /* framebuffer can be larger than crtc scanout area. */
371 regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = fb->pitches[0] / 8;
372 regp->CRTC[NV_CIO_CR_ULINE_INDEX] = 0x00;
373 regp->CRTC[NV_CIO_CR_VBS_INDEX] = vertBlankStart;
374 regp->CRTC[NV_CIO_CR_VBE_INDEX] = vertBlankEnd;
375 regp->CRTC[NV_CIO_CR_MODE_INDEX] = 0x43;
376 regp->CRTC[NV_CIO_CR_LCOMP_INDEX] = 0xff;
379 * Some extended CRTC registers (they are not saved with the rest of the vga regs).
382 /* framebuffer can be larger than crtc scanout area. */
383 regp->CRTC[NV_CIO_CRE_RPC0_INDEX] =
384 XLATE(fb->pitches[0] / 8, 8, NV_CIO_CRE_RPC0_OFFSET_10_8);
385 regp->CRTC[NV_CIO_CRE_42] =
386 XLATE(fb->pitches[0] / 8, 11, NV_CIO_CRE_42_OFFSET_11);
387 regp->CRTC[NV_CIO_CRE_RPC1_INDEX] = mode->crtc_hdisplay < 1280 ?
388 MASK(NV_CIO_CRE_RPC1_LARGE) : 0x00;
389 regp->CRTC[NV_CIO_CRE_LSR_INDEX] = XLATE(horizBlankEnd, 6, NV_CIO_CRE_LSR_HBE_6) |
390 XLATE(vertBlankStart, 10, NV_CIO_CRE_LSR_VBS_10) |
391 XLATE(vertStart, 10, NV_CIO_CRE_LSR_VRS_10) |
392 XLATE(vertDisplay, 10, NV_CIO_CRE_LSR_VDE_10) |
393 XLATE(vertTotal, 10, NV_CIO_CRE_LSR_VDT_10);
394 regp->CRTC[NV_CIO_CRE_HEB__INDEX] = XLATE(horizStart, 8, NV_CIO_CRE_HEB_HRS_8) |
395 XLATE(horizBlankStart, 8, NV_CIO_CRE_HEB_HBS_8) |
396 XLATE(horizDisplay, 8, NV_CIO_CRE_HEB_HDE_8) |
397 XLATE(horizTotal, 8, NV_CIO_CRE_HEB_HDT_8);
398 regp->CRTC[NV_CIO_CRE_EBR_INDEX] = XLATE(vertBlankStart, 11, NV_CIO_CRE_EBR_VBS_11) |
399 XLATE(vertStart, 11, NV_CIO_CRE_EBR_VRS_11) |
400 XLATE(vertDisplay, 11, NV_CIO_CRE_EBR_VDE_11) |
401 XLATE(vertTotal, 11, NV_CIO_CRE_EBR_VDT_11);
403 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
404 horizTotal = (horizTotal >> 1) & ~1;
405 regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = horizTotal;
406 regp->CRTC[NV_CIO_CRE_HEB__INDEX] |= XLATE(horizTotal, 8, NV_CIO_CRE_HEB_ILC_8);
408 regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = 0xff; /* interlace off */
411 * Graphics Display Controller
413 regp->Graphics[NV_VIO_GX_SR_INDEX] = 0x00;
414 regp->Graphics[NV_VIO_GX_SREN_INDEX] = 0x00;
415 regp->Graphics[NV_VIO_GX_CCOMP_INDEX] = 0x00;
416 regp->Graphics[NV_VIO_GX_ROP_INDEX] = 0x00;
417 regp->Graphics[NV_VIO_GX_READ_MAP_INDEX] = 0x00;
418 regp->Graphics[NV_VIO_GX_MODE_INDEX] = 0x40; /* 256 color mode */
419 regp->Graphics[NV_VIO_GX_MISC_INDEX] = 0x05; /* map 64k mem + graphic mode */
420 regp->Graphics[NV_VIO_GX_DONT_CARE_INDEX] = 0x0F;
421 regp->Graphics[NV_VIO_GX_BIT_MASK_INDEX] = 0xFF;
423 regp->Attribute[0] = 0x00; /* standard colormap translation */
424 regp->Attribute[1] = 0x01;
425 regp->Attribute[2] = 0x02;
426 regp->Attribute[3] = 0x03;
427 regp->Attribute[4] = 0x04;
428 regp->Attribute[5] = 0x05;
429 regp->Attribute[6] = 0x06;
430 regp->Attribute[7] = 0x07;
431 regp->Attribute[8] = 0x08;
432 regp->Attribute[9] = 0x09;
433 regp->Attribute[10] = 0x0A;
434 regp->Attribute[11] = 0x0B;
435 regp->Attribute[12] = 0x0C;
436 regp->Attribute[13] = 0x0D;
437 regp->Attribute[14] = 0x0E;
438 regp->Attribute[15] = 0x0F;
439 regp->Attribute[NV_CIO_AR_MODE_INDEX] = 0x01; /* Enable graphic mode */
441 regp->Attribute[NV_CIO_AR_OSCAN_INDEX] = 0x00;
442 regp->Attribute[NV_CIO_AR_PLANE_INDEX] = 0x0F; /* enable all color planes */
443 regp->Attribute[NV_CIO_AR_HPP_INDEX] = 0x00;
444 regp->Attribute[NV_CIO_AR_CSEL_INDEX] = 0x00;
448 * Sets up registers for the given mode/adjusted_mode pair.
450 * The clocks, CRTCs and outputs attached to this CRTC must be off.
452 * This shouldn't enable any clocks, CRTCs, or outputs, but they should
453 * be easily turned on/off after this.
456 nv_crtc_mode_set_regs(struct drm_crtc *crtc, struct drm_display_mode * mode)
458 struct drm_device *dev = crtc->dev;
459 struct nouveau_drm *drm = nouveau_drm(dev);
460 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
461 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
462 struct nv04_crtc_reg *savep = &nv04_display(dev)->saved_reg.crtc_reg[nv_crtc->index];
463 struct drm_encoder *encoder;
464 bool lvds_output = false, tmds_output = false, tv_output = false,
465 off_chip_digital = false;
467 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
468 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
469 bool digital = false;
471 if (encoder->crtc != crtc)
474 if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS)
475 digital = lvds_output = true;
476 if (nv_encoder->dcb->type == DCB_OUTPUT_TV)
478 if (nv_encoder->dcb->type == DCB_OUTPUT_TMDS)
479 digital = tmds_output = true;
480 if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP && digital)
481 off_chip_digital = true;
484 /* Registers not directly related to the (s)vga mode */
486 /* What is the meaning of this register? */
487 /* A few popular values are 0x18, 0x1c, 0x38, 0x3c */
488 regp->CRTC[NV_CIO_CRE_ENH_INDEX] = savep->CRTC[NV_CIO_CRE_ENH_INDEX] & ~(1<<5);
490 regp->crtc_eng_ctrl = 0;
491 /* Except for rare conditions I2C is enabled on the primary crtc */
492 if (nv_crtc->index == 0)
493 regp->crtc_eng_ctrl |= NV_CRTC_FSEL_I2C;
495 /* Set overlay to desired crtc. */
496 if (dev->overlayAdaptor) {
497 NVPortPrivPtr pPriv = GET_OVERLAY_PRIVATE(dev);
498 if (pPriv->overlayCRTC == nv_crtc->index)
499 regp->crtc_eng_ctrl |= NV_CRTC_FSEL_OVERLAY;
503 /* ADDRESS_SPACE_PNVM is the same as setting HCUR_ASI */
504 regp->cursor_cfg = NV_PCRTC_CURSOR_CONFIG_CUR_LINES_64 |
505 NV_PCRTC_CURSOR_CONFIG_CUR_PIXELS_64 |
506 NV_PCRTC_CURSOR_CONFIG_ADDRESS_SPACE_PNVM;
507 if (drm->device.info.chipset >= 0x11)
508 regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_CUR_BPP_32;
509 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
510 regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_DOUBLE_SCAN_ENABLE;
512 /* Unblock some timings */
513 regp->CRTC[NV_CIO_CRE_53] = 0;
514 regp->CRTC[NV_CIO_CRE_54] = 0;
516 /* 0x00 is disabled, 0x11 is lvds, 0x22 crt and 0x88 tmds */
518 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x11;
519 else if (tmds_output)
520 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x88;
522 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x22;
524 /* These values seem to vary */
525 /* This register seems to be used by the bios to make certain decisions on some G70 cards? */
526 regp->CRTC[NV_CIO_CRE_SCRATCH4__INDEX] = savep->CRTC[NV_CIO_CRE_SCRATCH4__INDEX];
528 nv_crtc_set_digital_vibrance(crtc, nv_crtc->saturation);
530 /* probably a scratch reg, but kept for cargo-cult purposes:
531 * bit0: crtc0?, head A
533 * bit7: (only in X), head A
535 if (nv_crtc->index == 0)
536 regp->CRTC[NV_CIO_CRE_4B] = savep->CRTC[NV_CIO_CRE_4B] | 0x80;
538 /* The blob seems to take the current value from crtc 0, add 4 to that
539 * and reuse the old value for crtc 1 */
540 regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] = nv04_display(dev)->saved_reg.crtc_reg[0].CRTC[NV_CIO_CRE_TVOUT_LATENCY];
542 regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] += 4;
544 /* the blob sometimes sets |= 0x10 (which is the same as setting |=
545 * 1 << 30 on 0x60.830), for no apparent reason */
546 regp->CRTC[NV_CIO_CRE_59] = off_chip_digital;
548 if (drm->device.info.family >= NV_DEVICE_INFO_V0_RANKINE)
549 regp->CRTC[0x9f] = off_chip_digital ? 0x11 : 0x1;
551 regp->crtc_830 = mode->crtc_vdisplay - 3;
552 regp->crtc_834 = mode->crtc_vdisplay - 1;
554 if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE)
555 /* This is what the blob does */
556 regp->crtc_850 = NVReadCRTC(dev, 0, NV_PCRTC_850);
558 if (drm->device.info.family >= NV_DEVICE_INFO_V0_RANKINE)
559 regp->gpio_ext = NVReadCRTC(dev, 0, NV_PCRTC_GPIO_EXT);
561 if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS)
562 regp->crtc_cfg = NV10_PCRTC_CONFIG_START_ADDRESS_HSYNC;
564 regp->crtc_cfg = NV04_PCRTC_CONFIG_START_ADDRESS_HSYNC;
567 if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE) {
568 regp->CRTC[NV_CIO_CRE_85] = 0xFF;
569 regp->CRTC[NV_CIO_CRE_86] = 0x1;
572 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] = (crtc->primary->fb->depth + 1) / 8;
573 /* Enable slaved mode (called MODE_TV in nv4ref.h) */
574 if (lvds_output || tmds_output || tv_output)
575 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (1 << 7);
577 /* Generic PRAMDAC regs */
579 if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS)
580 /* Only bit that bios and blob set. */
581 regp->nv10_cursync = (1 << 25);
583 regp->ramdac_gen_ctrl = NV_PRAMDAC_GENERAL_CONTROL_BPC_8BITS |
584 NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE_SEL |
585 NV_PRAMDAC_GENERAL_CONTROL_PIXMIX_ON;
586 if (crtc->primary->fb->depth == 16)
587 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL;
588 if (drm->device.info.chipset >= 0x11)
589 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_PIPE_LONG;
591 regp->ramdac_630 = 0; /* turn off green mode (tv test pattern?) */
594 nv_crtc_set_image_sharpening(crtc, nv_crtc->sharpness);
596 /* Some values the blob sets */
597 regp->ramdac_8c0 = 0x100;
598 regp->ramdac_a20 = 0x0;
599 regp->ramdac_a24 = 0xfffff;
600 regp->ramdac_a34 = 0x1;
604 nv_crtc_swap_fbs(struct drm_crtc *crtc, struct drm_framebuffer *old_fb)
606 struct nv04_display *disp = nv04_display(crtc->dev);
607 struct nouveau_framebuffer *nvfb = nouveau_framebuffer(crtc->primary->fb);
608 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
611 ret = nouveau_bo_pin(nvfb->nvbo, TTM_PL_FLAG_VRAM, false);
613 if (disp->image[nv_crtc->index])
614 nouveau_bo_unpin(disp->image[nv_crtc->index]);
615 nouveau_bo_ref(nvfb->nvbo, &disp->image[nv_crtc->index]);
622 * Sets up registers for the given mode/adjusted_mode pair.
624 * The clocks, CRTCs and outputs attached to this CRTC must be off.
626 * This shouldn't enable any clocks, CRTCs, or outputs, but they should
627 * be easily turned on/off after this.
630 nv_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode,
631 struct drm_display_mode *adjusted_mode,
632 int x, int y, struct drm_framebuffer *old_fb)
634 struct drm_device *dev = crtc->dev;
635 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
636 struct nouveau_drm *drm = nouveau_drm(dev);
639 NV_DEBUG(drm, "CTRC mode on CRTC %d:\n", nv_crtc->index);
640 drm_mode_debug_printmodeline(adjusted_mode);
642 ret = nv_crtc_swap_fbs(crtc, old_fb);
646 /* unlock must come after turning off FP_TG_CONTROL in output_prepare */
647 nv_lock_vga_crtc_shadow(dev, nv_crtc->index, -1);
649 nv_crtc_mode_set_vga(crtc, adjusted_mode);
650 /* calculated in nv04_dfp_prepare, nv40 needs it written before calculating PLLs */
651 if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE)
652 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, nv04_display(dev)->mode_reg.sel_clk);
653 nv_crtc_mode_set_regs(crtc, adjusted_mode);
654 nv_crtc_calc_state_ext(crtc, mode, adjusted_mode->clock);
658 static void nv_crtc_save(struct drm_crtc *crtc)
660 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
661 struct drm_device *dev = crtc->dev;
662 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg;
663 struct nv04_crtc_reg *crtc_state = &state->crtc_reg[nv_crtc->index];
664 struct nv04_mode_state *saved = &nv04_display(dev)->saved_reg;
665 struct nv04_crtc_reg *crtc_saved = &saved->crtc_reg[nv_crtc->index];
667 if (nv_two_heads(crtc->dev))
668 NVSetOwner(crtc->dev, nv_crtc->index);
670 nouveau_hw_save_state(crtc->dev, nv_crtc->index, saved);
672 /* init some state to saved value */
673 state->sel_clk = saved->sel_clk & ~(0x5 << 16);
674 crtc_state->CRTC[NV_CIO_CRE_LCD__INDEX] = crtc_saved->CRTC[NV_CIO_CRE_LCD__INDEX];
675 state->pllsel = saved->pllsel & ~(PLLSEL_VPLL1_MASK | PLLSEL_VPLL2_MASK | PLLSEL_TV_MASK);
676 crtc_state->gpio_ext = crtc_saved->gpio_ext;
679 static void nv_crtc_restore(struct drm_crtc *crtc)
681 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
682 struct drm_device *dev = crtc->dev;
683 int head = nv_crtc->index;
684 uint8_t saved_cr21 = nv04_display(dev)->saved_reg.crtc_reg[head].CRTC[NV_CIO_CRE_21];
686 if (nv_two_heads(crtc->dev))
687 NVSetOwner(crtc->dev, head);
689 nouveau_hw_load_state(crtc->dev, head, &nv04_display(dev)->saved_reg);
690 nv_lock_vga_crtc_shadow(crtc->dev, head, saved_cr21);
692 nv_crtc->last_dpms = NV_DPMS_CLEARED;
695 static void nv_crtc_prepare(struct drm_crtc *crtc)
697 struct drm_device *dev = crtc->dev;
698 struct nouveau_drm *drm = nouveau_drm(dev);
699 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
700 const struct drm_crtc_helper_funcs *funcs = crtc->helper_private;
702 if (nv_two_heads(dev))
703 NVSetOwner(dev, nv_crtc->index);
705 drm_vblank_pre_modeset(dev, nv_crtc->index);
706 funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
708 NVBlankScreen(dev, nv_crtc->index, true);
710 /* Some more preparation. */
711 NVWriteCRTC(dev, nv_crtc->index, NV_PCRTC_CONFIG, NV_PCRTC_CONFIG_START_ADDRESS_NON_VGA);
712 if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE) {
713 uint32_t reg900 = NVReadRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900);
714 NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900, reg900 & ~0x10000);
718 static void nv_crtc_commit(struct drm_crtc *crtc)
720 struct drm_device *dev = crtc->dev;
721 const struct drm_crtc_helper_funcs *funcs = crtc->helper_private;
722 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
724 nouveau_hw_load_state(dev, nv_crtc->index, &nv04_display(dev)->mode_reg);
725 nv04_crtc_mode_set_base(crtc, crtc->x, crtc->y, NULL);
728 /* turn on LFB swapping */
730 uint8_t tmp = NVReadVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RCR);
731 tmp |= MASK(NV_CIO_CRE_RCR_ENDIAN_BIG);
732 NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RCR, tmp);
736 funcs->dpms(crtc, DRM_MODE_DPMS_ON);
737 drm_vblank_post_modeset(dev, nv_crtc->index);
740 static void nv_crtc_destroy(struct drm_crtc *crtc)
742 struct nv04_display *disp = nv04_display(crtc->dev);
743 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
748 drm_crtc_cleanup(crtc);
750 if (disp->image[nv_crtc->index])
751 nouveau_bo_unpin(disp->image[nv_crtc->index]);
752 nouveau_bo_ref(NULL, &disp->image[nv_crtc->index]);
754 nouveau_bo_unmap(nv_crtc->cursor.nvbo);
755 nouveau_bo_unpin(nv_crtc->cursor.nvbo);
756 nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
761 nv_crtc_gamma_load(struct drm_crtc *crtc)
763 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
764 struct drm_device *dev = nv_crtc->base.dev;
765 struct rgb { uint8_t r, g, b; } __attribute__((packed)) *rgbs;
768 rgbs = (struct rgb *)nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].DAC;
769 for (i = 0; i < 256; i++) {
770 rgbs[i].r = nv_crtc->lut.r[i] >> 8;
771 rgbs[i].g = nv_crtc->lut.g[i] >> 8;
772 rgbs[i].b = nv_crtc->lut.b[i] >> 8;
775 nouveau_hw_load_state_palette(dev, nv_crtc->index, &nv04_display(dev)->mode_reg);
779 nv_crtc_disable(struct drm_crtc *crtc)
781 struct nv04_display *disp = nv04_display(crtc->dev);
782 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
783 if (disp->image[nv_crtc->index])
784 nouveau_bo_unpin(disp->image[nv_crtc->index]);
785 nouveau_bo_ref(NULL, &disp->image[nv_crtc->index]);
789 nv_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, uint32_t start,
792 int end = (start + size > 256) ? 256 : start + size, i;
793 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
795 for (i = start; i < end; i++) {
796 nv_crtc->lut.r[i] = r[i];
797 nv_crtc->lut.g[i] = g[i];
798 nv_crtc->lut.b[i] = b[i];
801 /* We need to know the depth before we upload, but it's possible to
802 * get called before a framebuffer is bound. If this is the case,
803 * mark the lut values as dirty by setting depth==0, and it'll be
804 * uploaded on the first mode_set_base()
806 if (!nv_crtc->base.primary->fb) {
807 nv_crtc->lut.depth = 0;
811 nv_crtc_gamma_load(crtc);
815 nv04_crtc_do_mode_set_base(struct drm_crtc *crtc,
816 struct drm_framebuffer *passed_fb,
817 int x, int y, bool atomic)
819 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
820 struct drm_device *dev = crtc->dev;
821 struct nouveau_drm *drm = nouveau_drm(dev);
822 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
823 struct drm_framebuffer *drm_fb;
824 struct nouveau_framebuffer *fb;
825 int arb_burst, arb_lwm;
827 NV_DEBUG(drm, "index %d\n", nv_crtc->index);
830 if (!atomic && !crtc->primary->fb) {
831 NV_DEBUG(drm, "No FB bound\n");
835 /* If atomic, we want to switch to the fb we were passed, so
836 * now we update pointers to do that.
840 fb = nouveau_framebuffer(passed_fb);
842 drm_fb = crtc->primary->fb;
843 fb = nouveau_framebuffer(crtc->primary->fb);
846 nv_crtc->fb.offset = fb->nvbo->bo.offset;
848 if (nv_crtc->lut.depth != drm_fb->depth) {
849 nv_crtc->lut.depth = drm_fb->depth;
850 nv_crtc_gamma_load(crtc);
853 /* Update the framebuffer format. */
854 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] &= ~3;
855 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (crtc->primary->fb->depth + 1) / 8;
856 regp->ramdac_gen_ctrl &= ~NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL;
857 if (crtc->primary->fb->depth == 16)
858 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL;
859 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_PIXEL_INDEX);
860 NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_GENERAL_CONTROL,
861 regp->ramdac_gen_ctrl);
863 regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = drm_fb->pitches[0] >> 3;
864 regp->CRTC[NV_CIO_CRE_RPC0_INDEX] =
865 XLATE(drm_fb->pitches[0] >> 3, 8, NV_CIO_CRE_RPC0_OFFSET_10_8);
866 regp->CRTC[NV_CIO_CRE_42] =
867 XLATE(drm_fb->pitches[0] / 8, 11, NV_CIO_CRE_42_OFFSET_11);
868 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_RPC0_INDEX);
869 crtc_wr_cio_state(crtc, regp, NV_CIO_CR_OFFSET_INDEX);
870 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_42);
872 /* Update the framebuffer location. */
873 regp->fb_start = nv_crtc->fb.offset & ~3;
874 regp->fb_start += (y * drm_fb->pitches[0]) + (x * drm_fb->bits_per_pixel / 8);
875 nv_set_crtc_base(dev, nv_crtc->index, regp->fb_start);
877 /* Update the arbitration parameters. */
878 nouveau_calc_arb(dev, crtc->mode.clock, drm_fb->bits_per_pixel,
879 &arb_burst, &arb_lwm);
881 regp->CRTC[NV_CIO_CRE_FF_INDEX] = arb_burst;
882 regp->CRTC[NV_CIO_CRE_FFLWM__INDEX] = arb_lwm & 0xff;
883 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FF_INDEX);
884 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FFLWM__INDEX);
886 if (drm->device.info.family >= NV_DEVICE_INFO_V0_KELVIN) {
887 regp->CRTC[NV_CIO_CRE_47] = arb_lwm >> 8;
888 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_47);
895 nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
896 struct drm_framebuffer *old_fb)
898 int ret = nv_crtc_swap_fbs(crtc, old_fb);
901 return nv04_crtc_do_mode_set_base(crtc, old_fb, x, y, false);
905 nv04_crtc_mode_set_base_atomic(struct drm_crtc *crtc,
906 struct drm_framebuffer *fb,
907 int x, int y, enum mode_set_atomic state)
909 struct nouveau_drm *drm = nouveau_drm(crtc->dev);
910 struct drm_device *dev = drm->dev;
912 if (state == ENTER_ATOMIC_MODE_SET)
913 nouveau_fbcon_accel_save_disable(dev);
915 nouveau_fbcon_accel_restore(dev);
917 return nv04_crtc_do_mode_set_base(crtc, fb, x, y, true);
920 static void nv04_cursor_upload(struct drm_device *dev, struct nouveau_bo *src,
921 struct nouveau_bo *dst)
923 int width = nv_cursor_width(dev);
927 for (i = 0; i < width; i++) {
928 for (j = 0; j < width; j++) {
929 pixel = nouveau_bo_rd32(src, i*64 + j);
931 nouveau_bo_wr16(dst, i*width + j, (pixel & 0x80000000) >> 16
932 | (pixel & 0xf80000) >> 9
933 | (pixel & 0xf800) >> 6
934 | (pixel & 0xf8) >> 3);
939 static void nv11_cursor_upload(struct drm_device *dev, struct nouveau_bo *src,
940 struct nouveau_bo *dst)
945 /* nv11+ supports premultiplied (PM), or non-premultiplied (NPM) alpha
946 * cursors (though NPM in combination with fp dithering may not work on
947 * nv11, from "nv" driver history)
948 * NPM mode needs NV_PCRTC_CURSOR_CONFIG_ALPHA_BLEND set and is what the
949 * blob uses, however we get given PM cursors so we use PM mode
951 for (i = 0; i < 64 * 64; i++) {
952 pixel = nouveau_bo_rd32(src, i);
954 /* hw gets unhappy if alpha <= rgb values. for a PM image "less
955 * than" shouldn't happen; fix "equal to" case by adding one to
956 * alpha channel (slightly inaccurate, but so is attempting to
957 * get back to NPM images, due to limits of integer precision)
960 if (alpha > 0 && alpha < 255)
961 pixel = (pixel & 0x00ffffff) | ((alpha + 1) << 24);
965 struct nouveau_drm *drm = nouveau_drm(dev);
967 if (drm->device.info.chipset == 0x11) {
968 pixel = ((pixel & 0x000000ff) << 24) |
969 ((pixel & 0x0000ff00) << 8) |
970 ((pixel & 0x00ff0000) >> 8) |
971 ((pixel & 0xff000000) >> 24);
976 nouveau_bo_wr32(dst, i, pixel);
981 nv04_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
982 uint32_t buffer_handle, uint32_t width, uint32_t height)
984 struct nouveau_drm *drm = nouveau_drm(crtc->dev);
985 struct drm_device *dev = drm->dev;
986 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
987 struct nouveau_bo *cursor = NULL;
988 struct drm_gem_object *gem;
991 if (!buffer_handle) {
992 nv_crtc->cursor.hide(nv_crtc, true);
996 if (width != 64 || height != 64)
999 gem = drm_gem_object_lookup(dev, file_priv, buffer_handle);
1002 cursor = nouveau_gem_object(gem);
1004 ret = nouveau_bo_map(cursor);
1008 if (drm->device.info.chipset >= 0x11)
1009 nv11_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo);
1011 nv04_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo);
1013 nouveau_bo_unmap(cursor);
1014 nv_crtc->cursor.offset = nv_crtc->cursor.nvbo->bo.offset;
1015 nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset);
1016 nv_crtc->cursor.show(nv_crtc, true);
1018 drm_gem_object_unreference_unlocked(gem);
1023 nv04_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
1025 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1027 nv_crtc->cursor.set_pos(nv_crtc, x, y);
1032 nouveau_crtc_set_config(struct drm_mode_set *set)
1034 struct drm_device *dev;
1035 struct nouveau_drm *drm;
1037 struct drm_crtc *crtc;
1038 bool active = false;
1039 if (!set || !set->crtc)
1042 dev = set->crtc->dev;
1044 /* get a pm reference here */
1045 ret = pm_runtime_get_sync(dev->dev);
1046 if (ret < 0 && ret != -EACCES)
1049 ret = drm_crtc_helper_set_config(set);
1051 drm = nouveau_drm(dev);
1053 /* if we get here with no crtcs active then we can drop a reference */
1054 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1059 pm_runtime_mark_last_busy(dev->dev);
1060 /* if we have active crtcs and we don't have a power ref,
1061 take the current one */
1062 if (active && !drm->have_disp_power_ref) {
1063 drm->have_disp_power_ref = true;
1066 /* if we have no active crtcs, then drop the power ref
1068 if (!active && drm->have_disp_power_ref) {
1069 pm_runtime_put_autosuspend(dev->dev);
1070 drm->have_disp_power_ref = false;
1072 /* drop the power reference we got coming in here */
1073 pm_runtime_put_autosuspend(dev->dev);
1077 static const struct drm_crtc_funcs nv04_crtc_funcs = {
1078 .cursor_set = nv04_crtc_cursor_set,
1079 .cursor_move = nv04_crtc_cursor_move,
1080 .gamma_set = nv_crtc_gamma_set,
1081 .set_config = nouveau_crtc_set_config,
1082 .page_flip = nouveau_crtc_page_flip,
1083 .destroy = nv_crtc_destroy,
1086 static const struct drm_crtc_helper_funcs nv04_crtc_helper_funcs = {
1087 .dpms = nv_crtc_dpms,
1088 .prepare = nv_crtc_prepare,
1089 .commit = nv_crtc_commit,
1090 .mode_set = nv_crtc_mode_set,
1091 .mode_set_base = nv04_crtc_mode_set_base,
1092 .mode_set_base_atomic = nv04_crtc_mode_set_base_atomic,
1093 .load_lut = nv_crtc_gamma_load,
1094 .disable = nv_crtc_disable,
1098 nv04_crtc_create(struct drm_device *dev, int crtc_num)
1100 struct nouveau_crtc *nv_crtc;
1103 nv_crtc = kzalloc(sizeof(*nv_crtc), GFP_KERNEL);
1107 for (i = 0; i < 256; i++) {
1108 nv_crtc->lut.r[i] = i << 8;
1109 nv_crtc->lut.g[i] = i << 8;
1110 nv_crtc->lut.b[i] = i << 8;
1112 nv_crtc->lut.depth = 0;
1114 nv_crtc->index = crtc_num;
1115 nv_crtc->last_dpms = NV_DPMS_CLEARED;
1117 nv_crtc->save = nv_crtc_save;
1118 nv_crtc->restore = nv_crtc_restore;
1120 drm_crtc_init(dev, &nv_crtc->base, &nv04_crtc_funcs);
1121 drm_crtc_helper_add(&nv_crtc->base, &nv04_crtc_helper_funcs);
1122 drm_mode_crtc_set_gamma_size(&nv_crtc->base, 256);
1124 ret = nouveau_bo_new(dev, 64*64*4, 0x100, TTM_PL_FLAG_VRAM,
1125 0, 0x0000, NULL, NULL, &nv_crtc->cursor.nvbo);
1127 ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM, false);
1129 ret = nouveau_bo_map(nv_crtc->cursor.nvbo);
1131 nouveau_bo_unpin(nv_crtc->cursor.nvbo);
1134 nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
1137 nv04_cursor_init(nv_crtc);