drivers/gpu/drm/nouveau/core/subdev/device/nv50.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <subdev/device.h>
  26 #include <subdev/bios.h>
  27 #include <subdev/gpio.h>
  28 #include <subdev/i2c.h>
  29 #include <subdev/clock.h>
  30 #include <subdev/devinit.h>
  31 #include <subdev/mc.h>
  32 #include <subdev/timer.h>
  33
  34 int
  35 nv50_identify(struct nouveau_device *device)
  36 {
  37         switch (device->chipset) {
  38         case 0x50:
  39                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
  40                 device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
  41                 device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
  42                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv50_clock_oclass;
  43                 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
  44                 device->oclass[NVDEV_SUBDEV_MC     ] = &nv50_mc_oclass;
  45                 device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
  46                 break;
  47         case 0x84:
  48                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
  49                 device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
  50                 device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
  51                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv50_clock_oclass;
  52                 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
  53                 device->oclass[NVDEV_SUBDEV_MC     ] = &nv50_mc_oclass;
  54                 device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
  55                 break;
  56         case 0x86:
  57                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
  58                 device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
  59                 device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
  60                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv50_clock_oclass;
  61                 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
  62                 device->oclass[NVDEV_SUBDEV_MC     ] = &nv50_mc_oclass;
  63                 device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
  64                 break;
  65         case 0x92:
  66                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
  67                 device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
  68                 device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
  69                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv50_clock_oclass;
  70                 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
  71                 device->oclass[NVDEV_SUBDEV_MC     ] = &nv50_mc_oclass;
  72                 device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
  73                 break;
  74         case 0x94:
  75                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
  76                 device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
  77                 device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
  78                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv50_clock_oclass;
  79                 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
  80                 device->oclass[NVDEV_SUBDEV_MC     ] = &nv50_mc_oclass;
  81                 device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
  82                 break;
  83         case 0x96:
  84                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
  85                 device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
  86                 device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
  87                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv50_clock_oclass;
  88                 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
  89                 device->oclass[NVDEV_SUBDEV_MC     ] = &nv50_mc_oclass;
  90                 device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
  91                 break;
  92         case 0x98:
  93                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
  94                 device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
  95                 device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
  96                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv50_clock_oclass;
  97                 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
  98                 device->oclass[NVDEV_SUBDEV_MC     ] = &nv98_mc_oclass;
  99                 device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 100                 break;
 101         case 0xa0:
 102                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
 103                 device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
 104                 device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
 105                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv50_clock_oclass;
 106                 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
 107                 device->oclass[NVDEV_SUBDEV_MC     ] = &nv98_mc_oclass;
 108                 device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 109                 break;
 110         case 0xaa:
 111                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
 112                 device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
 113                 device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
 114                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv50_clock_oclass;
 115                 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
 116                 device->oclass[NVDEV_SUBDEV_MC     ] = &nv98_mc_oclass;
 117                 device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 118                 break;
 119         case 0xac:
 120                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
 121                 device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
 122                 device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
 123                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv50_clock_oclass;
 124                 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
 125                 device->oclass[NVDEV_SUBDEV_MC     ] = &nv98_mc_oclass;
 126                 device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 127                 break;
 128         case 0xa3:
 129                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
 130                 device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
 131                 device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
 132                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nva3_clock_oclass;
 133                 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
 134                 device->oclass[NVDEV_SUBDEV_MC     ] = &nv98_mc_oclass;
 135                 device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 136                 break;
 137         case 0xa5:
 138                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
 139                 device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
 140                 device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
 141                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nva3_clock_oclass;
 142                 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
 143                 device->oclass[NVDEV_SUBDEV_MC     ] = &nv98_mc_oclass;
 144                 device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 145                 break;
 146         case 0xa8:
 147                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
 148                 device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
 149                 device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
 150                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nva3_clock_oclass;
 151                 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
 152                 device->oclass[NVDEV_SUBDEV_MC     ] = &nv98_mc_oclass;
 153                 device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 154                 break;
 155         case 0xaf:
 156                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
 157                 device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
 158                 device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
 159                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nva3_clock_oclass;
 160                 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
 161                 device->oclass[NVDEV_SUBDEV_MC     ] = &nv98_mc_oclass;
 162                 device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 163                 break;
 164         default:
 165                 nv_fatal(device, "unknown Tesla chipset\n");
 166                 return -EINVAL;
 167         }
 168
 169         return 0;
 170 }