2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <core/gpuobj.h>
27 #include <subdev/timer.h>
28 #include <subdev/fb.h>
29 #include <subdev/vm.h>
33 struct nvc0_bar_priv_vm {
34 struct nouveau_gpuobj *mem;
35 struct nouveau_gpuobj *pgd;
36 struct nouveau_vm *vm;
39 struct nvc0_bar_priv {
40 struct nouveau_bar base;
42 struct nvc0_bar_priv_vm bar[2];
46 nvc0_bar_kmap(struct nouveau_bar *bar, struct nouveau_mem *mem,
47 u32 flags, struct nouveau_vma *vma)
49 struct nvc0_bar_priv *priv = (void *)bar;
52 ret = nouveau_vm_get(priv->bar[0].vm, mem->size << 12, 12, flags, vma);
56 nouveau_vm_map(vma, mem);
61 nvc0_bar_umap(struct nouveau_bar *bar, struct nouveau_mem *mem,
62 u32 flags, struct nouveau_vma *vma)
64 struct nvc0_bar_priv *priv = (void *)bar;
67 ret = nouveau_vm_get(priv->bar[1].vm, mem->size << 12,
68 mem->page_shift, flags, vma);
72 nouveau_vm_map(vma, mem);
77 nvc0_bar_unmap(struct nouveau_bar *bar, struct nouveau_vma *vma)
79 nouveau_vm_unmap(vma);
84 nvc0_bar_init_vm(struct nvc0_bar_priv *priv, struct nvc0_bar_priv_vm *bar_vm,
87 struct nouveau_device *device = nv_device(&priv->base);
88 struct nouveau_vm *vm;
89 resource_size_t bar_len;
92 ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 0, 0,
97 ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x8000, 0, 0,
102 bar_len = nv_device_resource_len(device, bar_nr);
104 ret = nouveau_vm_new(device, 0, bar_len, 0, &vm);
108 atomic_inc(&vm->engref[NVDEV_SUBDEV_BAR]);
111 * Bootstrap page table lookup.
114 ret = nouveau_gpuobj_new(nv_object(priv), NULL,
115 (bar_len >> 12) * 8, 0x1000,
116 NVOBJ_FLAG_ZERO_ALLOC,
118 vm->pgt[0].refcount[0] = 1;
123 ret = nouveau_vm_ref(vm, &bar_vm->vm, bar_vm->pgd);
124 nouveau_vm_ref(NULL, &vm, NULL);
128 nv_wo32(bar_vm->mem, 0x0200, lower_32_bits(bar_vm->pgd->addr));
129 nv_wo32(bar_vm->mem, 0x0204, upper_32_bits(bar_vm->pgd->addr));
130 nv_wo32(bar_vm->mem, 0x0208, lower_32_bits(bar_len - 1));
131 nv_wo32(bar_vm->mem, 0x020c, upper_32_bits(bar_len - 1));
137 nvc0_bar_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
138 struct nouveau_oclass *oclass, void *data, u32 size,
139 struct nouveau_object **pobject)
141 struct nouveau_device *device = nv_device(parent);
142 struct nvc0_bar_priv *priv;
143 bool has_bar3 = nv_device_resource_len(device, 3) != 0;
146 ret = nouveau_bar_create(parent, engine, oclass, &priv);
147 *pobject = nv_object(priv);
153 ret = nvc0_bar_init_vm(priv, &priv->bar[0], 3);
156 priv->base.alloc = nouveau_bar_alloc;
157 priv->base.kmap = nvc0_bar_kmap;
161 ret = nvc0_bar_init_vm(priv, &priv->bar[1], 1);
165 priv->base.umap = nvc0_bar_umap;
166 priv->base.unmap = nvc0_bar_unmap;
167 priv->base.flush = nv84_bar_flush;
168 spin_lock_init(&priv->lock);
173 nvc0_bar_dtor(struct nouveau_object *object)
175 struct nvc0_bar_priv *priv = (void *)object;
177 nouveau_vm_ref(NULL, &priv->bar[1].vm, priv->bar[1].pgd);
178 nouveau_gpuobj_ref(NULL, &priv->bar[1].pgd);
179 nouveau_gpuobj_ref(NULL, &priv->bar[1].mem);
181 if (priv->bar[0].vm) {
182 nouveau_gpuobj_ref(NULL, &priv->bar[0].vm->pgt[0].obj[0]);
183 nouveau_vm_ref(NULL, &priv->bar[0].vm, priv->bar[0].pgd);
185 nouveau_gpuobj_ref(NULL, &priv->bar[0].pgd);
186 nouveau_gpuobj_ref(NULL, &priv->bar[0].mem);
188 nouveau_bar_destroy(&priv->base);
192 nvc0_bar_init(struct nouveau_object *object)
194 struct nvc0_bar_priv *priv = (void *)object;
197 ret = nouveau_bar_init(&priv->base);
201 nv_mask(priv, 0x000200, 0x00000100, 0x00000000);
202 nv_mask(priv, 0x000200, 0x00000100, 0x00000100);
203 nv_mask(priv, 0x100c80, 0x00000001, 0x00000000);
205 nv_wr32(priv, 0x001704, 0x80000000 | priv->bar[1].mem->addr >> 12);
206 if (priv->bar[0].mem)
207 nv_wr32(priv, 0x001714,
208 0xc0000000 | priv->bar[0].mem->addr >> 12);
212 struct nouveau_oclass
214 .handle = NV_SUBDEV(BAR, 0xc0),
215 .ofuncs = &(struct nouveau_ofuncs) {
216 .ctor = nvc0_bar_ctor,
217 .dtor = nvc0_bar_dtor,
218 .init = nvc0_bar_init,
219 .fini = _nouveau_bar_fini,