2 * Copyright 2013 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <subdev/bios.h>
26 #include <subdev/bios/dcb.h>
27 #include <subdev/bios/dp.h>
28 #include <subdev/bios/init.h>
29 #include <subdev/i2c.h>
31 #include <engine/disp.h>
33 #include <core/class.h>
38 /******************************************************************************
40 *****************************************************************************/
42 struct nvkm_output_dp *outp;
53 dp_set_link_config(struct dp_state *dp)
55 struct nvkm_output_dp_impl *impl = (void *)nv_oclass(dp->outp);
56 struct nvkm_output_dp *outp = dp->outp;
57 struct nouveau_disp *disp = nouveau_disp(outp);
58 struct nouveau_bios *bios = nouveau_bios(disp);
59 struct nvbios_init init = {
60 .subdev = nv_subdev(disp),
63 .outp = &outp->base.info,
71 DBG("%d lanes at %d KB/s\n", dp->link_nr, dp->link_bw);
73 /* set desired link configuration on the source */
74 if ((lnkcmp = dp->outp->info.lnkcmp)) {
75 if (outp->version < 0x30) {
76 while ((dp->link_bw / 10) < nv_ro16(bios, lnkcmp))
78 init.offset = nv_ro16(bios, lnkcmp + 2);
80 while ((dp->link_bw / 27000) < nv_ro08(bios, lnkcmp))
82 init.offset = nv_ro16(bios, lnkcmp + 1);
88 ret = impl->lnk_ctl(outp, dp->link_nr, dp->link_bw / 27000,
89 outp->dpcd[DPCD_RC02] &
90 DPCD_RC02_ENHANCED_FRAME_CAP);
93 ERR("lnk_ctl failed with %d\n", ret);
97 impl->lnk_pwr(outp, dp->link_nr);
99 /* set desired link configuration on the sink */
100 sink[0] = dp->link_bw / 27000;
101 sink[1] = dp->link_nr;
102 if (outp->dpcd[DPCD_RC02] & DPCD_RC02_ENHANCED_FRAME_CAP)
103 sink[1] |= DPCD_LC01_ENHANCED_FRAME_EN;
105 return nv_wraux(outp->base.edid, DPCD_LC00_LINK_BW_SET, sink, 2);
109 dp_set_training_pattern(struct dp_state *dp, u8 pattern)
111 struct nvkm_output_dp_impl *impl = (void *)nv_oclass(dp->outp);
112 struct nvkm_output_dp *outp = dp->outp;
115 DBG("training pattern %d\n", pattern);
116 impl->pattern(outp, pattern);
118 nv_rdaux(outp->base.edid, DPCD_LC02, &sink_tp, 1);
119 sink_tp &= ~DPCD_LC02_TRAINING_PATTERN_SET;
121 nv_wraux(outp->base.edid, DPCD_LC02, &sink_tp, 1);
125 dp_link_train_commit(struct dp_state *dp, bool pc)
127 struct nvkm_output_dp_impl *impl = (void *)nv_oclass(dp->outp);
128 struct nvkm_output_dp *outp = dp->outp;
131 for (i = 0; i < dp->link_nr; i++) {
132 u8 lane = (dp->stat[4 + (i >> 1)] >> ((i & 1) * 4)) & 0xf;
133 u8 lpc2 = (dp->pc2stat >> (i * 2)) & 0x3;
134 u8 lpre = (lane & 0x0c) >> 2;
135 u8 lvsw = (lane & 0x03) >> 0;
141 lpc2 = hipc | DPCD_LC0F_LANE0_MAX_POST_CURSOR2_REACHED;
143 lpre = hipe | DPCD_LC03_MAX_SWING_REACHED; /* yes. */
144 lvsw = hivs = 3 - (lpre & 3);
147 lvsw = hivs | DPCD_LC03_MAX_SWING_REACHED;
150 dp->conf[i] = (lpre << 3) | lvsw;
151 dp->pc2conf[i >> 1] |= lpc2 << ((i & 1) * 4);
153 DBG("config lane %d %02x %02x\n", i, dp->conf[i], lpc2);
154 impl->drv_ctl(outp, i, lvsw & 3, lpre & 3, lpc2 & 3);
157 ret = nv_wraux(outp->base.edid, DPCD_LC03(0), dp->conf, 4);
162 ret = nv_wraux(outp->base.edid, DPCD_LC0F, dp->pc2conf, 2);
171 dp_link_train_update(struct dp_state *dp, bool pc, u32 delay)
173 struct nvkm_output_dp *outp = dp->outp;
176 if (outp->dpcd[DPCD_RC0E_AUX_RD_INTERVAL])
177 mdelay(outp->dpcd[DPCD_RC0E_AUX_RD_INTERVAL] * 4);
181 ret = nv_rdaux(outp->base.edid, DPCD_LS02, dp->stat, 6);
186 ret = nv_rdaux(outp->base.edid, DPCD_LS0C, &dp->pc2stat, 1);
189 DBG("status %6ph pc2 %02x\n", dp->stat, dp->pc2stat);
191 DBG("status %6ph\n", dp->stat);
198 dp_link_train_cr(struct dp_state *dp)
200 bool cr_done = false, abort = false;
201 int voltage = dp->conf[0] & DPCD_LC03_VOLTAGE_SWING_SET;
204 dp_set_training_pattern(dp, 1);
207 if (dp_link_train_commit(dp, false) ||
208 dp_link_train_update(dp, false, 100))
212 for (i = 0; i < dp->link_nr; i++) {
213 u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf;
214 if (!(lane & DPCD_LS02_LANE0_CR_DONE)) {
216 if (dp->conf[i] & DPCD_LC03_MAX_SWING_REACHED)
222 if ((dp->conf[0] & DPCD_LC03_VOLTAGE_SWING_SET) != voltage) {
223 voltage = dp->conf[0] & DPCD_LC03_VOLTAGE_SWING_SET;
226 } while (!cr_done && !abort && ++tries < 5);
228 return cr_done ? 0 : -1;
232 dp_link_train_eq(struct dp_state *dp)
234 struct nvkm_output_dp *outp = dp->outp;
235 bool eq_done = false, cr_done = true;
238 if (outp->dpcd[2] & DPCD_RC02_TPS3_SUPPORTED)
239 dp_set_training_pattern(dp, 3);
241 dp_set_training_pattern(dp, 2);
245 dp_link_train_commit(dp, dp->pc2)) ||
246 dp_link_train_update(dp, dp->pc2, 400))
249 eq_done = !!(dp->stat[2] & DPCD_LS04_INTERLANE_ALIGN_DONE);
250 for (i = 0; i < dp->link_nr && eq_done; i++) {
251 u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf;
252 if (!(lane & DPCD_LS02_LANE0_CR_DONE))
254 if (!(lane & DPCD_LS02_LANE0_CHANNEL_EQ_DONE) ||
255 !(lane & DPCD_LS02_LANE0_SYMBOL_LOCKED))
258 } while (!eq_done && cr_done && ++tries <= 5);
260 return eq_done ? 0 : -1;
264 dp_link_train_init(struct dp_state *dp, bool spread)
266 struct nvkm_output_dp *outp = dp->outp;
267 struct nouveau_disp *disp = nouveau_disp(outp);
268 struct nouveau_bios *bios = nouveau_bios(disp);
269 struct nvbios_init init = {
270 .subdev = nv_subdev(disp),
272 .outp = &outp->base.info,
277 /* set desired spread */
279 init.offset = outp->info.script[2];
281 init.offset = outp->info.script[3];
284 /* pre-train script */
285 init.offset = outp->info.script[0];
290 dp_link_train_fini(struct dp_state *dp)
292 struct nvkm_output_dp *outp = dp->outp;
293 struct nouveau_disp *disp = nouveau_disp(outp);
294 struct nouveau_bios *bios = nouveau_bios(disp);
295 struct nvbios_init init = {
296 .subdev = nv_subdev(disp),
298 .outp = &outp->base.info,
303 /* post-train script */
304 init.offset = outp->info.script[1],
308 static const struct dp_rates {
312 } nouveau_dp_rates[] = {
313 { 2160000, 0x14, 4 },
314 { 1080000, 0x0a, 4 },
315 { 1080000, 0x14, 2 },
326 nouveau_dp_train(struct work_struct *w)
328 struct nvkm_output_dp *outp = container_of(w, typeof(*outp), lt.work);
329 struct nouveau_disp *disp = nouveau_disp(outp);
330 const struct dp_rates *cfg = nouveau_dp_rates;
331 struct dp_state _dp = {
337 /* bring capabilities within encoder limits */
338 if (nv_mclass(disp) < NVD0_DISP_CLASS)
339 outp->dpcd[2] &= ~DPCD_RC02_TPS3_SUPPORTED;
340 if ((outp->dpcd[2] & 0x1f) > outp->base.info.dpconf.link_nr) {
341 outp->dpcd[2] &= ~DPCD_RC02_MAX_LANE_COUNT;
342 outp->dpcd[2] |= outp->base.info.dpconf.link_nr;
344 if (outp->dpcd[1] > outp->base.info.dpconf.link_bw)
345 outp->dpcd[1] = outp->base.info.dpconf.link_bw;
346 dp->pc2 = outp->dpcd[2] & DPCD_RC02_TPS3_SUPPORTED;
348 /* restrict link config to the lowest required rate, if requested */
350 datarate = (datarate / 8) * 10; /* 8B/10B coding overhead */
351 while (cfg[1].rate >= datarate)
356 /* disable link interrupt handling during link training */
357 nvkm_notify_put(&outp->irq);
359 /* enable down-spreading and execute pre-train script from vbios */
360 dp_link_train_init(dp, outp->dpcd[3] & 0x01);
362 while (ret = -EIO, (++cfg)->rate) {
363 /* select next configuration supported by encoder and sink */
364 while (cfg->nr > (outp->dpcd[2] & DPCD_RC02_MAX_LANE_COUNT) ||
365 cfg->bw > (outp->dpcd[DPCD_RC01_MAX_LINK_RATE]))
367 dp->link_bw = cfg->bw * 27000;
368 dp->link_nr = cfg->nr;
370 /* program selected link configuration */
371 ret = dp_set_link_config(dp);
373 /* attempt to train the link at this configuration */
374 memset(dp->stat, 0x00, sizeof(dp->stat));
375 if (!dp_link_train_cr(dp) &&
376 !dp_link_train_eq(dp))
380 /* dp_set_link_config() handled training, or
381 * we failed to communicate with the sink.
387 /* finish link training and execute post-train script from vbios */
388 dp_set_training_pattern(dp, 0);
390 ERR("link training failed\n");
392 dp_link_train_fini(dp);
394 /* signal completion and enable link interrupt handling */
395 DBG("training complete\n");
396 atomic_set(&outp->lt.done, 1);
397 wake_up(&outp->lt.wait);
398 nvkm_notify_get(&outp->irq);