1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2013 Red Hat
5 * Author: Rob Clark <robdclark@gmail.com>
8 #include <linux/kthread.h>
9 #include <uapi/linux/sched/types.h>
10 #include <drm/drm_of.h>
13 #include "msm_debugfs.h"
14 #include "msm_fence.h"
18 #include "adreno/adreno_gpu.h"
23 * - 1.0.0 - initial interface
24 * - 1.1.0 - adds madvise, and support for submits with > 4 cmd buffers
25 * - 1.2.0 - adds explicit fence support for submit ioctl
26 * - 1.3.0 - adds GMEM_BASE + NR_RINGS params, SUBMITQUEUE_NEW +
27 * SUBMITQUEUE_CLOSE ioctls, and MSM_INFO_IOVA flag for
29 * - 1.4.0 - softpin, MSM_RELOC_BO_DUMP, and GEM_INFO support to set/get
30 * GEM object's debug name
31 * - 1.5.0 - Add SUBMITQUERY_QUERY ioctl
33 #define MSM_VERSION_MAJOR 1
34 #define MSM_VERSION_MINOR 5
35 #define MSM_VERSION_PATCHLEVEL 0
37 static const struct drm_mode_config_funcs mode_config_funcs = {
38 .fb_create = msm_framebuffer_create,
39 .output_poll_changed = drm_fb_helper_output_poll_changed,
40 .atomic_check = drm_atomic_helper_check,
41 .atomic_commit = drm_atomic_helper_commit,
44 static const struct drm_mode_config_helper_funcs mode_config_helper_funcs = {
45 .atomic_commit_tail = msm_atomic_commit_tail,
48 #ifdef CONFIG_DRM_MSM_REGISTER_LOGGING
49 static bool reglog = false;
50 MODULE_PARM_DESC(reglog, "Enable register read/write logging");
51 module_param(reglog, bool, 0600);
56 #ifdef CONFIG_DRM_FBDEV_EMULATION
57 static bool fbdev = true;
58 MODULE_PARM_DESC(fbdev, "Enable fbdev compat layer");
59 module_param(fbdev, bool, 0600);
62 static char *vram = "16m";
63 MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU)");
64 module_param(vram, charp, 0);
66 bool dumpstate = false;
67 MODULE_PARM_DESC(dumpstate, "Dump KMS state on errors");
68 module_param(dumpstate, bool, 0600);
70 static bool modeset = true;
71 MODULE_PARM_DESC(modeset, "Use kernel modesetting [KMS] (1=on (default), 0=disable)");
72 module_param(modeset, bool, 0600);
78 int msm_clk_bulk_get(struct device *dev, struct clk_bulk_data **bulk)
80 struct property *prop;
82 struct clk_bulk_data *local;
83 int i = 0, ret, count;
85 count = of_property_count_strings(dev->of_node, "clock-names");
89 local = devm_kcalloc(dev, sizeof(struct clk_bulk_data *),
94 of_property_for_each_string(dev->of_node, "clock-names", prop, name) {
95 local[i].id = devm_kstrdup(dev, name, GFP_KERNEL);
97 devm_kfree(dev, local);
104 ret = devm_clk_bulk_get(dev, count, local);
107 for (i = 0; i < count; i++)
108 devm_kfree(dev, (void *) local[i].id);
109 devm_kfree(dev, local);
118 struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count,
124 snprintf(n, sizeof(n), "%s_clk", name);
126 for (i = 0; bulk && i < count; i++) {
127 if (!strcmp(bulk[i].id, name) || !strcmp(bulk[i].id, n))
135 struct clk *msm_clk_get(struct platform_device *pdev, const char *name)
140 clk = devm_clk_get(&pdev->dev, name);
141 if (!IS_ERR(clk) || PTR_ERR(clk) == -EPROBE_DEFER)
144 snprintf(name2, sizeof(name2), "%s_clk", name);
146 clk = devm_clk_get(&pdev->dev, name2);
148 dev_warn(&pdev->dev, "Using legacy clk name binding. Use "
149 "\"%s\" instead of \"%s\"\n", name, name2);
154 void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
157 struct resource *res;
162 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
164 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
167 DRM_DEV_ERROR(&pdev->dev, "failed to get memory resource: %s\n", name);
168 return ERR_PTR(-EINVAL);
171 size = resource_size(res);
173 ptr = devm_ioremap_nocache(&pdev->dev, res->start, size);
175 DRM_DEV_ERROR(&pdev->dev, "failed to ioremap: %s\n", name);
176 return ERR_PTR(-ENOMEM);
180 printk(KERN_DEBUG "IO:region %s %p %08lx\n", dbgname, ptr, size);
185 void msm_writel(u32 data, void __iomem *addr)
188 printk(KERN_DEBUG "IO:W %p %08x\n", addr, data);
192 u32 msm_readl(const void __iomem *addr)
194 u32 val = readl(addr);
196 pr_err("IO:R %p %08x\n", addr, val);
200 struct msm_vblank_work {
201 struct work_struct work;
204 struct msm_drm_private *priv;
207 static void vblank_ctrl_worker(struct work_struct *work)
209 struct msm_vblank_work *vbl_work = container_of(work,
210 struct msm_vblank_work, work);
211 struct msm_drm_private *priv = vbl_work->priv;
212 struct msm_kms *kms = priv->kms;
214 if (vbl_work->enable)
215 kms->funcs->enable_vblank(kms, priv->crtcs[vbl_work->crtc_id]);
217 kms->funcs->disable_vblank(kms, priv->crtcs[vbl_work->crtc_id]);
222 static int vblank_ctrl_queue_work(struct msm_drm_private *priv,
223 int crtc_id, bool enable)
225 struct msm_vblank_work *vbl_work;
227 vbl_work = kzalloc(sizeof(*vbl_work), GFP_ATOMIC);
231 INIT_WORK(&vbl_work->work, vblank_ctrl_worker);
233 vbl_work->crtc_id = crtc_id;
234 vbl_work->enable = enable;
235 vbl_work->priv = priv;
237 queue_work(priv->wq, &vbl_work->work);
242 static int msm_drm_uninit(struct device *dev)
244 struct platform_device *pdev = to_platform_device(dev);
245 struct drm_device *ddev = platform_get_drvdata(pdev);
246 struct msm_drm_private *priv = ddev->dev_private;
247 struct msm_kms *kms = priv->kms;
248 struct msm_mdss *mdss = priv->mdss;
252 * Shutdown the hw if we're far enough along where things might be on.
253 * If we run this too early, we'll end up panicking in any variety of
254 * places. Since we don't register the drm device until late in
255 * msm_drm_init, drm_dev->registered is used as an indicator that the
256 * shutdown will be successful.
258 if (ddev->registered) {
259 drm_dev_unregister(ddev);
260 drm_atomic_helper_shutdown(ddev);
263 /* We must cancel and cleanup any pending vblank enable/disable
264 * work before drm_irq_uninstall() to avoid work re-enabling an
265 * irq after uninstall has disabled it.
268 flush_workqueue(priv->wq);
270 /* clean up event worker threads */
271 for (i = 0; i < priv->num_crtcs; i++) {
272 if (priv->event_thread[i].thread) {
273 kthread_destroy_worker(&priv->event_thread[i].worker);
274 priv->event_thread[i].thread = NULL;
278 msm_gem_shrinker_cleanup(ddev);
280 drm_kms_helper_poll_fini(ddev);
282 msm_perf_debugfs_cleanup(priv);
283 msm_rd_debugfs_cleanup(priv);
285 #ifdef CONFIG_DRM_FBDEV_EMULATION
286 if (fbdev && priv->fbdev)
287 msm_fbdev_free(ddev);
290 drm_mode_config_cleanup(ddev);
292 pm_runtime_get_sync(dev);
293 drm_irq_uninstall(ddev);
294 pm_runtime_put_sync(dev);
296 if (kms && kms->funcs)
297 kms->funcs->destroy(kms);
299 if (priv->vram.paddr) {
300 unsigned long attrs = DMA_ATTR_NO_KERNEL_MAPPING;
301 drm_mm_takedown(&priv->vram.mm);
302 dma_free_attrs(dev, priv->vram.size, NULL,
303 priv->vram.paddr, attrs);
306 component_unbind_all(dev, ddev);
308 if (mdss && mdss->funcs)
309 mdss->funcs->destroy(ddev);
311 ddev->dev_private = NULL;
314 destroy_workqueue(priv->wq);
324 static int get_mdp_ver(struct platform_device *pdev)
326 struct device *dev = &pdev->dev;
328 return (int) (unsigned long) of_device_get_match_data(dev);
331 #include <linux/of_address.h>
333 bool msm_use_mmu(struct drm_device *dev)
335 struct msm_drm_private *priv = dev->dev_private;
337 /* a2xx comes with its own MMU */
338 return priv->is_a2xx || iommu_present(&platform_bus_type);
341 static int msm_init_vram(struct drm_device *dev)
343 struct msm_drm_private *priv = dev->dev_private;
344 struct device_node *node;
345 unsigned long size = 0;
348 /* In the device-tree world, we could have a 'memory-region'
349 * phandle, which gives us a link to our "vram". Allocating
350 * is all nicely abstracted behind the dma api, but we need
351 * to know the entire size to allocate it all in one go. There
353 * 1) device with no IOMMU, in which case we need exclusive
354 * access to a VRAM carveout big enough for all gpu
356 * 2) device with IOMMU, but where the bootloader puts up
357 * a splash screen. In this case, the VRAM carveout
358 * need only be large enough for fbdev fb. But we need
359 * exclusive access to the buffer to avoid the kernel
360 * using those pages for other purposes (which appears
361 * as corruption on screen before we have a chance to
362 * load and do initial modeset)
365 node = of_parse_phandle(dev->dev->of_node, "memory-region", 0);
368 ret = of_address_to_resource(node, 0, &r);
372 size = r.end - r.start;
373 DRM_INFO("using VRAM carveout: %lx@%pa\n", size, &r.start);
375 /* if we have no IOMMU, then we need to use carveout allocator.
376 * Grab the entire CMA chunk carved out in early startup in
379 } else if (!msm_use_mmu(dev)) {
380 DRM_INFO("using %s VRAM carveout\n", vram);
381 size = memparse(vram, NULL);
385 unsigned long attrs = 0;
388 priv->vram.size = size;
390 drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1);
391 spin_lock_init(&priv->vram.lock);
393 attrs |= DMA_ATTR_NO_KERNEL_MAPPING;
394 attrs |= DMA_ATTR_WRITE_COMBINE;
396 /* note that for no-kernel-mapping, the vaddr returned
397 * is bogus, but non-null if allocation succeeded:
399 p = dma_alloc_attrs(dev->dev, size,
400 &priv->vram.paddr, GFP_KERNEL, attrs);
402 DRM_DEV_ERROR(dev->dev, "failed to allocate VRAM\n");
403 priv->vram.paddr = 0;
407 DRM_DEV_INFO(dev->dev, "VRAM: %08x->%08x\n",
408 (uint32_t)priv->vram.paddr,
409 (uint32_t)(priv->vram.paddr + size));
415 static int msm_drm_init(struct device *dev, struct drm_driver *drv)
417 struct platform_device *pdev = to_platform_device(dev);
418 struct drm_device *ddev;
419 struct msm_drm_private *priv;
421 struct msm_mdss *mdss;
423 struct sched_param param;
425 ddev = drm_dev_alloc(drv, dev);
427 DRM_DEV_ERROR(dev, "failed to allocate drm_device\n");
428 return PTR_ERR(ddev);
431 platform_set_drvdata(pdev, ddev);
433 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
436 goto err_put_drm_dev;
439 ddev->dev_private = priv;
442 switch (get_mdp_ver(pdev)) {
444 ret = mdp5_mdss_init(ddev);
447 ret = dpu_mdss_init(ddev);
458 priv->wq = alloc_ordered_workqueue("msm", 0);
460 INIT_WORK(&priv->free_work, msm_gem_free_work);
461 init_llist_head(&priv->free_list);
463 INIT_LIST_HEAD(&priv->inactive_list);
465 drm_mode_config_init(ddev);
467 /* Bind all our sub-components: */
468 ret = component_bind_all(dev, ddev);
470 goto err_destroy_mdss;
472 ret = msm_init_vram(ddev);
476 msm_gem_shrinker_init(ddev);
478 switch (get_mdp_ver(pdev)) {
480 kms = mdp4_kms_init(ddev);
484 kms = mdp5_kms_init(ddev);
487 kms = dpu_kms_init(ddev);
491 /* valid only for the dummy headless case, where of_node=NULL */
492 WARN_ON(dev->of_node);
498 DRM_DEV_ERROR(dev, "failed to load kms\n");
504 /* Enable normalization of plane zpos */
505 ddev->mode_config.normalize_zpos = true;
508 ret = kms->funcs->hw_init(kms);
510 DRM_DEV_ERROR(dev, "kms hw init failed: %d\n", ret);
515 ddev->mode_config.funcs = &mode_config_funcs;
516 ddev->mode_config.helper_private = &mode_config_helper_funcs;
519 * this priority was found during empiric testing to have appropriate
520 * realtime scheduling to process display updates and interact with
521 * other real time and normal priority task
523 param.sched_priority = 16;
524 for (i = 0; i < priv->num_crtcs; i++) {
525 /* initialize event thread */
526 priv->event_thread[i].crtc_id = priv->crtcs[i]->base.id;
527 kthread_init_worker(&priv->event_thread[i].worker);
528 priv->event_thread[i].dev = ddev;
529 priv->event_thread[i].thread =
530 kthread_run(kthread_worker_fn,
531 &priv->event_thread[i].worker,
532 "crtc_event:%d", priv->event_thread[i].crtc_id);
533 if (IS_ERR(priv->event_thread[i].thread)) {
534 DRM_DEV_ERROR(dev, "failed to create crtc_event kthread\n");
535 priv->event_thread[i].thread = NULL;
539 ret = sched_setscheduler(priv->event_thread[i].thread,
542 dev_warn(dev, "event_thread set priority failed:%d\n",
546 ret = drm_vblank_init(ddev, priv->num_crtcs);
548 DRM_DEV_ERROR(dev, "failed to initialize vblank\n");
553 pm_runtime_get_sync(dev);
554 ret = drm_irq_install(ddev, kms->irq);
555 pm_runtime_put_sync(dev);
557 DRM_DEV_ERROR(dev, "failed to install IRQ handler\n");
562 ret = drm_dev_register(ddev, 0);
566 drm_mode_config_reset(ddev);
568 #ifdef CONFIG_DRM_FBDEV_EMULATION
570 priv->fbdev = msm_fbdev_init(ddev);
573 ret = msm_debugfs_late_init(ddev);
577 drm_kms_helper_poll_init(ddev);
585 if (mdss && mdss->funcs)
586 mdss->funcs->destroy(ddev);
598 static void load_gpu(struct drm_device *dev)
600 static DEFINE_MUTEX(init_lock);
601 struct msm_drm_private *priv = dev->dev_private;
603 mutex_lock(&init_lock);
606 priv->gpu = adreno_load_gpu(dev);
608 mutex_unlock(&init_lock);
611 static int context_init(struct drm_device *dev, struct drm_file *file)
613 struct msm_drm_private *priv = dev->dev_private;
614 struct msm_file_private *ctx;
616 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
620 msm_submitqueue_init(dev, ctx);
622 ctx->aspace = priv->gpu ? priv->gpu->aspace : NULL;
623 file->driver_priv = ctx;
628 static int msm_open(struct drm_device *dev, struct drm_file *file)
630 /* For now, load gpu on open.. to avoid the requirement of having
631 * firmware in the initrd.
635 return context_init(dev, file);
638 static void context_close(struct msm_file_private *ctx)
640 msm_submitqueue_close(ctx);
644 static void msm_postclose(struct drm_device *dev, struct drm_file *file)
646 struct msm_drm_private *priv = dev->dev_private;
647 struct msm_file_private *ctx = file->driver_priv;
649 mutex_lock(&dev->struct_mutex);
650 if (ctx == priv->lastctx)
651 priv->lastctx = NULL;
652 mutex_unlock(&dev->struct_mutex);
657 static irqreturn_t msm_irq(int irq, void *arg)
659 struct drm_device *dev = arg;
660 struct msm_drm_private *priv = dev->dev_private;
661 struct msm_kms *kms = priv->kms;
663 return kms->funcs->irq(kms);
666 static void msm_irq_preinstall(struct drm_device *dev)
668 struct msm_drm_private *priv = dev->dev_private;
669 struct msm_kms *kms = priv->kms;
671 kms->funcs->irq_preinstall(kms);
674 static int msm_irq_postinstall(struct drm_device *dev)
676 struct msm_drm_private *priv = dev->dev_private;
677 struct msm_kms *kms = priv->kms;
680 if (kms->funcs->irq_postinstall)
681 return kms->funcs->irq_postinstall(kms);
686 static void msm_irq_uninstall(struct drm_device *dev)
688 struct msm_drm_private *priv = dev->dev_private;
689 struct msm_kms *kms = priv->kms;
691 kms->funcs->irq_uninstall(kms);
694 static int msm_enable_vblank(struct drm_device *dev, unsigned int pipe)
696 struct msm_drm_private *priv = dev->dev_private;
697 struct msm_kms *kms = priv->kms;
700 DBG("dev=%p, crtc=%u", dev, pipe);
701 return vblank_ctrl_queue_work(priv, pipe, true);
704 static void msm_disable_vblank(struct drm_device *dev, unsigned int pipe)
706 struct msm_drm_private *priv = dev->dev_private;
707 struct msm_kms *kms = priv->kms;
710 DBG("dev=%p, crtc=%u", dev, pipe);
711 vblank_ctrl_queue_work(priv, pipe, false);
718 static int msm_ioctl_get_param(struct drm_device *dev, void *data,
719 struct drm_file *file)
721 struct msm_drm_private *priv = dev->dev_private;
722 struct drm_msm_param *args = data;
725 /* for now, we just have 3d pipe.. eventually this would need to
726 * be more clever to dispatch to appropriate gpu module:
728 if (args->pipe != MSM_PIPE_3D0)
736 return gpu->funcs->get_param(gpu, args->param, &args->value);
739 static int msm_ioctl_gem_new(struct drm_device *dev, void *data,
740 struct drm_file *file)
742 struct drm_msm_gem_new *args = data;
744 if (args->flags & ~MSM_BO_FLAGS) {
745 DRM_ERROR("invalid flags: %08x\n", args->flags);
749 return msm_gem_new_handle(dev, file, args->size,
750 args->flags, &args->handle, NULL);
753 static inline ktime_t to_ktime(struct drm_msm_timespec timeout)
755 return ktime_set(timeout.tv_sec, timeout.tv_nsec);
758 static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data,
759 struct drm_file *file)
761 struct drm_msm_gem_cpu_prep *args = data;
762 struct drm_gem_object *obj;
763 ktime_t timeout = to_ktime(args->timeout);
766 if (args->op & ~MSM_PREP_FLAGS) {
767 DRM_ERROR("invalid op: %08x\n", args->op);
771 obj = drm_gem_object_lookup(file, args->handle);
775 ret = msm_gem_cpu_prep(obj, args->op, &timeout);
777 drm_gem_object_put_unlocked(obj);
782 static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data,
783 struct drm_file *file)
785 struct drm_msm_gem_cpu_fini *args = data;
786 struct drm_gem_object *obj;
789 obj = drm_gem_object_lookup(file, args->handle);
793 ret = msm_gem_cpu_fini(obj);
795 drm_gem_object_put_unlocked(obj);
800 static int msm_ioctl_gem_info_iova(struct drm_device *dev,
801 struct drm_gem_object *obj, uint64_t *iova)
803 struct msm_drm_private *priv = dev->dev_private;
809 * Don't pin the memory here - just get an address so that userspace can
812 return msm_gem_get_iova(obj, priv->gpu->aspace, iova);
815 static int msm_ioctl_gem_info(struct drm_device *dev, void *data,
816 struct drm_file *file)
818 struct drm_msm_gem_info *args = data;
819 struct drm_gem_object *obj;
820 struct msm_gem_object *msm_obj;
826 switch (args->info) {
827 case MSM_INFO_GET_OFFSET:
828 case MSM_INFO_GET_IOVA:
829 /* value returned as immediate, not pointer, so len==0: */
833 case MSM_INFO_SET_NAME:
834 case MSM_INFO_GET_NAME:
840 obj = drm_gem_object_lookup(file, args->handle);
844 msm_obj = to_msm_bo(obj);
846 switch (args->info) {
847 case MSM_INFO_GET_OFFSET:
848 args->value = msm_gem_mmap_offset(obj);
850 case MSM_INFO_GET_IOVA:
851 ret = msm_ioctl_gem_info_iova(dev, obj, &args->value);
853 case MSM_INFO_SET_NAME:
854 /* length check should leave room for terminating null: */
855 if (args->len >= sizeof(msm_obj->name)) {
859 if (copy_from_user(msm_obj->name, u64_to_user_ptr(args->value),
861 msm_obj->name[0] = '\0';
865 msm_obj->name[args->len] = '\0';
866 for (i = 0; i < args->len; i++) {
867 if (!isprint(msm_obj->name[i])) {
868 msm_obj->name[i] = '\0';
873 case MSM_INFO_GET_NAME:
874 if (args->value && (args->len < strlen(msm_obj->name))) {
878 args->len = strlen(msm_obj->name);
880 if (copy_to_user(u64_to_user_ptr(args->value),
881 msm_obj->name, args->len))
887 drm_gem_object_put_unlocked(obj);
892 static int msm_ioctl_wait_fence(struct drm_device *dev, void *data,
893 struct drm_file *file)
895 struct msm_drm_private *priv = dev->dev_private;
896 struct drm_msm_wait_fence *args = data;
897 ktime_t timeout = to_ktime(args->timeout);
898 struct msm_gpu_submitqueue *queue;
899 struct msm_gpu *gpu = priv->gpu;
903 DRM_ERROR("invalid pad: %08x\n", args->pad);
910 queue = msm_submitqueue_get(file->driver_priv, args->queueid);
914 ret = msm_wait_fence(gpu->rb[queue->prio]->fctx, args->fence, &timeout,
917 msm_submitqueue_put(queue);
921 static int msm_ioctl_gem_madvise(struct drm_device *dev, void *data,
922 struct drm_file *file)
924 struct drm_msm_gem_madvise *args = data;
925 struct drm_gem_object *obj;
928 switch (args->madv) {
929 case MSM_MADV_DONTNEED:
930 case MSM_MADV_WILLNEED:
936 ret = mutex_lock_interruptible(&dev->struct_mutex);
940 obj = drm_gem_object_lookup(file, args->handle);
946 ret = msm_gem_madvise(obj, args->madv);
948 args->retained = ret;
952 drm_gem_object_put(obj);
955 mutex_unlock(&dev->struct_mutex);
960 static int msm_ioctl_submitqueue_new(struct drm_device *dev, void *data,
961 struct drm_file *file)
963 struct drm_msm_submitqueue *args = data;
965 if (args->flags & ~MSM_SUBMITQUEUE_FLAGS)
968 return msm_submitqueue_create(dev, file->driver_priv, args->prio,
969 args->flags, &args->id);
972 static int msm_ioctl_submitqueue_query(struct drm_device *dev, void *data,
973 struct drm_file *file)
975 return msm_submitqueue_query(dev, file->driver_priv, data);
978 static int msm_ioctl_submitqueue_close(struct drm_device *dev, void *data,
979 struct drm_file *file)
981 u32 id = *(u32 *) data;
983 return msm_submitqueue_remove(file->driver_priv, id);
986 static const struct drm_ioctl_desc msm_ioctls[] = {
987 DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_AUTH|DRM_RENDER_ALLOW),
988 DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_AUTH|DRM_RENDER_ALLOW),
989 DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_AUTH|DRM_RENDER_ALLOW),
990 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_AUTH|DRM_RENDER_ALLOW),
991 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_AUTH|DRM_RENDER_ALLOW),
992 DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_AUTH|DRM_RENDER_ALLOW),
993 DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_AUTH|DRM_RENDER_ALLOW),
994 DRM_IOCTL_DEF_DRV(MSM_GEM_MADVISE, msm_ioctl_gem_madvise, DRM_AUTH|DRM_RENDER_ALLOW),
995 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_NEW, msm_ioctl_submitqueue_new, DRM_AUTH|DRM_RENDER_ALLOW),
996 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_CLOSE, msm_ioctl_submitqueue_close, DRM_AUTH|DRM_RENDER_ALLOW),
997 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_QUERY, msm_ioctl_submitqueue_query, DRM_AUTH|DRM_RENDER_ALLOW),
1000 static const struct vm_operations_struct vm_ops = {
1001 .fault = msm_gem_fault,
1002 .open = drm_gem_vm_open,
1003 .close = drm_gem_vm_close,
1006 static const struct file_operations fops = {
1007 .owner = THIS_MODULE,
1009 .release = drm_release,
1010 .unlocked_ioctl = drm_ioctl,
1011 .compat_ioctl = drm_compat_ioctl,
1014 .llseek = no_llseek,
1015 .mmap = msm_gem_mmap,
1018 static struct drm_driver msm_driver = {
1019 .driver_features = DRIVER_GEM |
1025 .postclose = msm_postclose,
1026 .lastclose = drm_fb_helper_lastclose,
1027 .irq_handler = msm_irq,
1028 .irq_preinstall = msm_irq_preinstall,
1029 .irq_postinstall = msm_irq_postinstall,
1030 .irq_uninstall = msm_irq_uninstall,
1031 .enable_vblank = msm_enable_vblank,
1032 .disable_vblank = msm_disable_vblank,
1033 .gem_free_object_unlocked = msm_gem_free_object,
1034 .gem_vm_ops = &vm_ops,
1035 .dumb_create = msm_gem_dumb_create,
1036 .dumb_map_offset = msm_gem_dumb_map_offset,
1037 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1038 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1039 .gem_prime_export = drm_gem_prime_export,
1040 .gem_prime_import = drm_gem_prime_import,
1041 .gem_prime_pin = msm_gem_prime_pin,
1042 .gem_prime_unpin = msm_gem_prime_unpin,
1043 .gem_prime_get_sg_table = msm_gem_prime_get_sg_table,
1044 .gem_prime_import_sg_table = msm_gem_prime_import_sg_table,
1045 .gem_prime_vmap = msm_gem_prime_vmap,
1046 .gem_prime_vunmap = msm_gem_prime_vunmap,
1047 .gem_prime_mmap = msm_gem_prime_mmap,
1048 #ifdef CONFIG_DEBUG_FS
1049 .debugfs_init = msm_debugfs_init,
1051 .ioctls = msm_ioctls,
1052 .num_ioctls = ARRAY_SIZE(msm_ioctls),
1055 .desc = "MSM Snapdragon DRM",
1057 .major = MSM_VERSION_MAJOR,
1058 .minor = MSM_VERSION_MINOR,
1059 .patchlevel = MSM_VERSION_PATCHLEVEL,
1062 #ifdef CONFIG_PM_SLEEP
1063 static int msm_pm_suspend(struct device *dev)
1065 struct drm_device *ddev = dev_get_drvdata(dev);
1066 struct msm_drm_private *priv = ddev->dev_private;
1068 if (WARN_ON(priv->pm_state))
1069 drm_atomic_state_put(priv->pm_state);
1071 priv->pm_state = drm_atomic_helper_suspend(ddev);
1072 if (IS_ERR(priv->pm_state)) {
1073 int ret = PTR_ERR(priv->pm_state);
1074 DRM_ERROR("Failed to suspend dpu, %d\n", ret);
1081 static int msm_pm_resume(struct device *dev)
1083 struct drm_device *ddev = dev_get_drvdata(dev);
1084 struct msm_drm_private *priv = ddev->dev_private;
1087 if (WARN_ON(!priv->pm_state))
1090 ret = drm_atomic_helper_resume(ddev, priv->pm_state);
1092 priv->pm_state = NULL;
1099 static int msm_runtime_suspend(struct device *dev)
1101 struct drm_device *ddev = dev_get_drvdata(dev);
1102 struct msm_drm_private *priv = ddev->dev_private;
1103 struct msm_mdss *mdss = priv->mdss;
1107 if (mdss && mdss->funcs)
1108 return mdss->funcs->disable(mdss);
1113 static int msm_runtime_resume(struct device *dev)
1115 struct drm_device *ddev = dev_get_drvdata(dev);
1116 struct msm_drm_private *priv = ddev->dev_private;
1117 struct msm_mdss *mdss = priv->mdss;
1121 if (mdss && mdss->funcs)
1122 return mdss->funcs->enable(mdss);
1128 static const struct dev_pm_ops msm_pm_ops = {
1129 SET_SYSTEM_SLEEP_PM_OPS(msm_pm_suspend, msm_pm_resume)
1130 SET_RUNTIME_PM_OPS(msm_runtime_suspend, msm_runtime_resume, NULL)
1134 * Componentized driver support:
1138 * NOTE: duplication of the same code as exynos or imx (or probably any other).
1139 * so probably some room for some helpers
1141 static int compare_of(struct device *dev, void *data)
1143 return dev->of_node == data;
1147 * Identify what components need to be added by parsing what remote-endpoints
1148 * our MDP output ports are connected to. In the case of LVDS on MDP4, there
1149 * is no external component that we need to add since LVDS is within MDP4
1152 static int add_components_mdp(struct device *mdp_dev,
1153 struct component_match **matchptr)
1155 struct device_node *np = mdp_dev->of_node;
1156 struct device_node *ep_node;
1157 struct device *master_dev;
1160 * on MDP4 based platforms, the MDP platform device is the component
1161 * master that adds other display interface components to itself.
1163 * on MDP5 based platforms, the MDSS platform device is the component
1164 * master that adds MDP5 and other display interface components to
1167 if (of_device_is_compatible(np, "qcom,mdp4"))
1168 master_dev = mdp_dev;
1170 master_dev = mdp_dev->parent;
1172 for_each_endpoint_of_node(np, ep_node) {
1173 struct device_node *intf;
1174 struct of_endpoint ep;
1177 ret = of_graph_parse_endpoint(ep_node, &ep);
1179 DRM_DEV_ERROR(mdp_dev, "unable to parse port endpoint\n");
1180 of_node_put(ep_node);
1185 * The LCDC/LVDS port on MDP4 is a speacial case where the
1186 * remote-endpoint isn't a component that we need to add
1188 if (of_device_is_compatible(np, "qcom,mdp4") &&
1193 * It's okay if some of the ports don't have a remote endpoint
1194 * specified. It just means that the port isn't connected to
1195 * any external interface.
1197 intf = of_graph_get_remote_port_parent(ep_node);
1201 if (of_device_is_available(intf))
1202 drm_of_component_match_add(master_dev, matchptr,
1211 static int compare_name_mdp(struct device *dev, void *data)
1213 return (strstr(dev_name(dev), "mdp") != NULL);
1216 static int add_display_components(struct device *dev,
1217 struct component_match **matchptr)
1219 struct device *mdp_dev;
1223 * MDP5/DPU based devices don't have a flat hierarchy. There is a top
1224 * level parent: MDSS, and children: MDP5/DPU, DSI, HDMI, eDP etc.
1225 * Populate the children devices, find the MDP5/DPU node, and then add
1226 * the interfaces to our components list.
1228 if (of_device_is_compatible(dev->of_node, "qcom,mdss") ||
1229 of_device_is_compatible(dev->of_node, "qcom,sdm845-mdss")) {
1230 ret = of_platform_populate(dev->of_node, NULL, NULL, dev);
1232 DRM_DEV_ERROR(dev, "failed to populate children devices\n");
1236 mdp_dev = device_find_child(dev, NULL, compare_name_mdp);
1238 DRM_DEV_ERROR(dev, "failed to find MDSS MDP node\n");
1239 of_platform_depopulate(dev);
1243 put_device(mdp_dev);
1245 /* add the MDP component itself */
1246 drm_of_component_match_add(dev, matchptr, compare_of,
1253 ret = add_components_mdp(mdp_dev, matchptr);
1255 of_platform_depopulate(dev);
1261 * We don't know what's the best binding to link the gpu with the drm device.
1262 * Fow now, we just hunt for all the possible gpus that we support, and add them
1265 static const struct of_device_id msm_gpu_match[] = {
1266 { .compatible = "qcom,adreno" },
1267 { .compatible = "qcom,adreno-3xx" },
1268 { .compatible = "amd,imageon" },
1269 { .compatible = "qcom,kgsl-3d0" },
1273 static int add_gpu_components(struct device *dev,
1274 struct component_match **matchptr)
1276 struct device_node *np;
1278 np = of_find_matching_node(NULL, msm_gpu_match);
1282 if (of_device_is_available(np))
1283 drm_of_component_match_add(dev, matchptr, compare_of, np);
1290 static int msm_drm_bind(struct device *dev)
1292 return msm_drm_init(dev, &msm_driver);
1295 static void msm_drm_unbind(struct device *dev)
1297 msm_drm_uninit(dev);
1300 static const struct component_master_ops msm_drm_ops = {
1301 .bind = msm_drm_bind,
1302 .unbind = msm_drm_unbind,
1309 static int msm_pdev_probe(struct platform_device *pdev)
1311 struct component_match *match = NULL;
1314 if (get_mdp_ver(pdev)) {
1315 ret = add_display_components(&pdev->dev, &match);
1320 ret = add_gpu_components(&pdev->dev, &match);
1324 /* on all devices that I am aware of, iommu's which can map
1325 * any address the cpu can see are used:
1327 ret = dma_set_mask_and_coherent(&pdev->dev, ~0);
1331 ret = component_master_add_with_match(&pdev->dev, &msm_drm_ops, match);
1338 of_platform_depopulate(&pdev->dev);
1342 static int msm_pdev_remove(struct platform_device *pdev)
1344 component_master_del(&pdev->dev, &msm_drm_ops);
1345 of_platform_depopulate(&pdev->dev);
1350 static const struct of_device_id dt_match[] = {
1351 { .compatible = "qcom,mdp4", .data = (void *)KMS_MDP4 },
1352 { .compatible = "qcom,mdss", .data = (void *)KMS_MDP5 },
1353 { .compatible = "qcom,sdm845-mdss", .data = (void *)KMS_DPU },
1356 MODULE_DEVICE_TABLE(of, dt_match);
1358 static struct platform_driver msm_platform_driver = {
1359 .probe = msm_pdev_probe,
1360 .remove = msm_pdev_remove,
1363 .of_match_table = dt_match,
1368 static int __init msm_drm_register(void)
1378 msm_hdmi_register();
1380 return platform_driver_register(&msm_platform_driver);
1383 static void __exit msm_drm_unregister(void)
1386 platform_driver_unregister(&msm_platform_driver);
1387 msm_hdmi_unregister();
1388 adreno_unregister();
1389 msm_edp_unregister();
1390 msm_dsi_unregister();
1391 msm_mdp_unregister();
1392 msm_dpu_unregister();
1395 module_init(msm_drm_register);
1396 module_exit(msm_drm_unregister);
1398 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
1399 MODULE_DESCRIPTION("MSM DRM Driver");
1400 MODULE_LICENSE("GPL");