2 * Copyright (c) 2014-2015 The Linux Foundation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
17 struct mdp5_cfg_handler {
19 struct mdp5_cfg config;
22 /* mdp5_cfg must be exposed (used in mdp5.xml.h) */
23 const struct mdp5_cfg_hw *mdp5_cfg = NULL;
25 const struct mdp5_cfg_hw msm8x74v1_config = {
37 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4, [SSPP_VIG2] = 7,
38 [SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
39 [SSPP_RGB0] = 16, [SSPP_RGB1] = 17, [SSPP_RGB2] = 18,
44 .base = { 0x00600, 0x00700, 0x00800, 0x00900, 0x00a00 },
45 .flush_hw_mask = 0x0003ffff,
49 .base = { 0x01200, 0x01600, 0x01a00 },
50 .caps = MDP_PIPE_CAP_HFLIP |
58 .base = { 0x01e00, 0x02200, 0x02600 },
59 .caps = MDP_PIPE_CAP_HFLIP |
66 .base = { 0x02a00, 0x02e00 },
67 .caps = MDP_PIPE_CAP_HFLIP |
73 .base = { 0x03200, 0x03600, 0x03a00, 0x03e00, 0x04200 },
78 .base = { 0x04600, 0x04a00, 0x04e00 },
82 .base = { 0x21b00, 0x21c00, 0x21d00 },
85 .base = { 0x21100, 0x21300, 0x21500, 0x21700 },
96 const struct mdp5_cfg_hw msm8x74v2_config = {
101 .caps = MDP_CAP_SMP |
108 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4, [SSPP_VIG2] = 7,
109 [SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
110 [SSPP_RGB0] = 16, [SSPP_RGB1] = 17, [SSPP_RGB2] = 18,
115 .base = { 0x00600, 0x00700, 0x00800, 0x00900, 0x00a00 },
116 .flush_hw_mask = 0x0003ffff,
120 .base = { 0x01200, 0x01600, 0x01a00 },
121 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
122 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |
123 MDP_PIPE_CAP_DECIMATION,
127 .base = { 0x01e00, 0x02200, 0x02600 },
128 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
129 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_DECIMATION,
133 .base = { 0x02a00, 0x02e00 },
134 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
138 .base = { 0x03200, 0x03600, 0x03a00, 0x03e00, 0x04200 },
141 .max_height = 0xFFFF,
145 .base = { 0x04600, 0x04a00, 0x04e00 },
149 .base = { 0x13100, 0x13300 },
153 .base = { 0x12d00, 0x12e00, 0x12f00 },
156 .base = { 0x12500, 0x12700, 0x12900, 0x12b00 },
164 .max_clk = 200000000,
167 const struct mdp5_cfg_hw apq8084_config = {
172 .caps = MDP_CAP_SMP |
179 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4,
180 [SSPP_VIG2] = 7, [SSPP_VIG3] = 19,
181 [SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
182 [SSPP_RGB0] = 16, [SSPP_RGB1] = 17,
183 [SSPP_RGB2] = 18, [SSPP_RGB3] = 22,
185 .reserved_state[0] = GENMASK(7, 0), /* first 8 MMBs */
187 /* Two SMP blocks are statically tied to RGB pipes: */
188 [16] = 2, [17] = 2, [18] = 2, [22] = 2,
193 .base = { 0x00600, 0x00700, 0x00800, 0x00900, 0x00a00 },
194 .flush_hw_mask = 0x003fffff,
198 .base = { 0x01200, 0x01600, 0x01a00, 0x01e00 },
199 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
200 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |
201 MDP_PIPE_CAP_DECIMATION,
205 .base = { 0x02200, 0x02600, 0x02a00, 0x02e00 },
206 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
207 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_DECIMATION,
211 .base = { 0x03200, 0x03600 },
212 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
216 .base = { 0x03a00, 0x03e00, 0x04200, 0x04600, 0x04a00, 0x04e00 },
219 .max_height = 0xFFFF,
223 .base = { 0x05200, 0x05600, 0x05a00, 0x05e00 },
228 .base = { 0x13500, 0x13700, 0x13900 },
232 .base = { 0x12f00, 0x13000, 0x13100, 0x13200 },
235 .base = { 0x12500, 0x12700, 0x12900, 0x12b00, 0x12d00 },
243 .max_clk = 320000000,
246 const struct mdp5_cfg_hw msm8x16_config = {
251 .caps = MDP_CAP_SMP |
258 [SSPP_VIG0] = 1, [SSPP_DMA0] = 4,
259 [SSPP_RGB0] = 7, [SSPP_RGB1] = 8,
264 .base = { 0x02000, 0x02200, 0x02400, 0x02600, 0x02800 },
265 .flush_hw_mask = 0x4003ffff,
270 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
271 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |
272 MDP_PIPE_CAP_DECIMATION,
276 .base = { 0x15000, 0x17000 },
277 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
278 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_DECIMATION,
283 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
286 .count = 2, /* LM0 and LM3 */
287 .base = { 0x45000, 0x48000 },
290 .max_height = 0xFFFF,
298 .base = { 0x00000, 0x6b800 },
304 .max_clk = 320000000,
307 const struct mdp5_cfg_hw msm8x94_config = {
312 .caps = MDP_CAP_SMP |
319 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4,
320 [SSPP_VIG2] = 7, [SSPP_VIG3] = 19,
321 [SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
322 [SSPP_RGB0] = 16, [SSPP_RGB1] = 17,
323 [SSPP_RGB2] = 18, [SSPP_RGB3] = 22,
325 .reserved_state[0] = GENMASK(23, 0), /* first 24 MMBs */
327 [1] = 1, [4] = 1, [7] = 1, [19] = 1,
328 [16] = 5, [17] = 5, [18] = 5, [22] = 5,
333 .base = { 0x02000, 0x02200, 0x02400, 0x02600, 0x02800 },
334 .flush_hw_mask = 0xf0ffffff,
338 .base = { 0x05000, 0x07000, 0x09000, 0x0b000 },
339 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
340 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |
341 MDP_PIPE_CAP_DECIMATION,
345 .base = { 0x15000, 0x17000, 0x19000, 0x1b000 },
346 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
347 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_DECIMATION,
351 .base = { 0x25000, 0x27000 },
352 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
356 .base = { 0x45000, 0x46000, 0x47000, 0x48000, 0x49000, 0x4a000 },
359 .max_height = 0xFFFF,
363 .base = { 0x55000, 0x57000, 0x59000, 0x5b000 },
368 .base = { 0x79000, 0x79800, 0x7a000 },
372 .base = { 0x71000, 0x71800, 0x72000, 0x72800 },
375 .base = { 0x6b000, 0x6b800, 0x6c000, 0x6c800, 0x6d000 },
383 .max_clk = 400000000,
386 const struct mdp5_cfg_hw msm8x96_config = {
391 .caps = MDP_CAP_DSC |
397 .base = { 0x02000, 0x02200, 0x02400, 0x02600, 0x02800 },
398 .flush_hw_mask = 0xf4ffffff,
402 .base = { 0x05000, 0x07000, 0x09000, 0x0b000 },
403 .caps = MDP_PIPE_CAP_HFLIP |
407 MDP_PIPE_CAP_DECIMATION |
408 MDP_PIPE_CAP_SW_PIX_EXT |
413 .base = { 0x15000, 0x17000, 0x19000, 0x1b000 },
414 .caps = MDP_PIPE_CAP_HFLIP |
417 MDP_PIPE_CAP_DECIMATION |
418 MDP_PIPE_CAP_SW_PIX_EXT |
423 .base = { 0x25000, 0x27000 },
424 .caps = MDP_PIPE_CAP_HFLIP |
426 MDP_PIPE_CAP_SW_PIX_EXT |
431 .base = { 0x45000, 0x46000, 0x47000, 0x48000, 0x49000, 0x4a000 },
434 .max_height = 0xFFFF,
438 .base = { 0x55000, 0x57000 },
442 .base = { 0x79000, 0x79800, 0x7a000 },
446 .base = { 0x71000, 0x71800, 0x72000, 0x72800 },
454 .base = { 0x81000, 0x81400 },
457 .base = { 0x6b000, 0x6b800, 0x6c000, 0x6c800, 0x6d000 },
465 .max_clk = 412500000,
468 static const struct mdp5_cfg_handler cfg_handlers[] = {
469 { .revision = 0, .config = { .hw = &msm8x74v1_config } },
470 { .revision = 2, .config = { .hw = &msm8x74v2_config } },
471 { .revision = 3, .config = { .hw = &apq8084_config } },
472 { .revision = 6, .config = { .hw = &msm8x16_config } },
473 { .revision = 9, .config = { .hw = &msm8x94_config } },
474 { .revision = 7, .config = { .hw = &msm8x96_config } },
477 static struct mdp5_cfg_platform *mdp5_get_config(struct platform_device *dev);
479 const struct mdp5_cfg_hw *mdp5_cfg_get_hw_config(struct mdp5_cfg_handler *cfg_handler)
481 return cfg_handler->config.hw;
484 struct mdp5_cfg *mdp5_cfg_get_config(struct mdp5_cfg_handler *cfg_handler)
486 return &cfg_handler->config;
489 int mdp5_cfg_get_hw_rev(struct mdp5_cfg_handler *cfg_handler)
491 return cfg_handler->revision;
494 void mdp5_cfg_destroy(struct mdp5_cfg_handler *cfg_handler)
499 struct mdp5_cfg_handler *mdp5_cfg_init(struct mdp5_kms *mdp5_kms,
500 uint32_t major, uint32_t minor)
502 struct drm_device *dev = mdp5_kms->dev;
503 struct platform_device *pdev = dev->platformdev;
504 struct mdp5_cfg_handler *cfg_handler;
505 struct mdp5_cfg_platform *pconfig;
508 cfg_handler = kzalloc(sizeof(*cfg_handler), GFP_KERNEL);
509 if (unlikely(!cfg_handler)) {
515 dev_err(dev->dev, "unexpected MDP major version: v%d.%d\n",
521 /* only after mdp5_cfg global pointer's init can we access the hw */
522 for (i = 0; i < ARRAY_SIZE(cfg_handlers); i++) {
523 if (cfg_handlers[i].revision != minor)
525 mdp5_cfg = cfg_handlers[i].config.hw;
529 if (unlikely(!mdp5_cfg)) {
530 dev_err(dev->dev, "unexpected MDP minor revision: v%d.%d\n",
536 cfg_handler->revision = minor;
537 cfg_handler->config.hw = mdp5_cfg;
539 pconfig = mdp5_get_config(pdev);
540 memcpy(&cfg_handler->config.platform, pconfig, sizeof(*pconfig));
542 DBG("MDP5: %s hw config selected", mdp5_cfg->name);
548 mdp5_cfg_destroy(cfg_handler);
553 static struct mdp5_cfg_platform *mdp5_get_config(struct platform_device *dev)
555 static struct mdp5_cfg_platform config = {};
557 config.iommu = iommu_domain_alloc(&platform_bus_type);