2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
20 #include <drm/drm_mode.h>
22 #include "drm_crtc_helper.h"
23 #include "drm_flip_work.h"
33 /* which mixer/encoder we route output to: */
39 uint32_t width, height;
42 /* next cursor to scan-out: */
44 struct drm_gem_object *next_bo;
46 /* current cursor being scanned out: */
47 struct drm_gem_object *scanout_bo;
51 /* if there is a pending flip, these will be non-null: */
52 struct drm_pending_vblank_event *event;
54 #define PENDING_CURSOR 0x1
55 #define PENDING_FLIP 0x2
58 /* for unref'ing cursor bo's after scanout completes: */
59 struct drm_flip_work unref_cursor_work;
61 struct mdp_irq vblank;
64 #define to_mdp4_crtc(x) container_of(x, struct mdp4_crtc, base)
66 static struct mdp4_kms *get_kms(struct drm_crtc *crtc)
68 struct msm_drm_private *priv = crtc->dev->dev_private;
69 return to_mdp4_kms(to_mdp_kms(priv->kms));
72 static void request_pending(struct drm_crtc *crtc, uint32_t pending)
74 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
76 atomic_or(pending, &mdp4_crtc->pending);
77 mdp_irq_register(&get_kms(crtc)->base, &mdp4_crtc->vblank);
80 static void crtc_flush(struct drm_crtc *crtc)
82 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
83 struct mdp4_kms *mdp4_kms = get_kms(crtc);
84 struct drm_plane *plane;
87 drm_atomic_crtc_for_each_plane(plane, crtc) {
88 enum mdp4_pipe pipe_id = mdp4_plane_pipe(plane);
89 flush |= pipe2flush(pipe_id);
92 flush |= ovlp2flush(mdp4_crtc->ovlp);
94 DBG("%s: flush=%08x", mdp4_crtc->name, flush);
96 mdp4_write(mdp4_kms, REG_MDP4_OVERLAY_FLUSH, flush);
99 /* if file!=NULL, this is preclose potential cancel-flip path */
100 static void complete_flip(struct drm_crtc *crtc, struct drm_file *file)
102 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
103 struct drm_device *dev = crtc->dev;
104 struct drm_pending_vblank_event *event;
107 spin_lock_irqsave(&dev->event_lock, flags);
108 event = mdp4_crtc->event;
110 /* if regular vblank case (!file) or if cancel-flip from
111 * preclose on file that requested flip, then send the
114 if (!file || (event->base.file_priv == file)) {
115 mdp4_crtc->event = NULL;
116 DBG("%s: send event: %p", mdp4_crtc->name, event);
117 drm_send_vblank_event(dev, mdp4_crtc->id, event);
120 spin_unlock_irqrestore(&dev->event_lock, flags);
123 static void unref_cursor_worker(struct drm_flip_work *work, void *val)
125 struct mdp4_crtc *mdp4_crtc =
126 container_of(work, struct mdp4_crtc, unref_cursor_work);
127 struct mdp4_kms *mdp4_kms = get_kms(&mdp4_crtc->base);
129 msm_gem_put_iova(val, mdp4_kms->id);
130 drm_gem_object_unreference_unlocked(val);
133 static void mdp4_crtc_destroy(struct drm_crtc *crtc)
135 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
137 drm_crtc_cleanup(crtc);
138 drm_flip_work_cleanup(&mdp4_crtc->unref_cursor_work);
143 static void mdp4_crtc_dpms(struct drm_crtc *crtc, int mode)
145 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
146 struct mdp4_kms *mdp4_kms = get_kms(crtc);
147 bool enabled = (mode == DRM_MODE_DPMS_ON);
149 DBG("%s: mode=%d", mdp4_crtc->name, mode);
151 if (enabled != mdp4_crtc->enabled) {
153 mdp4_enable(mdp4_kms);
154 mdp_irq_register(&mdp4_kms->base, &mdp4_crtc->err);
156 mdp_irq_unregister(&mdp4_kms->base, &mdp4_crtc->err);
157 mdp4_disable(mdp4_kms);
159 mdp4_crtc->enabled = enabled;
163 static bool mdp4_crtc_mode_fixup(struct drm_crtc *crtc,
164 const struct drm_display_mode *mode,
165 struct drm_display_mode *adjusted_mode)
170 /* statically (for now) map planes to mixer stage (z-order): */
171 static const int idxs[] = {
182 /* setup mixer config, for which we need to consider all crtc's and
183 * the planes attached to them
185 * TODO may possibly need some extra locking here
187 static void setup_mixer(struct mdp4_kms *mdp4_kms)
189 struct drm_mode_config *config = &mdp4_kms->dev->mode_config;
190 struct drm_crtc *crtc;
191 uint32_t mixer_cfg = 0;
192 static const enum mdp_mixer_stage_id stages[] = {
193 STAGE_BASE, STAGE0, STAGE1, STAGE2, STAGE3,
196 list_for_each_entry(crtc, &config->crtc_list, head) {
197 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
198 struct drm_plane *plane;
200 drm_atomic_crtc_for_each_plane(plane, crtc) {
201 enum mdp4_pipe pipe_id = mdp4_plane_pipe(plane);
202 int idx = idxs[pipe_id];
203 mixer_cfg = mixercfg(mixer_cfg, mdp4_crtc->mixer,
204 pipe_id, stages[idx]);
208 mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG, mixer_cfg);
211 static void blend_setup(struct drm_crtc *crtc)
213 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
214 struct mdp4_kms *mdp4_kms = get_kms(crtc);
215 struct drm_plane *plane;
216 int i, ovlp = mdp4_crtc->ovlp;
217 bool alpha[4]= { false, false, false, false };
219 mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_LOW0(ovlp), 0);
220 mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_LOW1(ovlp), 0);
221 mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_HIGH0(ovlp), 0);
222 mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_HIGH1(ovlp), 0);
224 drm_atomic_crtc_for_each_plane(plane, crtc) {
225 enum mdp4_pipe pipe_id = mdp4_plane_pipe(plane);
226 int idx = idxs[pipe_id];
228 const struct mdp_format *format =
229 to_mdp_format(msm_framebuffer_format(plane->fb));
230 alpha[idx-1] = format->alpha_enable;
234 for (i = 0; i < 4; i++) {
238 op = MDP4_OVLP_STAGE_OP_FG_ALPHA(FG_PIXEL) |
239 MDP4_OVLP_STAGE_OP_BG_ALPHA(FG_PIXEL) |
240 MDP4_OVLP_STAGE_OP_BG_INV_ALPHA;
242 op = MDP4_OVLP_STAGE_OP_FG_ALPHA(FG_CONST) |
243 MDP4_OVLP_STAGE_OP_BG_ALPHA(BG_CONST);
246 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_FG_ALPHA(ovlp, i), 0xff);
247 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_BG_ALPHA(ovlp, i), 0x00);
248 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_OP(ovlp, i), op);
249 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_CO3(ovlp, i), 1);
250 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_LOW0(ovlp, i), 0);
251 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_LOW1(ovlp, i), 0);
252 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_HIGH0(ovlp, i), 0);
253 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_HIGH1(ovlp, i), 0);
256 setup_mixer(mdp4_kms);
259 static void mdp4_crtc_mode_set_nofb(struct drm_crtc *crtc)
261 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
262 struct mdp4_kms *mdp4_kms = get_kms(crtc);
263 enum mdp4_dma dma = mdp4_crtc->dma;
264 int ovlp = mdp4_crtc->ovlp;
265 struct drm_display_mode *mode;
267 if (WARN_ON(!crtc->state))
270 mode = &crtc->state->adjusted_mode;
272 DBG("%s: set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x",
273 mdp4_crtc->name, mode->base.id, mode->name,
274 mode->vrefresh, mode->clock,
275 mode->hdisplay, mode->hsync_start,
276 mode->hsync_end, mode->htotal,
277 mode->vdisplay, mode->vsync_start,
278 mode->vsync_end, mode->vtotal,
279 mode->type, mode->flags);
281 mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_SIZE(dma),
282 MDP4_DMA_SRC_SIZE_WIDTH(mode->hdisplay) |
283 MDP4_DMA_SRC_SIZE_HEIGHT(mode->vdisplay));
285 /* take data from pipe: */
286 mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_BASE(dma), 0);
287 mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_STRIDE(dma), 0);
288 mdp4_write(mdp4_kms, REG_MDP4_DMA_DST_SIZE(dma),
289 MDP4_DMA_DST_SIZE_WIDTH(0) |
290 MDP4_DMA_DST_SIZE_HEIGHT(0));
292 mdp4_write(mdp4_kms, REG_MDP4_OVLP_BASE(ovlp), 0);
293 mdp4_write(mdp4_kms, REG_MDP4_OVLP_SIZE(ovlp),
294 MDP4_OVLP_SIZE_WIDTH(mode->hdisplay) |
295 MDP4_OVLP_SIZE_HEIGHT(mode->vdisplay));
296 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STRIDE(ovlp), 0);
298 mdp4_write(mdp4_kms, REG_MDP4_OVLP_CFG(ovlp), 1);
301 mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(0), 0x00ff0000);
302 mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(1), 0x00ff0000);
303 mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(2), 0x00ff0000);
307 static void mdp4_crtc_prepare(struct drm_crtc *crtc)
309 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
310 DBG("%s", mdp4_crtc->name);
311 /* make sure we hold a ref to mdp clks while setting up mode: */
312 drm_crtc_vblank_get(crtc);
313 mdp4_enable(get_kms(crtc));
314 mdp4_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
317 static void mdp4_crtc_commit(struct drm_crtc *crtc)
319 mdp4_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
321 /* drop the ref to mdp clk's that we got in prepare: */
322 mdp4_disable(get_kms(crtc));
323 drm_crtc_vblank_put(crtc);
326 static void mdp4_crtc_load_lut(struct drm_crtc *crtc)
330 static int mdp4_crtc_atomic_check(struct drm_crtc *crtc,
331 struct drm_crtc_state *state)
333 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
334 DBG("%s: check", mdp4_crtc->name);
335 // TODO anything else to check?
339 static void mdp4_crtc_atomic_begin(struct drm_crtc *crtc)
341 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
342 DBG("%s: begin", mdp4_crtc->name);
345 static void mdp4_crtc_atomic_flush(struct drm_crtc *crtc)
347 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
348 struct drm_device *dev = crtc->dev;
351 DBG("%s: event: %p", mdp4_crtc->name, crtc->state->event);
353 WARN_ON(mdp4_crtc->event);
355 spin_lock_irqsave(&dev->event_lock, flags);
356 mdp4_crtc->event = crtc->state->event;
357 spin_unlock_irqrestore(&dev->event_lock, flags);
361 request_pending(crtc, PENDING_FLIP);
364 static int mdp4_crtc_set_property(struct drm_crtc *crtc,
365 struct drm_property *property, uint64_t val)
371 #define CURSOR_WIDTH 64
372 #define CURSOR_HEIGHT 64
374 /* called from IRQ to update cursor related registers (if needed). The
375 * cursor registers, other than x/y position, appear not to be double
376 * buffered, and changing them other than from vblank seems to trigger
379 static void update_cursor(struct drm_crtc *crtc)
381 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
382 struct mdp4_kms *mdp4_kms = get_kms(crtc);
383 enum mdp4_dma dma = mdp4_crtc->dma;
386 spin_lock_irqsave(&mdp4_crtc->cursor.lock, flags);
387 if (mdp4_crtc->cursor.stale) {
388 struct drm_gem_object *next_bo = mdp4_crtc->cursor.next_bo;
389 struct drm_gem_object *prev_bo = mdp4_crtc->cursor.scanout_bo;
390 uint32_t iova = mdp4_crtc->cursor.next_iova;
393 /* take a obj ref + iova ref when we start scanning out: */
394 drm_gem_object_reference(next_bo);
395 msm_gem_get_iova_locked(next_bo, mdp4_kms->id, &iova);
398 mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_SIZE(dma),
399 MDP4_DMA_CURSOR_SIZE_WIDTH(mdp4_crtc->cursor.width) |
400 MDP4_DMA_CURSOR_SIZE_HEIGHT(mdp4_crtc->cursor.height));
401 mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BASE(dma), iova);
402 mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BLEND_CONFIG(dma),
403 MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT(CURSOR_ARGB) |
404 MDP4_DMA_CURSOR_BLEND_CONFIG_CURSOR_EN);
406 /* disable cursor: */
407 mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BASE(dma),
408 mdp4_kms->blank_cursor_iova);
411 /* and drop the iova ref + obj rev when done scanning out: */
413 drm_flip_work_queue(&mdp4_crtc->unref_cursor_work, prev_bo);
415 mdp4_crtc->cursor.scanout_bo = next_bo;
416 mdp4_crtc->cursor.stale = false;
419 mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_POS(dma),
420 MDP4_DMA_CURSOR_POS_X(mdp4_crtc->cursor.x) |
421 MDP4_DMA_CURSOR_POS_Y(mdp4_crtc->cursor.y));
423 spin_unlock_irqrestore(&mdp4_crtc->cursor.lock, flags);
426 static int mdp4_crtc_cursor_set(struct drm_crtc *crtc,
427 struct drm_file *file_priv, uint32_t handle,
428 uint32_t width, uint32_t height)
430 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
431 struct mdp4_kms *mdp4_kms = get_kms(crtc);
432 struct drm_device *dev = crtc->dev;
433 struct drm_gem_object *cursor_bo, *old_bo;
438 if ((width > CURSOR_WIDTH) || (height > CURSOR_HEIGHT)) {
439 dev_err(dev->dev, "bad cursor size: %dx%d\n", width, height);
444 cursor_bo = drm_gem_object_lookup(dev, file_priv, handle);
452 ret = msm_gem_get_iova(cursor_bo, mdp4_kms->id, &iova);
459 spin_lock_irqsave(&mdp4_crtc->cursor.lock, flags);
460 old_bo = mdp4_crtc->cursor.next_bo;
461 mdp4_crtc->cursor.next_bo = cursor_bo;
462 mdp4_crtc->cursor.next_iova = iova;
463 mdp4_crtc->cursor.width = width;
464 mdp4_crtc->cursor.height = height;
465 mdp4_crtc->cursor.stale = true;
466 spin_unlock_irqrestore(&mdp4_crtc->cursor.lock, flags);
469 /* drop our previous reference: */
470 drm_flip_work_queue(&mdp4_crtc->unref_cursor_work, old_bo);
473 request_pending(crtc, PENDING_CURSOR);
478 drm_gem_object_unreference_unlocked(cursor_bo);
482 static int mdp4_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
484 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
487 spin_lock_irqsave(&mdp4_crtc->cursor.lock, flags);
488 mdp4_crtc->cursor.x = x;
489 mdp4_crtc->cursor.y = y;
490 spin_unlock_irqrestore(&mdp4_crtc->cursor.lock, flags);
493 request_pending(crtc, PENDING_CURSOR);
498 static const struct drm_crtc_funcs mdp4_crtc_funcs = {
499 .set_config = drm_atomic_helper_set_config,
500 .destroy = mdp4_crtc_destroy,
501 .page_flip = drm_atomic_helper_page_flip,
502 .set_property = mdp4_crtc_set_property,
503 .cursor_set = mdp4_crtc_cursor_set,
504 .cursor_move = mdp4_crtc_cursor_move,
505 .reset = drm_atomic_helper_crtc_reset,
506 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
507 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
510 static const struct drm_crtc_helper_funcs mdp4_crtc_helper_funcs = {
511 .dpms = mdp4_crtc_dpms,
512 .mode_fixup = mdp4_crtc_mode_fixup,
513 .mode_set_nofb = mdp4_crtc_mode_set_nofb,
514 .mode_set = drm_helper_crtc_mode_set,
515 .mode_set_base = drm_helper_crtc_mode_set_base,
516 .prepare = mdp4_crtc_prepare,
517 .commit = mdp4_crtc_commit,
518 .load_lut = mdp4_crtc_load_lut,
519 .atomic_check = mdp4_crtc_atomic_check,
520 .atomic_begin = mdp4_crtc_atomic_begin,
521 .atomic_flush = mdp4_crtc_atomic_flush,
524 static void mdp4_crtc_vblank_irq(struct mdp_irq *irq, uint32_t irqstatus)
526 struct mdp4_crtc *mdp4_crtc = container_of(irq, struct mdp4_crtc, vblank);
527 struct drm_crtc *crtc = &mdp4_crtc->base;
528 struct msm_drm_private *priv = crtc->dev->dev_private;
531 mdp_irq_unregister(&get_kms(crtc)->base, &mdp4_crtc->vblank);
533 pending = atomic_xchg(&mdp4_crtc->pending, 0);
535 if (pending & PENDING_FLIP) {
536 complete_flip(crtc, NULL);
539 if (pending & PENDING_CURSOR) {
541 drm_flip_work_commit(&mdp4_crtc->unref_cursor_work, priv->wq);
545 static void mdp4_crtc_err_irq(struct mdp_irq *irq, uint32_t irqstatus)
547 struct mdp4_crtc *mdp4_crtc = container_of(irq, struct mdp4_crtc, err);
548 struct drm_crtc *crtc = &mdp4_crtc->base;
549 DBG("%s: error: %08x", mdp4_crtc->name, irqstatus);
553 uint32_t mdp4_crtc_vblank(struct drm_crtc *crtc)
555 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
556 return mdp4_crtc->vblank.irqmask;
559 void mdp4_crtc_cancel_pending_flip(struct drm_crtc *crtc, struct drm_file *file)
561 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
562 DBG("%s: cancel: %p", mdp4_crtc->name, file);
563 complete_flip(crtc, file);
566 /* set dma config, ie. the format the encoder wants. */
567 void mdp4_crtc_set_config(struct drm_crtc *crtc, uint32_t config)
569 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
570 struct mdp4_kms *mdp4_kms = get_kms(crtc);
572 mdp4_write(mdp4_kms, REG_MDP4_DMA_CONFIG(mdp4_crtc->dma), config);
575 /* set interface for routing crtc->encoder: */
576 void mdp4_crtc_set_intf(struct drm_crtc *crtc, enum mdp4_intf intf, int mixer)
578 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
579 struct mdp4_kms *mdp4_kms = get_kms(crtc);
582 intf_sel = mdp4_read(mdp4_kms, REG_MDP4_DISP_INTF_SEL);
584 switch (mdp4_crtc->dma) {
586 intf_sel &= ~MDP4_DISP_INTF_SEL_PRIM__MASK;
587 intf_sel |= MDP4_DISP_INTF_SEL_PRIM(intf);
590 intf_sel &= ~MDP4_DISP_INTF_SEL_SEC__MASK;
591 intf_sel |= MDP4_DISP_INTF_SEL_SEC(intf);
594 intf_sel &= ~MDP4_DISP_INTF_SEL_EXT__MASK;
595 intf_sel |= MDP4_DISP_INTF_SEL_EXT(intf);
599 if (intf == INTF_DSI_VIDEO) {
600 intf_sel &= ~MDP4_DISP_INTF_SEL_DSI_CMD;
601 intf_sel |= MDP4_DISP_INTF_SEL_DSI_VIDEO;
602 } else if (intf == INTF_DSI_CMD) {
603 intf_sel &= ~MDP4_DISP_INTF_SEL_DSI_VIDEO;
604 intf_sel |= MDP4_DISP_INTF_SEL_DSI_CMD;
607 mdp4_crtc->mixer = mixer;
611 DBG("%s: intf_sel=%08x", mdp4_crtc->name, intf_sel);
613 mdp4_write(mdp4_kms, REG_MDP4_DISP_INTF_SEL, intf_sel);
616 static const char *dma_names[] = {
617 "DMA_P", "DMA_S", "DMA_E",
620 /* initialize crtc */
621 struct drm_crtc *mdp4_crtc_init(struct drm_device *dev,
622 struct drm_plane *plane, int id, int ovlp_id,
623 enum mdp4_dma dma_id)
625 struct drm_crtc *crtc = NULL;
626 struct mdp4_crtc *mdp4_crtc;
628 mdp4_crtc = kzalloc(sizeof(*mdp4_crtc), GFP_KERNEL);
630 return ERR_PTR(-ENOMEM);
632 crtc = &mdp4_crtc->base;
636 mdp4_crtc->ovlp = ovlp_id;
637 mdp4_crtc->dma = dma_id;
639 mdp4_crtc->vblank.irqmask = dma2irq(mdp4_crtc->dma);
640 mdp4_crtc->vblank.irq = mdp4_crtc_vblank_irq;
642 mdp4_crtc->err.irqmask = dma2err(mdp4_crtc->dma);
643 mdp4_crtc->err.irq = mdp4_crtc_err_irq;
645 snprintf(mdp4_crtc->name, sizeof(mdp4_crtc->name), "%s:%d",
646 dma_names[dma_id], ovlp_id);
648 spin_lock_init(&mdp4_crtc->cursor.lock);
650 drm_flip_work_init(&mdp4_crtc->unref_cursor_work,
651 "unref cursor", unref_cursor_worker);
653 drm_crtc_init_with_planes(dev, crtc, plane, NULL, &mdp4_crtc_funcs);
654 drm_crtc_helper_add(crtc, &mdp4_crtc_helper_funcs);
657 mdp4_plane_install_properties(plane, &crtc->base);