2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
20 #include <drm/drm_mode.h>
22 #include "drm_crtc_helper.h"
23 #include "drm_flip_work.h"
28 struct drm_plane *plane;
29 struct drm_plane *planes[8];
35 /* which mixer/encoder we route output to: */
41 uint32_t width, height;
43 /* next cursor to scan-out: */
45 struct drm_gem_object *next_bo;
47 /* current cursor being scanned out: */
48 struct drm_gem_object *scanout_bo;
52 /* if there is a pending flip, these will be non-null: */
53 struct drm_pending_vblank_event *event;
54 struct msm_fence_cb pageflip_cb;
56 #define PENDING_CURSOR 0x1
57 #define PENDING_FLIP 0x2
60 /* the fb that we currently hold a scanout ref to: */
61 struct drm_framebuffer *fb;
63 /* for unref'ing framebuffers after scanout completes: */
64 struct drm_flip_work unref_fb_work;
66 /* for unref'ing cursor bo's after scanout completes: */
67 struct drm_flip_work unref_cursor_work;
69 struct mdp_irq vblank;
72 #define to_mdp4_crtc(x) container_of(x, struct mdp4_crtc, base)
74 static struct mdp4_kms *get_kms(struct drm_crtc *crtc)
76 struct msm_drm_private *priv = crtc->dev->dev_private;
77 return to_mdp4_kms(to_mdp_kms(priv->kms));
80 static void update_fb(struct drm_crtc *crtc, bool async,
81 struct drm_framebuffer *new_fb)
83 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
84 struct drm_framebuffer *old_fb = mdp4_crtc->fb;
87 drm_flip_work_queue(&mdp4_crtc->unref_fb_work, old_fb);
89 /* grab reference to incoming scanout fb: */
90 drm_framebuffer_reference(new_fb);
91 mdp4_crtc->base.fb = new_fb;
92 mdp4_crtc->fb = new_fb;
95 /* enable vblank to pick up the old_fb */
96 mdp_irq_register(&get_kms(crtc)->base, &mdp4_crtc->vblank);
100 /* if file!=NULL, this is preclose potential cancel-flip path */
101 static void complete_flip(struct drm_crtc *crtc, struct drm_file *file)
103 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
104 struct drm_device *dev = crtc->dev;
105 struct drm_pending_vblank_event *event;
108 spin_lock_irqsave(&dev->event_lock, flags);
109 event = mdp4_crtc->event;
111 /* if regular vblank case (!file) or if cancel-flip from
112 * preclose on file that requested flip, then send the
115 if (!file || (event->base.file_priv == file)) {
116 mdp4_crtc->event = NULL;
117 drm_send_vblank_event(dev, mdp4_crtc->id, event);
120 spin_unlock_irqrestore(&dev->event_lock, flags);
123 static void crtc_flush(struct drm_crtc *crtc)
125 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
126 struct mdp4_kms *mdp4_kms = get_kms(crtc);
127 uint32_t i, flush = 0;
129 for (i = 0; i < ARRAY_SIZE(mdp4_crtc->planes); i++) {
130 struct drm_plane *plane = mdp4_crtc->planes[i];
132 enum mdp4_pipe pipe_id = mdp4_plane_pipe(plane);
133 flush |= pipe2flush(pipe_id);
136 flush |= ovlp2flush(mdp4_crtc->ovlp);
138 DBG("%s: flush=%08x", mdp4_crtc->name, flush);
140 mdp4_write(mdp4_kms, REG_MDP4_OVERLAY_FLUSH, flush);
143 static void request_pending(struct drm_crtc *crtc, uint32_t pending)
145 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
147 atomic_or(pending, &mdp4_crtc->pending);
148 mdp_irq_register(&get_kms(crtc)->base, &mdp4_crtc->vblank);
151 static void pageflip_cb(struct msm_fence_cb *cb)
153 struct mdp4_crtc *mdp4_crtc =
154 container_of(cb, struct mdp4_crtc, pageflip_cb);
155 struct drm_crtc *crtc = &mdp4_crtc->base;
156 struct drm_framebuffer *fb = crtc->fb;
161 mdp4_plane_set_scanout(mdp4_crtc->plane, fb);
164 /* enable vblank to complete flip: */
165 request_pending(crtc, PENDING_FLIP);
168 static void unref_fb_worker(struct drm_flip_work *work, void *val)
170 struct mdp4_crtc *mdp4_crtc =
171 container_of(work, struct mdp4_crtc, unref_fb_work);
172 struct drm_device *dev = mdp4_crtc->base.dev;
174 mutex_lock(&dev->mode_config.mutex);
175 drm_framebuffer_unreference(val);
176 mutex_unlock(&dev->mode_config.mutex);
179 static void unref_cursor_worker(struct drm_flip_work *work, void *val)
181 struct mdp4_crtc *mdp4_crtc =
182 container_of(work, struct mdp4_crtc, unref_cursor_work);
183 struct mdp4_kms *mdp4_kms = get_kms(&mdp4_crtc->base);
185 msm_gem_put_iova(val, mdp4_kms->id);
186 drm_gem_object_unreference_unlocked(val);
189 static void mdp4_crtc_destroy(struct drm_crtc *crtc)
191 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
193 mdp4_crtc->plane->funcs->destroy(mdp4_crtc->plane);
195 drm_crtc_cleanup(crtc);
196 drm_flip_work_cleanup(&mdp4_crtc->unref_fb_work);
197 drm_flip_work_cleanup(&mdp4_crtc->unref_cursor_work);
202 static void mdp4_crtc_dpms(struct drm_crtc *crtc, int mode)
204 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
205 struct mdp4_kms *mdp4_kms = get_kms(crtc);
206 bool enabled = (mode == DRM_MODE_DPMS_ON);
208 DBG("%s: mode=%d", mdp4_crtc->name, mode);
210 if (enabled != mdp4_crtc->enabled) {
212 mdp4_enable(mdp4_kms);
213 mdp_irq_register(&mdp4_kms->base, &mdp4_crtc->err);
215 mdp_irq_unregister(&mdp4_kms->base, &mdp4_crtc->err);
216 mdp4_disable(mdp4_kms);
218 mdp4_crtc->enabled = enabled;
222 static bool mdp4_crtc_mode_fixup(struct drm_crtc *crtc,
223 const struct drm_display_mode *mode,
224 struct drm_display_mode *adjusted_mode)
229 static void blend_setup(struct drm_crtc *crtc)
231 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
232 struct mdp4_kms *mdp4_kms = get_kms(crtc);
233 int i, ovlp = mdp4_crtc->ovlp;
234 uint32_t mixer_cfg = 0;
235 static const enum mdp_mixer_stage_id stages[] = {
236 STAGE_BASE, STAGE0, STAGE1, STAGE2, STAGE3,
238 /* statically (for now) map planes to mixer stage (z-order): */
239 static const int idxs[] = {
249 bool alpha[4]= { false, false, false, false };
251 mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_LOW0(ovlp), 0);
252 mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_LOW1(ovlp), 0);
253 mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_HIGH0(ovlp), 0);
254 mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_HIGH1(ovlp), 0);
256 /* TODO single register for all CRTCs, so this won't work properly
257 * when multiple CRTCs are active..
259 for (i = 0; i < ARRAY_SIZE(mdp4_crtc->planes); i++) {
260 struct drm_plane *plane = mdp4_crtc->planes[i];
262 enum mdp4_pipe pipe_id = mdp4_plane_pipe(plane);
263 int idx = idxs[pipe_id];
265 const struct mdp_format *format =
266 to_mdp_format(msm_framebuffer_format(plane->fb));
267 alpha[idx-1] = format->alpha_enable;
269 mixer_cfg |= mixercfg(mdp4_crtc->mixer, pipe_id, stages[idx]);
273 /* this shouldn't happen.. and seems to cause underflow: */
276 for (i = 0; i < 4; i++) {
280 op = MDP4_OVLP_STAGE_OP_FG_ALPHA(FG_PIXEL) |
281 MDP4_OVLP_STAGE_OP_BG_ALPHA(FG_PIXEL) |
282 MDP4_OVLP_STAGE_OP_BG_INV_ALPHA;
284 op = MDP4_OVLP_STAGE_OP_FG_ALPHA(FG_CONST) |
285 MDP4_OVLP_STAGE_OP_BG_ALPHA(BG_CONST);
288 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_FG_ALPHA(ovlp, i), 0xff);
289 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_BG_ALPHA(ovlp, i), 0x00);
290 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_OP(ovlp, i), op);
291 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_CO3(ovlp, i), 1);
292 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_LOW0(ovlp, i), 0);
293 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_LOW1(ovlp, i), 0);
294 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_HIGH0(ovlp, i), 0);
295 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_HIGH1(ovlp, i), 0);
298 mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG, mixer_cfg);
301 static int mdp4_crtc_mode_set(struct drm_crtc *crtc,
302 struct drm_display_mode *mode,
303 struct drm_display_mode *adjusted_mode,
305 struct drm_framebuffer *old_fb)
307 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
308 struct mdp4_kms *mdp4_kms = get_kms(crtc);
309 enum mdp4_dma dma = mdp4_crtc->dma;
310 int ret, ovlp = mdp4_crtc->ovlp;
312 mode = adjusted_mode;
314 DBG("%s: set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x",
315 mdp4_crtc->name, mode->base.id, mode->name,
316 mode->vrefresh, mode->clock,
317 mode->hdisplay, mode->hsync_start,
318 mode->hsync_end, mode->htotal,
319 mode->vdisplay, mode->vsync_start,
320 mode->vsync_end, mode->vtotal,
321 mode->type, mode->flags);
323 mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_SIZE(dma),
324 MDP4_DMA_SRC_SIZE_WIDTH(mode->hdisplay) |
325 MDP4_DMA_SRC_SIZE_HEIGHT(mode->vdisplay));
327 /* take data from pipe: */
328 mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_BASE(dma), 0);
329 mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_STRIDE(dma),
330 crtc->fb->pitches[0]);
331 mdp4_write(mdp4_kms, REG_MDP4_DMA_DST_SIZE(dma),
332 MDP4_DMA_DST_SIZE_WIDTH(0) |
333 MDP4_DMA_DST_SIZE_HEIGHT(0));
335 mdp4_write(mdp4_kms, REG_MDP4_OVLP_BASE(ovlp), 0);
336 mdp4_write(mdp4_kms, REG_MDP4_OVLP_SIZE(ovlp),
337 MDP4_OVLP_SIZE_WIDTH(mode->hdisplay) |
338 MDP4_OVLP_SIZE_HEIGHT(mode->vdisplay));
339 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STRIDE(ovlp),
340 crtc->fb->pitches[0]);
342 mdp4_write(mdp4_kms, REG_MDP4_OVLP_CFG(ovlp), 1);
344 update_fb(crtc, false, crtc->fb);
346 ret = mdp4_plane_mode_set(mdp4_crtc->plane, crtc, crtc->fb,
347 0, 0, mode->hdisplay, mode->vdisplay,
349 mode->hdisplay << 16, mode->vdisplay << 16);
351 dev_err(crtc->dev->dev, "%s: failed to set mode on plane: %d\n",
352 mdp4_crtc->name, ret);
357 mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(0), 0x00ff0000);
358 mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(1), 0x00ff0000);
359 mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(2), 0x00ff0000);
365 static void mdp4_crtc_prepare(struct drm_crtc *crtc)
367 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
368 DBG("%s", mdp4_crtc->name);
369 /* make sure we hold a ref to mdp clks while setting up mode: */
370 mdp4_enable(get_kms(crtc));
371 mdp4_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
374 static void mdp4_crtc_commit(struct drm_crtc *crtc)
376 mdp4_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
378 /* drop the ref to mdp clk's that we got in prepare: */
379 mdp4_disable(get_kms(crtc));
382 static int mdp4_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
383 struct drm_framebuffer *old_fb)
385 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
386 struct drm_plane *plane = mdp4_crtc->plane;
387 struct drm_display_mode *mode = &crtc->mode;
389 update_fb(crtc, false, crtc->fb);
391 return mdp4_plane_mode_set(plane, crtc, crtc->fb,
392 0, 0, mode->hdisplay, mode->vdisplay,
394 mode->hdisplay << 16, mode->vdisplay << 16);
397 static void mdp4_crtc_load_lut(struct drm_crtc *crtc)
401 static int mdp4_crtc_page_flip(struct drm_crtc *crtc,
402 struct drm_framebuffer *new_fb,
403 struct drm_pending_vblank_event *event,
404 uint32_t page_flip_flags)
406 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
407 struct drm_device *dev = crtc->dev;
408 struct drm_gem_object *obj;
411 if (mdp4_crtc->event) {
412 dev_err(dev->dev, "already pending flip!\n");
416 obj = msm_framebuffer_bo(new_fb, 0);
418 spin_lock_irqsave(&dev->event_lock, flags);
419 mdp4_crtc->event = event;
420 spin_unlock_irqrestore(&dev->event_lock, flags);
422 update_fb(crtc, true, new_fb);
424 return msm_gem_queue_inactive_cb(obj, &mdp4_crtc->pageflip_cb);
427 static int mdp4_crtc_set_property(struct drm_crtc *crtc,
428 struct drm_property *property, uint64_t val)
434 #define CURSOR_WIDTH 64
435 #define CURSOR_HEIGHT 64
437 /* called from IRQ to update cursor related registers (if needed). The
438 * cursor registers, other than x/y position, appear not to be double
439 * buffered, and changing them other than from vblank seems to trigger
442 static void update_cursor(struct drm_crtc *crtc)
444 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
445 enum mdp4_dma dma = mdp4_crtc->dma;
448 spin_lock_irqsave(&mdp4_crtc->cursor.lock, flags);
449 if (mdp4_crtc->cursor.stale) {
450 struct mdp4_kms *mdp4_kms = get_kms(crtc);
451 struct drm_gem_object *next_bo = mdp4_crtc->cursor.next_bo;
452 struct drm_gem_object *prev_bo = mdp4_crtc->cursor.scanout_bo;
453 uint32_t iova = mdp4_crtc->cursor.next_iova;
456 /* take a obj ref + iova ref when we start scanning out: */
457 drm_gem_object_reference(next_bo);
458 msm_gem_get_iova_locked(next_bo, mdp4_kms->id, &iova);
461 mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_SIZE(dma),
462 MDP4_DMA_CURSOR_SIZE_WIDTH(mdp4_crtc->cursor.width) |
463 MDP4_DMA_CURSOR_SIZE_HEIGHT(mdp4_crtc->cursor.height));
464 mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BASE(dma), iova);
465 mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BLEND_CONFIG(dma),
466 MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT(CURSOR_ARGB) |
467 MDP4_DMA_CURSOR_BLEND_CONFIG_CURSOR_EN);
469 /* disable cursor: */
470 mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BASE(dma), 0);
471 mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BLEND_CONFIG(dma),
472 MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT(CURSOR_ARGB));
475 /* and drop the iova ref + obj rev when done scanning out: */
477 drm_flip_work_queue(&mdp4_crtc->unref_cursor_work, prev_bo);
479 mdp4_crtc->cursor.scanout_bo = next_bo;
480 mdp4_crtc->cursor.stale = false;
482 spin_unlock_irqrestore(&mdp4_crtc->cursor.lock, flags);
485 static int mdp4_crtc_cursor_set(struct drm_crtc *crtc,
486 struct drm_file *file_priv, uint32_t handle,
487 uint32_t width, uint32_t height)
489 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
490 struct mdp4_kms *mdp4_kms = get_kms(crtc);
491 struct drm_device *dev = crtc->dev;
492 struct drm_gem_object *cursor_bo, *old_bo;
497 if ((width > CURSOR_WIDTH) || (height > CURSOR_HEIGHT)) {
498 dev_err(dev->dev, "bad cursor size: %dx%d\n", width, height);
503 cursor_bo = drm_gem_object_lookup(dev, file_priv, handle);
511 ret = msm_gem_get_iova(cursor_bo, mdp4_kms->id, &iova);
518 spin_lock_irqsave(&mdp4_crtc->cursor.lock, flags);
519 old_bo = mdp4_crtc->cursor.next_bo;
520 mdp4_crtc->cursor.next_bo = cursor_bo;
521 mdp4_crtc->cursor.next_iova = iova;
522 mdp4_crtc->cursor.width = width;
523 mdp4_crtc->cursor.height = height;
524 mdp4_crtc->cursor.stale = true;
525 spin_unlock_irqrestore(&mdp4_crtc->cursor.lock, flags);
528 /* drop our previous reference: */
529 msm_gem_put_iova(old_bo, mdp4_kms->id);
530 drm_gem_object_unreference_unlocked(old_bo);
533 request_pending(crtc, PENDING_CURSOR);
538 drm_gem_object_unreference_unlocked(cursor_bo);
542 static int mdp4_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
544 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
545 struct mdp4_kms *mdp4_kms = get_kms(crtc);
546 enum mdp4_dma dma = mdp4_crtc->dma;
548 mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_POS(dma),
549 MDP4_DMA_CURSOR_POS_X(x) |
550 MDP4_DMA_CURSOR_POS_Y(y));
555 static const struct drm_crtc_funcs mdp4_crtc_funcs = {
556 .set_config = drm_crtc_helper_set_config,
557 .destroy = mdp4_crtc_destroy,
558 .page_flip = mdp4_crtc_page_flip,
559 .set_property = mdp4_crtc_set_property,
560 .cursor_set = mdp4_crtc_cursor_set,
561 .cursor_move = mdp4_crtc_cursor_move,
564 static const struct drm_crtc_helper_funcs mdp4_crtc_helper_funcs = {
565 .dpms = mdp4_crtc_dpms,
566 .mode_fixup = mdp4_crtc_mode_fixup,
567 .mode_set = mdp4_crtc_mode_set,
568 .prepare = mdp4_crtc_prepare,
569 .commit = mdp4_crtc_commit,
570 .mode_set_base = mdp4_crtc_mode_set_base,
571 .load_lut = mdp4_crtc_load_lut,
574 static void mdp4_crtc_vblank_irq(struct mdp_irq *irq, uint32_t irqstatus)
576 struct mdp4_crtc *mdp4_crtc = container_of(irq, struct mdp4_crtc, vblank);
577 struct drm_crtc *crtc = &mdp4_crtc->base;
578 struct msm_drm_private *priv = crtc->dev->dev_private;
581 mdp_irq_unregister(&get_kms(crtc)->base, &mdp4_crtc->vblank);
583 pending = atomic_xchg(&mdp4_crtc->pending, 0);
585 if (pending & PENDING_FLIP) {
586 complete_flip(crtc, NULL);
587 drm_flip_work_commit(&mdp4_crtc->unref_fb_work, priv->wq);
590 if (pending & PENDING_CURSOR) {
592 drm_flip_work_commit(&mdp4_crtc->unref_cursor_work, priv->wq);
596 static void mdp4_crtc_err_irq(struct mdp_irq *irq, uint32_t irqstatus)
598 struct mdp4_crtc *mdp4_crtc = container_of(irq, struct mdp4_crtc, err);
599 struct drm_crtc *crtc = &mdp4_crtc->base;
600 DBG("%s: error: %08x", mdp4_crtc->name, irqstatus);
604 uint32_t mdp4_crtc_vblank(struct drm_crtc *crtc)
606 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
607 return mdp4_crtc->vblank.irqmask;
610 void mdp4_crtc_cancel_pending_flip(struct drm_crtc *crtc, struct drm_file *file)
612 DBG("cancel: %p", file);
613 complete_flip(crtc, file);
616 /* set dma config, ie. the format the encoder wants. */
617 void mdp4_crtc_set_config(struct drm_crtc *crtc, uint32_t config)
619 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
620 struct mdp4_kms *mdp4_kms = get_kms(crtc);
622 mdp4_write(mdp4_kms, REG_MDP4_DMA_CONFIG(mdp4_crtc->dma), config);
625 /* set interface for routing crtc->encoder: */
626 void mdp4_crtc_set_intf(struct drm_crtc *crtc, enum mdp4_intf intf)
628 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
629 struct mdp4_kms *mdp4_kms = get_kms(crtc);
632 intf_sel = mdp4_read(mdp4_kms, REG_MDP4_DISP_INTF_SEL);
634 switch (mdp4_crtc->dma) {
636 intf_sel &= ~MDP4_DISP_INTF_SEL_PRIM__MASK;
637 intf_sel |= MDP4_DISP_INTF_SEL_PRIM(intf);
640 intf_sel &= ~MDP4_DISP_INTF_SEL_SEC__MASK;
641 intf_sel |= MDP4_DISP_INTF_SEL_SEC(intf);
644 intf_sel &= ~MDP4_DISP_INTF_SEL_EXT__MASK;
645 intf_sel |= MDP4_DISP_INTF_SEL_EXT(intf);
649 if (intf == INTF_DSI_VIDEO) {
650 intf_sel &= ~MDP4_DISP_INTF_SEL_DSI_CMD;
651 intf_sel |= MDP4_DISP_INTF_SEL_DSI_VIDEO;
652 mdp4_crtc->mixer = 0;
653 } else if (intf == INTF_DSI_CMD) {
654 intf_sel &= ~MDP4_DISP_INTF_SEL_DSI_VIDEO;
655 intf_sel |= MDP4_DISP_INTF_SEL_DSI_CMD;
656 mdp4_crtc->mixer = 0;
657 } else if (intf == INTF_LCDC_DTV){
658 mdp4_crtc->mixer = 1;
663 DBG("%s: intf_sel=%08x", mdp4_crtc->name, intf_sel);
665 mdp4_write(mdp4_kms, REG_MDP4_DISP_INTF_SEL, intf_sel);
668 static void set_attach(struct drm_crtc *crtc, enum mdp4_pipe pipe_id,
669 struct drm_plane *plane)
671 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
673 BUG_ON(pipe_id >= ARRAY_SIZE(mdp4_crtc->planes));
675 if (mdp4_crtc->planes[pipe_id] == plane)
678 mdp4_crtc->planes[pipe_id] = plane;
680 if (mdp4_crtc->enabled && (plane != mdp4_crtc->plane))
684 void mdp4_crtc_attach(struct drm_crtc *crtc, struct drm_plane *plane)
686 set_attach(crtc, mdp4_plane_pipe(plane), plane);
689 void mdp4_crtc_detach(struct drm_crtc *crtc, struct drm_plane *plane)
691 set_attach(crtc, mdp4_plane_pipe(plane), NULL);
694 static const char *dma_names[] = {
695 "DMA_P", "DMA_S", "DMA_E",
698 /* initialize crtc */
699 struct drm_crtc *mdp4_crtc_init(struct drm_device *dev,
700 struct drm_plane *plane, int id, int ovlp_id,
701 enum mdp4_dma dma_id)
703 struct drm_crtc *crtc = NULL;
704 struct mdp4_crtc *mdp4_crtc;
707 mdp4_crtc = kzalloc(sizeof(*mdp4_crtc), GFP_KERNEL);
713 crtc = &mdp4_crtc->base;
715 mdp4_crtc->plane = plane;
717 mdp4_crtc->ovlp = ovlp_id;
718 mdp4_crtc->dma = dma_id;
720 mdp4_crtc->vblank.irqmask = dma2irq(mdp4_crtc->dma);
721 mdp4_crtc->vblank.irq = mdp4_crtc_vblank_irq;
723 mdp4_crtc->err.irqmask = dma2err(mdp4_crtc->dma);
724 mdp4_crtc->err.irq = mdp4_crtc_err_irq;
726 snprintf(mdp4_crtc->name, sizeof(mdp4_crtc->name), "%s:%d",
727 dma_names[dma_id], ovlp_id);
729 spin_lock_init(&mdp4_crtc->cursor.lock);
731 ret = drm_flip_work_init(&mdp4_crtc->unref_fb_work, 16,
732 "unref fb", unref_fb_worker);
736 ret = drm_flip_work_init(&mdp4_crtc->unref_cursor_work, 64,
737 "unref cursor", unref_cursor_worker);
739 INIT_FENCE_CB(&mdp4_crtc->pageflip_cb, pageflip_cb);
741 drm_crtc_init(dev, crtc, &mdp4_crtc_funcs);
742 drm_crtc_helper_add(crtc, &mdp4_crtc_helper_funcs);
744 mdp4_plane_install_properties(mdp4_crtc->plane, &crtc->base);
750 mdp4_crtc_destroy(crtc);