2 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/clk.h>
15 #include <linux/delay.h>
16 #include <linux/err.h>
17 #include <linux/gpio.h>
18 #include <linux/gpio/consumer.h>
19 #include <linux/interrupt.h>
20 #include <linux/of_device.h>
21 #include <linux/of_gpio.h>
22 #include <linux/of_irq.h>
23 #include <linux/pinctrl/consumer.h>
24 #include <linux/of_graph.h>
25 #include <linux/regulator/consumer.h>
26 #include <linux/spinlock.h>
27 #include <linux/mfd/syscon.h>
28 #include <linux/regmap.h>
29 #include <video/mipi_display.h>
37 static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor)
45 * From DSI6G(v3), addition of a 6G_HW_VERSION register at offset 0
46 * makes all other registers 4-byte shifted down.
48 * In order to identify between DSI6G(v3) and beyond, and DSIv2 and
49 * older, we read the DSI_VERSION register without any shift(offset
50 * 0x1f0). In the case of DSIv2, this hast to be a non-zero value. In
51 * the case of DSI6G, this has to be zero (the offset points to a
52 * scratch register which we never touch)
55 ver = msm_readl(base + REG_DSI_VERSION);
57 /* older dsi host, there is no register shift */
58 ver = FIELD(ver, DSI_VERSION_MAJOR);
59 if (ver <= MSM_DSI_VER_MAJOR_V2) {
69 * newer host, offset 0 has 6G_HW_VERSION, the rest of the
70 * registers are shifted down, read DSI_VERSION again with
73 ver = msm_readl(base + DSI_6G_REG_SHIFT + REG_DSI_VERSION);
74 ver = FIELD(ver, DSI_VERSION_MAJOR);
75 if (ver == MSM_DSI_VER_MAJOR_6G) {
78 *minor = msm_readl(base + REG_DSI_6G_HW_VERSION);
86 #define DSI_ERR_STATE_ACK 0x0000
87 #define DSI_ERR_STATE_TIMEOUT 0x0001
88 #define DSI_ERR_STATE_DLN0_PHY 0x0002
89 #define DSI_ERR_STATE_FIFO 0x0004
90 #define DSI_ERR_STATE_MDP_FIFO_UNDERFLOW 0x0008
91 #define DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION 0x0010
92 #define DSI_ERR_STATE_PLL_UNLOCKED 0x0020
94 #define DSI_CLK_CTRL_ENABLE_CLKS \
95 (DSI_CLK_CTRL_AHBS_HCLK_ON | DSI_CLK_CTRL_AHBM_SCLK_ON | \
96 DSI_CLK_CTRL_PCLK_ON | DSI_CLK_CTRL_DSICLK_ON | \
97 DSI_CLK_CTRL_BYTECLK_ON | DSI_CLK_CTRL_ESCCLK_ON | \
98 DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK)
100 struct msm_dsi_host {
101 struct mipi_dsi_host base;
103 struct platform_device *pdev;
104 struct drm_device *dev;
108 void __iomem *ctrl_base;
109 struct regulator_bulk_data supplies[DSI_DEV_REGULATOR_MAX];
111 struct clk *bus_clks[DSI_BUS_CLK_MAX];
113 struct clk *byte_clk;
115 struct clk *pixel_clk;
116 struct clk *byte_clk_src;
117 struct clk *pixel_clk_src;
118 struct clk *byte_intf_clk;
123 /* DSI v2 specific clocks */
125 struct clk *esc_clk_src;
126 struct clk *dsi_clk_src;
130 struct gpio_desc *disp_en_gpio;
131 struct gpio_desc *te_gpio;
133 const struct msm_dsi_cfg_handler *cfg_hnd;
135 struct completion dma_comp;
136 struct completion video_comp;
137 struct mutex dev_mutex;
138 struct mutex cmd_mutex;
139 spinlock_t intr_lock; /* Protect interrupt ctrl register */
142 struct work_struct err_work;
143 struct work_struct hpd_work;
144 struct workqueue_struct *workqueue;
146 /* DSI 6G TX buffer*/
147 struct drm_gem_object *tx_gem_obj;
149 /* DSI v2 TX buffer */
151 dma_addr_t tx_buf_paddr;
159 struct drm_display_mode *mode;
161 /* connected device info */
162 struct device_node *device_node;
163 unsigned int channel;
165 enum mipi_dsi_pixel_format format;
166 unsigned long mode_flags;
168 /* lane data parsed via DT */
172 u32 dma_cmd_ctrl_restore;
180 static u32 dsi_get_bpp(const enum mipi_dsi_pixel_format fmt)
183 case MIPI_DSI_FMT_RGB565: return 16;
184 case MIPI_DSI_FMT_RGB666_PACKED: return 18;
185 case MIPI_DSI_FMT_RGB666:
186 case MIPI_DSI_FMT_RGB888:
191 static inline u32 dsi_read(struct msm_dsi_host *msm_host, u32 reg)
193 return msm_readl(msm_host->ctrl_base + reg);
195 static inline void dsi_write(struct msm_dsi_host *msm_host, u32 reg, u32 data)
197 msm_writel(data, msm_host->ctrl_base + reg);
200 static int dsi_host_regulator_enable(struct msm_dsi_host *msm_host);
201 static void dsi_host_regulator_disable(struct msm_dsi_host *msm_host);
203 static const struct msm_dsi_cfg_handler *dsi_get_config(
204 struct msm_dsi_host *msm_host)
206 const struct msm_dsi_cfg_handler *cfg_hnd = NULL;
207 struct device *dev = &msm_host->pdev->dev;
208 struct regulator *gdsc_reg;
211 u32 major = 0, minor = 0;
213 gdsc_reg = regulator_get(dev, "gdsc");
214 if (IS_ERR(gdsc_reg)) {
215 pr_err("%s: cannot get gdsc\n", __func__);
219 ahb_clk = msm_clk_get(msm_host->pdev, "iface");
220 if (IS_ERR(ahb_clk)) {
221 pr_err("%s: cannot get interface clock\n", __func__);
225 pm_runtime_get_sync(dev);
227 ret = regulator_enable(gdsc_reg);
229 pr_err("%s: unable to enable gdsc\n", __func__);
233 ret = clk_prepare_enable(ahb_clk);
235 pr_err("%s: unable to enable ahb_clk\n", __func__);
239 ret = dsi_get_version(msm_host->ctrl_base, &major, &minor);
241 pr_err("%s: Invalid version\n", __func__);
245 cfg_hnd = msm_dsi_cfg_get(major, minor);
247 DBG("%s: Version %x:%x\n", __func__, major, minor);
250 clk_disable_unprepare(ahb_clk);
252 regulator_disable(gdsc_reg);
253 pm_runtime_put_sync(dev);
255 regulator_put(gdsc_reg);
260 static inline struct msm_dsi_host *to_msm_dsi_host(struct mipi_dsi_host *host)
262 return container_of(host, struct msm_dsi_host, base);
265 static void dsi_host_regulator_disable(struct msm_dsi_host *msm_host)
267 struct regulator_bulk_data *s = msm_host->supplies;
268 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs;
269 int num = msm_host->cfg_hnd->cfg->reg_cfg.num;
273 for (i = num - 1; i >= 0; i--)
274 if (regs[i].disable_load >= 0)
275 regulator_set_load(s[i].consumer,
276 regs[i].disable_load);
278 regulator_bulk_disable(num, s);
281 static int dsi_host_regulator_enable(struct msm_dsi_host *msm_host)
283 struct regulator_bulk_data *s = msm_host->supplies;
284 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs;
285 int num = msm_host->cfg_hnd->cfg->reg_cfg.num;
289 for (i = 0; i < num; i++) {
290 if (regs[i].enable_load >= 0) {
291 ret = regulator_set_load(s[i].consumer,
292 regs[i].enable_load);
294 pr_err("regulator %d set op mode failed, %d\n",
301 ret = regulator_bulk_enable(num, s);
303 pr_err("regulator enable failed, %d\n", ret);
310 for (i--; i >= 0; i--)
311 regulator_set_load(s[i].consumer, regs[i].disable_load);
315 static int dsi_regulator_init(struct msm_dsi_host *msm_host)
317 struct regulator_bulk_data *s = msm_host->supplies;
318 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs;
319 int num = msm_host->cfg_hnd->cfg->reg_cfg.num;
322 for (i = 0; i < num; i++)
323 s[i].supply = regs[i].name;
325 ret = devm_regulator_bulk_get(&msm_host->pdev->dev, num, s);
327 pr_err("%s: failed to init regulator, ret=%d\n",
335 static int dsi_clk_init(struct msm_dsi_host *msm_host)
337 struct platform_device *pdev = msm_host->pdev;
338 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
339 const struct msm_dsi_config *cfg = cfg_hnd->cfg;
343 for (i = 0; i < cfg->num_bus_clks; i++) {
344 msm_host->bus_clks[i] = msm_clk_get(pdev,
345 cfg->bus_clk_names[i]);
346 if (IS_ERR(msm_host->bus_clks[i])) {
347 ret = PTR_ERR(msm_host->bus_clks[i]);
348 pr_err("%s: Unable to get %s clock, ret = %d\n",
349 __func__, cfg->bus_clk_names[i], ret);
354 /* get link and source clocks */
355 msm_host->byte_clk = msm_clk_get(pdev, "byte");
356 if (IS_ERR(msm_host->byte_clk)) {
357 ret = PTR_ERR(msm_host->byte_clk);
358 pr_err("%s: can't find dsi_byte clock. ret=%d\n",
360 msm_host->byte_clk = NULL;
364 msm_host->pixel_clk = msm_clk_get(pdev, "pixel");
365 if (IS_ERR(msm_host->pixel_clk)) {
366 ret = PTR_ERR(msm_host->pixel_clk);
367 pr_err("%s: can't find dsi_pixel clock. ret=%d\n",
369 msm_host->pixel_clk = NULL;
373 msm_host->esc_clk = msm_clk_get(pdev, "core");
374 if (IS_ERR(msm_host->esc_clk)) {
375 ret = PTR_ERR(msm_host->esc_clk);
376 pr_err("%s: can't find dsi_esc clock. ret=%d\n",
378 msm_host->esc_clk = NULL;
382 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G &&
383 cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V2_2_1) {
384 msm_host->byte_intf_clk = msm_clk_get(pdev, "byte_intf");
385 if (IS_ERR(msm_host->byte_intf_clk)) {
386 ret = PTR_ERR(msm_host->byte_intf_clk);
387 pr_err("%s: can't find byte_intf clock. ret=%d\n",
392 msm_host->byte_intf_clk = NULL;
395 msm_host->byte_clk_src = clk_get_parent(msm_host->byte_clk);
396 if (!msm_host->byte_clk_src) {
398 pr_err("%s: can't find byte_clk clock. ret=%d\n", __func__, ret);
402 msm_host->pixel_clk_src = clk_get_parent(msm_host->pixel_clk);
403 if (!msm_host->pixel_clk_src) {
405 pr_err("%s: can't find pixel_clk clock. ret=%d\n", __func__, ret);
409 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_V2) {
410 msm_host->src_clk = msm_clk_get(pdev, "src");
411 if (IS_ERR(msm_host->src_clk)) {
412 ret = PTR_ERR(msm_host->src_clk);
413 pr_err("%s: can't find src clock. ret=%d\n",
415 msm_host->src_clk = NULL;
419 msm_host->esc_clk_src = clk_get_parent(msm_host->esc_clk);
420 if (!msm_host->esc_clk_src) {
422 pr_err("%s: can't get esc clock parent. ret=%d\n",
427 msm_host->dsi_clk_src = clk_get_parent(msm_host->src_clk);
428 if (!msm_host->dsi_clk_src) {
430 pr_err("%s: can't get src clock parent. ret=%d\n",
438 static int dsi_bus_clk_enable(struct msm_dsi_host *msm_host)
440 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg;
443 DBG("id=%d", msm_host->id);
445 for (i = 0; i < cfg->num_bus_clks; i++) {
446 ret = clk_prepare_enable(msm_host->bus_clks[i]);
448 pr_err("%s: failed to enable bus clock %d ret %d\n",
457 clk_disable_unprepare(msm_host->bus_clks[i]);
462 static void dsi_bus_clk_disable(struct msm_dsi_host *msm_host)
464 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg;
469 for (i = cfg->num_bus_clks - 1; i >= 0; i--)
470 clk_disable_unprepare(msm_host->bus_clks[i]);
473 int msm_dsi_runtime_suspend(struct device *dev)
475 struct platform_device *pdev = to_platform_device(dev);
476 struct msm_dsi *msm_dsi = platform_get_drvdata(pdev);
477 struct mipi_dsi_host *host = msm_dsi->host;
478 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
480 if (!msm_host->cfg_hnd)
483 dsi_bus_clk_disable(msm_host);
488 int msm_dsi_runtime_resume(struct device *dev)
490 struct platform_device *pdev = to_platform_device(dev);
491 struct msm_dsi *msm_dsi = platform_get_drvdata(pdev);
492 struct mipi_dsi_host *host = msm_dsi->host;
493 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
495 if (!msm_host->cfg_hnd)
498 return dsi_bus_clk_enable(msm_host);
501 static int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host)
505 DBG("Set clk rates: pclk=%d, byteclk=%d",
506 msm_host->mode->clock, msm_host->byte_clk_rate);
508 ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate);
510 pr_err("%s: Failed to set rate byte clk, %d\n", __func__, ret);
514 ret = clk_set_rate(msm_host->pixel_clk, msm_host->mode->clock * 1000);
516 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret);
520 if (msm_host->byte_intf_clk) {
521 ret = clk_set_rate(msm_host->byte_intf_clk,
522 msm_host->byte_clk_rate / 2);
524 pr_err("%s: Failed to set rate byte intf clk, %d\n",
530 ret = clk_prepare_enable(msm_host->esc_clk);
532 pr_err("%s: Failed to enable dsi esc clk\n", __func__);
536 ret = clk_prepare_enable(msm_host->byte_clk);
538 pr_err("%s: Failed to enable dsi byte clk\n", __func__);
542 ret = clk_prepare_enable(msm_host->pixel_clk);
544 pr_err("%s: Failed to enable dsi pixel clk\n", __func__);
548 if (msm_host->byte_intf_clk) {
549 ret = clk_prepare_enable(msm_host->byte_intf_clk);
551 pr_err("%s: Failed to enable byte intf clk\n",
553 goto byte_intf_clk_err;
560 clk_disable_unprepare(msm_host->pixel_clk);
562 clk_disable_unprepare(msm_host->byte_clk);
564 clk_disable_unprepare(msm_host->esc_clk);
569 static int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host)
573 DBG("Set clk rates: pclk=%d, byteclk=%d, esc_clk=%d, dsi_src_clk=%d",
574 msm_host->mode->clock, msm_host->byte_clk_rate,
575 msm_host->esc_clk_rate, msm_host->src_clk_rate);
577 ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate);
579 pr_err("%s: Failed to set rate byte clk, %d\n", __func__, ret);
583 ret = clk_set_rate(msm_host->esc_clk, msm_host->esc_clk_rate);
585 pr_err("%s: Failed to set rate esc clk, %d\n", __func__, ret);
589 ret = clk_set_rate(msm_host->src_clk, msm_host->src_clk_rate);
591 pr_err("%s: Failed to set rate src clk, %d\n", __func__, ret);
595 ret = clk_set_rate(msm_host->pixel_clk, msm_host->mode->clock * 1000);
597 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret);
601 ret = clk_prepare_enable(msm_host->byte_clk);
603 pr_err("%s: Failed to enable dsi byte clk\n", __func__);
607 ret = clk_prepare_enable(msm_host->esc_clk);
609 pr_err("%s: Failed to enable dsi esc clk\n", __func__);
613 ret = clk_prepare_enable(msm_host->src_clk);
615 pr_err("%s: Failed to enable dsi src clk\n", __func__);
619 ret = clk_prepare_enable(msm_host->pixel_clk);
621 pr_err("%s: Failed to enable dsi pixel clk\n", __func__);
628 clk_disable_unprepare(msm_host->src_clk);
630 clk_disable_unprepare(msm_host->esc_clk);
632 clk_disable_unprepare(msm_host->byte_clk);
637 static int dsi_link_clk_enable(struct msm_dsi_host *msm_host)
639 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
641 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G)
642 return dsi_link_clk_enable_6g(msm_host);
644 return dsi_link_clk_enable_v2(msm_host);
647 static void dsi_link_clk_disable(struct msm_dsi_host *msm_host)
649 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
651 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) {
652 clk_disable_unprepare(msm_host->esc_clk);
653 clk_disable_unprepare(msm_host->pixel_clk);
654 if (msm_host->byte_intf_clk)
655 clk_disable_unprepare(msm_host->byte_intf_clk);
656 clk_disable_unprepare(msm_host->byte_clk);
658 clk_disable_unprepare(msm_host->pixel_clk);
659 clk_disable_unprepare(msm_host->src_clk);
660 clk_disable_unprepare(msm_host->esc_clk);
661 clk_disable_unprepare(msm_host->byte_clk);
665 static int dsi_calc_clk_rate(struct msm_dsi_host *msm_host)
667 struct drm_display_mode *mode = msm_host->mode;
668 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
669 u8 lanes = msm_host->lanes;
670 u32 bpp = dsi_get_bpp(msm_host->format);
674 pr_err("%s: mode not set\n", __func__);
678 pclk_rate = mode->clock * 1000;
680 msm_host->byte_clk_rate = (pclk_rate * bpp) / (8 * lanes);
682 pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__);
683 msm_host->byte_clk_rate = (pclk_rate * bpp) / 8;
686 DBG("pclk=%d, bclk=%d", pclk_rate, msm_host->byte_clk_rate);
688 msm_host->esc_clk_rate = clk_get_rate(msm_host->esc_clk);
690 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_V2) {
691 unsigned int esc_mhz, esc_div;
692 unsigned long byte_mhz;
694 msm_host->src_clk_rate = (pclk_rate * bpp) / 8;
697 * esc clock is byte clock followed by a 4 bit divider,
698 * we need to find an escape clock frequency within the
699 * mipi DSI spec range within the maximum divider limit
700 * We iterate here between an escape clock frequencey
701 * between 20 Mhz to 5 Mhz and pick up the first one
702 * that can be supported by our divider
705 byte_mhz = msm_host->byte_clk_rate / 1000000;
707 for (esc_mhz = 20; esc_mhz >= 5; esc_mhz--) {
708 esc_div = DIV_ROUND_UP(byte_mhz, esc_mhz);
711 * TODO: Ideally, we shouldn't know what sort of divider
712 * is available in mmss_cc, we're just assuming that
713 * it'll always be a 4 bit divider. Need to come up with
716 if (esc_div >= 1 && esc_div <= 16)
723 msm_host->esc_clk_rate = msm_host->byte_clk_rate / esc_div;
725 DBG("esc=%d, src=%d", msm_host->esc_clk_rate,
726 msm_host->src_clk_rate);
732 static void dsi_intr_ctrl(struct msm_dsi_host *msm_host, u32 mask, int enable)
737 spin_lock_irqsave(&msm_host->intr_lock, flags);
738 intr = dsi_read(msm_host, REG_DSI_INTR_CTRL);
745 DBG("intr=%x enable=%d", intr, enable);
747 dsi_write(msm_host, REG_DSI_INTR_CTRL, intr);
748 spin_unlock_irqrestore(&msm_host->intr_lock, flags);
751 static inline enum dsi_traffic_mode dsi_get_traffic_mode(const u32 mode_flags)
753 if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
755 else if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
756 return NON_BURST_SYNCH_PULSE;
758 return NON_BURST_SYNCH_EVENT;
761 static inline enum dsi_vid_dst_format dsi_get_vid_fmt(
762 const enum mipi_dsi_pixel_format mipi_fmt)
765 case MIPI_DSI_FMT_RGB888: return VID_DST_FORMAT_RGB888;
766 case MIPI_DSI_FMT_RGB666: return VID_DST_FORMAT_RGB666_LOOSE;
767 case MIPI_DSI_FMT_RGB666_PACKED: return VID_DST_FORMAT_RGB666;
768 case MIPI_DSI_FMT_RGB565: return VID_DST_FORMAT_RGB565;
769 default: return VID_DST_FORMAT_RGB888;
773 static inline enum dsi_cmd_dst_format dsi_get_cmd_fmt(
774 const enum mipi_dsi_pixel_format mipi_fmt)
777 case MIPI_DSI_FMT_RGB888: return CMD_DST_FORMAT_RGB888;
778 case MIPI_DSI_FMT_RGB666_PACKED:
779 case MIPI_DSI_FMT_RGB666: return CMD_DST_FORMAT_RGB666;
780 case MIPI_DSI_FMT_RGB565: return CMD_DST_FORMAT_RGB565;
781 default: return CMD_DST_FORMAT_RGB888;
785 static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable,
786 struct msm_dsi_phy_shared_timings *phy_shared_timings)
788 u32 flags = msm_host->mode_flags;
789 enum mipi_dsi_pixel_format mipi_fmt = msm_host->format;
790 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
794 dsi_write(msm_host, REG_DSI_CTRL, 0);
798 if (flags & MIPI_DSI_MODE_VIDEO) {
799 if (flags & MIPI_DSI_MODE_VIDEO_HSE)
800 data |= DSI_VID_CFG0_PULSE_MODE_HSA_HE;
801 if (flags & MIPI_DSI_MODE_VIDEO_HFP)
802 data |= DSI_VID_CFG0_HFP_POWER_STOP;
803 if (flags & MIPI_DSI_MODE_VIDEO_HBP)
804 data |= DSI_VID_CFG0_HBP_POWER_STOP;
805 if (flags & MIPI_DSI_MODE_VIDEO_HSA)
806 data |= DSI_VID_CFG0_HSA_POWER_STOP;
807 /* Always set low power stop mode for BLLP
808 * to let command engine send packets
810 data |= DSI_VID_CFG0_EOF_BLLP_POWER_STOP |
811 DSI_VID_CFG0_BLLP_POWER_STOP;
812 data |= DSI_VID_CFG0_TRAFFIC_MODE(dsi_get_traffic_mode(flags));
813 data |= DSI_VID_CFG0_DST_FORMAT(dsi_get_vid_fmt(mipi_fmt));
814 data |= DSI_VID_CFG0_VIRT_CHANNEL(msm_host->channel);
815 dsi_write(msm_host, REG_DSI_VID_CFG0, data);
817 /* Do not swap RGB colors */
818 data = DSI_VID_CFG1_RGB_SWAP(SWAP_RGB);
819 dsi_write(msm_host, REG_DSI_VID_CFG1, 0);
821 /* Do not swap RGB colors */
822 data = DSI_CMD_CFG0_RGB_SWAP(SWAP_RGB);
823 data |= DSI_CMD_CFG0_DST_FORMAT(dsi_get_cmd_fmt(mipi_fmt));
824 dsi_write(msm_host, REG_DSI_CMD_CFG0, data);
826 data = DSI_CMD_CFG1_WR_MEM_START(MIPI_DCS_WRITE_MEMORY_START) |
827 DSI_CMD_CFG1_WR_MEM_CONTINUE(
828 MIPI_DCS_WRITE_MEMORY_CONTINUE);
829 /* Always insert DCS command */
830 data |= DSI_CMD_CFG1_INSERT_DCS_COMMAND;
831 dsi_write(msm_host, REG_DSI_CMD_CFG1, data);
834 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL,
835 DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER |
836 DSI_CMD_DMA_CTRL_LOW_POWER);
839 /* Always assume dedicated TE pin */
840 data |= DSI_TRIG_CTRL_TE;
841 data |= DSI_TRIG_CTRL_MDP_TRIGGER(TRIGGER_NONE);
842 data |= DSI_TRIG_CTRL_DMA_TRIGGER(TRIGGER_SW);
843 data |= DSI_TRIG_CTRL_STREAM(msm_host->channel);
844 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) &&
845 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_2))
846 data |= DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME;
847 dsi_write(msm_host, REG_DSI_TRIG_CTRL, data);
849 data = DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(phy_shared_timings->clk_post) |
850 DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(phy_shared_timings->clk_pre);
851 dsi_write(msm_host, REG_DSI_CLKOUT_TIMING_CTRL, data);
853 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) &&
854 (cfg_hnd->minor > MSM_DSI_6G_VER_MINOR_V1_0) &&
855 phy_shared_timings->clk_pre_inc_by_2)
856 dsi_write(msm_host, REG_DSI_T_CLK_PRE_EXTEND,
857 DSI_T_CLK_PRE_EXTEND_INC_BY_2_BYTECLK);
860 if (!(flags & MIPI_DSI_MODE_EOT_PACKET))
861 data |= DSI_EOT_PACKET_CTRL_TX_EOT_APPEND;
862 dsi_write(msm_host, REG_DSI_EOT_PACKET_CTRL, data);
864 /* allow only ack-err-status to generate interrupt */
865 dsi_write(msm_host, REG_DSI_ERR_INT_MASK0, 0x13ff3fe0);
867 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1);
869 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);
871 data = DSI_CTRL_CLK_EN;
873 DBG("lane number=%d", msm_host->lanes);
874 data |= ((DSI_CTRL_LANE0 << msm_host->lanes) - DSI_CTRL_LANE0);
876 dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL,
877 DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(msm_host->dlane_swap));
879 if (!(flags & MIPI_DSI_CLOCK_NON_CONTINUOUS))
880 dsi_write(msm_host, REG_DSI_LANE_CTRL,
881 DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST);
883 data |= DSI_CTRL_ENABLE;
885 dsi_write(msm_host, REG_DSI_CTRL, data);
888 static void dsi_timing_setup(struct msm_dsi_host *msm_host)
890 struct drm_display_mode *mode = msm_host->mode;
891 u32 hs_start = 0, vs_start = 0; /* take sync start as 0 */
892 u32 h_total = mode->htotal;
893 u32 v_total = mode->vtotal;
894 u32 hs_end = mode->hsync_end - mode->hsync_start;
895 u32 vs_end = mode->vsync_end - mode->vsync_start;
896 u32 ha_start = h_total - mode->hsync_start;
897 u32 ha_end = ha_start + mode->hdisplay;
898 u32 va_start = v_total - mode->vsync_start;
899 u32 va_end = va_start + mode->vdisplay;
904 if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) {
905 dsi_write(msm_host, REG_DSI_ACTIVE_H,
906 DSI_ACTIVE_H_START(ha_start) |
907 DSI_ACTIVE_H_END(ha_end));
908 dsi_write(msm_host, REG_DSI_ACTIVE_V,
909 DSI_ACTIVE_V_START(va_start) |
910 DSI_ACTIVE_V_END(va_end));
911 dsi_write(msm_host, REG_DSI_TOTAL,
912 DSI_TOTAL_H_TOTAL(h_total - 1) |
913 DSI_TOTAL_V_TOTAL(v_total - 1));
915 dsi_write(msm_host, REG_DSI_ACTIVE_HSYNC,
916 DSI_ACTIVE_HSYNC_START(hs_start) |
917 DSI_ACTIVE_HSYNC_END(hs_end));
918 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_HPOS, 0);
919 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_VPOS,
920 DSI_ACTIVE_VSYNC_VPOS_START(vs_start) |
921 DSI_ACTIVE_VSYNC_VPOS_END(vs_end));
922 } else { /* command mode */
923 /* image data and 1 byte write_memory_start cmd */
924 wc = mode->hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1;
926 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM_CTRL,
927 DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT(wc) |
928 DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL(
930 DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE(
931 MIPI_DSI_DCS_LONG_WRITE));
933 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM_TOTAL,
934 DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL(mode->hdisplay) |
935 DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL(mode->vdisplay));
939 static void dsi_sw_reset(struct msm_dsi_host *msm_host)
941 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);
942 wmb(); /* clocks need to be enabled before reset */
944 dsi_write(msm_host, REG_DSI_RESET, 1);
945 wmb(); /* make sure reset happen */
946 dsi_write(msm_host, REG_DSI_RESET, 0);
949 static void dsi_op_mode_config(struct msm_dsi_host *msm_host,
950 bool video_mode, bool enable)
954 dsi_ctrl = dsi_read(msm_host, REG_DSI_CTRL);
957 dsi_ctrl &= ~(DSI_CTRL_ENABLE | DSI_CTRL_VID_MODE_EN |
958 DSI_CTRL_CMD_MODE_EN);
959 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE |
960 DSI_IRQ_MASK_VIDEO_DONE, 0);
963 dsi_ctrl |= DSI_CTRL_VID_MODE_EN;
964 } else { /* command mode */
965 dsi_ctrl |= DSI_CTRL_CMD_MODE_EN;
966 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE, 1);
968 dsi_ctrl |= DSI_CTRL_ENABLE;
971 dsi_write(msm_host, REG_DSI_CTRL, dsi_ctrl);
974 static void dsi_set_tx_power_mode(int mode, struct msm_dsi_host *msm_host)
978 data = dsi_read(msm_host, REG_DSI_CMD_DMA_CTRL);
981 data &= ~DSI_CMD_DMA_CTRL_LOW_POWER;
983 data |= DSI_CMD_DMA_CTRL_LOW_POWER;
985 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, data);
988 static void dsi_wait4video_done(struct msm_dsi_host *msm_host)
991 struct device *dev = &msm_host->pdev->dev;
993 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 1);
995 reinit_completion(&msm_host->video_comp);
997 ret = wait_for_completion_timeout(&msm_host->video_comp,
998 msecs_to_jiffies(70));
1001 dev_err(dev, "wait for video done timed out\n");
1003 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 0);
1006 static void dsi_wait4video_eng_busy(struct msm_dsi_host *msm_host)
1008 if (!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO))
1011 if (msm_host->power_on && msm_host->enabled) {
1012 dsi_wait4video_done(msm_host);
1013 /* delay 4 ms to skip BLLP */
1014 usleep_range(2000, 4000);
1019 static int dsi_tx_buf_alloc(struct msm_dsi_host *msm_host, int size)
1021 struct drm_device *dev = msm_host->dev;
1022 struct msm_drm_private *priv = dev->dev_private;
1023 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
1027 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) {
1028 msm_host->tx_gem_obj = msm_gem_new(dev, size, MSM_BO_UNCACHED);
1029 if (IS_ERR(msm_host->tx_gem_obj)) {
1030 ret = PTR_ERR(msm_host->tx_gem_obj);
1031 pr_err("%s: failed to allocate gem, %d\n",
1033 msm_host->tx_gem_obj = NULL;
1037 ret = msm_gem_get_iova(msm_host->tx_gem_obj,
1038 priv->kms->aspace, &iova);
1039 mutex_unlock(&dev->struct_mutex);
1041 pr_err("%s: failed to get iova, %d\n", __func__, ret);
1046 pr_err("%s: buf NOT 8 bytes aligned\n", __func__);
1050 msm_host->tx_size = msm_host->tx_gem_obj->size;
1052 msm_host->tx_buf = dma_alloc_coherent(dev->dev, size,
1053 &msm_host->tx_buf_paddr, GFP_KERNEL);
1054 if (!msm_host->tx_buf) {
1056 pr_err("%s: failed to allocate tx buf, %d\n",
1061 msm_host->tx_size = size;
1067 static void dsi_tx_buf_free(struct msm_dsi_host *msm_host)
1069 struct drm_device *dev = msm_host->dev;
1071 if (msm_host->tx_gem_obj) {
1072 msm_gem_put_iova(msm_host->tx_gem_obj, 0);
1073 drm_gem_object_put_unlocked(msm_host->tx_gem_obj);
1074 msm_host->tx_gem_obj = NULL;
1077 if (msm_host->tx_buf)
1078 dma_free_coherent(dev->dev, msm_host->tx_size, msm_host->tx_buf,
1079 msm_host->tx_buf_paddr);
1083 * prepare cmd buffer to be txed
1085 static int dsi_cmd_dma_add(struct msm_dsi_host *msm_host,
1086 const struct mipi_dsi_msg *msg)
1088 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
1089 struct mipi_dsi_packet packet;
1094 ret = mipi_dsi_create_packet(&packet, msg);
1096 pr_err("%s: create packet failed, %d\n", __func__, ret);
1099 len = (packet.size + 3) & (~0x3);
1101 if (len > msm_host->tx_size) {
1102 pr_err("%s: packet size is too big\n", __func__);
1106 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) {
1107 data = msm_gem_get_vaddr(msm_host->tx_gem_obj);
1109 ret = PTR_ERR(data);
1110 pr_err("%s: get vaddr failed, %d\n", __func__, ret);
1114 data = msm_host->tx_buf;
1117 /* MSM specific command format in memory */
1118 data[0] = packet.header[1];
1119 data[1] = packet.header[2];
1120 data[2] = packet.header[0];
1121 data[3] = BIT(7); /* Last packet */
1122 if (mipi_dsi_packet_format_is_long(msg->type))
1124 if (msg->rx_buf && msg->rx_len)
1128 if (packet.payload && packet.payload_length)
1129 memcpy(data + 4, packet.payload, packet.payload_length);
1131 /* Append 0xff to the end */
1132 if (packet.size < len)
1133 memset(data + packet.size, 0xff, len - packet.size);
1135 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G)
1136 msm_gem_put_vaddr(msm_host->tx_gem_obj);
1142 * dsi_short_read1_resp: 1 parameter
1144 static int dsi_short_read1_resp(u8 *buf, const struct mipi_dsi_msg *msg)
1146 u8 *data = msg->rx_buf;
1147 if (data && (msg->rx_len >= 1)) {
1148 *data = buf[1]; /* strip out dcs type */
1151 pr_err("%s: read data does not match with rx_buf len %zu\n",
1152 __func__, msg->rx_len);
1158 * dsi_short_read2_resp: 2 parameter
1160 static int dsi_short_read2_resp(u8 *buf, const struct mipi_dsi_msg *msg)
1162 u8 *data = msg->rx_buf;
1163 if (data && (msg->rx_len >= 2)) {
1164 data[0] = buf[1]; /* strip out dcs type */
1168 pr_err("%s: read data does not match with rx_buf len %zu\n",
1169 __func__, msg->rx_len);
1174 static int dsi_long_read_resp(u8 *buf, const struct mipi_dsi_msg *msg)
1176 /* strip out 4 byte dcs header */
1177 if (msg->rx_buf && msg->rx_len)
1178 memcpy(msg->rx_buf, buf + 4, msg->rx_len);
1183 static int dsi_cmd_dma_tx(struct msm_dsi_host *msm_host, int len)
1185 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
1186 struct drm_device *dev = msm_host->dev;
1187 struct msm_drm_private *priv = dev->dev_private;
1192 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) {
1193 ret = msm_gem_get_iova(msm_host->tx_gem_obj,
1194 priv->kms->aspace, &dma_base);
1196 pr_err("%s: failed to get iova: %d\n", __func__, ret);
1200 dma_base = msm_host->tx_buf_paddr;
1203 reinit_completion(&msm_host->dma_comp);
1205 dsi_wait4video_eng_busy(msm_host);
1207 triggered = msm_dsi_manager_cmd_xfer_trigger(
1208 msm_host->id, dma_base, len);
1210 ret = wait_for_completion_timeout(&msm_host->dma_comp,
1211 msecs_to_jiffies(200));
1223 static int dsi_cmd_dma_rx(struct msm_dsi_host *msm_host,
1224 u8 *buf, int rx_byte, int pkt_size)
1226 u32 *lp, *temp, data;
1230 int repeated_bytes = 0;
1231 int buf_offset = buf - msm_host->rx_buf;
1235 cnt = (rx_byte + 3) >> 2;
1237 cnt = 4; /* 4 x 32 bits registers only */
1242 read_cnt = pkt_size + 6;
1245 * In case of multiple reads from the panel, after the first read, there
1246 * is possibility that there are some bytes in the payload repeating in
1247 * the RDBK_DATA registers. Since we read all the parameters from the
1248 * panel right from the first byte for every pass. We need to skip the
1249 * repeating bytes and then append the new parameters to the rx buffer.
1251 if (read_cnt > 16) {
1253 /* Any data more than 16 bytes will be shifted out.
1254 * The temp read buffer should already contain these bytes.
1255 * The remaining bytes in read buffer are the repeated bytes.
1257 bytes_shifted = read_cnt - 16;
1258 repeated_bytes = buf_offset - bytes_shifted;
1261 for (i = cnt - 1; i >= 0; i--) {
1262 data = dsi_read(msm_host, REG_DSI_RDBK_DATA(i));
1263 *temp++ = ntohl(data); /* to host byte order */
1264 DBG("data = 0x%x and ntohl(data) = 0x%x", data, ntohl(data));
1267 for (i = repeated_bytes; i < 16; i++)
1273 static int dsi_cmds2buf_tx(struct msm_dsi_host *msm_host,
1274 const struct mipi_dsi_msg *msg)
1277 int bllp_len = msm_host->mode->hdisplay *
1278 dsi_get_bpp(msm_host->format) / 8;
1280 len = dsi_cmd_dma_add(msm_host, msg);
1282 pr_err("%s: failed to add cmd type = 0x%x\n",
1283 __func__, msg->type);
1287 /* for video mode, do not send cmds more than
1288 * one pixel line, since it only transmit it
1291 /* TODO: if the command is sent in LP mode, the bit rate is only
1292 * half of esc clk rate. In this case, if the video is already
1293 * actively streaming, we need to check more carefully if the
1294 * command can be fit into one BLLP.
1296 if ((msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) && (len > bllp_len)) {
1297 pr_err("%s: cmd cannot fit into BLLP period, len=%d\n",
1302 ret = dsi_cmd_dma_tx(msm_host, len);
1304 pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, len=%d\n",
1305 __func__, msg->type, (*(u8 *)(msg->tx_buf)), len);
1312 static void dsi_sw_reset_restore(struct msm_dsi_host *msm_host)
1316 data0 = dsi_read(msm_host, REG_DSI_CTRL);
1318 data1 &= ~DSI_CTRL_ENABLE;
1319 dsi_write(msm_host, REG_DSI_CTRL, data1);
1321 * dsi controller need to be disabled before
1326 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);
1327 wmb(); /* make sure clocks enabled */
1329 /* dsi controller can only be reset while clocks are running */
1330 dsi_write(msm_host, REG_DSI_RESET, 1);
1331 wmb(); /* make sure reset happen */
1332 dsi_write(msm_host, REG_DSI_RESET, 0);
1333 wmb(); /* controller out of reset */
1334 dsi_write(msm_host, REG_DSI_CTRL, data0);
1335 wmb(); /* make sure dsi controller enabled again */
1338 static void dsi_hpd_worker(struct work_struct *work)
1340 struct msm_dsi_host *msm_host =
1341 container_of(work, struct msm_dsi_host, hpd_work);
1343 drm_helper_hpd_irq_event(msm_host->dev);
1346 static void dsi_err_worker(struct work_struct *work)
1348 struct msm_dsi_host *msm_host =
1349 container_of(work, struct msm_dsi_host, err_work);
1350 u32 status = msm_host->err_work_state;
1352 pr_err_ratelimited("%s: status=%x\n", __func__, status);
1353 if (status & DSI_ERR_STATE_MDP_FIFO_UNDERFLOW)
1354 dsi_sw_reset_restore(msm_host);
1356 /* It is safe to clear here because error irq is disabled. */
1357 msm_host->err_work_state = 0;
1359 /* enable dsi error interrupt */
1360 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1);
1363 static void dsi_ack_err_status(struct msm_dsi_host *msm_host)
1367 status = dsi_read(msm_host, REG_DSI_ACK_ERR_STATUS);
1370 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, status);
1371 /* Writing of an extra 0 needed to clear error bits */
1372 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, 0);
1373 msm_host->err_work_state |= DSI_ERR_STATE_ACK;
1377 static void dsi_timeout_status(struct msm_dsi_host *msm_host)
1381 status = dsi_read(msm_host, REG_DSI_TIMEOUT_STATUS);
1384 dsi_write(msm_host, REG_DSI_TIMEOUT_STATUS, status);
1385 msm_host->err_work_state |= DSI_ERR_STATE_TIMEOUT;
1389 static void dsi_dln0_phy_err(struct msm_dsi_host *msm_host)
1393 status = dsi_read(msm_host, REG_DSI_DLN0_PHY_ERR);
1395 if (status & (DSI_DLN0_PHY_ERR_DLN0_ERR_ESC |
1396 DSI_DLN0_PHY_ERR_DLN0_ERR_SYNC_ESC |
1397 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTROL |
1398 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0 |
1399 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1)) {
1400 dsi_write(msm_host, REG_DSI_DLN0_PHY_ERR, status);
1401 msm_host->err_work_state |= DSI_ERR_STATE_DLN0_PHY;
1405 static void dsi_fifo_status(struct msm_dsi_host *msm_host)
1409 status = dsi_read(msm_host, REG_DSI_FIFO_STATUS);
1411 /* fifo underflow, overflow */
1413 dsi_write(msm_host, REG_DSI_FIFO_STATUS, status);
1414 msm_host->err_work_state |= DSI_ERR_STATE_FIFO;
1415 if (status & DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW)
1416 msm_host->err_work_state |=
1417 DSI_ERR_STATE_MDP_FIFO_UNDERFLOW;
1421 static void dsi_status(struct msm_dsi_host *msm_host)
1425 status = dsi_read(msm_host, REG_DSI_STATUS0);
1427 if (status & DSI_STATUS0_INTERLEAVE_OP_CONTENTION) {
1428 dsi_write(msm_host, REG_DSI_STATUS0, status);
1429 msm_host->err_work_state |=
1430 DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION;
1434 static void dsi_clk_status(struct msm_dsi_host *msm_host)
1438 status = dsi_read(msm_host, REG_DSI_CLK_STATUS);
1440 if (status & DSI_CLK_STATUS_PLL_UNLOCKED) {
1441 dsi_write(msm_host, REG_DSI_CLK_STATUS, status);
1442 msm_host->err_work_state |= DSI_ERR_STATE_PLL_UNLOCKED;
1446 static void dsi_error(struct msm_dsi_host *msm_host)
1448 /* disable dsi error interrupt */
1449 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 0);
1451 dsi_clk_status(msm_host);
1452 dsi_fifo_status(msm_host);
1453 dsi_ack_err_status(msm_host);
1454 dsi_timeout_status(msm_host);
1455 dsi_status(msm_host);
1456 dsi_dln0_phy_err(msm_host);
1458 queue_work(msm_host->workqueue, &msm_host->err_work);
1461 static irqreturn_t dsi_host_irq(int irq, void *ptr)
1463 struct msm_dsi_host *msm_host = ptr;
1465 unsigned long flags;
1467 if (!msm_host->ctrl_base)
1470 spin_lock_irqsave(&msm_host->intr_lock, flags);
1471 isr = dsi_read(msm_host, REG_DSI_INTR_CTRL);
1472 dsi_write(msm_host, REG_DSI_INTR_CTRL, isr);
1473 spin_unlock_irqrestore(&msm_host->intr_lock, flags);
1475 DBG("isr=0x%x, id=%d", isr, msm_host->id);
1477 if (isr & DSI_IRQ_ERROR)
1478 dsi_error(msm_host);
1480 if (isr & DSI_IRQ_VIDEO_DONE)
1481 complete(&msm_host->video_comp);
1483 if (isr & DSI_IRQ_CMD_DMA_DONE)
1484 complete(&msm_host->dma_comp);
1489 static int dsi_host_init_panel_gpios(struct msm_dsi_host *msm_host,
1490 struct device *panel_device)
1492 msm_host->disp_en_gpio = devm_gpiod_get_optional(panel_device,
1495 if (IS_ERR(msm_host->disp_en_gpio)) {
1496 DBG("cannot get disp-enable-gpios %ld",
1497 PTR_ERR(msm_host->disp_en_gpio));
1498 return PTR_ERR(msm_host->disp_en_gpio);
1501 msm_host->te_gpio = devm_gpiod_get_optional(panel_device, "disp-te",
1503 if (IS_ERR(msm_host->te_gpio)) {
1504 DBG("cannot get disp-te-gpios %ld", PTR_ERR(msm_host->te_gpio));
1505 return PTR_ERR(msm_host->te_gpio);
1511 static int dsi_host_attach(struct mipi_dsi_host *host,
1512 struct mipi_dsi_device *dsi)
1514 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1517 if (dsi->lanes > msm_host->num_data_lanes)
1520 msm_host->channel = dsi->channel;
1521 msm_host->lanes = dsi->lanes;
1522 msm_host->format = dsi->format;
1523 msm_host->mode_flags = dsi->mode_flags;
1525 msm_dsi_manager_attach_dsi_device(msm_host->id, dsi->mode_flags);
1527 /* Some gpios defined in panel DT need to be controlled by host */
1528 ret = dsi_host_init_panel_gpios(msm_host, &dsi->dev);
1532 DBG("id=%d", msm_host->id);
1534 queue_work(msm_host->workqueue, &msm_host->hpd_work);
1539 static int dsi_host_detach(struct mipi_dsi_host *host,
1540 struct mipi_dsi_device *dsi)
1542 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1544 msm_host->device_node = NULL;
1546 DBG("id=%d", msm_host->id);
1548 queue_work(msm_host->workqueue, &msm_host->hpd_work);
1553 static ssize_t dsi_host_transfer(struct mipi_dsi_host *host,
1554 const struct mipi_dsi_msg *msg)
1556 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1559 if (!msg || !msm_host->power_on)
1562 mutex_lock(&msm_host->cmd_mutex);
1563 ret = msm_dsi_manager_cmd_xfer(msm_host->id, msg);
1564 mutex_unlock(&msm_host->cmd_mutex);
1569 static struct mipi_dsi_host_ops dsi_host_ops = {
1570 .attach = dsi_host_attach,
1571 .detach = dsi_host_detach,
1572 .transfer = dsi_host_transfer,
1576 * List of supported physical to logical lane mappings.
1577 * For example, the 2nd entry represents the following mapping:
1579 * "3012": Logic 3->Phys 0; Logic 0->Phys 1; Logic 1->Phys 2; Logic 2->Phys 3;
1581 static const int supported_data_lane_swaps[][4] = {
1592 static int dsi_host_parse_lane_data(struct msm_dsi_host *msm_host,
1593 struct device_node *ep)
1595 struct device *dev = &msm_host->pdev->dev;
1596 struct property *prop;
1598 int ret, i, len, num_lanes;
1600 prop = of_find_property(ep, "data-lanes", &len);
1603 "failed to find data lane mapping, using default\n");
1607 num_lanes = len / sizeof(u32);
1609 if (num_lanes < 1 || num_lanes > 4) {
1610 dev_err(dev, "bad number of data lanes\n");
1614 msm_host->num_data_lanes = num_lanes;
1616 ret = of_property_read_u32_array(ep, "data-lanes", lane_map,
1619 dev_err(dev, "failed to read lane data\n");
1624 * compare DT specified physical-logical lane mappings with the ones
1625 * supported by hardware
1627 for (i = 0; i < ARRAY_SIZE(supported_data_lane_swaps); i++) {
1628 const int *swap = supported_data_lane_swaps[i];
1632 * the data-lanes array we get from DT has a logical->physical
1633 * mapping. The "data lane swap" register field represents
1634 * supported configurations in a physical->logical mapping.
1635 * Translate the DT mapping to what we understand and find a
1636 * configuration that works.
1638 for (j = 0; j < num_lanes; j++) {
1639 if (lane_map[j] < 0 || lane_map[j] > 3)
1640 dev_err(dev, "bad physical lane entry %u\n",
1643 if (swap[lane_map[j]] != j)
1647 if (j == num_lanes) {
1648 msm_host->dlane_swap = i;
1656 static int dsi_host_parse_dt(struct msm_dsi_host *msm_host)
1658 struct device *dev = &msm_host->pdev->dev;
1659 struct device_node *np = dev->of_node;
1660 struct device_node *endpoint, *device_node;
1664 * Get the endpoint of the output port of the DSI host. In our case,
1665 * this is mapped to port number with reg = 1. Don't return an error if
1666 * the remote endpoint isn't defined. It's possible that there is
1667 * nothing connected to the dsi output.
1669 endpoint = of_graph_get_endpoint_by_regs(np, 1, -1);
1671 dev_dbg(dev, "%s: no endpoint\n", __func__);
1675 ret = dsi_host_parse_lane_data(msm_host, endpoint);
1677 dev_err(dev, "%s: invalid lane configuration %d\n",
1682 /* Get panel node from the output port's endpoint data */
1683 device_node = of_graph_get_remote_node(np, 1, 0);
1685 dev_dbg(dev, "%s: no valid device\n", __func__);
1689 msm_host->device_node = device_node;
1691 if (of_property_read_bool(np, "syscon-sfpb")) {
1692 msm_host->sfpb = syscon_regmap_lookup_by_phandle(np,
1694 if (IS_ERR(msm_host->sfpb)) {
1695 dev_err(dev, "%s: failed to get sfpb regmap\n",
1697 ret = PTR_ERR(msm_host->sfpb);
1701 of_node_put(device_node);
1704 of_node_put(endpoint);
1709 static int dsi_host_get_id(struct msm_dsi_host *msm_host)
1711 struct platform_device *pdev = msm_host->pdev;
1712 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg;
1713 struct resource *res;
1716 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dsi_ctrl");
1720 for (i = 0; i < cfg->num_dsi; i++) {
1721 if (cfg->io_start[i] == res->start)
1728 int msm_dsi_host_init(struct msm_dsi *msm_dsi)
1730 struct msm_dsi_host *msm_host = NULL;
1731 struct platform_device *pdev = msm_dsi->pdev;
1734 msm_host = devm_kzalloc(&pdev->dev, sizeof(*msm_host), GFP_KERNEL);
1736 pr_err("%s: FAILED: cannot alloc dsi host\n",
1742 msm_host->pdev = pdev;
1743 msm_dsi->host = &msm_host->base;
1745 ret = dsi_host_parse_dt(msm_host);
1747 pr_err("%s: failed to parse dt\n", __func__);
1751 msm_host->ctrl_base = msm_ioremap(pdev, "dsi_ctrl", "DSI CTRL");
1752 if (IS_ERR(msm_host->ctrl_base)) {
1753 pr_err("%s: unable to map Dsi ctrl base\n", __func__);
1754 ret = PTR_ERR(msm_host->ctrl_base);
1758 pm_runtime_enable(&pdev->dev);
1760 msm_host->cfg_hnd = dsi_get_config(msm_host);
1761 if (!msm_host->cfg_hnd) {
1763 pr_err("%s: get config failed\n", __func__);
1767 msm_host->id = dsi_host_get_id(msm_host);
1768 if (msm_host->id < 0) {
1770 pr_err("%s: unable to identify DSI host index\n", __func__);
1774 /* fixup base address by io offset */
1775 msm_host->ctrl_base += msm_host->cfg_hnd->cfg->io_offset;
1777 ret = dsi_regulator_init(msm_host);
1779 pr_err("%s: regulator init failed\n", __func__);
1783 ret = dsi_clk_init(msm_host);
1785 pr_err("%s: unable to initialize dsi clks\n", __func__);
1789 msm_host->rx_buf = devm_kzalloc(&pdev->dev, SZ_4K, GFP_KERNEL);
1790 if (!msm_host->rx_buf) {
1792 pr_err("%s: alloc rx temp buf failed\n", __func__);
1796 init_completion(&msm_host->dma_comp);
1797 init_completion(&msm_host->video_comp);
1798 mutex_init(&msm_host->dev_mutex);
1799 mutex_init(&msm_host->cmd_mutex);
1800 spin_lock_init(&msm_host->intr_lock);
1802 /* setup workqueue */
1803 msm_host->workqueue = alloc_ordered_workqueue("dsi_drm_work", 0);
1804 INIT_WORK(&msm_host->err_work, dsi_err_worker);
1805 INIT_WORK(&msm_host->hpd_work, dsi_hpd_worker);
1807 msm_dsi->id = msm_host->id;
1809 DBG("Dsi Host %d initialized", msm_host->id);
1816 void msm_dsi_host_destroy(struct mipi_dsi_host *host)
1818 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1821 dsi_tx_buf_free(msm_host);
1822 if (msm_host->workqueue) {
1823 flush_workqueue(msm_host->workqueue);
1824 destroy_workqueue(msm_host->workqueue);
1825 msm_host->workqueue = NULL;
1828 mutex_destroy(&msm_host->cmd_mutex);
1829 mutex_destroy(&msm_host->dev_mutex);
1831 pm_runtime_disable(&msm_host->pdev->dev);
1834 int msm_dsi_host_modeset_init(struct mipi_dsi_host *host,
1835 struct drm_device *dev)
1837 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1838 struct platform_device *pdev = msm_host->pdev;
1841 msm_host->irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
1842 if (msm_host->irq < 0) {
1843 ret = msm_host->irq;
1844 dev_err(dev->dev, "failed to get irq: %d\n", ret);
1848 ret = devm_request_irq(&pdev->dev, msm_host->irq,
1849 dsi_host_irq, IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
1850 "dsi_isr", msm_host);
1852 dev_err(&pdev->dev, "failed to request IRQ%u: %d\n",
1853 msm_host->irq, ret);
1857 msm_host->dev = dev;
1858 ret = dsi_tx_buf_alloc(msm_host, SZ_4K);
1860 pr_err("%s: alloc tx gem obj failed, %d\n", __func__, ret);
1867 int msm_dsi_host_register(struct mipi_dsi_host *host, bool check_defer)
1869 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1872 /* Register mipi dsi host */
1873 if (!msm_host->registered) {
1874 host->dev = &msm_host->pdev->dev;
1875 host->ops = &dsi_host_ops;
1876 ret = mipi_dsi_host_register(host);
1880 msm_host->registered = true;
1882 /* If the panel driver has not been probed after host register,
1883 * we should defer the host's probe.
1884 * It makes sure panel is connected when fbcon detects
1885 * connector status and gets the proper display mode to
1886 * create framebuffer.
1887 * Don't try to defer if there is nothing connected to the dsi
1890 if (check_defer && msm_host->device_node) {
1891 if (!of_drm_find_panel(msm_host->device_node))
1892 if (!of_drm_find_bridge(msm_host->device_node))
1893 return -EPROBE_DEFER;
1900 void msm_dsi_host_unregister(struct mipi_dsi_host *host)
1902 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1904 if (msm_host->registered) {
1905 mipi_dsi_host_unregister(host);
1908 msm_host->registered = false;
1912 int msm_dsi_host_xfer_prepare(struct mipi_dsi_host *host,
1913 const struct mipi_dsi_msg *msg)
1915 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1917 /* TODO: make sure dsi_cmd_mdp is idle.
1918 * Since DSI6G v1.2.0, we can set DSI_TRIG_CTRL.BLOCK_DMA_WITHIN_FRAME
1919 * to ask H/W to wait until cmd mdp is idle. S/W wait is not needed.
1920 * How to handle the old versions? Wait for mdp cmd done?
1924 * mdss interrupt is generated in mdp core clock domain
1925 * mdp clock need to be enabled to receive dsi interrupt
1927 pm_runtime_get_sync(&msm_host->pdev->dev);
1928 dsi_link_clk_enable(msm_host);
1930 /* TODO: vote for bus bandwidth */
1932 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM))
1933 dsi_set_tx_power_mode(0, msm_host);
1935 msm_host->dma_cmd_ctrl_restore = dsi_read(msm_host, REG_DSI_CTRL);
1936 dsi_write(msm_host, REG_DSI_CTRL,
1937 msm_host->dma_cmd_ctrl_restore |
1938 DSI_CTRL_CMD_MODE_EN |
1940 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 1);
1945 void msm_dsi_host_xfer_restore(struct mipi_dsi_host *host,
1946 const struct mipi_dsi_msg *msg)
1948 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1950 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 0);
1951 dsi_write(msm_host, REG_DSI_CTRL, msm_host->dma_cmd_ctrl_restore);
1953 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM))
1954 dsi_set_tx_power_mode(1, msm_host);
1956 /* TODO: unvote for bus bandwidth */
1958 dsi_link_clk_disable(msm_host);
1959 pm_runtime_put_autosuspend(&msm_host->pdev->dev);
1962 int msm_dsi_host_cmd_tx(struct mipi_dsi_host *host,
1963 const struct mipi_dsi_msg *msg)
1965 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1967 return dsi_cmds2buf_tx(msm_host, msg);
1970 int msm_dsi_host_cmd_rx(struct mipi_dsi_host *host,
1971 const struct mipi_dsi_msg *msg)
1973 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1974 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
1975 int data_byte, rx_byte, dlen, end;
1976 int short_response, diff, pkt_size, ret = 0;
1978 int rlen = msg->rx_len;
1987 data_byte = 10; /* first read */
1988 if (rlen < data_byte)
1991 pkt_size = data_byte;
1992 rx_byte = data_byte + 6; /* 4 header + 2 crc */
1995 buf = msm_host->rx_buf;
1998 u8 tx[2] = {pkt_size & 0xff, pkt_size >> 8};
1999 struct mipi_dsi_msg max_pkt_size_msg = {
2000 .channel = msg->channel,
2001 .type = MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE,
2006 DBG("rlen=%d pkt_size=%d rx_byte=%d",
2007 rlen, pkt_size, rx_byte);
2009 ret = dsi_cmds2buf_tx(msm_host, &max_pkt_size_msg);
2011 pr_err("%s: Set max pkt size failed, %d\n",
2016 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) &&
2017 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_1)) {
2018 /* Clear the RDBK_DATA registers */
2019 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL,
2020 DSI_RDBK_DATA_CTRL_CLR);
2021 wmb(); /* make sure the RDBK registers are cleared */
2022 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 0);
2023 wmb(); /* release cleared status before transfer */
2026 ret = dsi_cmds2buf_tx(msm_host, msg);
2027 if (ret < msg->tx_len) {
2028 pr_err("%s: Read cmd Tx failed, %d\n", __func__, ret);
2033 * once cmd_dma_done interrupt received,
2034 * return data from client is ready and stored
2035 * at RDBK_DATA register already
2036 * since rx fifo is 16 bytes, dcs header is kept at first loop,
2037 * after that dcs header lost during shift into registers
2039 dlen = dsi_cmd_dma_rx(msm_host, buf, rx_byte, pkt_size);
2047 if (rlen <= data_byte) {
2048 diff = data_byte - rlen;
2056 dlen -= 2; /* 2 crc */
2058 buf += dlen; /* next start position */
2059 data_byte = 14; /* NOT first read */
2060 if (rlen < data_byte)
2063 pkt_size += data_byte;
2064 DBG("buf=%p dlen=%d diff=%d", buf, dlen, diff);
2069 * For single Long read, if the requested rlen < 10,
2070 * we need to shift the start position of rx
2071 * data buffer to skip the bytes which are not
2074 if (pkt_size < 10 && !short_response)
2075 buf = msm_host->rx_buf + (10 - rlen);
2077 buf = msm_host->rx_buf;
2081 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
2082 pr_err("%s: rx ACK_ERR_PACLAGE\n", __func__);
2085 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
2086 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
2087 ret = dsi_short_read1_resp(buf, msg);
2089 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
2090 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
2091 ret = dsi_short_read2_resp(buf, msg);
2093 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
2094 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
2095 ret = dsi_long_read_resp(buf, msg);
2098 pr_warn("%s:Invalid response cmd\n", __func__);
2105 void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host, u32 dma_base,
2108 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2110 dsi_write(msm_host, REG_DSI_DMA_BASE, dma_base);
2111 dsi_write(msm_host, REG_DSI_DMA_LEN, len);
2112 dsi_write(msm_host, REG_DSI_TRIG_DMA, 1);
2114 /* Make sure trigger happens */
2118 int msm_dsi_host_set_src_pll(struct mipi_dsi_host *host,
2119 struct msm_dsi_pll *src_pll)
2121 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2122 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
2123 struct clk *byte_clk_provider, *pixel_clk_provider;
2126 ret = msm_dsi_pll_get_clk_provider(src_pll,
2127 &byte_clk_provider, &pixel_clk_provider);
2129 pr_info("%s: can't get provider from pll, don't set parent\n",
2134 ret = clk_set_parent(msm_host->byte_clk_src, byte_clk_provider);
2136 pr_err("%s: can't set parent to byte_clk_src. ret=%d\n",
2141 ret = clk_set_parent(msm_host->pixel_clk_src, pixel_clk_provider);
2143 pr_err("%s: can't set parent to pixel_clk_src. ret=%d\n",
2148 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_V2) {
2149 ret = clk_set_parent(msm_host->dsi_clk_src, pixel_clk_provider);
2151 pr_err("%s: can't set parent to dsi_clk_src. ret=%d\n",
2156 ret = clk_set_parent(msm_host->esc_clk_src, byte_clk_provider);
2158 pr_err("%s: can't set parent to esc_clk_src. ret=%d\n",
2168 void msm_dsi_host_reset_phy(struct mipi_dsi_host *host)
2170 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2173 dsi_write(msm_host, REG_DSI_PHY_RESET, DSI_PHY_RESET_RESET);
2174 /* Make sure fully reset */
2177 dsi_write(msm_host, REG_DSI_PHY_RESET, 0);
2181 void msm_dsi_host_get_phy_clk_req(struct mipi_dsi_host *host,
2182 struct msm_dsi_phy_clk_request *clk_req)
2184 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2187 ret = dsi_calc_clk_rate(msm_host);
2189 pr_err("%s: unable to calc clk rate, %d\n", __func__, ret);
2193 clk_req->bitclk_rate = msm_host->byte_clk_rate * 8;
2194 clk_req->escclk_rate = msm_host->esc_clk_rate;
2197 int msm_dsi_host_enable(struct mipi_dsi_host *host)
2199 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2201 dsi_op_mode_config(msm_host,
2202 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), true);
2204 /* TODO: clock should be turned off for command mode,
2205 * and only turned on before MDP START.
2206 * This part of code should be enabled once mdp driver support it.
2208 /* if (msm_panel->mode == MSM_DSI_CMD_MODE) {
2209 * dsi_link_clk_disable(msm_host);
2210 * pm_runtime_put_autosuspend(&msm_host->pdev->dev);
2213 msm_host->enabled = true;
2217 int msm_dsi_host_disable(struct mipi_dsi_host *host)
2219 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2221 msm_host->enabled = false;
2222 dsi_op_mode_config(msm_host,
2223 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), false);
2225 /* Since we have disabled INTF, the video engine won't stop so that
2226 * the cmd engine will be blocked.
2227 * Reset to disable video engine so that we can send off cmd.
2229 dsi_sw_reset(msm_host);
2234 static void msm_dsi_sfpb_config(struct msm_dsi_host *msm_host, bool enable)
2236 enum sfpb_ahb_arb_master_port_en en;
2238 if (!msm_host->sfpb)
2241 en = enable ? SFPB_MASTER_PORT_ENABLE : SFPB_MASTER_PORT_DISABLE;
2243 regmap_update_bits(msm_host->sfpb, REG_SFPB_GPREG,
2244 SFPB_GPREG_MASTER_PORT_EN__MASK,
2245 SFPB_GPREG_MASTER_PORT_EN(en));
2248 int msm_dsi_host_power_on(struct mipi_dsi_host *host,
2249 struct msm_dsi_phy_shared_timings *phy_shared_timings)
2251 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2254 mutex_lock(&msm_host->dev_mutex);
2255 if (msm_host->power_on) {
2256 DBG("dsi host already on");
2260 msm_dsi_sfpb_config(msm_host, true);
2262 ret = dsi_host_regulator_enable(msm_host);
2264 pr_err("%s:Failed to enable vregs.ret=%d\n",
2269 pm_runtime_get_sync(&msm_host->pdev->dev);
2270 ret = dsi_link_clk_enable(msm_host);
2272 pr_err("%s: failed to enable link clocks. ret=%d\n",
2274 goto fail_disable_reg;
2277 ret = pinctrl_pm_select_default_state(&msm_host->pdev->dev);
2279 pr_err("%s: failed to set pinctrl default state, %d\n",
2281 goto fail_disable_clk;
2284 dsi_timing_setup(msm_host);
2285 dsi_sw_reset(msm_host);
2286 dsi_ctrl_config(msm_host, true, phy_shared_timings);
2288 if (msm_host->disp_en_gpio)
2289 gpiod_set_value(msm_host->disp_en_gpio, 1);
2291 msm_host->power_on = true;
2292 mutex_unlock(&msm_host->dev_mutex);
2297 dsi_link_clk_disable(msm_host);
2298 pm_runtime_put_autosuspend(&msm_host->pdev->dev);
2300 dsi_host_regulator_disable(msm_host);
2302 mutex_unlock(&msm_host->dev_mutex);
2306 int msm_dsi_host_power_off(struct mipi_dsi_host *host)
2308 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2310 mutex_lock(&msm_host->dev_mutex);
2311 if (!msm_host->power_on) {
2312 DBG("dsi host already off");
2316 dsi_ctrl_config(msm_host, false, NULL);
2318 if (msm_host->disp_en_gpio)
2319 gpiod_set_value(msm_host->disp_en_gpio, 0);
2321 pinctrl_pm_select_sleep_state(&msm_host->pdev->dev);
2323 dsi_link_clk_disable(msm_host);
2324 pm_runtime_put_autosuspend(&msm_host->pdev->dev);
2326 dsi_host_regulator_disable(msm_host);
2328 msm_dsi_sfpb_config(msm_host, false);
2332 msm_host->power_on = false;
2335 mutex_unlock(&msm_host->dev_mutex);
2339 int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host,
2340 struct drm_display_mode *mode)
2342 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2344 if (msm_host->mode) {
2345 drm_mode_destroy(msm_host->dev, msm_host->mode);
2346 msm_host->mode = NULL;
2349 msm_host->mode = drm_mode_duplicate(msm_host->dev, mode);
2350 if (!msm_host->mode) {
2351 pr_err("%s: cannot duplicate mode\n", __func__);
2358 struct drm_panel *msm_dsi_host_get_panel(struct mipi_dsi_host *host,
2359 unsigned long *panel_flags)
2361 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2362 struct drm_panel *panel;
2364 panel = of_drm_find_panel(msm_host->device_node);
2366 *panel_flags = msm_host->mode_flags;
2371 struct drm_bridge *msm_dsi_host_get_bridge(struct mipi_dsi_host *host)
2373 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2375 return of_drm_find_bridge(msm_host->device_node);