1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
7 #include <linux/delay.h>
8 #include <linux/dma-mapping.h>
10 #include <linux/gpio/consumer.h>
11 #include <linux/interrupt.h>
12 #include <linux/mfd/syscon.h>
13 #include <linux/of_device.h>
14 #include <linux/of_graph.h>
15 #include <linux/of_irq.h>
16 #include <linux/pinctrl/consumer.h>
17 #include <linux/pm_opp.h>
18 #include <linux/regmap.h>
19 #include <linux/regulator/consumer.h>
20 #include <linux/spinlock.h>
22 #include <video/mipi_display.h>
31 #define DSI_RESET_TOGGLE_DELAY_MS 20
33 static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor)
41 * From DSI6G(v3), addition of a 6G_HW_VERSION register at offset 0
42 * makes all other registers 4-byte shifted down.
44 * In order to identify between DSI6G(v3) and beyond, and DSIv2 and
45 * older, we read the DSI_VERSION register without any shift(offset
46 * 0x1f0). In the case of DSIv2, this hast to be a non-zero value. In
47 * the case of DSI6G, this has to be zero (the offset points to a
48 * scratch register which we never touch)
51 ver = msm_readl(base + REG_DSI_VERSION);
53 /* older dsi host, there is no register shift */
54 ver = FIELD(ver, DSI_VERSION_MAJOR);
55 if (ver <= MSM_DSI_VER_MAJOR_V2) {
65 * newer host, offset 0 has 6G_HW_VERSION, the rest of the
66 * registers are shifted down, read DSI_VERSION again with
69 ver = msm_readl(base + DSI_6G_REG_SHIFT + REG_DSI_VERSION);
70 ver = FIELD(ver, DSI_VERSION_MAJOR);
71 if (ver == MSM_DSI_VER_MAJOR_6G) {
74 *minor = msm_readl(base + REG_DSI_6G_HW_VERSION);
82 #define DSI_ERR_STATE_ACK 0x0000
83 #define DSI_ERR_STATE_TIMEOUT 0x0001
84 #define DSI_ERR_STATE_DLN0_PHY 0x0002
85 #define DSI_ERR_STATE_FIFO 0x0004
86 #define DSI_ERR_STATE_MDP_FIFO_UNDERFLOW 0x0008
87 #define DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION 0x0010
88 #define DSI_ERR_STATE_PLL_UNLOCKED 0x0020
90 #define DSI_CLK_CTRL_ENABLE_CLKS \
91 (DSI_CLK_CTRL_AHBS_HCLK_ON | DSI_CLK_CTRL_AHBM_SCLK_ON | \
92 DSI_CLK_CTRL_PCLK_ON | DSI_CLK_CTRL_DSICLK_ON | \
93 DSI_CLK_CTRL_BYTECLK_ON | DSI_CLK_CTRL_ESCCLK_ON | \
94 DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK)
97 struct mipi_dsi_host base;
99 struct platform_device *pdev;
100 struct drm_device *dev;
104 void __iomem *ctrl_base;
105 struct regulator_bulk_data supplies[DSI_DEV_REGULATOR_MAX];
107 struct clk *bus_clks[DSI_BUS_CLK_MAX];
109 struct clk *byte_clk;
111 struct clk *pixel_clk;
112 struct clk *byte_clk_src;
113 struct clk *pixel_clk_src;
114 struct clk *byte_intf_clk;
116 struct opp_table *opp_table;
122 /* DSI v2 specific clocks */
124 struct clk *esc_clk_src;
125 struct clk *dsi_clk_src;
129 struct gpio_desc *disp_en_gpio;
130 struct gpio_desc *te_gpio;
132 const struct msm_dsi_cfg_handler *cfg_hnd;
134 struct completion dma_comp;
135 struct completion video_comp;
136 struct mutex dev_mutex;
137 struct mutex cmd_mutex;
138 spinlock_t intr_lock; /* Protect interrupt ctrl register */
141 struct work_struct err_work;
142 struct work_struct hpd_work;
143 struct workqueue_struct *workqueue;
145 /* DSI 6G TX buffer*/
146 struct drm_gem_object *tx_gem_obj;
148 /* DSI v2 TX buffer */
150 dma_addr_t tx_buf_paddr;
158 struct drm_display_mode *mode;
160 /* connected device info */
161 struct device_node *device_node;
162 unsigned int channel;
164 enum mipi_dsi_pixel_format format;
165 unsigned long mode_flags;
167 /* lane data parsed via DT */
171 u32 dma_cmd_ctrl_restore;
179 static u32 dsi_get_bpp(const enum mipi_dsi_pixel_format fmt)
182 case MIPI_DSI_FMT_RGB565: return 16;
183 case MIPI_DSI_FMT_RGB666_PACKED: return 18;
184 case MIPI_DSI_FMT_RGB666:
185 case MIPI_DSI_FMT_RGB888:
190 static inline u32 dsi_read(struct msm_dsi_host *msm_host, u32 reg)
192 return msm_readl(msm_host->ctrl_base + reg);
194 static inline void dsi_write(struct msm_dsi_host *msm_host, u32 reg, u32 data)
196 msm_writel(data, msm_host->ctrl_base + reg);
199 static int dsi_host_regulator_enable(struct msm_dsi_host *msm_host);
200 static void dsi_host_regulator_disable(struct msm_dsi_host *msm_host);
202 static const struct msm_dsi_cfg_handler *dsi_get_config(
203 struct msm_dsi_host *msm_host)
205 const struct msm_dsi_cfg_handler *cfg_hnd = NULL;
206 struct device *dev = &msm_host->pdev->dev;
207 struct regulator *gdsc_reg;
210 u32 major = 0, minor = 0;
212 gdsc_reg = regulator_get(dev, "gdsc");
213 if (IS_ERR(gdsc_reg)) {
214 pr_err("%s: cannot get gdsc\n", __func__);
218 ahb_clk = msm_clk_get(msm_host->pdev, "iface");
219 if (IS_ERR(ahb_clk)) {
220 pr_err("%s: cannot get interface clock\n", __func__);
224 pm_runtime_get_sync(dev);
226 ret = regulator_enable(gdsc_reg);
228 pr_err("%s: unable to enable gdsc\n", __func__);
232 ret = clk_prepare_enable(ahb_clk);
234 pr_err("%s: unable to enable ahb_clk\n", __func__);
238 ret = dsi_get_version(msm_host->ctrl_base, &major, &minor);
240 pr_err("%s: Invalid version\n", __func__);
244 cfg_hnd = msm_dsi_cfg_get(major, minor);
246 DBG("%s: Version %x:%x\n", __func__, major, minor);
249 clk_disable_unprepare(ahb_clk);
251 regulator_disable(gdsc_reg);
252 pm_runtime_put_sync(dev);
254 regulator_put(gdsc_reg);
259 static inline struct msm_dsi_host *to_msm_dsi_host(struct mipi_dsi_host *host)
261 return container_of(host, struct msm_dsi_host, base);
264 static void dsi_host_regulator_disable(struct msm_dsi_host *msm_host)
266 struct regulator_bulk_data *s = msm_host->supplies;
267 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs;
268 int num = msm_host->cfg_hnd->cfg->reg_cfg.num;
272 for (i = num - 1; i >= 0; i--)
273 if (regs[i].disable_load >= 0)
274 regulator_set_load(s[i].consumer,
275 regs[i].disable_load);
277 regulator_bulk_disable(num, s);
280 static int dsi_host_regulator_enable(struct msm_dsi_host *msm_host)
282 struct regulator_bulk_data *s = msm_host->supplies;
283 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs;
284 int num = msm_host->cfg_hnd->cfg->reg_cfg.num;
288 for (i = 0; i < num; i++) {
289 if (regs[i].enable_load >= 0) {
290 ret = regulator_set_load(s[i].consumer,
291 regs[i].enable_load);
293 pr_err("regulator %d set op mode failed, %d\n",
300 ret = regulator_bulk_enable(num, s);
302 pr_err("regulator enable failed, %d\n", ret);
309 for (i--; i >= 0; i--)
310 regulator_set_load(s[i].consumer, regs[i].disable_load);
314 static int dsi_regulator_init(struct msm_dsi_host *msm_host)
316 struct regulator_bulk_data *s = msm_host->supplies;
317 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs;
318 int num = msm_host->cfg_hnd->cfg->reg_cfg.num;
321 for (i = 0; i < num; i++)
322 s[i].supply = regs[i].name;
324 ret = devm_regulator_bulk_get(&msm_host->pdev->dev, num, s);
326 pr_err("%s: failed to init regulator, ret=%d\n",
334 int dsi_clk_init_v2(struct msm_dsi_host *msm_host)
336 struct platform_device *pdev = msm_host->pdev;
339 msm_host->src_clk = msm_clk_get(pdev, "src");
341 if (IS_ERR(msm_host->src_clk)) {
342 ret = PTR_ERR(msm_host->src_clk);
343 pr_err("%s: can't find src clock. ret=%d\n",
345 msm_host->src_clk = NULL;
349 msm_host->esc_clk_src = clk_get_parent(msm_host->esc_clk);
350 if (!msm_host->esc_clk_src) {
352 pr_err("%s: can't get esc clock parent. ret=%d\n",
357 msm_host->dsi_clk_src = clk_get_parent(msm_host->src_clk);
358 if (!msm_host->dsi_clk_src) {
360 pr_err("%s: can't get src clock parent. ret=%d\n",
367 int dsi_clk_init_6g_v2(struct msm_dsi_host *msm_host)
369 struct platform_device *pdev = msm_host->pdev;
372 msm_host->byte_intf_clk = msm_clk_get(pdev, "byte_intf");
373 if (IS_ERR(msm_host->byte_intf_clk)) {
374 ret = PTR_ERR(msm_host->byte_intf_clk);
375 pr_err("%s: can't find byte_intf clock. ret=%d\n",
382 static int dsi_clk_init(struct msm_dsi_host *msm_host)
384 struct platform_device *pdev = msm_host->pdev;
385 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
386 const struct msm_dsi_config *cfg = cfg_hnd->cfg;
390 for (i = 0; i < cfg->num_bus_clks; i++) {
391 msm_host->bus_clks[i] = msm_clk_get(pdev,
392 cfg->bus_clk_names[i]);
393 if (IS_ERR(msm_host->bus_clks[i])) {
394 ret = PTR_ERR(msm_host->bus_clks[i]);
395 pr_err("%s: Unable to get %s clock, ret = %d\n",
396 __func__, cfg->bus_clk_names[i], ret);
401 /* get link and source clocks */
402 msm_host->byte_clk = msm_clk_get(pdev, "byte");
403 if (IS_ERR(msm_host->byte_clk)) {
404 ret = PTR_ERR(msm_host->byte_clk);
405 pr_err("%s: can't find dsi_byte clock. ret=%d\n",
407 msm_host->byte_clk = NULL;
411 msm_host->pixel_clk = msm_clk_get(pdev, "pixel");
412 if (IS_ERR(msm_host->pixel_clk)) {
413 ret = PTR_ERR(msm_host->pixel_clk);
414 pr_err("%s: can't find dsi_pixel clock. ret=%d\n",
416 msm_host->pixel_clk = NULL;
420 msm_host->esc_clk = msm_clk_get(pdev, "core");
421 if (IS_ERR(msm_host->esc_clk)) {
422 ret = PTR_ERR(msm_host->esc_clk);
423 pr_err("%s: can't find dsi_esc clock. ret=%d\n",
425 msm_host->esc_clk = NULL;
429 msm_host->byte_clk_src = clk_get_parent(msm_host->byte_clk);
430 if (IS_ERR(msm_host->byte_clk_src)) {
431 ret = PTR_ERR(msm_host->byte_clk_src);
432 pr_err("%s: can't find byte_clk clock. ret=%d\n", __func__, ret);
436 msm_host->pixel_clk_src = clk_get_parent(msm_host->pixel_clk);
437 if (IS_ERR(msm_host->pixel_clk_src)) {
438 ret = PTR_ERR(msm_host->pixel_clk_src);
439 pr_err("%s: can't find pixel_clk clock. ret=%d\n", __func__, ret);
443 if (cfg_hnd->ops->clk_init_ver)
444 ret = cfg_hnd->ops->clk_init_ver(msm_host);
449 static int dsi_bus_clk_enable(struct msm_dsi_host *msm_host)
451 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg;
454 DBG("id=%d", msm_host->id);
456 for (i = 0; i < cfg->num_bus_clks; i++) {
457 ret = clk_prepare_enable(msm_host->bus_clks[i]);
459 pr_err("%s: failed to enable bus clock %d ret %d\n",
468 clk_disable_unprepare(msm_host->bus_clks[i]);
473 static void dsi_bus_clk_disable(struct msm_dsi_host *msm_host)
475 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg;
480 for (i = cfg->num_bus_clks - 1; i >= 0; i--)
481 clk_disable_unprepare(msm_host->bus_clks[i]);
484 int msm_dsi_runtime_suspend(struct device *dev)
486 struct platform_device *pdev = to_platform_device(dev);
487 struct msm_dsi *msm_dsi = platform_get_drvdata(pdev);
488 struct mipi_dsi_host *host = msm_dsi->host;
489 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
491 if (!msm_host->cfg_hnd)
494 dsi_bus_clk_disable(msm_host);
499 int msm_dsi_runtime_resume(struct device *dev)
501 struct platform_device *pdev = to_platform_device(dev);
502 struct msm_dsi *msm_dsi = platform_get_drvdata(pdev);
503 struct mipi_dsi_host *host = msm_dsi->host;
504 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
506 if (!msm_host->cfg_hnd)
509 return dsi_bus_clk_enable(msm_host);
512 int dsi_link_clk_set_rate_6g(struct msm_dsi_host *msm_host)
516 DBG("Set clk rates: pclk=%d, byteclk=%d",
517 msm_host->mode->clock, msm_host->byte_clk_rate);
519 ret = dev_pm_opp_set_rate(&msm_host->pdev->dev,
520 msm_host->byte_clk_rate);
522 pr_err("%s: dev_pm_opp_set_rate failed %d\n", __func__, ret);
526 ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate);
528 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret);
532 if (msm_host->byte_intf_clk) {
533 ret = clk_set_rate(msm_host->byte_intf_clk,
534 msm_host->byte_clk_rate / 2);
536 pr_err("%s: Failed to set rate byte intf clk, %d\n",
546 int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host)
550 ret = clk_prepare_enable(msm_host->esc_clk);
552 pr_err("%s: Failed to enable dsi esc clk\n", __func__);
556 ret = clk_prepare_enable(msm_host->byte_clk);
558 pr_err("%s: Failed to enable dsi byte clk\n", __func__);
562 ret = clk_prepare_enable(msm_host->pixel_clk);
564 pr_err("%s: Failed to enable dsi pixel clk\n", __func__);
568 if (msm_host->byte_intf_clk) {
569 ret = clk_prepare_enable(msm_host->byte_intf_clk);
571 pr_err("%s: Failed to enable byte intf clk\n",
573 goto byte_intf_clk_err;
580 clk_disable_unprepare(msm_host->pixel_clk);
582 clk_disable_unprepare(msm_host->byte_clk);
584 clk_disable_unprepare(msm_host->esc_clk);
589 int dsi_link_clk_set_rate_v2(struct msm_dsi_host *msm_host)
593 DBG("Set clk rates: pclk=%d, byteclk=%d, esc_clk=%d, dsi_src_clk=%d",
594 msm_host->mode->clock, msm_host->byte_clk_rate,
595 msm_host->esc_clk_rate, msm_host->src_clk_rate);
597 ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate);
599 pr_err("%s: Failed to set rate byte clk, %d\n", __func__, ret);
603 ret = clk_set_rate(msm_host->esc_clk, msm_host->esc_clk_rate);
605 pr_err("%s: Failed to set rate esc clk, %d\n", __func__, ret);
609 ret = clk_set_rate(msm_host->src_clk, msm_host->src_clk_rate);
611 pr_err("%s: Failed to set rate src clk, %d\n", __func__, ret);
615 ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate);
617 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret);
624 int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host)
628 ret = clk_prepare_enable(msm_host->byte_clk);
630 pr_err("%s: Failed to enable dsi byte clk\n", __func__);
634 ret = clk_prepare_enable(msm_host->esc_clk);
636 pr_err("%s: Failed to enable dsi esc clk\n", __func__);
640 ret = clk_prepare_enable(msm_host->src_clk);
642 pr_err("%s: Failed to enable dsi src clk\n", __func__);
646 ret = clk_prepare_enable(msm_host->pixel_clk);
648 pr_err("%s: Failed to enable dsi pixel clk\n", __func__);
655 clk_disable_unprepare(msm_host->src_clk);
657 clk_disable_unprepare(msm_host->esc_clk);
659 clk_disable_unprepare(msm_host->byte_clk);
664 void dsi_link_clk_disable_6g(struct msm_dsi_host *msm_host)
666 /* Drop the performance state vote */
667 dev_pm_opp_set_rate(&msm_host->pdev->dev, 0);
668 clk_disable_unprepare(msm_host->esc_clk);
669 clk_disable_unprepare(msm_host->pixel_clk);
670 if (msm_host->byte_intf_clk)
671 clk_disable_unprepare(msm_host->byte_intf_clk);
672 clk_disable_unprepare(msm_host->byte_clk);
675 void dsi_link_clk_disable_v2(struct msm_dsi_host *msm_host)
677 clk_disable_unprepare(msm_host->pixel_clk);
678 clk_disable_unprepare(msm_host->src_clk);
679 clk_disable_unprepare(msm_host->esc_clk);
680 clk_disable_unprepare(msm_host->byte_clk);
683 static u32 dsi_get_pclk_rate(struct msm_dsi_host *msm_host, bool is_dual_dsi)
685 struct drm_display_mode *mode = msm_host->mode;
688 pclk_rate = mode->clock * 1000;
691 * For dual DSI mode, the current DRM mode has the complete width of the
692 * panel. Since, the complete panel is driven by two DSI controllers,
693 * the clock rates have to be split between the two dsi controllers.
694 * Adjust the byte and pixel clock rates for each dsi host accordingly.
702 static void dsi_calc_pclk(struct msm_dsi_host *msm_host, bool is_dual_dsi)
704 u8 lanes = msm_host->lanes;
705 u32 bpp = dsi_get_bpp(msm_host->format);
706 u32 pclk_rate = dsi_get_pclk_rate(msm_host, is_dual_dsi);
707 u64 pclk_bpp = (u64)pclk_rate * bpp;
710 pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__);
714 do_div(pclk_bpp, (8 * lanes));
716 msm_host->pixel_clk_rate = pclk_rate;
717 msm_host->byte_clk_rate = pclk_bpp;
719 DBG("pclk=%d, bclk=%d", msm_host->pixel_clk_rate,
720 msm_host->byte_clk_rate);
724 int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_dual_dsi)
726 if (!msm_host->mode) {
727 pr_err("%s: mode not set\n", __func__);
731 dsi_calc_pclk(msm_host, is_dual_dsi);
732 msm_host->esc_clk_rate = clk_get_rate(msm_host->esc_clk);
736 int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_dual_dsi)
738 u32 bpp = dsi_get_bpp(msm_host->format);
740 unsigned int esc_mhz, esc_div;
741 unsigned long byte_mhz;
743 dsi_calc_pclk(msm_host, is_dual_dsi);
745 pclk_bpp = (u64)dsi_get_pclk_rate(msm_host, is_dual_dsi) * bpp;
747 msm_host->src_clk_rate = pclk_bpp;
750 * esc clock is byte clock followed by a 4 bit divider,
751 * we need to find an escape clock frequency within the
752 * mipi DSI spec range within the maximum divider limit
753 * We iterate here between an escape clock frequencey
754 * between 20 Mhz to 5 Mhz and pick up the first one
755 * that can be supported by our divider
758 byte_mhz = msm_host->byte_clk_rate / 1000000;
760 for (esc_mhz = 20; esc_mhz >= 5; esc_mhz--) {
761 esc_div = DIV_ROUND_UP(byte_mhz, esc_mhz);
764 * TODO: Ideally, we shouldn't know what sort of divider
765 * is available in mmss_cc, we're just assuming that
766 * it'll always be a 4 bit divider. Need to come up with
769 if (esc_div >= 1 && esc_div <= 16)
776 msm_host->esc_clk_rate = msm_host->byte_clk_rate / esc_div;
778 DBG("esc=%d, src=%d", msm_host->esc_clk_rate,
779 msm_host->src_clk_rate);
784 static void dsi_intr_ctrl(struct msm_dsi_host *msm_host, u32 mask, int enable)
789 spin_lock_irqsave(&msm_host->intr_lock, flags);
790 intr = dsi_read(msm_host, REG_DSI_INTR_CTRL);
797 DBG("intr=%x enable=%d", intr, enable);
799 dsi_write(msm_host, REG_DSI_INTR_CTRL, intr);
800 spin_unlock_irqrestore(&msm_host->intr_lock, flags);
803 static inline enum dsi_traffic_mode dsi_get_traffic_mode(const u32 mode_flags)
805 if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
807 else if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
808 return NON_BURST_SYNCH_PULSE;
810 return NON_BURST_SYNCH_EVENT;
813 static inline enum dsi_vid_dst_format dsi_get_vid_fmt(
814 const enum mipi_dsi_pixel_format mipi_fmt)
817 case MIPI_DSI_FMT_RGB888: return VID_DST_FORMAT_RGB888;
818 case MIPI_DSI_FMT_RGB666: return VID_DST_FORMAT_RGB666_LOOSE;
819 case MIPI_DSI_FMT_RGB666_PACKED: return VID_DST_FORMAT_RGB666;
820 case MIPI_DSI_FMT_RGB565: return VID_DST_FORMAT_RGB565;
821 default: return VID_DST_FORMAT_RGB888;
825 static inline enum dsi_cmd_dst_format dsi_get_cmd_fmt(
826 const enum mipi_dsi_pixel_format mipi_fmt)
829 case MIPI_DSI_FMT_RGB888: return CMD_DST_FORMAT_RGB888;
830 case MIPI_DSI_FMT_RGB666_PACKED:
831 case MIPI_DSI_FMT_RGB666: return CMD_DST_FORMAT_RGB666;
832 case MIPI_DSI_FMT_RGB565: return CMD_DST_FORMAT_RGB565;
833 default: return CMD_DST_FORMAT_RGB888;
837 static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable,
838 struct msm_dsi_phy_shared_timings *phy_shared_timings)
840 u32 flags = msm_host->mode_flags;
841 enum mipi_dsi_pixel_format mipi_fmt = msm_host->format;
842 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
843 u32 data = 0, lane_ctrl = 0;
846 dsi_write(msm_host, REG_DSI_CTRL, 0);
850 if (flags & MIPI_DSI_MODE_VIDEO) {
851 if (flags & MIPI_DSI_MODE_VIDEO_HSE)
852 data |= DSI_VID_CFG0_PULSE_MODE_HSA_HE;
853 if (flags & MIPI_DSI_MODE_VIDEO_NO_HFP)
854 data |= DSI_VID_CFG0_HFP_POWER_STOP;
855 if (flags & MIPI_DSI_MODE_VIDEO_NO_HBP)
856 data |= DSI_VID_CFG0_HBP_POWER_STOP;
857 if (flags & MIPI_DSI_MODE_VIDEO_NO_HSA)
858 data |= DSI_VID_CFG0_HSA_POWER_STOP;
859 /* Always set low power stop mode for BLLP
860 * to let command engine send packets
862 data |= DSI_VID_CFG0_EOF_BLLP_POWER_STOP |
863 DSI_VID_CFG0_BLLP_POWER_STOP;
864 data |= DSI_VID_CFG0_TRAFFIC_MODE(dsi_get_traffic_mode(flags));
865 data |= DSI_VID_CFG0_DST_FORMAT(dsi_get_vid_fmt(mipi_fmt));
866 data |= DSI_VID_CFG0_VIRT_CHANNEL(msm_host->channel);
867 dsi_write(msm_host, REG_DSI_VID_CFG0, data);
869 /* Do not swap RGB colors */
870 data = DSI_VID_CFG1_RGB_SWAP(SWAP_RGB);
871 dsi_write(msm_host, REG_DSI_VID_CFG1, 0);
873 /* Do not swap RGB colors */
874 data = DSI_CMD_CFG0_RGB_SWAP(SWAP_RGB);
875 data |= DSI_CMD_CFG0_DST_FORMAT(dsi_get_cmd_fmt(mipi_fmt));
876 dsi_write(msm_host, REG_DSI_CMD_CFG0, data);
878 data = DSI_CMD_CFG1_WR_MEM_START(MIPI_DCS_WRITE_MEMORY_START) |
879 DSI_CMD_CFG1_WR_MEM_CONTINUE(
880 MIPI_DCS_WRITE_MEMORY_CONTINUE);
881 /* Always insert DCS command */
882 data |= DSI_CMD_CFG1_INSERT_DCS_COMMAND;
883 dsi_write(msm_host, REG_DSI_CMD_CFG1, data);
886 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL,
887 DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER |
888 DSI_CMD_DMA_CTRL_LOW_POWER);
891 /* Always assume dedicated TE pin */
892 data |= DSI_TRIG_CTRL_TE;
893 data |= DSI_TRIG_CTRL_MDP_TRIGGER(TRIGGER_NONE);
894 data |= DSI_TRIG_CTRL_DMA_TRIGGER(TRIGGER_SW);
895 data |= DSI_TRIG_CTRL_STREAM(msm_host->channel);
896 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) &&
897 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_2))
898 data |= DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME;
899 dsi_write(msm_host, REG_DSI_TRIG_CTRL, data);
901 data = DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(phy_shared_timings->clk_post) |
902 DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(phy_shared_timings->clk_pre);
903 dsi_write(msm_host, REG_DSI_CLKOUT_TIMING_CTRL, data);
905 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) &&
906 (cfg_hnd->minor > MSM_DSI_6G_VER_MINOR_V1_0) &&
907 phy_shared_timings->clk_pre_inc_by_2)
908 dsi_write(msm_host, REG_DSI_T_CLK_PRE_EXTEND,
909 DSI_T_CLK_PRE_EXTEND_INC_BY_2_BYTECLK);
912 if (!(flags & MIPI_DSI_MODE_NO_EOT_PACKET))
913 data |= DSI_EOT_PACKET_CTRL_TX_EOT_APPEND;
914 dsi_write(msm_host, REG_DSI_EOT_PACKET_CTRL, data);
916 /* allow only ack-err-status to generate interrupt */
917 dsi_write(msm_host, REG_DSI_ERR_INT_MASK0, 0x13ff3fe0);
919 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1);
921 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);
923 data = DSI_CTRL_CLK_EN;
925 DBG("lane number=%d", msm_host->lanes);
926 data |= ((DSI_CTRL_LANE0 << msm_host->lanes) - DSI_CTRL_LANE0);
928 dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL,
929 DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(msm_host->dlane_swap));
931 if (!(flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) {
932 lane_ctrl = dsi_read(msm_host, REG_DSI_LANE_CTRL);
933 dsi_write(msm_host, REG_DSI_LANE_CTRL,
934 lane_ctrl | DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST);
937 data |= DSI_CTRL_ENABLE;
939 dsi_write(msm_host, REG_DSI_CTRL, data);
942 static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_dual_dsi)
944 struct drm_display_mode *mode = msm_host->mode;
945 u32 hs_start = 0, vs_start = 0; /* take sync start as 0 */
946 u32 h_total = mode->htotal;
947 u32 v_total = mode->vtotal;
948 u32 hs_end = mode->hsync_end - mode->hsync_start;
949 u32 vs_end = mode->vsync_end - mode->vsync_start;
950 u32 ha_start = h_total - mode->hsync_start;
951 u32 ha_end = ha_start + mode->hdisplay;
952 u32 va_start = v_total - mode->vsync_start;
953 u32 va_end = va_start + mode->vdisplay;
954 u32 hdisplay = mode->hdisplay;
960 * For dual DSI mode, the current DRM mode has
961 * the complete width of the panel. Since, the complete
962 * panel is driven by two DSI controllers, the horizontal
963 * timings have to be split between the two dsi controllers.
964 * Adjust the DSI host timing values accordingly.
974 if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) {
975 dsi_write(msm_host, REG_DSI_ACTIVE_H,
976 DSI_ACTIVE_H_START(ha_start) |
977 DSI_ACTIVE_H_END(ha_end));
978 dsi_write(msm_host, REG_DSI_ACTIVE_V,
979 DSI_ACTIVE_V_START(va_start) |
980 DSI_ACTIVE_V_END(va_end));
981 dsi_write(msm_host, REG_DSI_TOTAL,
982 DSI_TOTAL_H_TOTAL(h_total - 1) |
983 DSI_TOTAL_V_TOTAL(v_total - 1));
985 dsi_write(msm_host, REG_DSI_ACTIVE_HSYNC,
986 DSI_ACTIVE_HSYNC_START(hs_start) |
987 DSI_ACTIVE_HSYNC_END(hs_end));
988 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_HPOS, 0);
989 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_VPOS,
990 DSI_ACTIVE_VSYNC_VPOS_START(vs_start) |
991 DSI_ACTIVE_VSYNC_VPOS_END(vs_end));
992 } else { /* command mode */
993 /* image data and 1 byte write_memory_start cmd */
994 wc = hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1;
996 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_CTRL,
997 DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT(wc) |
998 DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL(
1000 DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE(
1001 MIPI_DSI_DCS_LONG_WRITE));
1003 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_TOTAL,
1004 DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL(hdisplay) |
1005 DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL(mode->vdisplay));
1009 static void dsi_sw_reset(struct msm_dsi_host *msm_host)
1011 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);
1012 wmb(); /* clocks need to be enabled before reset */
1014 dsi_write(msm_host, REG_DSI_RESET, 1);
1015 msleep(DSI_RESET_TOGGLE_DELAY_MS); /* make sure reset happen */
1016 dsi_write(msm_host, REG_DSI_RESET, 0);
1019 static void dsi_op_mode_config(struct msm_dsi_host *msm_host,
1020 bool video_mode, bool enable)
1024 dsi_ctrl = dsi_read(msm_host, REG_DSI_CTRL);
1027 dsi_ctrl &= ~(DSI_CTRL_ENABLE | DSI_CTRL_VID_MODE_EN |
1028 DSI_CTRL_CMD_MODE_EN);
1029 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE |
1030 DSI_IRQ_MASK_VIDEO_DONE, 0);
1033 dsi_ctrl |= DSI_CTRL_VID_MODE_EN;
1034 } else { /* command mode */
1035 dsi_ctrl |= DSI_CTRL_CMD_MODE_EN;
1036 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE, 1);
1038 dsi_ctrl |= DSI_CTRL_ENABLE;
1041 dsi_write(msm_host, REG_DSI_CTRL, dsi_ctrl);
1044 static void dsi_set_tx_power_mode(int mode, struct msm_dsi_host *msm_host)
1048 data = dsi_read(msm_host, REG_DSI_CMD_DMA_CTRL);
1051 data &= ~DSI_CMD_DMA_CTRL_LOW_POWER;
1053 data |= DSI_CMD_DMA_CTRL_LOW_POWER;
1055 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, data);
1058 static void dsi_wait4video_done(struct msm_dsi_host *msm_host)
1061 struct device *dev = &msm_host->pdev->dev;
1063 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 1);
1065 reinit_completion(&msm_host->video_comp);
1067 ret = wait_for_completion_timeout(&msm_host->video_comp,
1068 msecs_to_jiffies(70));
1071 DRM_DEV_ERROR(dev, "wait for video done timed out\n");
1073 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 0);
1076 static void dsi_wait4video_eng_busy(struct msm_dsi_host *msm_host)
1078 if (!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO))
1081 if (msm_host->power_on && msm_host->enabled) {
1082 dsi_wait4video_done(msm_host);
1083 /* delay 4 ms to skip BLLP */
1084 usleep_range(2000, 4000);
1088 int dsi_tx_buf_alloc_6g(struct msm_dsi_host *msm_host, int size)
1090 struct drm_device *dev = msm_host->dev;
1091 struct msm_drm_private *priv = dev->dev_private;
1095 data = msm_gem_kernel_new(dev, size, MSM_BO_UNCACHED,
1097 &msm_host->tx_gem_obj, &iova);
1100 msm_host->tx_gem_obj = NULL;
1101 return PTR_ERR(data);
1104 msm_gem_object_set_name(msm_host->tx_gem_obj, "tx_gem");
1106 msm_host->tx_size = msm_host->tx_gem_obj->size;
1111 int dsi_tx_buf_alloc_v2(struct msm_dsi_host *msm_host, int size)
1113 struct drm_device *dev = msm_host->dev;
1115 msm_host->tx_buf = dma_alloc_coherent(dev->dev, size,
1116 &msm_host->tx_buf_paddr, GFP_KERNEL);
1117 if (!msm_host->tx_buf)
1120 msm_host->tx_size = size;
1125 static void dsi_tx_buf_free(struct msm_dsi_host *msm_host)
1127 struct drm_device *dev = msm_host->dev;
1128 struct msm_drm_private *priv;
1131 * This is possible if we're tearing down before we've had a chance to
1132 * fully initialize. A very real possibility if our probe is deferred,
1133 * in which case we'll hit msm_dsi_host_destroy() without having run
1134 * through the dsi_tx_buf_alloc().
1139 priv = dev->dev_private;
1140 if (msm_host->tx_gem_obj) {
1141 msm_gem_unpin_iova(msm_host->tx_gem_obj, priv->kms->aspace);
1142 drm_gem_object_put(msm_host->tx_gem_obj);
1143 msm_host->tx_gem_obj = NULL;
1146 if (msm_host->tx_buf)
1147 dma_free_coherent(dev->dev, msm_host->tx_size, msm_host->tx_buf,
1148 msm_host->tx_buf_paddr);
1151 void *dsi_tx_buf_get_6g(struct msm_dsi_host *msm_host)
1153 return msm_gem_get_vaddr(msm_host->tx_gem_obj);
1156 void *dsi_tx_buf_get_v2(struct msm_dsi_host *msm_host)
1158 return msm_host->tx_buf;
1161 void dsi_tx_buf_put_6g(struct msm_dsi_host *msm_host)
1163 msm_gem_put_vaddr(msm_host->tx_gem_obj);
1167 * prepare cmd buffer to be txed
1169 static int dsi_cmd_dma_add(struct msm_dsi_host *msm_host,
1170 const struct mipi_dsi_msg *msg)
1172 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
1173 struct mipi_dsi_packet packet;
1178 ret = mipi_dsi_create_packet(&packet, msg);
1180 pr_err("%s: create packet failed, %d\n", __func__, ret);
1183 len = (packet.size + 3) & (~0x3);
1185 if (len > msm_host->tx_size) {
1186 pr_err("%s: packet size is too big\n", __func__);
1190 data = cfg_hnd->ops->tx_buf_get(msm_host);
1192 ret = PTR_ERR(data);
1193 pr_err("%s: get vaddr failed, %d\n", __func__, ret);
1197 /* MSM specific command format in memory */
1198 data[0] = packet.header[1];
1199 data[1] = packet.header[2];
1200 data[2] = packet.header[0];
1201 data[3] = BIT(7); /* Last packet */
1202 if (mipi_dsi_packet_format_is_long(msg->type))
1204 if (msg->rx_buf && msg->rx_len)
1208 if (packet.payload && packet.payload_length)
1209 memcpy(data + 4, packet.payload, packet.payload_length);
1211 /* Append 0xff to the end */
1212 if (packet.size < len)
1213 memset(data + packet.size, 0xff, len - packet.size);
1215 if (cfg_hnd->ops->tx_buf_put)
1216 cfg_hnd->ops->tx_buf_put(msm_host);
1222 * dsi_short_read1_resp: 1 parameter
1224 static int dsi_short_read1_resp(u8 *buf, const struct mipi_dsi_msg *msg)
1226 u8 *data = msg->rx_buf;
1227 if (data && (msg->rx_len >= 1)) {
1228 *data = buf[1]; /* strip out dcs type */
1231 pr_err("%s: read data does not match with rx_buf len %zu\n",
1232 __func__, msg->rx_len);
1238 * dsi_short_read2_resp: 2 parameter
1240 static int dsi_short_read2_resp(u8 *buf, const struct mipi_dsi_msg *msg)
1242 u8 *data = msg->rx_buf;
1243 if (data && (msg->rx_len >= 2)) {
1244 data[0] = buf[1]; /* strip out dcs type */
1248 pr_err("%s: read data does not match with rx_buf len %zu\n",
1249 __func__, msg->rx_len);
1254 static int dsi_long_read_resp(u8 *buf, const struct mipi_dsi_msg *msg)
1256 /* strip out 4 byte dcs header */
1257 if (msg->rx_buf && msg->rx_len)
1258 memcpy(msg->rx_buf, buf + 4, msg->rx_len);
1263 int dsi_dma_base_get_6g(struct msm_dsi_host *msm_host, uint64_t *dma_base)
1265 struct drm_device *dev = msm_host->dev;
1266 struct msm_drm_private *priv = dev->dev_private;
1271 return msm_gem_get_and_pin_iova(msm_host->tx_gem_obj,
1272 priv->kms->aspace, dma_base);
1275 int dsi_dma_base_get_v2(struct msm_dsi_host *msm_host, uint64_t *dma_base)
1280 *dma_base = msm_host->tx_buf_paddr;
1284 static int dsi_cmd_dma_tx(struct msm_dsi_host *msm_host, int len)
1286 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
1291 ret = cfg_hnd->ops->dma_base_get(msm_host, &dma_base);
1293 pr_err("%s: failed to get iova: %d\n", __func__, ret);
1297 reinit_completion(&msm_host->dma_comp);
1299 dsi_wait4video_eng_busy(msm_host);
1301 triggered = msm_dsi_manager_cmd_xfer_trigger(
1302 msm_host->id, dma_base, len);
1304 ret = wait_for_completion_timeout(&msm_host->dma_comp,
1305 msecs_to_jiffies(200));
1317 static int dsi_cmd_dma_rx(struct msm_dsi_host *msm_host,
1318 u8 *buf, int rx_byte, int pkt_size)
1324 int repeated_bytes = 0;
1325 int buf_offset = buf - msm_host->rx_buf;
1328 cnt = (rx_byte + 3) >> 2;
1330 cnt = 4; /* 4 x 32 bits registers only */
1335 read_cnt = pkt_size + 6;
1338 * In case of multiple reads from the panel, after the first read, there
1339 * is possibility that there are some bytes in the payload repeating in
1340 * the RDBK_DATA registers. Since we read all the parameters from the
1341 * panel right from the first byte for every pass. We need to skip the
1342 * repeating bytes and then append the new parameters to the rx buffer.
1344 if (read_cnt > 16) {
1346 /* Any data more than 16 bytes will be shifted out.
1347 * The temp read buffer should already contain these bytes.
1348 * The remaining bytes in read buffer are the repeated bytes.
1350 bytes_shifted = read_cnt - 16;
1351 repeated_bytes = buf_offset - bytes_shifted;
1354 for (i = cnt - 1; i >= 0; i--) {
1355 data = dsi_read(msm_host, REG_DSI_RDBK_DATA(i));
1356 *temp++ = ntohl(data); /* to host byte order */
1357 DBG("data = 0x%x and ntohl(data) = 0x%x", data, ntohl(data));
1360 for (i = repeated_bytes; i < 16; i++)
1366 static int dsi_cmds2buf_tx(struct msm_dsi_host *msm_host,
1367 const struct mipi_dsi_msg *msg)
1370 int bllp_len = msm_host->mode->hdisplay *
1371 dsi_get_bpp(msm_host->format) / 8;
1373 len = dsi_cmd_dma_add(msm_host, msg);
1375 pr_err("%s: failed to add cmd type = 0x%x\n",
1376 __func__, msg->type);
1380 /* for video mode, do not send cmds more than
1381 * one pixel line, since it only transmit it
1384 /* TODO: if the command is sent in LP mode, the bit rate is only
1385 * half of esc clk rate. In this case, if the video is already
1386 * actively streaming, we need to check more carefully if the
1387 * command can be fit into one BLLP.
1389 if ((msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) && (len > bllp_len)) {
1390 pr_err("%s: cmd cannot fit into BLLP period, len=%d\n",
1395 ret = dsi_cmd_dma_tx(msm_host, len);
1397 pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, len=%d\n",
1398 __func__, msg->type, (*(u8 *)(msg->tx_buf)), len);
1405 static void dsi_sw_reset_restore(struct msm_dsi_host *msm_host)
1409 data0 = dsi_read(msm_host, REG_DSI_CTRL);
1411 data1 &= ~DSI_CTRL_ENABLE;
1412 dsi_write(msm_host, REG_DSI_CTRL, data1);
1414 * dsi controller need to be disabled before
1419 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);
1420 wmb(); /* make sure clocks enabled */
1422 /* dsi controller can only be reset while clocks are running */
1423 dsi_write(msm_host, REG_DSI_RESET, 1);
1424 msleep(DSI_RESET_TOGGLE_DELAY_MS); /* make sure reset happen */
1425 dsi_write(msm_host, REG_DSI_RESET, 0);
1426 wmb(); /* controller out of reset */
1427 dsi_write(msm_host, REG_DSI_CTRL, data0);
1428 wmb(); /* make sure dsi controller enabled again */
1431 static void dsi_hpd_worker(struct work_struct *work)
1433 struct msm_dsi_host *msm_host =
1434 container_of(work, struct msm_dsi_host, hpd_work);
1436 drm_helper_hpd_irq_event(msm_host->dev);
1439 static void dsi_err_worker(struct work_struct *work)
1441 struct msm_dsi_host *msm_host =
1442 container_of(work, struct msm_dsi_host, err_work);
1443 u32 status = msm_host->err_work_state;
1445 pr_err_ratelimited("%s: status=%x\n", __func__, status);
1446 if (status & DSI_ERR_STATE_MDP_FIFO_UNDERFLOW)
1447 dsi_sw_reset_restore(msm_host);
1449 /* It is safe to clear here because error irq is disabled. */
1450 msm_host->err_work_state = 0;
1452 /* enable dsi error interrupt */
1453 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1);
1456 static void dsi_ack_err_status(struct msm_dsi_host *msm_host)
1460 status = dsi_read(msm_host, REG_DSI_ACK_ERR_STATUS);
1463 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, status);
1464 /* Writing of an extra 0 needed to clear error bits */
1465 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, 0);
1466 msm_host->err_work_state |= DSI_ERR_STATE_ACK;
1470 static void dsi_timeout_status(struct msm_dsi_host *msm_host)
1474 status = dsi_read(msm_host, REG_DSI_TIMEOUT_STATUS);
1477 dsi_write(msm_host, REG_DSI_TIMEOUT_STATUS, status);
1478 msm_host->err_work_state |= DSI_ERR_STATE_TIMEOUT;
1482 static void dsi_dln0_phy_err(struct msm_dsi_host *msm_host)
1486 status = dsi_read(msm_host, REG_DSI_DLN0_PHY_ERR);
1488 if (status & (DSI_DLN0_PHY_ERR_DLN0_ERR_ESC |
1489 DSI_DLN0_PHY_ERR_DLN0_ERR_SYNC_ESC |
1490 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTROL |
1491 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0 |
1492 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1)) {
1493 dsi_write(msm_host, REG_DSI_DLN0_PHY_ERR, status);
1494 msm_host->err_work_state |= DSI_ERR_STATE_DLN0_PHY;
1498 static void dsi_fifo_status(struct msm_dsi_host *msm_host)
1502 status = dsi_read(msm_host, REG_DSI_FIFO_STATUS);
1504 /* fifo underflow, overflow */
1506 dsi_write(msm_host, REG_DSI_FIFO_STATUS, status);
1507 msm_host->err_work_state |= DSI_ERR_STATE_FIFO;
1508 if (status & DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW)
1509 msm_host->err_work_state |=
1510 DSI_ERR_STATE_MDP_FIFO_UNDERFLOW;
1514 static void dsi_status(struct msm_dsi_host *msm_host)
1518 status = dsi_read(msm_host, REG_DSI_STATUS0);
1520 if (status & DSI_STATUS0_INTERLEAVE_OP_CONTENTION) {
1521 dsi_write(msm_host, REG_DSI_STATUS0, status);
1522 msm_host->err_work_state |=
1523 DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION;
1527 static void dsi_clk_status(struct msm_dsi_host *msm_host)
1531 status = dsi_read(msm_host, REG_DSI_CLK_STATUS);
1533 if (status & DSI_CLK_STATUS_PLL_UNLOCKED) {
1534 dsi_write(msm_host, REG_DSI_CLK_STATUS, status);
1535 msm_host->err_work_state |= DSI_ERR_STATE_PLL_UNLOCKED;
1539 static void dsi_error(struct msm_dsi_host *msm_host)
1541 /* disable dsi error interrupt */
1542 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 0);
1544 dsi_clk_status(msm_host);
1545 dsi_fifo_status(msm_host);
1546 dsi_ack_err_status(msm_host);
1547 dsi_timeout_status(msm_host);
1548 dsi_status(msm_host);
1549 dsi_dln0_phy_err(msm_host);
1551 queue_work(msm_host->workqueue, &msm_host->err_work);
1554 static irqreturn_t dsi_host_irq(int irq, void *ptr)
1556 struct msm_dsi_host *msm_host = ptr;
1558 unsigned long flags;
1560 if (!msm_host->ctrl_base)
1563 spin_lock_irqsave(&msm_host->intr_lock, flags);
1564 isr = dsi_read(msm_host, REG_DSI_INTR_CTRL);
1565 dsi_write(msm_host, REG_DSI_INTR_CTRL, isr);
1566 spin_unlock_irqrestore(&msm_host->intr_lock, flags);
1568 DBG("isr=0x%x, id=%d", isr, msm_host->id);
1570 if (isr & DSI_IRQ_ERROR)
1571 dsi_error(msm_host);
1573 if (isr & DSI_IRQ_VIDEO_DONE)
1574 complete(&msm_host->video_comp);
1576 if (isr & DSI_IRQ_CMD_DMA_DONE)
1577 complete(&msm_host->dma_comp);
1582 static int dsi_host_init_panel_gpios(struct msm_dsi_host *msm_host,
1583 struct device *panel_device)
1585 msm_host->disp_en_gpio = devm_gpiod_get_optional(panel_device,
1588 if (IS_ERR(msm_host->disp_en_gpio)) {
1589 DBG("cannot get disp-enable-gpios %ld",
1590 PTR_ERR(msm_host->disp_en_gpio));
1591 return PTR_ERR(msm_host->disp_en_gpio);
1594 msm_host->te_gpio = devm_gpiod_get_optional(panel_device, "disp-te",
1596 if (IS_ERR(msm_host->te_gpio)) {
1597 DBG("cannot get disp-te-gpios %ld", PTR_ERR(msm_host->te_gpio));
1598 return PTR_ERR(msm_host->te_gpio);
1604 static int dsi_host_attach(struct mipi_dsi_host *host,
1605 struct mipi_dsi_device *dsi)
1607 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1610 if (dsi->lanes > msm_host->num_data_lanes)
1613 msm_host->channel = dsi->channel;
1614 msm_host->lanes = dsi->lanes;
1615 msm_host->format = dsi->format;
1616 msm_host->mode_flags = dsi->mode_flags;
1618 /* Some gpios defined in panel DT need to be controlled by host */
1619 ret = dsi_host_init_panel_gpios(msm_host, &dsi->dev);
1623 DBG("id=%d", msm_host->id);
1625 queue_work(msm_host->workqueue, &msm_host->hpd_work);
1630 static int dsi_host_detach(struct mipi_dsi_host *host,
1631 struct mipi_dsi_device *dsi)
1633 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1635 msm_host->device_node = NULL;
1637 DBG("id=%d", msm_host->id);
1639 queue_work(msm_host->workqueue, &msm_host->hpd_work);
1644 static ssize_t dsi_host_transfer(struct mipi_dsi_host *host,
1645 const struct mipi_dsi_msg *msg)
1647 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1650 if (!msg || !msm_host->power_on)
1653 mutex_lock(&msm_host->cmd_mutex);
1654 ret = msm_dsi_manager_cmd_xfer(msm_host->id, msg);
1655 mutex_unlock(&msm_host->cmd_mutex);
1660 static const struct mipi_dsi_host_ops dsi_host_ops = {
1661 .attach = dsi_host_attach,
1662 .detach = dsi_host_detach,
1663 .transfer = dsi_host_transfer,
1667 * List of supported physical to logical lane mappings.
1668 * For example, the 2nd entry represents the following mapping:
1670 * "3012": Logic 3->Phys 0; Logic 0->Phys 1; Logic 1->Phys 2; Logic 2->Phys 3;
1672 static const int supported_data_lane_swaps[][4] = {
1683 static int dsi_host_parse_lane_data(struct msm_dsi_host *msm_host,
1684 struct device_node *ep)
1686 struct device *dev = &msm_host->pdev->dev;
1687 struct property *prop;
1689 int ret, i, len, num_lanes;
1691 prop = of_find_property(ep, "data-lanes", &len);
1694 "failed to find data lane mapping, using default\n");
1698 num_lanes = len / sizeof(u32);
1700 if (num_lanes < 1 || num_lanes > 4) {
1701 DRM_DEV_ERROR(dev, "bad number of data lanes\n");
1705 msm_host->num_data_lanes = num_lanes;
1707 ret = of_property_read_u32_array(ep, "data-lanes", lane_map,
1710 DRM_DEV_ERROR(dev, "failed to read lane data\n");
1715 * compare DT specified physical-logical lane mappings with the ones
1716 * supported by hardware
1718 for (i = 0; i < ARRAY_SIZE(supported_data_lane_swaps); i++) {
1719 const int *swap = supported_data_lane_swaps[i];
1723 * the data-lanes array we get from DT has a logical->physical
1724 * mapping. The "data lane swap" register field represents
1725 * supported configurations in a physical->logical mapping.
1726 * Translate the DT mapping to what we understand and find a
1727 * configuration that works.
1729 for (j = 0; j < num_lanes; j++) {
1730 if (lane_map[j] < 0 || lane_map[j] > 3)
1731 DRM_DEV_ERROR(dev, "bad physical lane entry %u\n",
1734 if (swap[lane_map[j]] != j)
1738 if (j == num_lanes) {
1739 msm_host->dlane_swap = i;
1747 static int dsi_host_parse_dt(struct msm_dsi_host *msm_host)
1749 struct device *dev = &msm_host->pdev->dev;
1750 struct device_node *np = dev->of_node;
1751 struct device_node *endpoint, *device_node;
1755 * Get the endpoint of the output port of the DSI host. In our case,
1756 * this is mapped to port number with reg = 1. Don't return an error if
1757 * the remote endpoint isn't defined. It's possible that there is
1758 * nothing connected to the dsi output.
1760 endpoint = of_graph_get_endpoint_by_regs(np, 1, -1);
1762 DRM_DEV_DEBUG(dev, "%s: no endpoint\n", __func__);
1766 ret = dsi_host_parse_lane_data(msm_host, endpoint);
1768 DRM_DEV_ERROR(dev, "%s: invalid lane configuration %d\n",
1774 /* Get panel node from the output port's endpoint data */
1775 device_node = of_graph_get_remote_node(np, 1, 0);
1777 DRM_DEV_DEBUG(dev, "%s: no valid device\n", __func__);
1782 msm_host->device_node = device_node;
1784 if (of_property_read_bool(np, "syscon-sfpb")) {
1785 msm_host->sfpb = syscon_regmap_lookup_by_phandle(np,
1787 if (IS_ERR(msm_host->sfpb)) {
1788 DRM_DEV_ERROR(dev, "%s: failed to get sfpb regmap\n",
1790 ret = PTR_ERR(msm_host->sfpb);
1794 of_node_put(device_node);
1797 of_node_put(endpoint);
1802 static int dsi_host_get_id(struct msm_dsi_host *msm_host)
1804 struct platform_device *pdev = msm_host->pdev;
1805 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg;
1806 struct resource *res;
1809 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dsi_ctrl");
1813 for (i = 0; i < cfg->num_dsi; i++) {
1814 if (cfg->io_start[i] == res->start)
1821 int msm_dsi_host_init(struct msm_dsi *msm_dsi)
1823 struct msm_dsi_host *msm_host = NULL;
1824 struct platform_device *pdev = msm_dsi->pdev;
1827 msm_host = devm_kzalloc(&pdev->dev, sizeof(*msm_host), GFP_KERNEL);
1833 msm_host->pdev = pdev;
1834 msm_dsi->host = &msm_host->base;
1836 ret = dsi_host_parse_dt(msm_host);
1838 pr_err("%s: failed to parse dt\n", __func__);
1842 msm_host->ctrl_base = msm_ioremap(pdev, "dsi_ctrl", "DSI CTRL");
1843 if (IS_ERR(msm_host->ctrl_base)) {
1844 pr_err("%s: unable to map Dsi ctrl base\n", __func__);
1845 ret = PTR_ERR(msm_host->ctrl_base);
1849 pm_runtime_enable(&pdev->dev);
1851 msm_host->cfg_hnd = dsi_get_config(msm_host);
1852 if (!msm_host->cfg_hnd) {
1854 pr_err("%s: get config failed\n", __func__);
1858 msm_host->id = dsi_host_get_id(msm_host);
1859 if (msm_host->id < 0) {
1861 pr_err("%s: unable to identify DSI host index\n", __func__);
1865 /* fixup base address by io offset */
1866 msm_host->ctrl_base += msm_host->cfg_hnd->cfg->io_offset;
1868 ret = dsi_regulator_init(msm_host);
1870 pr_err("%s: regulator init failed\n", __func__);
1874 ret = dsi_clk_init(msm_host);
1876 pr_err("%s: unable to initialize dsi clks\n", __func__);
1880 msm_host->rx_buf = devm_kzalloc(&pdev->dev, SZ_4K, GFP_KERNEL);
1881 if (!msm_host->rx_buf) {
1883 pr_err("%s: alloc rx temp buf failed\n", __func__);
1887 msm_host->opp_table = dev_pm_opp_set_clkname(&pdev->dev, "byte");
1888 if (IS_ERR(msm_host->opp_table))
1889 return PTR_ERR(msm_host->opp_table);
1890 /* OPP table is optional */
1891 ret = dev_pm_opp_of_add_table(&pdev->dev);
1892 if (ret && ret != -ENODEV) {
1893 dev_err(&pdev->dev, "invalid OPP table in device tree\n");
1894 dev_pm_opp_put_clkname(msm_host->opp_table);
1898 init_completion(&msm_host->dma_comp);
1899 init_completion(&msm_host->video_comp);
1900 mutex_init(&msm_host->dev_mutex);
1901 mutex_init(&msm_host->cmd_mutex);
1902 spin_lock_init(&msm_host->intr_lock);
1904 /* setup workqueue */
1905 msm_host->workqueue = alloc_ordered_workqueue("dsi_drm_work", 0);
1906 INIT_WORK(&msm_host->err_work, dsi_err_worker);
1907 INIT_WORK(&msm_host->hpd_work, dsi_hpd_worker);
1909 msm_dsi->id = msm_host->id;
1911 DBG("Dsi Host %d initialized", msm_host->id);
1918 void msm_dsi_host_destroy(struct mipi_dsi_host *host)
1920 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1923 dsi_tx_buf_free(msm_host);
1924 if (msm_host->workqueue) {
1925 flush_workqueue(msm_host->workqueue);
1926 destroy_workqueue(msm_host->workqueue);
1927 msm_host->workqueue = NULL;
1930 mutex_destroy(&msm_host->cmd_mutex);
1931 mutex_destroy(&msm_host->dev_mutex);
1933 dev_pm_opp_of_remove_table(&msm_host->pdev->dev);
1934 dev_pm_opp_put_clkname(msm_host->opp_table);
1935 pm_runtime_disable(&msm_host->pdev->dev);
1938 int msm_dsi_host_modeset_init(struct mipi_dsi_host *host,
1939 struct drm_device *dev)
1941 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1942 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
1943 struct platform_device *pdev = msm_host->pdev;
1946 msm_host->irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
1947 if (msm_host->irq < 0) {
1948 ret = msm_host->irq;
1949 DRM_DEV_ERROR(dev->dev, "failed to get irq: %d\n", ret);
1953 ret = devm_request_irq(&pdev->dev, msm_host->irq,
1954 dsi_host_irq, IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
1955 "dsi_isr", msm_host);
1957 DRM_DEV_ERROR(&pdev->dev, "failed to request IRQ%u: %d\n",
1958 msm_host->irq, ret);
1962 msm_host->dev = dev;
1963 ret = cfg_hnd->ops->tx_buf_alloc(msm_host, SZ_4K);
1965 pr_err("%s: alloc tx gem obj failed, %d\n", __func__, ret);
1972 int msm_dsi_host_register(struct mipi_dsi_host *host, bool check_defer)
1974 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1977 /* Register mipi dsi host */
1978 if (!msm_host->registered) {
1979 host->dev = &msm_host->pdev->dev;
1980 host->ops = &dsi_host_ops;
1981 ret = mipi_dsi_host_register(host);
1985 msm_host->registered = true;
1987 /* If the panel driver has not been probed after host register,
1988 * we should defer the host's probe.
1989 * It makes sure panel is connected when fbcon detects
1990 * connector status and gets the proper display mode to
1991 * create framebuffer.
1992 * Don't try to defer if there is nothing connected to the dsi
1995 if (check_defer && msm_host->device_node) {
1996 if (IS_ERR(of_drm_find_panel(msm_host->device_node)))
1997 if (!of_drm_find_bridge(msm_host->device_node))
1998 return -EPROBE_DEFER;
2005 void msm_dsi_host_unregister(struct mipi_dsi_host *host)
2007 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2009 if (msm_host->registered) {
2010 mipi_dsi_host_unregister(host);
2013 msm_host->registered = false;
2017 int msm_dsi_host_xfer_prepare(struct mipi_dsi_host *host,
2018 const struct mipi_dsi_msg *msg)
2020 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2021 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
2023 /* TODO: make sure dsi_cmd_mdp is idle.
2024 * Since DSI6G v1.2.0, we can set DSI_TRIG_CTRL.BLOCK_DMA_WITHIN_FRAME
2025 * to ask H/W to wait until cmd mdp is idle. S/W wait is not needed.
2026 * How to handle the old versions? Wait for mdp cmd done?
2030 * mdss interrupt is generated in mdp core clock domain
2031 * mdp clock need to be enabled to receive dsi interrupt
2033 pm_runtime_get_sync(&msm_host->pdev->dev);
2034 cfg_hnd->ops->link_clk_set_rate(msm_host);
2035 cfg_hnd->ops->link_clk_enable(msm_host);
2037 /* TODO: vote for bus bandwidth */
2039 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM))
2040 dsi_set_tx_power_mode(0, msm_host);
2042 msm_host->dma_cmd_ctrl_restore = dsi_read(msm_host, REG_DSI_CTRL);
2043 dsi_write(msm_host, REG_DSI_CTRL,
2044 msm_host->dma_cmd_ctrl_restore |
2045 DSI_CTRL_CMD_MODE_EN |
2047 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 1);
2052 void msm_dsi_host_xfer_restore(struct mipi_dsi_host *host,
2053 const struct mipi_dsi_msg *msg)
2055 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2056 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
2058 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 0);
2059 dsi_write(msm_host, REG_DSI_CTRL, msm_host->dma_cmd_ctrl_restore);
2061 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM))
2062 dsi_set_tx_power_mode(1, msm_host);
2064 /* TODO: unvote for bus bandwidth */
2066 cfg_hnd->ops->link_clk_disable(msm_host);
2067 pm_runtime_put_autosuspend(&msm_host->pdev->dev);
2070 int msm_dsi_host_cmd_tx(struct mipi_dsi_host *host,
2071 const struct mipi_dsi_msg *msg)
2073 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2075 return dsi_cmds2buf_tx(msm_host, msg);
2078 int msm_dsi_host_cmd_rx(struct mipi_dsi_host *host,
2079 const struct mipi_dsi_msg *msg)
2081 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2082 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
2083 int data_byte, rx_byte, dlen, end;
2084 int short_response, diff, pkt_size, ret = 0;
2086 int rlen = msg->rx_len;
2095 data_byte = 10; /* first read */
2096 if (rlen < data_byte)
2099 pkt_size = data_byte;
2100 rx_byte = data_byte + 6; /* 4 header + 2 crc */
2103 buf = msm_host->rx_buf;
2106 u8 tx[2] = {pkt_size & 0xff, pkt_size >> 8};
2107 struct mipi_dsi_msg max_pkt_size_msg = {
2108 .channel = msg->channel,
2109 .type = MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE,
2114 DBG("rlen=%d pkt_size=%d rx_byte=%d",
2115 rlen, pkt_size, rx_byte);
2117 ret = dsi_cmds2buf_tx(msm_host, &max_pkt_size_msg);
2119 pr_err("%s: Set max pkt size failed, %d\n",
2124 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) &&
2125 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_1)) {
2126 /* Clear the RDBK_DATA registers */
2127 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL,
2128 DSI_RDBK_DATA_CTRL_CLR);
2129 wmb(); /* make sure the RDBK registers are cleared */
2130 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 0);
2131 wmb(); /* release cleared status before transfer */
2134 ret = dsi_cmds2buf_tx(msm_host, msg);
2135 if (ret < msg->tx_len) {
2136 pr_err("%s: Read cmd Tx failed, %d\n", __func__, ret);
2141 * once cmd_dma_done interrupt received,
2142 * return data from client is ready and stored
2143 * at RDBK_DATA register already
2144 * since rx fifo is 16 bytes, dcs header is kept at first loop,
2145 * after that dcs header lost during shift into registers
2147 dlen = dsi_cmd_dma_rx(msm_host, buf, rx_byte, pkt_size);
2155 if (rlen <= data_byte) {
2156 diff = data_byte - rlen;
2164 dlen -= 2; /* 2 crc */
2166 buf += dlen; /* next start position */
2167 data_byte = 14; /* NOT first read */
2168 if (rlen < data_byte)
2171 pkt_size += data_byte;
2172 DBG("buf=%p dlen=%d diff=%d", buf, dlen, diff);
2177 * For single Long read, if the requested rlen < 10,
2178 * we need to shift the start position of rx
2179 * data buffer to skip the bytes which are not
2182 if (pkt_size < 10 && !short_response)
2183 buf = msm_host->rx_buf + (10 - rlen);
2185 buf = msm_host->rx_buf;
2189 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
2190 pr_err("%s: rx ACK_ERR_PACLAGE\n", __func__);
2193 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
2194 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
2195 ret = dsi_short_read1_resp(buf, msg);
2197 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
2198 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
2199 ret = dsi_short_read2_resp(buf, msg);
2201 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
2202 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
2203 ret = dsi_long_read_resp(buf, msg);
2206 pr_warn("%s:Invalid response cmd\n", __func__);
2213 void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host, u32 dma_base,
2216 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2218 dsi_write(msm_host, REG_DSI_DMA_BASE, dma_base);
2219 dsi_write(msm_host, REG_DSI_DMA_LEN, len);
2220 dsi_write(msm_host, REG_DSI_TRIG_DMA, 1);
2222 /* Make sure trigger happens */
2226 int msm_dsi_host_set_src_pll(struct mipi_dsi_host *host,
2227 struct msm_dsi_phy *src_phy)
2229 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2230 struct clk *byte_clk_provider, *pixel_clk_provider;
2233 ret = msm_dsi_phy_get_clk_provider(src_phy,
2234 &byte_clk_provider, &pixel_clk_provider);
2236 pr_info("%s: can't get provider from pll, don't set parent\n",
2241 ret = clk_set_parent(msm_host->byte_clk_src, byte_clk_provider);
2243 pr_err("%s: can't set parent to byte_clk_src. ret=%d\n",
2248 ret = clk_set_parent(msm_host->pixel_clk_src, pixel_clk_provider);
2250 pr_err("%s: can't set parent to pixel_clk_src. ret=%d\n",
2255 if (msm_host->dsi_clk_src) {
2256 ret = clk_set_parent(msm_host->dsi_clk_src, pixel_clk_provider);
2258 pr_err("%s: can't set parent to dsi_clk_src. ret=%d\n",
2264 if (msm_host->esc_clk_src) {
2265 ret = clk_set_parent(msm_host->esc_clk_src, byte_clk_provider);
2267 pr_err("%s: can't set parent to esc_clk_src. ret=%d\n",
2277 void msm_dsi_host_reset_phy(struct mipi_dsi_host *host)
2279 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2282 dsi_write(msm_host, REG_DSI_PHY_RESET, DSI_PHY_RESET_RESET);
2283 /* Make sure fully reset */
2286 dsi_write(msm_host, REG_DSI_PHY_RESET, 0);
2290 void msm_dsi_host_get_phy_clk_req(struct mipi_dsi_host *host,
2291 struct msm_dsi_phy_clk_request *clk_req,
2294 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2295 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
2298 ret = cfg_hnd->ops->calc_clk_rate(msm_host, is_dual_dsi);
2300 pr_err("%s: unable to calc clk rate, %d\n", __func__, ret);
2304 clk_req->bitclk_rate = msm_host->byte_clk_rate * 8;
2305 clk_req->escclk_rate = msm_host->esc_clk_rate;
2308 int msm_dsi_host_enable(struct mipi_dsi_host *host)
2310 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2312 dsi_op_mode_config(msm_host,
2313 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), true);
2315 /* TODO: clock should be turned off for command mode,
2316 * and only turned on before MDP START.
2317 * This part of code should be enabled once mdp driver support it.
2319 /* if (msm_panel->mode == MSM_DSI_CMD_MODE) {
2320 * dsi_link_clk_disable(msm_host);
2321 * pm_runtime_put_autosuspend(&msm_host->pdev->dev);
2324 msm_host->enabled = true;
2328 int msm_dsi_host_disable(struct mipi_dsi_host *host)
2330 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2332 msm_host->enabled = false;
2333 dsi_op_mode_config(msm_host,
2334 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), false);
2336 /* Since we have disabled INTF, the video engine won't stop so that
2337 * the cmd engine will be blocked.
2338 * Reset to disable video engine so that we can send off cmd.
2340 dsi_sw_reset(msm_host);
2345 static void msm_dsi_sfpb_config(struct msm_dsi_host *msm_host, bool enable)
2347 enum sfpb_ahb_arb_master_port_en en;
2349 if (!msm_host->sfpb)
2352 en = enable ? SFPB_MASTER_PORT_ENABLE : SFPB_MASTER_PORT_DISABLE;
2354 regmap_update_bits(msm_host->sfpb, REG_SFPB_GPREG,
2355 SFPB_GPREG_MASTER_PORT_EN__MASK,
2356 SFPB_GPREG_MASTER_PORT_EN(en));
2359 int msm_dsi_host_power_on(struct mipi_dsi_host *host,
2360 struct msm_dsi_phy_shared_timings *phy_shared_timings,
2363 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2364 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
2367 mutex_lock(&msm_host->dev_mutex);
2368 if (msm_host->power_on) {
2369 DBG("dsi host already on");
2373 msm_dsi_sfpb_config(msm_host, true);
2375 ret = dsi_host_regulator_enable(msm_host);
2377 pr_err("%s:Failed to enable vregs.ret=%d\n",
2382 pm_runtime_get_sync(&msm_host->pdev->dev);
2383 ret = cfg_hnd->ops->link_clk_set_rate(msm_host);
2385 ret = cfg_hnd->ops->link_clk_enable(msm_host);
2387 pr_err("%s: failed to enable link clocks. ret=%d\n",
2389 goto fail_disable_reg;
2392 ret = pinctrl_pm_select_default_state(&msm_host->pdev->dev);
2394 pr_err("%s: failed to set pinctrl default state, %d\n",
2396 goto fail_disable_clk;
2399 dsi_timing_setup(msm_host, is_dual_dsi);
2400 dsi_sw_reset(msm_host);
2401 dsi_ctrl_config(msm_host, true, phy_shared_timings);
2403 if (msm_host->disp_en_gpio)
2404 gpiod_set_value(msm_host->disp_en_gpio, 1);
2406 msm_host->power_on = true;
2407 mutex_unlock(&msm_host->dev_mutex);
2412 cfg_hnd->ops->link_clk_disable(msm_host);
2413 pm_runtime_put_autosuspend(&msm_host->pdev->dev);
2415 dsi_host_regulator_disable(msm_host);
2417 mutex_unlock(&msm_host->dev_mutex);
2421 int msm_dsi_host_power_off(struct mipi_dsi_host *host)
2423 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2424 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
2426 mutex_lock(&msm_host->dev_mutex);
2427 if (!msm_host->power_on) {
2428 DBG("dsi host already off");
2432 dsi_ctrl_config(msm_host, false, NULL);
2434 if (msm_host->disp_en_gpio)
2435 gpiod_set_value(msm_host->disp_en_gpio, 0);
2437 pinctrl_pm_select_sleep_state(&msm_host->pdev->dev);
2439 cfg_hnd->ops->link_clk_disable(msm_host);
2440 pm_runtime_put_autosuspend(&msm_host->pdev->dev);
2442 dsi_host_regulator_disable(msm_host);
2444 msm_dsi_sfpb_config(msm_host, false);
2448 msm_host->power_on = false;
2451 mutex_unlock(&msm_host->dev_mutex);
2455 int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host,
2456 const struct drm_display_mode *mode)
2458 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2460 if (msm_host->mode) {
2461 drm_mode_destroy(msm_host->dev, msm_host->mode);
2462 msm_host->mode = NULL;
2465 msm_host->mode = drm_mode_duplicate(msm_host->dev, mode);
2466 if (!msm_host->mode) {
2467 pr_err("%s: cannot duplicate mode\n", __func__);
2474 struct drm_panel *msm_dsi_host_get_panel(struct mipi_dsi_host *host)
2476 return of_drm_find_panel(to_msm_dsi_host(host)->device_node);
2479 unsigned long msm_dsi_host_get_mode_flags(struct mipi_dsi_host *host)
2481 return to_msm_dsi_host(host)->mode_flags;
2484 struct drm_bridge *msm_dsi_host_get_bridge(struct mipi_dsi_host *host)
2486 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2488 return of_drm_find_bridge(msm_host->device_node);