drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2013 Red Hat
   4  * Author: Rob Clark <robdclark@gmail.com>
   5  */
   6
   7 #include "mdp4_kms.h"
   8
   9 #define DOWN_SCALE_MAX  8
  10 #define UP_SCALE_MAX    8
  11
  12 struct mdp4_plane {
  13         struct drm_plane base;
  14         const char *name;
  15
  16         enum mdp4_pipe pipe;
  17
  18         uint32_t caps;
  19         uint32_t nformats;
  20         uint32_t formats[32];
  21
  22         bool enabled;
  23 };
  24 #define to_mdp4_plane(x) container_of(x, struct mdp4_plane, base)
  25
  26 /* MDP format helper functions */
  27 static inline
  28 enum mdp4_frame_format mdp4_get_frame_format(struct drm_framebuffer *fb)
  29 {
  30         bool is_tile = false;
  31
  32         if (fb->modifier == DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
  33                 is_tile = true;
  34
  35         if (fb->format->format == DRM_FORMAT_NV12 && is_tile)
  36                 return FRAME_TILE_YCBCR_420;
  37
  38         return FRAME_LINEAR;
  39 }
  40
  41 static void mdp4_plane_set_scanout(struct drm_plane *plane,
  42                 struct drm_framebuffer *fb);
  43 static int mdp4_plane_mode_set(struct drm_plane *plane,
  44                 struct drm_crtc *crtc, struct drm_framebuffer *fb,
  45                 int crtc_x, int crtc_y,
  46                 unsigned int crtc_w, unsigned int crtc_h,
  47                 uint32_t src_x, uint32_t src_y,
  48                 uint32_t src_w, uint32_t src_h);
  49
  50 static struct mdp4_kms *get_kms(struct drm_plane *plane)
  51 {
  52         struct msm_drm_private *priv = plane->dev->dev_private;
  53         return to_mdp4_kms(to_mdp_kms(priv->kms));
  54 }
  55
  56 static void mdp4_plane_destroy(struct drm_plane *plane)
  57 {
  58         struct mdp4_plane *mdp4_plane = to_mdp4_plane(plane);
  59
  60         drm_plane_cleanup(plane);
  61
  62         kfree(mdp4_plane);
  63 }
  64
  65 /* helper to install properties which are common to planes and crtcs */
  66 static void mdp4_plane_install_properties(struct drm_plane *plane,
  67                 struct drm_mode_object *obj)
  68 {
  69         // XXX
  70 }
  71
  72 static int mdp4_plane_set_property(struct drm_plane *plane,
  73                 struct drm_property *property, uint64_t val)
  74 {
  75         // XXX
  76         return -EINVAL;
  77 }
  78
  79 static const struct drm_plane_funcs mdp4_plane_funcs = {
  80                 .update_plane = drm_atomic_helper_update_plane,
  81                 .disable_plane = drm_atomic_helper_disable_plane,
  82                 .destroy = mdp4_plane_destroy,
  83                 .set_property = mdp4_plane_set_property,
  84                 .reset = drm_atomic_helper_plane_reset,
  85                 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
  86                 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
  87 };
  88
  89 static void mdp4_plane_cleanup_fb(struct drm_plane *plane,
  90                                   struct drm_plane_state *old_state)
  91 {
  92         struct mdp4_plane *mdp4_plane = to_mdp4_plane(plane);
  93         struct mdp4_kms *mdp4_kms = get_kms(plane);
  94         struct msm_kms *kms = &mdp4_kms->base.base;
  95         struct drm_framebuffer *fb = old_state->fb;
  96
  97         if (!fb)
  98                 return;
  99
 100         DBG("%s: cleanup: FB[%u]", mdp4_plane->name, fb->base.id);
 101         msm_framebuffer_cleanup(fb, kms->aspace);
 102 }
 103
 104
 105 static int mdp4_plane_atomic_check(struct drm_plane *plane,
 106                 struct drm_plane_state *state)
 107 {
 108         return 0;
 109 }
 110
 111 static void mdp4_plane_atomic_update(struct drm_plane *plane,
 112                                      struct drm_plane_state *old_state)
 113 {
 114         struct drm_plane_state *state = plane->state;
 115         int ret;
 116
 117         ret = mdp4_plane_mode_set(plane,
 118                         state->crtc, state->fb,
 119                         state->crtc_x, state->crtc_y,
 120                         state->crtc_w, state->crtc_h,
 121                         state->src_x,  state->src_y,
 122                         state->src_w, state->src_h);
 123         /* atomic_check should have ensured that this doesn't fail */
 124         WARN_ON(ret < 0);
 125 }
 126
 127 static const struct drm_plane_helper_funcs mdp4_plane_helper_funcs = {
 128                 .prepare_fb = msm_atomic_prepare_fb,
 129                 .cleanup_fb = mdp4_plane_cleanup_fb,
 130                 .atomic_check = mdp4_plane_atomic_check,
 131                 .atomic_update = mdp4_plane_atomic_update,
 132 };
 133
 134 static void mdp4_plane_set_scanout(struct drm_plane *plane,
 135                 struct drm_framebuffer *fb)
 136 {
 137         struct mdp4_plane *mdp4_plane = to_mdp4_plane(plane);
 138         struct mdp4_kms *mdp4_kms = get_kms(plane);
 139         struct msm_kms *kms = &mdp4_kms->base.base;
 140         enum mdp4_pipe pipe = mdp4_plane->pipe;
 141
 142         mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_STRIDE_A(pipe),
 143                         MDP4_PIPE_SRC_STRIDE_A_P0(fb->pitches[0]) |
 144                         MDP4_PIPE_SRC_STRIDE_A_P1(fb->pitches[1]));
 145
 146         mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_STRIDE_B(pipe),
 147                         MDP4_PIPE_SRC_STRIDE_B_P2(fb->pitches[2]) |
 148                         MDP4_PIPE_SRC_STRIDE_B_P3(fb->pitches[3]));
 149
 150         mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRCP0_BASE(pipe),
 151                         msm_framebuffer_iova(fb, kms->aspace, 0));
 152         mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRCP1_BASE(pipe),
 153                         msm_framebuffer_iova(fb, kms->aspace, 1));
 154         mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRCP2_BASE(pipe),
 155                         msm_framebuffer_iova(fb, kms->aspace, 2));
 156         mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRCP3_BASE(pipe),
 157                         msm_framebuffer_iova(fb, kms->aspace, 3));
 158 }
 159
 160 static void mdp4_write_csc_config(struct mdp4_kms *mdp4_kms,
 161                 enum mdp4_pipe pipe, struct csc_cfg *csc)
 162 {
 163         int i;
 164
 165         for (i = 0; i < ARRAY_SIZE(csc->matrix); i++) {
 166                 mdp4_write(mdp4_kms, REG_MDP4_PIPE_CSC_MV(pipe, i),
 167                                 csc->matrix[i]);
 168         }
 169
 170         for (i = 0; i < ARRAY_SIZE(csc->post_bias) ; i++) {
 171                 mdp4_write(mdp4_kms, REG_MDP4_PIPE_CSC_PRE_BV(pipe, i),
 172                                 csc->pre_bias[i]);
 173
 174                 mdp4_write(mdp4_kms, REG_MDP4_PIPE_CSC_POST_BV(pipe, i),
 175                                 csc->post_bias[i]);
 176         }
 177
 178         for (i = 0; i < ARRAY_SIZE(csc->post_clamp) ; i++) {
 179                 mdp4_write(mdp4_kms, REG_MDP4_PIPE_CSC_PRE_LV(pipe, i),
 180                                 csc->pre_clamp[i]);
 181
 182                 mdp4_write(mdp4_kms, REG_MDP4_PIPE_CSC_POST_LV(pipe, i),
 183                                 csc->post_clamp[i]);
 184         }
 185 }
 186
 187 #define MDP4_VG_PHASE_STEP_DEFAULT      0x20000000
 188
 189 static int mdp4_plane_mode_set(struct drm_plane *plane,
 190                 struct drm_crtc *crtc, struct drm_framebuffer *fb,
 191                 int crtc_x, int crtc_y,
 192                 unsigned int crtc_w, unsigned int crtc_h,
 193                 uint32_t src_x, uint32_t src_y,
 194                 uint32_t src_w, uint32_t src_h)
 195 {
 196         struct drm_device *dev = plane->dev;
 197         struct mdp4_plane *mdp4_plane = to_mdp4_plane(plane);
 198         struct mdp4_kms *mdp4_kms = get_kms(plane);
 199         enum mdp4_pipe pipe = mdp4_plane->pipe;
 200         const struct mdp_format *format;
 201         uint32_t op_mode = 0;
 202         uint32_t phasex_step = MDP4_VG_PHASE_STEP_DEFAULT;
 203         uint32_t phasey_step = MDP4_VG_PHASE_STEP_DEFAULT;
 204         enum mdp4_frame_format frame_type;
 205
 206         if (!(crtc && fb)) {
 207                 DBG("%s: disabled!", mdp4_plane->name);
 208                 return 0;
 209         }
 210
 211         frame_type = mdp4_get_frame_format(fb);
 212
 213         /* src values are in Q16 fixed point, convert to integer: */
 214         src_x = src_x >> 16;
 215         src_y = src_y >> 16;
 216         src_w = src_w >> 16;
 217         src_h = src_h >> 16;
 218
 219         DBG("%s: FB[%u] %u,%u,%u,%u -> CRTC[%u] %d,%d,%u,%u", mdp4_plane->name,
 220                         fb->base.id, src_x, src_y, src_w, src_h,
 221                         crtc->base.id, crtc_x, crtc_y, crtc_w, crtc_h);
 222
 223         format = to_mdp_format(msm_framebuffer_format(fb));
 224
 225         if (src_w > (crtc_w * DOWN_SCALE_MAX)) {
 226                 DRM_DEV_ERROR(dev->dev, "Width down scaling exceeds limits!\n");
 227                 return -ERANGE;
 228         }
 229
 230         if (src_h > (crtc_h * DOWN_SCALE_MAX)) {
 231                 DRM_DEV_ERROR(dev->dev, "Height down scaling exceeds limits!\n");
 232                 return -ERANGE;
 233         }
 234
 235         if (crtc_w > (src_w * UP_SCALE_MAX)) {
 236                 DRM_DEV_ERROR(dev->dev, "Width up scaling exceeds limits!\n");
 237                 return -ERANGE;
 238         }
 239
 240         if (crtc_h > (src_h * UP_SCALE_MAX)) {
 241                 DRM_DEV_ERROR(dev->dev, "Height up scaling exceeds limits!\n");
 242                 return -ERANGE;
 243         }
 244
 245         if (src_w != crtc_w) {
 246                 uint32_t sel_unit = SCALE_FIR;
 247                 op_mode |= MDP4_PIPE_OP_MODE_SCALEX_EN;
 248
 249                 if (MDP_FORMAT_IS_YUV(format)) {
 250                         if (crtc_w > src_w)
 251                                 sel_unit = SCALE_PIXEL_RPT;
 252                         else if (crtc_w <= (src_w / 4))
 253                                 sel_unit = SCALE_MN_PHASE;
 254
 255                         op_mode |= MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL(sel_unit);
 256                         phasex_step = mult_frac(MDP4_VG_PHASE_STEP_DEFAULT,
 257                                         src_w, crtc_w);
 258                 }
 259         }
 260
 261         if (src_h != crtc_h) {
 262                 uint32_t sel_unit = SCALE_FIR;
 263                 op_mode |= MDP4_PIPE_OP_MODE_SCALEY_EN;
 264
 265                 if (MDP_FORMAT_IS_YUV(format)) {
 266
 267                         if (crtc_h > src_h)
 268                                 sel_unit = SCALE_PIXEL_RPT;
 269                         else if (crtc_h <= (src_h / 4))
 270                                 sel_unit = SCALE_MN_PHASE;
 271
 272                         op_mode |= MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL(sel_unit);
 273                         phasey_step = mult_frac(MDP4_VG_PHASE_STEP_DEFAULT,
 274                                         src_h, crtc_h);
 275                 }
 276         }
 277
 278         mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_SIZE(pipe),
 279                         MDP4_PIPE_SRC_SIZE_WIDTH(src_w) |
 280                         MDP4_PIPE_SRC_SIZE_HEIGHT(src_h));
 281
 282         mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_XY(pipe),
 283                         MDP4_PIPE_SRC_XY_X(src_x) |
 284                         MDP4_PIPE_SRC_XY_Y(src_y));
 285
 286         mdp4_write(mdp4_kms, REG_MDP4_PIPE_DST_SIZE(pipe),
 287                         MDP4_PIPE_DST_SIZE_WIDTH(crtc_w) |
 288                         MDP4_PIPE_DST_SIZE_HEIGHT(crtc_h));
 289
 290         mdp4_write(mdp4_kms, REG_MDP4_PIPE_DST_XY(pipe),
 291                         MDP4_PIPE_DST_XY_X(crtc_x) |
 292                         MDP4_PIPE_DST_XY_Y(crtc_y));
 293
 294         mdp4_plane_set_scanout(plane, fb);
 295
 296         mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_FORMAT(pipe),
 297                         MDP4_PIPE_SRC_FORMAT_A_BPC(format->bpc_a) |
 298                         MDP4_PIPE_SRC_FORMAT_R_BPC(format->bpc_r) |
 299                         MDP4_PIPE_SRC_FORMAT_G_BPC(format->bpc_g) |
 300                         MDP4_PIPE_SRC_FORMAT_B_BPC(format->bpc_b) |
 301                         COND(format->alpha_enable, MDP4_PIPE_SRC_FORMAT_ALPHA_ENABLE) |
 302                         MDP4_PIPE_SRC_FORMAT_CPP(format->cpp - 1) |
 303                         MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT(format->unpack_count - 1) |
 304                         MDP4_PIPE_SRC_FORMAT_FETCH_PLANES(format->fetch_type) |
 305                         MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP(format->chroma_sample) |
 306                         MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT(frame_type) |
 307                         COND(format->unpack_tight, MDP4_PIPE_SRC_FORMAT_UNPACK_TIGHT));
 308
 309         mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_UNPACK(pipe),
 310                         MDP4_PIPE_SRC_UNPACK_ELEM0(format->unpack[0]) |
 311                         MDP4_PIPE_SRC_UNPACK_ELEM1(format->unpack[1]) |
 312                         MDP4_PIPE_SRC_UNPACK_ELEM2(format->unpack[2]) |
 313                         MDP4_PIPE_SRC_UNPACK_ELEM3(format->unpack[3]));
 314
 315         if (MDP_FORMAT_IS_YUV(format)) {
 316                 struct csc_cfg *csc = mdp_get_default_csc_cfg(CSC_YUV2RGB);
 317
 318                 op_mode |= MDP4_PIPE_OP_MODE_SRC_YCBCR;
 319                 op_mode |= MDP4_PIPE_OP_MODE_CSC_EN;
 320                 mdp4_write_csc_config(mdp4_kms, pipe, csc);
 321         }
 322
 323         mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(pipe), op_mode);
 324         mdp4_write(mdp4_kms, REG_MDP4_PIPE_PHASEX_STEP(pipe), phasex_step);
 325         mdp4_write(mdp4_kms, REG_MDP4_PIPE_PHASEY_STEP(pipe), phasey_step);
 326
 327         if (frame_type != FRAME_LINEAR)
 328                 mdp4_write(mdp4_kms, REG_MDP4_PIPE_SSTILE_FRAME_SIZE(pipe),
 329                                 MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH(src_w) |
 330                                 MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT(src_h));
 331
 332         return 0;
 333 }
 334
 335 static const char *pipe_names[] = {
 336                 "VG1", "VG2",
 337                 "RGB1", "RGB2", "RGB3",
 338                 "VG3", "VG4",
 339 };
 340
 341 enum mdp4_pipe mdp4_plane_pipe(struct drm_plane *plane)
 342 {
 343         struct mdp4_plane *mdp4_plane = to_mdp4_plane(plane);
 344         return mdp4_plane->pipe;
 345 }
 346
 347 /* initialize plane */
 348 struct drm_plane *mdp4_plane_init(struct drm_device *dev,
 349                 enum mdp4_pipe pipe_id, bool private_plane)
 350 {
 351         struct drm_plane *plane = NULL;
 352         struct mdp4_plane *mdp4_plane;
 353         int ret;
 354         enum drm_plane_type type;
 355
 356         mdp4_plane = kzalloc(sizeof(*mdp4_plane), GFP_KERNEL);
 357         if (!mdp4_plane) {
 358                 ret = -ENOMEM;
 359                 goto fail;
 360         }
 361
 362         plane = &mdp4_plane->base;
 363
 364         mdp4_plane->pipe = pipe_id;
 365         mdp4_plane->name = pipe_names[pipe_id];
 366         mdp4_plane->caps = mdp4_pipe_caps(pipe_id);
 367
 368         mdp4_plane->nformats = mdp_get_formats(mdp4_plane->formats,
 369                         ARRAY_SIZE(mdp4_plane->formats),
 370                         !pipe_supports_yuv(mdp4_plane->caps));
 371
 372         type = private_plane ? DRM_PLANE_TYPE_PRIMARY : DRM_PLANE_TYPE_OVERLAY;
 373         ret = drm_universal_plane_init(dev, plane, 0xff, &mdp4_plane_funcs,
 374                                  mdp4_plane->formats, mdp4_plane->nformats,
 375                                  NULL, type, NULL);
 376         if (ret)
 377                 goto fail;
 378
 379         drm_plane_helper_add(plane, &mdp4_plane_helper_funcs);
 380
 381         mdp4_plane_install_properties(plane, &plane->base);
 382
 383         return plane;
 384
 385 fail:
 386         if (plane)
 387                 mdp4_plane_destroy(plane);
 388
 389         return ERR_PTR(ret);
 390 }