drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c

   1 /*
   2  * Copyright (C) 2013 Red Hat
   3  * Author: Rob Clark <robdclark@gmail.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published by
   7  * the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include <drm/drm_crtc.h>
  19 #include <drm/drm_crtc_helper.h>
  20
  21 #include "mdp4_kms.h"
  22
  23 struct mdp4_dtv_encoder {
  24         struct drm_encoder base;
  25         struct clk *hdmi_clk;
  26         struct clk *mdp_clk;
  27         unsigned long int pixclock;
  28         bool enabled;
  29         uint32_t bsc;
  30 };
  31 #define to_mdp4_dtv_encoder(x) container_of(x, struct mdp4_dtv_encoder, base)
  32
  33 static struct mdp4_kms *get_kms(struct drm_encoder *encoder)
  34 {
  35         struct msm_drm_private *priv = encoder->dev->dev_private;
  36         return to_mdp4_kms(to_mdp_kms(priv->kms));
  37 }
  38
  39 #ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING
  40 #include <mach/board.h>
  41 /* not ironically named at all.. no, really.. */
  42 static void bs_init(struct mdp4_dtv_encoder *mdp4_dtv_encoder)
  43 {
  44         struct drm_device *dev = mdp4_dtv_encoder->base.dev;
  45         struct lcdc_platform_data *dtv_pdata = mdp4_find_pdata("dtv.0");
  46
  47         if (!dtv_pdata) {
  48                 DRM_DEV_ERROR(dev->dev, "could not find dtv pdata\n");
  49                 return;
  50         }
  51
  52         if (dtv_pdata->bus_scale_table) {
  53                 mdp4_dtv_encoder->bsc = msm_bus_scale_register_client(
  54                                 dtv_pdata->bus_scale_table);
  55                 DBG("bus scale client: %08x", mdp4_dtv_encoder->bsc);
  56                 DBG("lcdc_power_save: %p", dtv_pdata->lcdc_power_save);
  57                 if (dtv_pdata->lcdc_power_save)
  58                         dtv_pdata->lcdc_power_save(1);
  59         }
  60 }
  61
  62 static void bs_fini(struct mdp4_dtv_encoder *mdp4_dtv_encoder)
  63 {
  64         if (mdp4_dtv_encoder->bsc) {
  65                 msm_bus_scale_unregister_client(mdp4_dtv_encoder->bsc);
  66                 mdp4_dtv_encoder->bsc = 0;
  67         }
  68 }
  69
  70 static void bs_set(struct mdp4_dtv_encoder *mdp4_dtv_encoder, int idx)
  71 {
  72         if (mdp4_dtv_encoder->bsc) {
  73                 DBG("set bus scaling: %d", idx);
  74                 msm_bus_scale_client_update_request(mdp4_dtv_encoder->bsc, idx);
  75         }
  76 }
  77 #else
  78 static void bs_init(struct mdp4_dtv_encoder *mdp4_dtv_encoder) {}
  79 static void bs_fini(struct mdp4_dtv_encoder *mdp4_dtv_encoder) {}
  80 static void bs_set(struct mdp4_dtv_encoder *mdp4_dtv_encoder, int idx) {}
  81 #endif
  82
  83 static void mdp4_dtv_encoder_destroy(struct drm_encoder *encoder)
  84 {
  85         struct mdp4_dtv_encoder *mdp4_dtv_encoder = to_mdp4_dtv_encoder(encoder);
  86         bs_fini(mdp4_dtv_encoder);
  87         drm_encoder_cleanup(encoder);
  88         kfree(mdp4_dtv_encoder);
  89 }
  90
  91 static const struct drm_encoder_funcs mdp4_dtv_encoder_funcs = {
  92         .destroy = mdp4_dtv_encoder_destroy,
  93 };
  94
  95 static void mdp4_dtv_encoder_mode_set(struct drm_encoder *encoder,
  96                 struct drm_display_mode *mode,
  97                 struct drm_display_mode *adjusted_mode)
  98 {
  99         struct mdp4_dtv_encoder *mdp4_dtv_encoder = to_mdp4_dtv_encoder(encoder);
 100         struct mdp4_kms *mdp4_kms = get_kms(encoder);
 101         uint32_t dtv_hsync_skew, vsync_period, vsync_len, ctrl_pol;
 102         uint32_t display_v_start, display_v_end;
 103         uint32_t hsync_start_x, hsync_end_x;
 104
 105         mode = adjusted_mode;
 106
 107         DBG("set mode: " DRM_MODE_FMT, DRM_MODE_ARG(mode));
 108
 109         mdp4_dtv_encoder->pixclock = mode->clock * 1000;
 110
 111         DBG("pixclock=%lu", mdp4_dtv_encoder->pixclock);
 112
 113         ctrl_pol = 0;
 114         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 115                 ctrl_pol |= MDP4_DTV_CTRL_POLARITY_HSYNC_LOW;
 116         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 117                 ctrl_pol |= MDP4_DTV_CTRL_POLARITY_VSYNC_LOW;
 118         /* probably need to get DATA_EN polarity from panel.. */
 119
 120         dtv_hsync_skew = 0;  /* get this from panel? */
 121
 122         hsync_start_x = (mode->htotal - mode->hsync_start);
 123         hsync_end_x = mode->htotal - (mode->hsync_start - mode->hdisplay) - 1;
 124
 125         vsync_period = mode->vtotal * mode->htotal;
 126         vsync_len = (mode->vsync_end - mode->vsync_start) * mode->htotal;
 127         display_v_start = (mode->vtotal - mode->vsync_start) * mode->htotal + dtv_hsync_skew;
 128         display_v_end = vsync_period - ((mode->vsync_start - mode->vdisplay) * mode->htotal) + dtv_hsync_skew - 1;
 129
 130         mdp4_write(mdp4_kms, REG_MDP4_DTV_HSYNC_CTRL,
 131                         MDP4_DTV_HSYNC_CTRL_PULSEW(mode->hsync_end - mode->hsync_start) |
 132                         MDP4_DTV_HSYNC_CTRL_PERIOD(mode->htotal));
 133         mdp4_write(mdp4_kms, REG_MDP4_DTV_VSYNC_PERIOD, vsync_period);
 134         mdp4_write(mdp4_kms, REG_MDP4_DTV_VSYNC_LEN, vsync_len);
 135         mdp4_write(mdp4_kms, REG_MDP4_DTV_DISPLAY_HCTRL,
 136                         MDP4_DTV_DISPLAY_HCTRL_START(hsync_start_x) |
 137                         MDP4_DTV_DISPLAY_HCTRL_END(hsync_end_x));
 138         mdp4_write(mdp4_kms, REG_MDP4_DTV_DISPLAY_VSTART, display_v_start);
 139         mdp4_write(mdp4_kms, REG_MDP4_DTV_DISPLAY_VEND, display_v_end);
 140         mdp4_write(mdp4_kms, REG_MDP4_DTV_BORDER_CLR, 0);
 141         mdp4_write(mdp4_kms, REG_MDP4_DTV_UNDERFLOW_CLR,
 142                         MDP4_DTV_UNDERFLOW_CLR_ENABLE_RECOVERY |
 143                         MDP4_DTV_UNDERFLOW_CLR_COLOR(0xff));
 144         mdp4_write(mdp4_kms, REG_MDP4_DTV_HSYNC_SKEW, dtv_hsync_skew);
 145         mdp4_write(mdp4_kms, REG_MDP4_DTV_CTRL_POLARITY, ctrl_pol);
 146         mdp4_write(mdp4_kms, REG_MDP4_DTV_ACTIVE_HCTL,
 147                         MDP4_DTV_ACTIVE_HCTL_START(0) |
 148                         MDP4_DTV_ACTIVE_HCTL_END(0));
 149         mdp4_write(mdp4_kms, REG_MDP4_DTV_ACTIVE_VSTART, 0);
 150         mdp4_write(mdp4_kms, REG_MDP4_DTV_ACTIVE_VEND, 0);
 151 }
 152
 153 static void mdp4_dtv_encoder_disable(struct drm_encoder *encoder)
 154 {
 155         struct mdp4_dtv_encoder *mdp4_dtv_encoder = to_mdp4_dtv_encoder(encoder);
 156         struct mdp4_kms *mdp4_kms = get_kms(encoder);
 157
 158         if (WARN_ON(!mdp4_dtv_encoder->enabled))
 159                 return;
 160
 161         mdp4_write(mdp4_kms, REG_MDP4_DTV_ENABLE, 0);
 162
 163         /*
 164          * Wait for a vsync so we know the ENABLE=0 latched before
 165          * the (connector) source of the vsync's gets disabled,
 166          * otherwise we end up in a funny state if we re-enable
 167          * before the disable latches, which results that some of
 168          * the settings changes for the new modeset (like new
 169          * scanout buffer) don't latch properly..
 170          */
 171         mdp_irq_wait(&mdp4_kms->base, MDP4_IRQ_EXTERNAL_VSYNC);
 172
 173         clk_disable_unprepare(mdp4_dtv_encoder->hdmi_clk);
 174         clk_disable_unprepare(mdp4_dtv_encoder->mdp_clk);
 175
 176         bs_set(mdp4_dtv_encoder, 0);
 177
 178         mdp4_dtv_encoder->enabled = false;
 179 }
 180
 181 static void mdp4_dtv_encoder_enable(struct drm_encoder *encoder)
 182 {
 183         struct drm_device *dev = encoder->dev;
 184         struct mdp4_dtv_encoder *mdp4_dtv_encoder = to_mdp4_dtv_encoder(encoder);
 185         struct mdp4_kms *mdp4_kms = get_kms(encoder);
 186         unsigned long pc = mdp4_dtv_encoder->pixclock;
 187         int ret;
 188
 189         if (WARN_ON(mdp4_dtv_encoder->enabled))
 190                 return;
 191
 192         mdp4_crtc_set_config(encoder->crtc,
 193                         MDP4_DMA_CONFIG_R_BPC(BPC8) |
 194                         MDP4_DMA_CONFIG_G_BPC(BPC8) |
 195                         MDP4_DMA_CONFIG_B_BPC(BPC8) |
 196                         MDP4_DMA_CONFIG_PACK(0x21));
 197         mdp4_crtc_set_intf(encoder->crtc, INTF_LCDC_DTV, 1);
 198
 199         bs_set(mdp4_dtv_encoder, 1);
 200
 201         DBG("setting mdp_clk=%lu", pc);
 202
 203         ret = clk_set_rate(mdp4_dtv_encoder->mdp_clk, pc);
 204         if (ret)
 205                 DRM_DEV_ERROR(dev->dev, "failed to set mdp_clk to %lu: %d\n",
 206                         pc, ret);
 207
 208         ret = clk_prepare_enable(mdp4_dtv_encoder->mdp_clk);
 209         if (ret)
 210                 DRM_DEV_ERROR(dev->dev, "failed to enabled mdp_clk: %d\n", ret);
 211
 212         ret = clk_prepare_enable(mdp4_dtv_encoder->hdmi_clk);
 213         if (ret)
 214                 DRM_DEV_ERROR(dev->dev, "failed to enable hdmi_clk: %d\n", ret);
 215
 216         mdp4_write(mdp4_kms, REG_MDP4_DTV_ENABLE, 1);
 217
 218         mdp4_dtv_encoder->enabled = true;
 219 }
 220
 221 static const struct drm_encoder_helper_funcs mdp4_dtv_encoder_helper_funcs = {
 222         .mode_set = mdp4_dtv_encoder_mode_set,
 223         .enable = mdp4_dtv_encoder_enable,
 224         .disable = mdp4_dtv_encoder_disable,
 225 };
 226
 227 long mdp4_dtv_round_pixclk(struct drm_encoder *encoder, unsigned long rate)
 228 {
 229         struct mdp4_dtv_encoder *mdp4_dtv_encoder = to_mdp4_dtv_encoder(encoder);
 230         return clk_round_rate(mdp4_dtv_encoder->mdp_clk, rate);
 231 }
 232
 233 /* initialize encoder */
 234 struct drm_encoder *mdp4_dtv_encoder_init(struct drm_device *dev)
 235 {
 236         struct drm_encoder *encoder = NULL;
 237         struct mdp4_dtv_encoder *mdp4_dtv_encoder;
 238         int ret;
 239
 240         mdp4_dtv_encoder = kzalloc(sizeof(*mdp4_dtv_encoder), GFP_KERNEL);
 241         if (!mdp4_dtv_encoder) {
 242                 ret = -ENOMEM;
 243                 goto fail;
 244         }
 245
 246         encoder = &mdp4_dtv_encoder->base;
 247
 248         drm_encoder_init(dev, encoder, &mdp4_dtv_encoder_funcs,
 249                          DRM_MODE_ENCODER_TMDS, NULL);
 250         drm_encoder_helper_add(encoder, &mdp4_dtv_encoder_helper_funcs);
 251
 252         mdp4_dtv_encoder->hdmi_clk = devm_clk_get(dev->dev, "hdmi_clk");
 253         if (IS_ERR(mdp4_dtv_encoder->hdmi_clk)) {
 254                 DRM_DEV_ERROR(dev->dev, "failed to get hdmi_clk\n");
 255                 ret = PTR_ERR(mdp4_dtv_encoder->hdmi_clk);
 256                 goto fail;
 257         }
 258
 259         mdp4_dtv_encoder->mdp_clk = devm_clk_get(dev->dev, "tv_clk");
 260         if (IS_ERR(mdp4_dtv_encoder->mdp_clk)) {
 261                 DRM_DEV_ERROR(dev->dev, "failed to get tv_clk\n");
 262                 ret = PTR_ERR(mdp4_dtv_encoder->mdp_clk);
 263                 goto fail;
 264         }
 265
 266         bs_init(mdp4_dtv_encoder);
 267
 268         return encoder;
 269
 270 fail:
 271         if (encoder)
 272                 mdp4_dtv_encoder_destroy(encoder);
 273
 274         return ERR_PTR(ret);
 275 }