drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c

   1 /*
   2  * Copyright (C) 2013 Red Hat
   3  * Author: Rob Clark <robdclark@gmail.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published by
   7  * the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include <drm/drm_crtc.h>
  19 #include <drm/drm_crtc_helper.h>
  20 #include <drm/drm_flip_work.h>
  21 #include <drm/drm_mode.h>
  22
  23 #include "mdp4_kms.h"
  24
  25 struct mdp4_crtc {
  26         struct drm_crtc base;
  27         char name[8];
  28         int id;
  29         int ovlp;
  30         enum mdp4_dma dma;
  31         bool enabled;
  32
  33         /* which mixer/encoder we route output to: */
  34         int mixer;
  35
  36         struct {
  37                 spinlock_t lock;
  38                 bool stale;
  39                 uint32_t width, height;
  40                 uint32_t x, y;
  41
  42                 /* next cursor to scan-out: */
  43                 uint32_t next_iova;
  44                 struct drm_gem_object *next_bo;
  45
  46                 /* current cursor being scanned out: */
  47                 struct drm_gem_object *scanout_bo;
  48         } cursor;
  49
  50
  51         /* if there is a pending flip, these will be non-null: */
  52         struct drm_pending_vblank_event *event;
  53
  54         /* Bits have been flushed at the last commit,
  55          * used to decide if a vsync has happened since last commit.
  56          */
  57         u32 flushed_mask;
  58
  59 #define PENDING_CURSOR 0x1
  60 #define PENDING_FLIP   0x2
  61         atomic_t pending;
  62
  63         /* for unref'ing cursor bo's after scanout completes: */
  64         struct drm_flip_work unref_cursor_work;
  65
  66         struct mdp_irq vblank;
  67         struct mdp_irq err;
  68 };
  69 #define to_mdp4_crtc(x) container_of(x, struct mdp4_crtc, base)
  70
  71 static struct mdp4_kms *get_kms(struct drm_crtc *crtc)
  72 {
  73         struct msm_drm_private *priv = crtc->dev->dev_private;
  74         return to_mdp4_kms(to_mdp_kms(priv->kms));
  75 }
  76
  77 static void request_pending(struct drm_crtc *crtc, uint32_t pending)
  78 {
  79         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
  80
  81         atomic_or(pending, &mdp4_crtc->pending);
  82         mdp_irq_register(&get_kms(crtc)->base, &mdp4_crtc->vblank);
  83 }
  84
  85 static void crtc_flush(struct drm_crtc *crtc)
  86 {
  87         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
  88         struct mdp4_kms *mdp4_kms = get_kms(crtc);
  89         struct drm_plane *plane;
  90         uint32_t flush = 0;
  91
  92         drm_atomic_crtc_for_each_plane(plane, crtc) {
  93                 enum mdp4_pipe pipe_id = mdp4_plane_pipe(plane);
  94                 flush |= pipe2flush(pipe_id);
  95         }
  96
  97         flush |= ovlp2flush(mdp4_crtc->ovlp);
  98
  99         DBG("%s: flush=%08x", mdp4_crtc->name, flush);
 100
 101         mdp4_crtc->flushed_mask = flush;
 102
 103         mdp4_write(mdp4_kms, REG_MDP4_OVERLAY_FLUSH, flush);
 104 }
 105
 106 /* if file!=NULL, this is preclose potential cancel-flip path */
 107 static void complete_flip(struct drm_crtc *crtc, struct drm_file *file)
 108 {
 109         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
 110         struct drm_device *dev = crtc->dev;
 111         struct drm_pending_vblank_event *event;
 112         unsigned long flags;
 113
 114         spin_lock_irqsave(&dev->event_lock, flags);
 115         event = mdp4_crtc->event;
 116         if (event) {
 117                 mdp4_crtc->event = NULL;
 118                 DBG("%s: send event: %p", mdp4_crtc->name, event);
 119                 drm_crtc_send_vblank_event(crtc, event);
 120         }
 121         spin_unlock_irqrestore(&dev->event_lock, flags);
 122 }
 123
 124 static void unref_cursor_worker(struct drm_flip_work *work, void *val)
 125 {
 126         struct mdp4_crtc *mdp4_crtc =
 127                 container_of(work, struct mdp4_crtc, unref_cursor_work);
 128         struct mdp4_kms *mdp4_kms = get_kms(&mdp4_crtc->base);
 129         struct msm_kms *kms = &mdp4_kms->base.base;
 130
 131         msm_gem_unpin_iova(val, kms->aspace);
 132         drm_gem_object_put_unlocked(val);
 133 }
 134
 135 static void mdp4_crtc_destroy(struct drm_crtc *crtc)
 136 {
 137         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
 138
 139         drm_crtc_cleanup(crtc);
 140         drm_flip_work_cleanup(&mdp4_crtc->unref_cursor_work);
 141
 142         kfree(mdp4_crtc);
 143 }
 144
 145 /* statically (for now) map planes to mixer stage (z-order): */
 146 static const int idxs[] = {
 147                 [VG1]  = 1,
 148                 [VG2]  = 2,
 149                 [RGB1] = 0,
 150                 [RGB2] = 0,
 151                 [RGB3] = 0,
 152                 [VG3]  = 3,
 153                 [VG4]  = 4,
 154
 155 };
 156
 157 /* setup mixer config, for which we need to consider all crtc's and
 158  * the planes attached to them
 159  *
 160  * TODO may possibly need some extra locking here
 161  */
 162 static void setup_mixer(struct mdp4_kms *mdp4_kms)
 163 {
 164         struct drm_mode_config *config = &mdp4_kms->dev->mode_config;
 165         struct drm_crtc *crtc;
 166         uint32_t mixer_cfg = 0;
 167         static const enum mdp_mixer_stage_id stages[] = {
 168                         STAGE_BASE, STAGE0, STAGE1, STAGE2, STAGE3,
 169         };
 170
 171         list_for_each_entry(crtc, &config->crtc_list, head) {
 172                 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
 173                 struct drm_plane *plane;
 174
 175                 drm_atomic_crtc_for_each_plane(plane, crtc) {
 176                         enum mdp4_pipe pipe_id = mdp4_plane_pipe(plane);
 177                         int idx = idxs[pipe_id];
 178                         mixer_cfg = mixercfg(mixer_cfg, mdp4_crtc->mixer,
 179                                         pipe_id, stages[idx]);
 180                 }
 181         }
 182
 183         mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG, mixer_cfg);
 184 }
 185
 186 static void blend_setup(struct drm_crtc *crtc)
 187 {
 188         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
 189         struct mdp4_kms *mdp4_kms = get_kms(crtc);
 190         struct drm_plane *plane;
 191         int i, ovlp = mdp4_crtc->ovlp;
 192         bool alpha[4]= { false, false, false, false };
 193
 194         mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_LOW0(ovlp), 0);
 195         mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_LOW1(ovlp), 0);
 196         mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_HIGH0(ovlp), 0);
 197         mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_HIGH1(ovlp), 0);
 198
 199         drm_atomic_crtc_for_each_plane(plane, crtc) {
 200                 enum mdp4_pipe pipe_id = mdp4_plane_pipe(plane);
 201                 int idx = idxs[pipe_id];
 202                 if (idx > 0) {
 203                         const struct mdp_format *format =
 204                                         to_mdp_format(msm_framebuffer_format(plane->state->fb));
 205                         alpha[idx-1] = format->alpha_enable;
 206                 }
 207         }
 208
 209         for (i = 0; i < 4; i++) {
 210                 uint32_t op;
 211
 212                 if (alpha[i]) {
 213                         op = MDP4_OVLP_STAGE_OP_FG_ALPHA(FG_PIXEL) |
 214                                         MDP4_OVLP_STAGE_OP_BG_ALPHA(FG_PIXEL) |
 215                                         MDP4_OVLP_STAGE_OP_BG_INV_ALPHA;
 216                 } else {
 217                         op = MDP4_OVLP_STAGE_OP_FG_ALPHA(FG_CONST) |
 218                                         MDP4_OVLP_STAGE_OP_BG_ALPHA(BG_CONST);
 219                 }
 220
 221                 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_FG_ALPHA(ovlp, i), 0xff);
 222                 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_BG_ALPHA(ovlp, i), 0x00);
 223                 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_OP(ovlp, i), op);
 224                 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_CO3(ovlp, i), 1);
 225                 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_LOW0(ovlp, i), 0);
 226                 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_LOW1(ovlp, i), 0);
 227                 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_HIGH0(ovlp, i), 0);
 228                 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_HIGH1(ovlp, i), 0);
 229         }
 230
 231         setup_mixer(mdp4_kms);
 232 }
 233
 234 static void mdp4_crtc_mode_set_nofb(struct drm_crtc *crtc)
 235 {
 236         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
 237         struct mdp4_kms *mdp4_kms = get_kms(crtc);
 238         enum mdp4_dma dma = mdp4_crtc->dma;
 239         int ovlp = mdp4_crtc->ovlp;
 240         struct drm_display_mode *mode;
 241
 242         if (WARN_ON(!crtc->state))
 243                 return;
 244
 245         mode = &crtc->state->adjusted_mode;
 246
 247         DBG("%s: set mode: " DRM_MODE_FMT,
 248                         mdp4_crtc->name, DRM_MODE_ARG(mode));
 249
 250         mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_SIZE(dma),
 251                         MDP4_DMA_SRC_SIZE_WIDTH(mode->hdisplay) |
 252                         MDP4_DMA_SRC_SIZE_HEIGHT(mode->vdisplay));
 253
 254         /* take data from pipe: */
 255         mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_BASE(dma), 0);
 256         mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_STRIDE(dma), 0);
 257         mdp4_write(mdp4_kms, REG_MDP4_DMA_DST_SIZE(dma),
 258                         MDP4_DMA_DST_SIZE_WIDTH(0) |
 259                         MDP4_DMA_DST_SIZE_HEIGHT(0));
 260
 261         mdp4_write(mdp4_kms, REG_MDP4_OVLP_BASE(ovlp), 0);
 262         mdp4_write(mdp4_kms, REG_MDP4_OVLP_SIZE(ovlp),
 263                         MDP4_OVLP_SIZE_WIDTH(mode->hdisplay) |
 264                         MDP4_OVLP_SIZE_HEIGHT(mode->vdisplay));
 265         mdp4_write(mdp4_kms, REG_MDP4_OVLP_STRIDE(ovlp), 0);
 266
 267         mdp4_write(mdp4_kms, REG_MDP4_OVLP_CFG(ovlp), 1);
 268
 269         if (dma == DMA_E) {
 270                 mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(0), 0x00ff0000);
 271                 mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(1), 0x00ff0000);
 272                 mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(2), 0x00ff0000);
 273         }
 274 }
 275
 276 static void mdp4_crtc_atomic_disable(struct drm_crtc *crtc,
 277                                      struct drm_crtc_state *old_state)
 278 {
 279         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
 280         struct mdp4_kms *mdp4_kms = get_kms(crtc);
 281
 282         DBG("%s", mdp4_crtc->name);
 283
 284         if (WARN_ON(!mdp4_crtc->enabled))
 285                 return;
 286
 287         /* Disable/save vblank irq handling before power is disabled */
 288         drm_crtc_vblank_off(crtc);
 289
 290         mdp_irq_unregister(&mdp4_kms->base, &mdp4_crtc->err);
 291         mdp4_disable(mdp4_kms);
 292
 293         mdp4_crtc->enabled = false;
 294 }
 295
 296 static void mdp4_crtc_atomic_enable(struct drm_crtc *crtc,
 297                                     struct drm_crtc_state *old_state)
 298 {
 299         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
 300         struct mdp4_kms *mdp4_kms = get_kms(crtc);
 301
 302         DBG("%s", mdp4_crtc->name);
 303
 304         if (WARN_ON(mdp4_crtc->enabled))
 305                 return;
 306
 307         mdp4_enable(mdp4_kms);
 308
 309         /* Restore vblank irq handling after power is enabled */
 310         drm_crtc_vblank_on(crtc);
 311
 312         mdp_irq_register(&mdp4_kms->base, &mdp4_crtc->err);
 313
 314         crtc_flush(crtc);
 315
 316         mdp4_crtc->enabled = true;
 317 }
 318
 319 static int mdp4_crtc_atomic_check(struct drm_crtc *crtc,
 320                 struct drm_crtc_state *state)
 321 {
 322         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
 323         DBG("%s: check", mdp4_crtc->name);
 324         // TODO anything else to check?
 325         return 0;
 326 }
 327
 328 static void mdp4_crtc_atomic_begin(struct drm_crtc *crtc,
 329                                    struct drm_crtc_state *old_crtc_state)
 330 {
 331         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
 332         DBG("%s: begin", mdp4_crtc->name);
 333 }
 334
 335 static void mdp4_crtc_atomic_flush(struct drm_crtc *crtc,
 336                                    struct drm_crtc_state *old_crtc_state)
 337 {
 338         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
 339         struct drm_device *dev = crtc->dev;
 340         unsigned long flags;
 341
 342         DBG("%s: event: %p", mdp4_crtc->name, crtc->state->event);
 343
 344         WARN_ON(mdp4_crtc->event);
 345
 346         spin_lock_irqsave(&dev->event_lock, flags);
 347         mdp4_crtc->event = crtc->state->event;
 348         crtc->state->event = NULL;
 349         spin_unlock_irqrestore(&dev->event_lock, flags);
 350
 351         blend_setup(crtc);
 352         crtc_flush(crtc);
 353         request_pending(crtc, PENDING_FLIP);
 354 }
 355
 356 #define CURSOR_WIDTH 64
 357 #define CURSOR_HEIGHT 64
 358
 359 /* called from IRQ to update cursor related registers (if needed).  The
 360  * cursor registers, other than x/y position, appear not to be double
 361  * buffered, and changing them other than from vblank seems to trigger
 362  * underflow.
 363  */
 364 static void update_cursor(struct drm_crtc *crtc)
 365 {
 366         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
 367         struct mdp4_kms *mdp4_kms = get_kms(crtc);
 368         struct msm_kms *kms = &mdp4_kms->base.base;
 369         enum mdp4_dma dma = mdp4_crtc->dma;
 370         unsigned long flags;
 371
 372         spin_lock_irqsave(&mdp4_crtc->cursor.lock, flags);
 373         if (mdp4_crtc->cursor.stale) {
 374                 struct drm_gem_object *next_bo = mdp4_crtc->cursor.next_bo;
 375                 struct drm_gem_object *prev_bo = mdp4_crtc->cursor.scanout_bo;
 376                 uint64_t iova = mdp4_crtc->cursor.next_iova;
 377
 378                 if (next_bo) {
 379                         /* take a obj ref + iova ref when we start scanning out: */
 380                         drm_gem_object_get(next_bo);
 381                         msm_gem_get_and_pin_iova(next_bo, kms->aspace, &iova);
 382
 383                         /* enable cursor: */
 384                         mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_SIZE(dma),
 385                                         MDP4_DMA_CURSOR_SIZE_WIDTH(mdp4_crtc->cursor.width) |
 386                                         MDP4_DMA_CURSOR_SIZE_HEIGHT(mdp4_crtc->cursor.height));
 387                         mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BASE(dma), iova);
 388                         mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BLEND_CONFIG(dma),
 389                                         MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT(CURSOR_ARGB) |
 390                                         MDP4_DMA_CURSOR_BLEND_CONFIG_CURSOR_EN);
 391                 } else {
 392                         /* disable cursor: */
 393                         mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BASE(dma),
 394                                         mdp4_kms->blank_cursor_iova);
 395                 }
 396
 397                 /* and drop the iova ref + obj rev when done scanning out: */
 398                 if (prev_bo)
 399                         drm_flip_work_queue(&mdp4_crtc->unref_cursor_work, prev_bo);
 400
 401                 mdp4_crtc->cursor.scanout_bo = next_bo;
 402                 mdp4_crtc->cursor.stale = false;
 403         }
 404
 405         mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_POS(dma),
 406                         MDP4_DMA_CURSOR_POS_X(mdp4_crtc->cursor.x) |
 407                         MDP4_DMA_CURSOR_POS_Y(mdp4_crtc->cursor.y));
 408
 409         spin_unlock_irqrestore(&mdp4_crtc->cursor.lock, flags);
 410 }
 411
 412 static int mdp4_crtc_cursor_set(struct drm_crtc *crtc,
 413                 struct drm_file *file_priv, uint32_t handle,
 414                 uint32_t width, uint32_t height)
 415 {
 416         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
 417         struct mdp4_kms *mdp4_kms = get_kms(crtc);
 418         struct msm_kms *kms = &mdp4_kms->base.base;
 419         struct drm_device *dev = crtc->dev;
 420         struct drm_gem_object *cursor_bo, *old_bo;
 421         unsigned long flags;
 422         uint64_t iova;
 423         int ret;
 424
 425         if ((width > CURSOR_WIDTH) || (height > CURSOR_HEIGHT)) {
 426                 DRM_DEV_ERROR(dev->dev, "bad cursor size: %dx%d\n", width, height);
 427                 return -EINVAL;
 428         }
 429
 430         if (handle) {
 431                 cursor_bo = drm_gem_object_lookup(file_priv, handle);
 432                 if (!cursor_bo)
 433                         return -ENOENT;
 434         } else {
 435                 cursor_bo = NULL;
 436         }
 437
 438         if (cursor_bo) {
 439                 ret = msm_gem_get_and_pin_iova(cursor_bo, kms->aspace, &iova);
 440                 if (ret)
 441                         goto fail;
 442         } else {
 443                 iova = 0;
 444         }
 445
 446         spin_lock_irqsave(&mdp4_crtc->cursor.lock, flags);
 447         old_bo = mdp4_crtc->cursor.next_bo;
 448         mdp4_crtc->cursor.next_bo   = cursor_bo;
 449         mdp4_crtc->cursor.next_iova = iova;
 450         mdp4_crtc->cursor.width     = width;
 451         mdp4_crtc->cursor.height    = height;
 452         mdp4_crtc->cursor.stale     = true;
 453         spin_unlock_irqrestore(&mdp4_crtc->cursor.lock, flags);
 454
 455         if (old_bo) {
 456                 /* drop our previous reference: */
 457                 drm_flip_work_queue(&mdp4_crtc->unref_cursor_work, old_bo);
 458         }
 459
 460         request_pending(crtc, PENDING_CURSOR);
 461
 462         return 0;
 463
 464 fail:
 465         drm_gem_object_put_unlocked(cursor_bo);
 466         return ret;
 467 }
 468
 469 static int mdp4_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
 470 {
 471         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
 472         unsigned long flags;
 473
 474         spin_lock_irqsave(&mdp4_crtc->cursor.lock, flags);
 475         mdp4_crtc->cursor.x = x;
 476         mdp4_crtc->cursor.y = y;
 477         spin_unlock_irqrestore(&mdp4_crtc->cursor.lock, flags);
 478
 479         crtc_flush(crtc);
 480         request_pending(crtc, PENDING_CURSOR);
 481
 482         return 0;
 483 }
 484
 485 static const struct drm_crtc_funcs mdp4_crtc_funcs = {
 486         .set_config = drm_atomic_helper_set_config,
 487         .destroy = mdp4_crtc_destroy,
 488         .page_flip = drm_atomic_helper_page_flip,
 489         .cursor_set = mdp4_crtc_cursor_set,
 490         .cursor_move = mdp4_crtc_cursor_move,
 491         .reset = drm_atomic_helper_crtc_reset,
 492         .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
 493         .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
 494 };
 495
 496 static const struct drm_crtc_helper_funcs mdp4_crtc_helper_funcs = {
 497         .mode_set_nofb = mdp4_crtc_mode_set_nofb,
 498         .atomic_check = mdp4_crtc_atomic_check,
 499         .atomic_begin = mdp4_crtc_atomic_begin,
 500         .atomic_flush = mdp4_crtc_atomic_flush,
 501         .atomic_enable = mdp4_crtc_atomic_enable,
 502         .atomic_disable = mdp4_crtc_atomic_disable,
 503 };
 504
 505 static void mdp4_crtc_vblank_irq(struct mdp_irq *irq, uint32_t irqstatus)
 506 {
 507         struct mdp4_crtc *mdp4_crtc = container_of(irq, struct mdp4_crtc, vblank);
 508         struct drm_crtc *crtc = &mdp4_crtc->base;
 509         struct msm_drm_private *priv = crtc->dev->dev_private;
 510         unsigned pending;
 511
 512         mdp_irq_unregister(&get_kms(crtc)->base, &mdp4_crtc->vblank);
 513
 514         pending = atomic_xchg(&mdp4_crtc->pending, 0);
 515
 516         if (pending & PENDING_FLIP) {
 517                 complete_flip(crtc, NULL);
 518         }
 519
 520         if (pending & PENDING_CURSOR) {
 521                 update_cursor(crtc);
 522                 drm_flip_work_commit(&mdp4_crtc->unref_cursor_work, priv->wq);
 523         }
 524 }
 525
 526 static void mdp4_crtc_err_irq(struct mdp_irq *irq, uint32_t irqstatus)
 527 {
 528         struct mdp4_crtc *mdp4_crtc = container_of(irq, struct mdp4_crtc, err);
 529         struct drm_crtc *crtc = &mdp4_crtc->base;
 530         DBG("%s: error: %08x", mdp4_crtc->name, irqstatus);
 531         crtc_flush(crtc);
 532 }
 533
 534 static void mdp4_crtc_wait_for_flush_done(struct drm_crtc *crtc)
 535 {
 536         struct drm_device *dev = crtc->dev;
 537         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
 538         struct mdp4_kms *mdp4_kms = get_kms(crtc);
 539         int ret;
 540
 541         ret = drm_crtc_vblank_get(crtc);
 542         if (ret)
 543                 return;
 544
 545         ret = wait_event_timeout(dev->vblank[drm_crtc_index(crtc)].queue,
 546                 !(mdp4_read(mdp4_kms, REG_MDP4_OVERLAY_FLUSH) &
 547                         mdp4_crtc->flushed_mask),
 548                 msecs_to_jiffies(50));
 549         if (ret <= 0)
 550                 dev_warn(dev->dev, "vblank time out, crtc=%d\n", mdp4_crtc->id);
 551
 552         mdp4_crtc->flushed_mask = 0;
 553
 554         drm_crtc_vblank_put(crtc);
 555 }
 556
 557 uint32_t mdp4_crtc_vblank(struct drm_crtc *crtc)
 558 {
 559         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
 560         return mdp4_crtc->vblank.irqmask;
 561 }
 562
 563 /* set dma config, ie. the format the encoder wants. */
 564 void mdp4_crtc_set_config(struct drm_crtc *crtc, uint32_t config)
 565 {
 566         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
 567         struct mdp4_kms *mdp4_kms = get_kms(crtc);
 568
 569         mdp4_write(mdp4_kms, REG_MDP4_DMA_CONFIG(mdp4_crtc->dma), config);
 570 }
 571
 572 /* set interface for routing crtc->encoder: */
 573 void mdp4_crtc_set_intf(struct drm_crtc *crtc, enum mdp4_intf intf, int mixer)
 574 {
 575         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
 576         struct mdp4_kms *mdp4_kms = get_kms(crtc);
 577         uint32_t intf_sel;
 578
 579         intf_sel = mdp4_read(mdp4_kms, REG_MDP4_DISP_INTF_SEL);
 580
 581         switch (mdp4_crtc->dma) {
 582         case DMA_P:
 583                 intf_sel &= ~MDP4_DISP_INTF_SEL_PRIM__MASK;
 584                 intf_sel |= MDP4_DISP_INTF_SEL_PRIM(intf);
 585                 break;
 586         case DMA_S:
 587                 intf_sel &= ~MDP4_DISP_INTF_SEL_SEC__MASK;
 588                 intf_sel |= MDP4_DISP_INTF_SEL_SEC(intf);
 589                 break;
 590         case DMA_E:
 591                 intf_sel &= ~MDP4_DISP_INTF_SEL_EXT__MASK;
 592                 intf_sel |= MDP4_DISP_INTF_SEL_EXT(intf);
 593                 break;
 594         }
 595
 596         if (intf == INTF_DSI_VIDEO) {
 597                 intf_sel &= ~MDP4_DISP_INTF_SEL_DSI_CMD;
 598                 intf_sel |= MDP4_DISP_INTF_SEL_DSI_VIDEO;
 599         } else if (intf == INTF_DSI_CMD) {
 600                 intf_sel &= ~MDP4_DISP_INTF_SEL_DSI_VIDEO;
 601                 intf_sel |= MDP4_DISP_INTF_SEL_DSI_CMD;
 602         }
 603
 604         mdp4_crtc->mixer = mixer;
 605
 606         blend_setup(crtc);
 607
 608         DBG("%s: intf_sel=%08x", mdp4_crtc->name, intf_sel);
 609
 610         mdp4_write(mdp4_kms, REG_MDP4_DISP_INTF_SEL, intf_sel);
 611 }
 612
 613 void mdp4_crtc_wait_for_commit_done(struct drm_crtc *crtc)
 614 {
 615         /* wait_for_flush_done is the only case for now.
 616          * Later we will have command mode CRTC to wait for
 617          * other event.
 618          */
 619         mdp4_crtc_wait_for_flush_done(crtc);
 620 }
 621
 622 static const char *dma_names[] = {
 623                 "DMA_P", "DMA_S", "DMA_E",
 624 };
 625
 626 /* initialize crtc */
 627 struct drm_crtc *mdp4_crtc_init(struct drm_device *dev,
 628                 struct drm_plane *plane, int id, int ovlp_id,
 629                 enum mdp4_dma dma_id)
 630 {
 631         struct drm_crtc *crtc = NULL;
 632         struct mdp4_crtc *mdp4_crtc;
 633
 634         mdp4_crtc = kzalloc(sizeof(*mdp4_crtc), GFP_KERNEL);
 635         if (!mdp4_crtc)
 636                 return ERR_PTR(-ENOMEM);
 637
 638         crtc = &mdp4_crtc->base;
 639
 640         mdp4_crtc->id = id;
 641
 642         mdp4_crtc->ovlp = ovlp_id;
 643         mdp4_crtc->dma = dma_id;
 644
 645         mdp4_crtc->vblank.irqmask = dma2irq(mdp4_crtc->dma);
 646         mdp4_crtc->vblank.irq = mdp4_crtc_vblank_irq;
 647
 648         mdp4_crtc->err.irqmask = dma2err(mdp4_crtc->dma);
 649         mdp4_crtc->err.irq = mdp4_crtc_err_irq;
 650
 651         snprintf(mdp4_crtc->name, sizeof(mdp4_crtc->name), "%s:%d",
 652                         dma_names[dma_id], ovlp_id);
 653
 654         spin_lock_init(&mdp4_crtc->cursor.lock);
 655
 656         drm_flip_work_init(&mdp4_crtc->unref_cursor_work,
 657                         "unref cursor", unref_cursor_worker);
 658
 659         drm_crtc_init_with_planes(dev, crtc, plane, NULL, &mdp4_crtc_funcs,
 660                                   NULL);
 661         drm_crtc_helper_add(crtc, &mdp4_crtc_helper_funcs);
 662
 663         return crtc;
 664 }