2 * Copyright (C) 2014-2018 The Linux Foundation. All rights reserved.
3 * Copyright (C) 2013 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published by
8 * the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
19 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
21 #include <linux/debugfs.h>
22 #include <linux/dma-buf.h>
24 #include <drm/drm_atomic_uapi.h>
28 #include "dpu_formats.h"
29 #include "dpu_hw_sspp.h"
30 #include "dpu_hw_catalog_format.h"
31 #include "dpu_trace.h"
34 #include "dpu_plane.h"
36 #define DPU_DEBUG_PLANE(pl, fmt, ...) DPU_DEBUG("plane%d " fmt,\
37 (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
39 #define DPU_ERROR_PLANE(pl, fmt, ...) DPU_ERROR("plane%d " fmt,\
40 (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
42 #define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci))
43 #define PHASE_STEP_SHIFT 21
44 #define PHASE_STEP_UNIT_SCALE ((int) (1 << PHASE_STEP_SHIFT))
45 #define PHASE_RESIDUAL 15
47 #define SHARP_STRENGTH_DEFAULT 32
48 #define SHARP_EDGE_THR_DEFAULT 112
49 #define SHARP_SMOOTH_THR_DEFAULT 8
50 #define SHARP_NOISE_THR_DEFAULT 2
52 #define DPU_NAME_SIZE 12
54 #define DPU_PLANE_COLOR_FILL_FLAG BIT(31)
55 #define DPU_ZPOS_MAX 255
57 /* multirect rect index */
64 #define DPU_QSEED3_DEFAULT_PRELOAD_H 0x4
65 #define DPU_QSEED3_DEFAULT_PRELOAD_V 0x3
67 #define DEFAULT_REFRESH_RATE 60
70 * enum dpu_plane_qos - Different qos configurations for each pipe
72 * @DPU_PLANE_QOS_VBLANK_CTRL: Setup VBLANK qos for the pipe.
73 * @DPU_PLANE_QOS_VBLANK_AMORTIZE: Enables Amortization within pipe.
74 * this configuration is mutually exclusive from VBLANK_CTRL.
75 * @DPU_PLANE_QOS_PANIC_CTRL: Setup panic for the pipe.
78 DPU_PLANE_QOS_VBLANK_CTRL = BIT(0),
79 DPU_PLANE_QOS_VBLANK_AMORTIZE = BIT(1),
80 DPU_PLANE_QOS_PANIC_CTRL = BIT(2),
84 * struct dpu_plane - local dpu plane structure
85 * @aspace: address space pointer
86 * @csc_ptr: Points to dpu_csc_cfg structure to use for current
87 * @mplane_list: List of multirect planes of the same pipe
88 * @catalog: Points to dpu catalog structure
89 * @revalidate: force revalidation of all the plane properties
92 struct drm_plane base;
97 uint32_t features; /* capabilities from catalog */
99 struct dpu_hw_pipe *pipe_hw;
100 struct dpu_hw_pipe_cfg pipe_cfg;
101 struct dpu_hw_pipe_qos_cfg pipe_qos_cfg;
106 struct list_head mplane_list;
107 struct dpu_mdss_cfg *catalog;
109 struct dpu_csc_cfg *csc_ptr;
111 const struct dpu_sspp_sub_blks *pipe_sblk;
112 char pipe_name[DPU_NAME_SIZE];
114 /* debugfs related stuff */
115 struct dentry *debugfs_root;
116 struct dpu_debugfs_regset32 debugfs_src;
117 struct dpu_debugfs_regset32 debugfs_scaler;
118 struct dpu_debugfs_regset32 debugfs_csc;
119 bool debugfs_default_scale;
122 static const uint64_t supported_format_modifiers[] = {
123 DRM_FORMAT_MOD_QCOM_COMPRESSED,
124 DRM_FORMAT_MOD_LINEAR,
125 DRM_FORMAT_MOD_INVALID
128 #define to_dpu_plane(x) container_of(x, struct dpu_plane, base)
130 static struct dpu_kms *_dpu_plane_get_kms(struct drm_plane *plane)
132 struct msm_drm_private *priv = plane->dev->dev_private;
134 return to_dpu_kms(priv->kms);
138 * _dpu_plane_calc_fill_level - calculate fill level of the given source format
139 * @plane: Pointer to drm plane
140 * @fmt: Pointer to source buffer format
141 * @src_wdith: width of source buffer
142 * Return: fill level corresponding to the source buffer/format or 0 if error
144 static int _dpu_plane_calc_fill_level(struct drm_plane *plane,
145 const struct dpu_format *fmt, u32 src_width)
147 struct dpu_plane *pdpu, *tmp;
148 struct dpu_plane_state *pstate;
152 if (!fmt || !plane->state || !src_width || !fmt->bpp) {
153 DPU_ERROR("invalid arguments\n");
157 pdpu = to_dpu_plane(plane);
158 pstate = to_dpu_plane_state(plane->state);
159 fixed_buff_size = pdpu->pipe_sblk->common->pixel_ram_size;
161 list_for_each_entry(tmp, &pdpu->mplane_list, mplane_list) {
162 if (!tmp->base.state->visible)
164 DPU_DEBUG("plane%d/%d src_width:%d/%d\n",
165 pdpu->base.base.id, tmp->base.base.id,
167 drm_rect_width(&tmp->pipe_cfg.src_rect));
168 src_width = max_t(u32, src_width,
169 drm_rect_width(&tmp->pipe_cfg.src_rect));
172 if (fmt->fetch_planes == DPU_PLANE_PSEUDO_PLANAR) {
173 if (fmt->chroma_sample == DPU_CHROMA_420) {
175 total_fl = (fixed_buff_size / 2) /
176 ((src_width + 32) * fmt->bpp);
179 total_fl = (fixed_buff_size / 2) * 2 /
180 ((src_width + 32) * fmt->bpp);
183 if (pstate->multirect_mode == DPU_SSPP_MULTIRECT_PARALLEL) {
184 total_fl = (fixed_buff_size / 2) * 2 /
185 ((src_width + 32) * fmt->bpp);
187 total_fl = (fixed_buff_size) * 2 /
188 ((src_width + 32) * fmt->bpp);
192 DPU_DEBUG("plane%u: pnum:%d fmt: %4.4s w:%u fl:%u\n",
193 plane->base.id, pdpu->pipe - SSPP_VIG0,
194 (char *)&fmt->base.pixel_format,
195 src_width, total_fl);
201 * _dpu_plane_get_qos_lut - get LUT mapping based on fill level
202 * @tbl: Pointer to LUT table
203 * @total_fl: fill level
204 * Return: LUT setting corresponding to the fill level
206 static u64 _dpu_plane_get_qos_lut(const struct dpu_qos_lut_tbl *tbl,
211 if (!tbl || !tbl->nentry || !tbl->entries)
214 for (i = 0; i < tbl->nentry; i++)
215 if (total_fl <= tbl->entries[i].fl)
216 return tbl->entries[i].lut;
218 /* if last fl is zero, use as default */
219 if (!tbl->entries[i-1].fl)
220 return tbl->entries[i-1].lut;
226 * _dpu_plane_set_qos_lut - set QoS LUT of the given plane
227 * @plane: Pointer to drm plane
228 * @fb: Pointer to framebuffer associated with the given plane
230 static void _dpu_plane_set_qos_lut(struct drm_plane *plane,
231 struct drm_framebuffer *fb)
233 struct dpu_plane *pdpu = to_dpu_plane(plane);
234 const struct dpu_format *fmt = NULL;
236 u32 total_fl = 0, lut_usage;
238 if (!pdpu->is_rt_pipe) {
239 lut_usage = DPU_QOS_LUT_USAGE_NRT;
241 fmt = dpu_get_dpu_format_ext(
244 total_fl = _dpu_plane_calc_fill_level(plane, fmt,
245 drm_rect_width(&pdpu->pipe_cfg.src_rect));
247 if (fmt && DPU_FORMAT_IS_LINEAR(fmt))
248 lut_usage = DPU_QOS_LUT_USAGE_LINEAR;
250 lut_usage = DPU_QOS_LUT_USAGE_MACROTILE;
253 qos_lut = _dpu_plane_get_qos_lut(
254 &pdpu->catalog->perf.qos_lut_tbl[lut_usage], total_fl);
256 pdpu->pipe_qos_cfg.creq_lut = qos_lut;
258 trace_dpu_perf_set_qos_luts(pdpu->pipe - SSPP_VIG0,
259 (fmt) ? fmt->base.pixel_format : 0,
260 pdpu->is_rt_pipe, total_fl, qos_lut, lut_usage);
262 DPU_DEBUG("plane%u: pnum:%d fmt: %4.4s rt:%d fl:%u lut:0x%llx\n",
264 pdpu->pipe - SSPP_VIG0,
265 fmt ? (char *)&fmt->base.pixel_format : NULL,
266 pdpu->is_rt_pipe, total_fl, qos_lut);
268 pdpu->pipe_hw->ops.setup_creq_lut(pdpu->pipe_hw, &pdpu->pipe_qos_cfg);
272 * _dpu_plane_set_panic_lut - set danger/safe LUT of the given plane
273 * @plane: Pointer to drm plane
274 * @fb: Pointer to framebuffer associated with the given plane
276 static void _dpu_plane_set_danger_lut(struct drm_plane *plane,
277 struct drm_framebuffer *fb)
279 struct dpu_plane *pdpu = to_dpu_plane(plane);
280 const struct dpu_format *fmt = NULL;
281 u32 danger_lut, safe_lut;
283 if (!pdpu->is_rt_pipe) {
284 danger_lut = pdpu->catalog->perf.danger_lut_tbl
285 [DPU_QOS_LUT_USAGE_NRT];
286 safe_lut = pdpu->catalog->perf.safe_lut_tbl
287 [DPU_QOS_LUT_USAGE_NRT];
289 fmt = dpu_get_dpu_format_ext(
293 if (fmt && DPU_FORMAT_IS_LINEAR(fmt)) {
294 danger_lut = pdpu->catalog->perf.danger_lut_tbl
295 [DPU_QOS_LUT_USAGE_LINEAR];
296 safe_lut = pdpu->catalog->perf.safe_lut_tbl
297 [DPU_QOS_LUT_USAGE_LINEAR];
299 danger_lut = pdpu->catalog->perf.danger_lut_tbl
300 [DPU_QOS_LUT_USAGE_MACROTILE];
301 safe_lut = pdpu->catalog->perf.safe_lut_tbl
302 [DPU_QOS_LUT_USAGE_MACROTILE];
306 pdpu->pipe_qos_cfg.danger_lut = danger_lut;
307 pdpu->pipe_qos_cfg.safe_lut = safe_lut;
309 trace_dpu_perf_set_danger_luts(pdpu->pipe - SSPP_VIG0,
310 (fmt) ? fmt->base.pixel_format : 0,
311 (fmt) ? fmt->fetch_mode : 0,
312 pdpu->pipe_qos_cfg.danger_lut,
313 pdpu->pipe_qos_cfg.safe_lut);
315 DPU_DEBUG("plane%u: pnum:%d fmt: %4.4s mode:%d luts[0x%x, 0x%x]\n",
317 pdpu->pipe - SSPP_VIG0,
318 fmt ? (char *)&fmt->base.pixel_format : NULL,
319 fmt ? fmt->fetch_mode : -1,
320 pdpu->pipe_qos_cfg.danger_lut,
321 pdpu->pipe_qos_cfg.safe_lut);
323 pdpu->pipe_hw->ops.setup_danger_safe_lut(pdpu->pipe_hw,
324 &pdpu->pipe_qos_cfg);
328 * _dpu_plane_set_qos_ctrl - set QoS control of the given plane
329 * @plane: Pointer to drm plane
330 * @enable: true to enable QoS control
331 * @flags: QoS control mode (enum dpu_plane_qos)
333 static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane,
334 bool enable, u32 flags)
336 struct dpu_plane *pdpu = to_dpu_plane(plane);
338 if (flags & DPU_PLANE_QOS_VBLANK_CTRL) {
339 pdpu->pipe_qos_cfg.creq_vblank = pdpu->pipe_sblk->creq_vblank;
340 pdpu->pipe_qos_cfg.danger_vblank =
341 pdpu->pipe_sblk->danger_vblank;
342 pdpu->pipe_qos_cfg.vblank_en = enable;
345 if (flags & DPU_PLANE_QOS_VBLANK_AMORTIZE) {
346 /* this feature overrules previous VBLANK_CTRL */
347 pdpu->pipe_qos_cfg.vblank_en = false;
348 pdpu->pipe_qos_cfg.creq_vblank = 0; /* clear vblank bits */
351 if (flags & DPU_PLANE_QOS_PANIC_CTRL)
352 pdpu->pipe_qos_cfg.danger_safe_en = enable;
354 if (!pdpu->is_rt_pipe) {
355 pdpu->pipe_qos_cfg.vblank_en = false;
356 pdpu->pipe_qos_cfg.danger_safe_en = false;
359 DPU_DEBUG("plane%u: pnum:%d ds:%d vb:%d pri[0x%x, 0x%x] is_rt:%d\n",
361 pdpu->pipe - SSPP_VIG0,
362 pdpu->pipe_qos_cfg.danger_safe_en,
363 pdpu->pipe_qos_cfg.vblank_en,
364 pdpu->pipe_qos_cfg.creq_vblank,
365 pdpu->pipe_qos_cfg.danger_vblank,
368 pdpu->pipe_hw->ops.setup_qos_ctrl(pdpu->pipe_hw,
369 &pdpu->pipe_qos_cfg);
373 * _dpu_plane_set_ot_limit - set OT limit for the given plane
374 * @plane: Pointer to drm plane
375 * @crtc: Pointer to drm crtc
377 static void _dpu_plane_set_ot_limit(struct drm_plane *plane,
378 struct drm_crtc *crtc)
380 struct dpu_plane *pdpu = to_dpu_plane(plane);
381 struct dpu_vbif_set_ot_params ot_params;
382 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
384 memset(&ot_params, 0, sizeof(ot_params));
385 ot_params.xin_id = pdpu->pipe_hw->cap->xin_id;
386 ot_params.num = pdpu->pipe_hw->idx - SSPP_NONE;
387 ot_params.width = drm_rect_width(&pdpu->pipe_cfg.src_rect);
388 ot_params.height = drm_rect_height(&pdpu->pipe_cfg.src_rect);
389 ot_params.is_wfd = !pdpu->is_rt_pipe;
390 ot_params.frame_rate = drm_mode_vrefresh(&crtc->mode);
391 ot_params.vbif_idx = VBIF_RT;
392 ot_params.clk_ctrl = pdpu->pipe_hw->cap->clk_ctrl;
395 dpu_vbif_set_ot_limit(dpu_kms, &ot_params);
399 * _dpu_plane_set_vbif_qos - set vbif QoS for the given plane
400 * @plane: Pointer to drm plane
402 static void _dpu_plane_set_qos_remap(struct drm_plane *plane)
404 struct dpu_plane *pdpu = to_dpu_plane(plane);
405 struct dpu_vbif_set_qos_params qos_params;
406 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
408 memset(&qos_params, 0, sizeof(qos_params));
409 qos_params.vbif_idx = VBIF_RT;
410 qos_params.clk_ctrl = pdpu->pipe_hw->cap->clk_ctrl;
411 qos_params.xin_id = pdpu->pipe_hw->cap->xin_id;
412 qos_params.num = pdpu->pipe_hw->idx - SSPP_VIG0;
413 qos_params.is_rt = pdpu->is_rt_pipe;
415 DPU_DEBUG("plane%d pipe:%d vbif:%d xin:%d rt:%d, clk_ctrl:%d\n",
416 plane->base.id, qos_params.num,
418 qos_params.xin_id, qos_params.is_rt,
419 qos_params.clk_ctrl);
421 dpu_vbif_set_qos_remap(dpu_kms, &qos_params);
424 static void _dpu_plane_set_scanout(struct drm_plane *plane,
425 struct dpu_plane_state *pstate,
426 struct dpu_hw_pipe_cfg *pipe_cfg,
427 struct drm_framebuffer *fb)
429 struct dpu_plane *pdpu = to_dpu_plane(plane);
430 struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base);
431 struct msm_gem_address_space *aspace = kms->base.aspace;
434 ret = dpu_format_populate_layout(aspace, fb, &pipe_cfg->layout);
436 DPU_DEBUG_PLANE(pdpu, "not updating same src addrs\n");
438 DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret);
439 else if (pdpu->pipe_hw->ops.setup_sourceaddress) {
440 trace_dpu_plane_set_scanout(pdpu->pipe_hw->idx,
442 pstate->multirect_index);
443 pdpu->pipe_hw->ops.setup_sourceaddress(pdpu->pipe_hw, pipe_cfg,
444 pstate->multirect_index);
448 static void _dpu_plane_setup_scaler3(struct dpu_plane *pdpu,
449 struct dpu_plane_state *pstate,
450 uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h,
451 struct dpu_hw_scaler3_cfg *scale_cfg,
452 const struct dpu_format *fmt,
453 uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v)
457 memset(scale_cfg, 0, sizeof(*scale_cfg));
458 memset(&pstate->pixel_ext, 0, sizeof(struct dpu_hw_pixel_ext));
460 scale_cfg->phase_step_x[DPU_SSPP_COMP_0] =
461 mult_frac((1 << PHASE_STEP_SHIFT), src_w, dst_w);
462 scale_cfg->phase_step_y[DPU_SSPP_COMP_0] =
463 mult_frac((1 << PHASE_STEP_SHIFT), src_h, dst_h);
466 scale_cfg->phase_step_y[DPU_SSPP_COMP_1_2] =
467 scale_cfg->phase_step_y[DPU_SSPP_COMP_0] / chroma_subsmpl_v;
468 scale_cfg->phase_step_x[DPU_SSPP_COMP_1_2] =
469 scale_cfg->phase_step_x[DPU_SSPP_COMP_0] / chroma_subsmpl_h;
471 scale_cfg->phase_step_x[DPU_SSPP_COMP_2] =
472 scale_cfg->phase_step_x[DPU_SSPP_COMP_1_2];
473 scale_cfg->phase_step_y[DPU_SSPP_COMP_2] =
474 scale_cfg->phase_step_y[DPU_SSPP_COMP_1_2];
476 scale_cfg->phase_step_x[DPU_SSPP_COMP_3] =
477 scale_cfg->phase_step_x[DPU_SSPP_COMP_0];
478 scale_cfg->phase_step_y[DPU_SSPP_COMP_3] =
479 scale_cfg->phase_step_y[DPU_SSPP_COMP_0];
481 for (i = 0; i < DPU_MAX_PLANES; i++) {
482 scale_cfg->src_width[i] = src_w;
483 scale_cfg->src_height[i] = src_h;
484 if (i == DPU_SSPP_COMP_1_2 || i == DPU_SSPP_COMP_2) {
485 scale_cfg->src_width[i] /= chroma_subsmpl_h;
486 scale_cfg->src_height[i] /= chroma_subsmpl_v;
488 scale_cfg->preload_x[i] = DPU_QSEED3_DEFAULT_PRELOAD_H;
489 scale_cfg->preload_y[i] = DPU_QSEED3_DEFAULT_PRELOAD_V;
490 pstate->pixel_ext.num_ext_pxls_top[i] =
491 scale_cfg->src_height[i];
492 pstate->pixel_ext.num_ext_pxls_left[i] =
493 scale_cfg->src_width[i];
495 if (!(DPU_FORMAT_IS_YUV(fmt)) && (src_h == dst_h)
499 scale_cfg->dst_width = dst_w;
500 scale_cfg->dst_height = dst_h;
501 scale_cfg->y_rgb_filter_cfg = DPU_SCALE_BIL;
502 scale_cfg->uv_filter_cfg = DPU_SCALE_BIL;
503 scale_cfg->alpha_filter_cfg = DPU_SCALE_ALPHA_BIL;
504 scale_cfg->lut_flag = 0;
505 scale_cfg->blend_cfg = 1;
506 scale_cfg->enable = 1;
509 static void _dpu_plane_setup_csc(struct dpu_plane *pdpu)
511 static const struct dpu_csc_cfg dpu_csc_YUV2RGB_601L = {
514 0x00012A00, 0x00000000, 0x00019880,
515 0x00012A00, 0xFFFF9B80, 0xFFFF3000,
516 0x00012A00, 0x00020480, 0x00000000,
519 { 0xfff0, 0xff80, 0xff80,},
522 { 0x10, 0xeb, 0x10, 0xf0, 0x10, 0xf0,},
523 { 0x00, 0xff, 0x00, 0xff, 0x00, 0xff,},
525 static const struct dpu_csc_cfg dpu_csc10_YUV2RGB_601L = {
528 0x00012A00, 0x00000000, 0x00019880,
529 0x00012A00, 0xFFFF9B80, 0xFFFF3000,
530 0x00012A00, 0x00020480, 0x00000000,
533 { 0xffc0, 0xfe00, 0xfe00,},
536 { 0x40, 0x3ac, 0x40, 0x3c0, 0x40, 0x3c0,},
537 { 0x00, 0x3ff, 0x00, 0x3ff, 0x00, 0x3ff,},
541 DPU_ERROR("invalid plane\n");
545 if (BIT(DPU_SSPP_CSC_10BIT) & pdpu->features)
546 pdpu->csc_ptr = (struct dpu_csc_cfg *)&dpu_csc10_YUV2RGB_601L;
548 pdpu->csc_ptr = (struct dpu_csc_cfg *)&dpu_csc_YUV2RGB_601L;
550 DPU_DEBUG_PLANE(pdpu, "using 0x%X 0x%X 0x%X...\n",
551 pdpu->csc_ptr->csc_mv[0],
552 pdpu->csc_ptr->csc_mv[1],
553 pdpu->csc_ptr->csc_mv[2]);
556 static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu,
557 struct dpu_plane_state *pstate,
558 const struct dpu_format *fmt, bool color_fill)
560 const struct drm_format_info *info = drm_format_info(fmt->base.pixel_format);
562 /* don't chroma subsample if decimating */
563 /* update scaler. calculate default config for QSEED3 */
564 _dpu_plane_setup_scaler3(pdpu, pstate,
565 drm_rect_width(&pdpu->pipe_cfg.src_rect),
566 drm_rect_height(&pdpu->pipe_cfg.src_rect),
567 drm_rect_width(&pdpu->pipe_cfg.dst_rect),
568 drm_rect_height(&pdpu->pipe_cfg.dst_rect),
569 &pstate->scaler3_cfg, fmt,
570 info->hsub, info->vsub);
574 * _dpu_plane_color_fill - enables color fill on plane
575 * @pdpu: Pointer to DPU plane object
576 * @color: RGB fill color value, [23..16] Blue, [15..8] Green, [7..0] Red
577 * @alpha: 8-bit fill alpha value, 255 selects 100% alpha
578 * Returns: 0 on success
580 static int _dpu_plane_color_fill(struct dpu_plane *pdpu,
581 uint32_t color, uint32_t alpha)
583 const struct dpu_format *fmt;
584 const struct drm_plane *plane = &pdpu->base;
585 struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state);
587 DPU_DEBUG_PLANE(pdpu, "\n");
590 * select fill format to match user property expectation,
591 * h/w only supports RGB variants
593 fmt = dpu_get_dpu_format(DRM_FORMAT_ABGR8888);
596 if (fmt && pdpu->pipe_hw->ops.setup_solidfill) {
597 pdpu->pipe_hw->ops.setup_solidfill(pdpu->pipe_hw,
598 (color & 0xFFFFFF) | ((alpha & 0xFF) << 24),
599 pstate->multirect_index);
601 /* override scaler/decimation if solid fill */
602 pdpu->pipe_cfg.src_rect.x1 = 0;
603 pdpu->pipe_cfg.src_rect.y1 = 0;
604 pdpu->pipe_cfg.src_rect.x2 =
605 drm_rect_width(&pdpu->pipe_cfg.dst_rect);
606 pdpu->pipe_cfg.src_rect.y2 =
607 drm_rect_height(&pdpu->pipe_cfg.dst_rect);
608 _dpu_plane_setup_scaler(pdpu, pstate, fmt, true);
610 if (pdpu->pipe_hw->ops.setup_format)
611 pdpu->pipe_hw->ops.setup_format(pdpu->pipe_hw,
612 fmt, DPU_SSPP_SOLID_FILL,
613 pstate->multirect_index);
615 if (pdpu->pipe_hw->ops.setup_rects)
616 pdpu->pipe_hw->ops.setup_rects(pdpu->pipe_hw,
618 pstate->multirect_index);
620 if (pdpu->pipe_hw->ops.setup_pe)
621 pdpu->pipe_hw->ops.setup_pe(pdpu->pipe_hw,
624 if (pdpu->pipe_hw->ops.setup_scaler &&
625 pstate->multirect_index != DPU_SSPP_RECT_1)
626 pdpu->pipe_hw->ops.setup_scaler(pdpu->pipe_hw,
627 &pdpu->pipe_cfg, &pstate->pixel_ext,
628 &pstate->scaler3_cfg);
634 void dpu_plane_clear_multirect(const struct drm_plane_state *drm_state)
636 struct dpu_plane_state *pstate = to_dpu_plane_state(drm_state);
638 pstate->multirect_index = DPU_SSPP_RECT_SOLO;
639 pstate->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
642 int dpu_plane_validate_multirect_v2(struct dpu_multirect_plane_states *plane)
644 struct dpu_plane_state *pstate[R_MAX];
645 const struct drm_plane_state *drm_state[R_MAX];
646 struct drm_rect src[R_MAX], dst[R_MAX];
647 struct dpu_plane *dpu_plane[R_MAX];
648 const struct dpu_format *fmt[R_MAX];
650 unsigned int max_tile_height = 1;
651 bool parallel_fetch_qualified = true;
652 bool has_tiled_rect = false;
654 for (i = 0; i < R_MAX; i++) {
655 const struct msm_format *msm_fmt;
657 drm_state[i] = i ? plane->r1 : plane->r0;
658 msm_fmt = msm_framebuffer_format(drm_state[i]->fb);
659 fmt[i] = to_dpu_format(msm_fmt);
661 if (DPU_FORMAT_IS_UBWC(fmt[i])) {
662 has_tiled_rect = true;
663 if (fmt[i]->tile_height > max_tile_height)
664 max_tile_height = fmt[i]->tile_height;
668 for (i = 0; i < R_MAX; i++) {
671 pstate[i] = to_dpu_plane_state(drm_state[i]);
672 dpu_plane[i] = to_dpu_plane(drm_state[i]->plane);
674 if (pstate[i] == NULL) {
675 DPU_ERROR("DPU plane state of plane id %d is NULL\n",
676 drm_state[i]->plane->base.id);
680 src[i].x1 = drm_state[i]->src_x >> 16;
681 src[i].y1 = drm_state[i]->src_y >> 16;
682 src[i].x2 = src[i].x1 + (drm_state[i]->src_w >> 16);
683 src[i].y2 = src[i].y1 + (drm_state[i]->src_h >> 16);
685 dst[i] = drm_plane_state_dest(drm_state[i]);
687 if (drm_rect_calc_hscale(&src[i], &dst[i], 1, 1) != 1 ||
688 drm_rect_calc_vscale(&src[i], &dst[i], 1, 1) != 1) {
689 DPU_ERROR_PLANE(dpu_plane[i],
690 "scaling is not supported in multirect mode\n");
694 if (DPU_FORMAT_IS_YUV(fmt[i])) {
695 DPU_ERROR_PLANE(dpu_plane[i],
696 "Unsupported format for multirect mode\n");
701 * SSPP PD_MEM is split half - one for each RECT.
702 * Tiled formats need 5 lines of buffering while fetching
703 * whereas linear formats need only 2 lines.
704 * So we cannot support more than half of the supported SSPP
705 * width for tiled formats.
707 width_threshold = dpu_plane[i]->pipe_sblk->common->maxlinewidth;
709 width_threshold /= 2;
711 if (parallel_fetch_qualified &&
712 drm_rect_width(&src[i]) > width_threshold)
713 parallel_fetch_qualified = false;
717 /* Validate RECT's and set the mode */
719 /* Prefer PARALLEL FETCH Mode over TIME_MX Mode */
720 if (parallel_fetch_qualified) {
721 pstate[R0]->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL;
722 pstate[R1]->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL;
728 buffer_lines = 2 * max_tile_height;
730 if (dst[R1].y1 >= dst[R0].y2 + buffer_lines ||
731 dst[R0].y1 >= dst[R1].y2 + buffer_lines) {
732 pstate[R0]->multirect_mode = DPU_SSPP_MULTIRECT_TIME_MX;
733 pstate[R1]->multirect_mode = DPU_SSPP_MULTIRECT_TIME_MX;
736 "No multirect mode possible for the planes (%d - %d)\n",
737 drm_state[R0]->plane->base.id,
738 drm_state[R1]->plane->base.id);
743 if (dpu_plane[R0]->is_virtual) {
744 pstate[R0]->multirect_index = DPU_SSPP_RECT_1;
745 pstate[R1]->multirect_index = DPU_SSPP_RECT_0;
747 pstate[R0]->multirect_index = DPU_SSPP_RECT_0;
748 pstate[R1]->multirect_index = DPU_SSPP_RECT_1;
751 DPU_DEBUG_PLANE(dpu_plane[R0], "R0: %d - %d\n",
752 pstate[R0]->multirect_mode, pstate[R0]->multirect_index);
753 DPU_DEBUG_PLANE(dpu_plane[R1], "R1: %d - %d\n",
754 pstate[R1]->multirect_mode, pstate[R1]->multirect_index);
759 * dpu_plane_get_ctl_flush - get control flush for the given plane
760 * @plane: Pointer to drm plane structure
761 * @ctl: Pointer to hardware control driver
762 * @flush_sspp: Pointer to sspp flush control word
764 void dpu_plane_get_ctl_flush(struct drm_plane *plane, struct dpu_hw_ctl *ctl,
767 *flush_sspp = ctl->ops.get_bitmask_sspp(ctl, dpu_plane_pipe(plane));
770 static int dpu_plane_prepare_fb(struct drm_plane *plane,
771 struct drm_plane_state *new_state)
773 struct drm_framebuffer *fb = new_state->fb;
774 struct dpu_plane *pdpu = to_dpu_plane(plane);
775 struct dpu_plane_state *pstate = to_dpu_plane_state(new_state);
776 struct dpu_hw_fmt_layout layout;
777 struct drm_gem_object *obj;
778 struct dma_fence *fence;
779 struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base);
785 DPU_DEBUG_PLANE(pdpu, "FB[%u]\n", fb->base.id);
788 pstate->aspace = kms->base.aspace;
791 * TODO: Need to sort out the msm_framebuffer_prepare() call below so
792 * we can use msm_atomic_prepare_fb() instead of doing the
793 * implicit fence and fb prepare by hand here.
795 obj = msm_framebuffer_bo(new_state->fb, 0);
796 fence = reservation_object_get_excl_rcu(obj->resv);
798 drm_atomic_set_fence_for_plane(new_state, fence);
800 if (pstate->aspace) {
801 ret = msm_framebuffer_prepare(new_state->fb,
804 DPU_ERROR("failed to prepare framebuffer\n");
809 /* validate framebuffer layout before commit */
810 ret = dpu_format_populate_layout(pstate->aspace,
811 new_state->fb, &layout);
813 DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret);
820 static void dpu_plane_cleanup_fb(struct drm_plane *plane,
821 struct drm_plane_state *old_state)
823 struct dpu_plane *pdpu = to_dpu_plane(plane);
824 struct dpu_plane_state *old_pstate;
826 if (!old_state || !old_state->fb)
829 old_pstate = to_dpu_plane_state(old_state);
831 DPU_DEBUG_PLANE(pdpu, "FB[%u]\n", old_state->fb->base.id);
833 msm_framebuffer_cleanup(old_state->fb, old_pstate->aspace);
836 static bool dpu_plane_validate_src(struct drm_rect *src,
837 struct drm_rect *fb_rect,
838 uint32_t min_src_size)
840 /* Ensure fb size is supported */
841 if (drm_rect_width(fb_rect) > MAX_IMG_WIDTH ||
842 drm_rect_height(fb_rect) > MAX_IMG_HEIGHT)
845 /* Ensure src rect is above the minimum size */
846 if (drm_rect_width(src) < min_src_size ||
847 drm_rect_height(src) < min_src_size)
850 /* Ensure src is fully encapsulated in fb */
851 return drm_rect_intersect(fb_rect, src) &&
852 drm_rect_equals(fb_rect, src);
855 static int dpu_plane_atomic_check(struct drm_plane *plane,
856 struct drm_plane_state *state)
858 int ret = 0, min_scale;
859 struct dpu_plane *pdpu = to_dpu_plane(plane);
860 const struct drm_crtc_state *crtc_state = NULL;
861 const struct dpu_format *fmt;
862 struct drm_rect src, dst, fb_rect = { 0 };
863 uint32_t min_src_size, max_linewidth;
866 crtc_state = drm_atomic_get_new_crtc_state(state->state,
869 min_scale = FRAC_16_16(1, pdpu->pipe_sblk->maxdwnscale);
870 ret = drm_atomic_helper_check_plane_state(state, crtc_state, min_scale,
871 pdpu->pipe_sblk->maxupscale << 16,
874 DPU_ERROR_PLANE(pdpu, "Check plane state failed (%d)\n", ret);
880 src.x1 = state->src_x >> 16;
881 src.y1 = state->src_y >> 16;
882 src.x2 = src.x1 + (state->src_w >> 16);
883 src.y2 = src.y1 + (state->src_h >> 16);
885 dst = drm_plane_state_dest(state);
887 fb_rect.x2 = state->fb->width;
888 fb_rect.y2 = state->fb->height;
890 max_linewidth = pdpu->pipe_sblk->common->maxlinewidth;
892 fmt = to_dpu_format(msm_framebuffer_format(state->fb));
894 min_src_size = DPU_FORMAT_IS_YUV(fmt) ? 2 : 1;
896 if (DPU_FORMAT_IS_YUV(fmt) &&
897 (!(pdpu->features & DPU_SSPP_SCALER) ||
898 !(pdpu->features & (BIT(DPU_SSPP_CSC)
899 | BIT(DPU_SSPP_CSC_10BIT))))) {
900 DPU_ERROR_PLANE(pdpu,
901 "plane doesn't have scaler/csc for yuv\n");
904 /* check src bounds */
905 } else if (!dpu_plane_validate_src(&src, &fb_rect, min_src_size)) {
906 DPU_ERROR_PLANE(pdpu, "invalid source " DRM_RECT_FMT "\n",
910 /* valid yuv image */
911 } else if (DPU_FORMAT_IS_YUV(fmt) &&
912 (src.x1 & 0x1 || src.y1 & 0x1 ||
913 drm_rect_width(&src) & 0x1 ||
914 drm_rect_height(&src) & 0x1)) {
915 DPU_ERROR_PLANE(pdpu, "invalid yuv source " DRM_RECT_FMT "\n",
919 /* min dst support */
920 } else if (drm_rect_width(&dst) < 0x1 || drm_rect_height(&dst) < 0x1) {
921 DPU_ERROR_PLANE(pdpu, "invalid dest rect " DRM_RECT_FMT "\n",
925 /* check decimated source width */
926 } else if (drm_rect_width(&src) > max_linewidth) {
927 DPU_ERROR_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n",
928 DRM_RECT_ARG(&src), max_linewidth);
935 void dpu_plane_flush(struct drm_plane *plane)
937 struct dpu_plane *pdpu;
938 struct dpu_plane_state *pstate;
940 if (!plane || !plane->state) {
941 DPU_ERROR("invalid plane\n");
945 pdpu = to_dpu_plane(plane);
946 pstate = to_dpu_plane_state(plane->state);
949 * These updates have to be done immediately before the plane flush
950 * timing, and may not be moved to the atomic_update/mode_set functions.
953 /* force white frame with 100% alpha pipe output on error */
954 _dpu_plane_color_fill(pdpu, 0xFFFFFF, 0xFF);
955 else if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG)
956 /* force 100% alpha */
957 _dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF);
958 else if (pdpu->pipe_hw && pdpu->csc_ptr && pdpu->pipe_hw->ops.setup_csc)
959 pdpu->pipe_hw->ops.setup_csc(pdpu->pipe_hw, pdpu->csc_ptr);
961 /* flag h/w flush complete */
963 pstate->pending = false;
967 * dpu_plane_set_error: enable/disable error condition
968 * @plane: pointer to drm_plane structure
970 void dpu_plane_set_error(struct drm_plane *plane, bool error)
972 struct dpu_plane *pdpu;
977 pdpu = to_dpu_plane(plane);
978 pdpu->is_error = error;
981 static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
984 struct dpu_plane *pdpu = to_dpu_plane(plane);
985 struct drm_plane_state *state = plane->state;
986 struct dpu_plane_state *pstate = to_dpu_plane_state(state);
987 struct drm_crtc *crtc = state->crtc;
988 struct drm_framebuffer *fb = state->fb;
989 const struct dpu_format *fmt =
990 to_dpu_format(msm_framebuffer_format(fb));
992 memset(&(pdpu->pipe_cfg), 0, sizeof(struct dpu_hw_pipe_cfg));
994 _dpu_plane_set_scanout(plane, pstate, &pdpu->pipe_cfg, fb);
996 pstate->pending = true;
998 pdpu->is_rt_pipe = (dpu_crtc_get_client_type(crtc) != NRT_CLIENT);
999 _dpu_plane_set_qos_ctrl(plane, false, DPU_PLANE_QOS_PANIC_CTRL);
1001 DPU_DEBUG_PLANE(pdpu, "FB[%u] " DRM_RECT_FP_FMT "->crtc%u " DRM_RECT_FMT
1002 ", %4.4s ubwc %d\n", fb->base.id, DRM_RECT_FP_ARG(&state->src),
1003 crtc->base.id, DRM_RECT_ARG(&state->dst),
1004 (char *)&fmt->base.pixel_format, DPU_FORMAT_IS_UBWC(fmt));
1006 pdpu->pipe_cfg.src_rect = state->src;
1008 /* state->src is 16.16, src_rect is not */
1009 pdpu->pipe_cfg.src_rect.x1 >>= 16;
1010 pdpu->pipe_cfg.src_rect.x2 >>= 16;
1011 pdpu->pipe_cfg.src_rect.y1 >>= 16;
1012 pdpu->pipe_cfg.src_rect.y2 >>= 16;
1014 pdpu->pipe_cfg.dst_rect = state->dst;
1016 _dpu_plane_setup_scaler(pdpu, pstate, fmt, false);
1018 /* override for color fill */
1019 if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) {
1020 /* skip remaining processing on color fill */
1024 if (pdpu->pipe_hw->ops.setup_rects) {
1025 pdpu->pipe_hw->ops.setup_rects(pdpu->pipe_hw,
1027 pstate->multirect_index);
1030 if (pdpu->pipe_hw->ops.setup_pe &&
1031 (pstate->multirect_index != DPU_SSPP_RECT_1))
1032 pdpu->pipe_hw->ops.setup_pe(pdpu->pipe_hw,
1033 &pstate->pixel_ext);
1036 * when programmed in multirect mode, scalar block will be
1037 * bypassed. Still we need to update alpha and bitwidth
1040 if (pdpu->pipe_hw->ops.setup_scaler &&
1041 pstate->multirect_index != DPU_SSPP_RECT_1)
1042 pdpu->pipe_hw->ops.setup_scaler(pdpu->pipe_hw,
1043 &pdpu->pipe_cfg, &pstate->pixel_ext,
1044 &pstate->scaler3_cfg);
1046 if (pdpu->pipe_hw->ops.setup_multirect)
1047 pdpu->pipe_hw->ops.setup_multirect(
1049 pstate->multirect_index,
1050 pstate->multirect_mode);
1052 if (pdpu->pipe_hw->ops.setup_format) {
1056 pdpu->pipe_hw->ops.setup_format(pdpu->pipe_hw, fmt, src_flags,
1057 pstate->multirect_index);
1059 if (pdpu->pipe_hw->ops.setup_cdp) {
1060 struct dpu_hw_pipe_cdp_cfg *cdp_cfg = &pstate->cdp_cfg;
1062 memset(cdp_cfg, 0, sizeof(struct dpu_hw_pipe_cdp_cfg));
1064 cdp_cfg->enable = pdpu->catalog->perf.cdp_cfg
1065 [DPU_PERF_CDP_USAGE_RT].rd_enable;
1066 cdp_cfg->ubwc_meta_enable =
1067 DPU_FORMAT_IS_UBWC(fmt);
1068 cdp_cfg->tile_amortize_enable =
1069 DPU_FORMAT_IS_UBWC(fmt) ||
1070 DPU_FORMAT_IS_TILE(fmt);
1071 cdp_cfg->preload_ahead = DPU_SSPP_CDP_PRELOAD_AHEAD_64;
1073 pdpu->pipe_hw->ops.setup_cdp(pdpu->pipe_hw, cdp_cfg);
1077 if (DPU_FORMAT_IS_YUV(fmt))
1078 _dpu_plane_setup_csc(pdpu);
1083 _dpu_plane_set_qos_lut(plane, fb);
1084 _dpu_plane_set_danger_lut(plane, fb);
1086 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
1087 _dpu_plane_set_qos_ctrl(plane, true, DPU_PLANE_QOS_PANIC_CTRL);
1088 _dpu_plane_set_ot_limit(plane, crtc);
1091 _dpu_plane_set_qos_remap(plane);
1094 static void _dpu_plane_atomic_disable(struct drm_plane *plane)
1096 struct dpu_plane *pdpu = to_dpu_plane(plane);
1097 struct drm_plane_state *state = plane->state;
1098 struct dpu_plane_state *pstate = to_dpu_plane_state(state);
1100 trace_dpu_plane_disable(DRMID(plane), is_dpu_plane_virtual(plane),
1101 pstate->multirect_mode);
1103 pstate->pending = true;
1105 if (is_dpu_plane_virtual(plane) &&
1106 pdpu->pipe_hw && pdpu->pipe_hw->ops.setup_multirect)
1107 pdpu->pipe_hw->ops.setup_multirect(pdpu->pipe_hw,
1108 DPU_SSPP_RECT_SOLO, DPU_SSPP_MULTIRECT_NONE);
1111 static void dpu_plane_atomic_update(struct drm_plane *plane,
1112 struct drm_plane_state *old_state)
1114 struct dpu_plane *pdpu = to_dpu_plane(plane);
1115 struct drm_plane_state *state = plane->state;
1117 pdpu->is_error = false;
1119 DPU_DEBUG_PLANE(pdpu, "\n");
1121 if (!state->visible) {
1122 _dpu_plane_atomic_disable(plane);
1124 dpu_plane_sspp_atomic_update(plane);
1128 void dpu_plane_restore(struct drm_plane *plane)
1130 struct dpu_plane *pdpu;
1132 if (!plane || !plane->state) {
1133 DPU_ERROR("invalid plane\n");
1137 pdpu = to_dpu_plane(plane);
1139 DPU_DEBUG_PLANE(pdpu, "\n");
1141 /* last plane state is same as current state */
1142 dpu_plane_atomic_update(plane, plane->state);
1145 static void dpu_plane_destroy(struct drm_plane *plane)
1147 struct dpu_plane *pdpu = plane ? to_dpu_plane(plane) : NULL;
1149 DPU_DEBUG_PLANE(pdpu, "\n");
1152 _dpu_plane_set_qos_ctrl(plane, false, DPU_PLANE_QOS_PANIC_CTRL);
1154 mutex_destroy(&pdpu->lock);
1156 /* this will destroy the states as well */
1157 drm_plane_cleanup(plane);
1159 dpu_hw_sspp_destroy(pdpu->pipe_hw);
1165 static void dpu_plane_destroy_state(struct drm_plane *plane,
1166 struct drm_plane_state *state)
1168 __drm_atomic_helper_plane_destroy_state(state);
1169 kfree(to_dpu_plane_state(state));
1172 static struct drm_plane_state *
1173 dpu_plane_duplicate_state(struct drm_plane *plane)
1175 struct dpu_plane *pdpu;
1176 struct dpu_plane_state *pstate;
1177 struct dpu_plane_state *old_state;
1180 DPU_ERROR("invalid plane\n");
1182 } else if (!plane->state) {
1183 DPU_ERROR("invalid plane state\n");
1187 old_state = to_dpu_plane_state(plane->state);
1188 pdpu = to_dpu_plane(plane);
1189 pstate = kmemdup(old_state, sizeof(*old_state), GFP_KERNEL);
1191 DPU_ERROR_PLANE(pdpu, "failed to allocate state\n");
1195 DPU_DEBUG_PLANE(pdpu, "\n");
1197 pstate->pending = false;
1199 __drm_atomic_helper_plane_duplicate_state(plane, &pstate->base);
1201 return &pstate->base;
1204 static void dpu_plane_reset(struct drm_plane *plane)
1206 struct dpu_plane *pdpu;
1207 struct dpu_plane_state *pstate;
1210 DPU_ERROR("invalid plane\n");
1214 pdpu = to_dpu_plane(plane);
1215 DPU_DEBUG_PLANE(pdpu, "\n");
1217 /* remove previous state, if present */
1219 dpu_plane_destroy_state(plane, plane->state);
1223 pstate = kzalloc(sizeof(*pstate), GFP_KERNEL);
1225 DPU_ERROR_PLANE(pdpu, "failed to allocate state\n");
1229 pstate->base.plane = plane;
1231 plane->state = &pstate->base;
1234 #ifdef CONFIG_DEBUG_FS
1235 static void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable)
1237 struct dpu_plane *pdpu = to_dpu_plane(plane);
1238 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
1240 if (!pdpu->is_rt_pipe)
1243 pm_runtime_get_sync(&dpu_kms->pdev->dev);
1244 _dpu_plane_set_qos_ctrl(plane, enable, DPU_PLANE_QOS_PANIC_CTRL);
1245 pm_runtime_put_sync(&dpu_kms->pdev->dev);
1248 static ssize_t _dpu_plane_danger_read(struct file *file,
1249 char __user *buff, size_t count, loff_t *ppos)
1251 struct dpu_kms *kms = file->private_data;
1255 len = scnprintf(buf, sizeof(buf), "%d\n", !kms->has_danger_ctrl);
1257 return simple_read_from_buffer(buff, count, ppos, buf, len);
1260 static void _dpu_plane_set_danger_state(struct dpu_kms *kms, bool enable)
1262 struct drm_plane *plane;
1264 drm_for_each_plane(plane, kms->dev) {
1265 if (plane->fb && plane->state) {
1266 dpu_plane_danger_signal_ctrl(plane, enable);
1267 DPU_DEBUG("plane:%d img:%dx%d ",
1268 plane->base.id, plane->fb->width,
1270 DPU_DEBUG("src[%d,%d,%d,%d] dst[%d,%d,%d,%d]\n",
1271 plane->state->src_x >> 16,
1272 plane->state->src_y >> 16,
1273 plane->state->src_w >> 16,
1274 plane->state->src_h >> 16,
1275 plane->state->crtc_x, plane->state->crtc_y,
1276 plane->state->crtc_w, plane->state->crtc_h);
1278 DPU_DEBUG("Inactive plane:%d\n", plane->base.id);
1283 static ssize_t _dpu_plane_danger_write(struct file *file,
1284 const char __user *user_buf, size_t count, loff_t *ppos)
1286 struct dpu_kms *kms = file->private_data;
1290 ret = kstrtouint_from_user(user_buf, count, 0, &disable_panic);
1294 if (disable_panic) {
1295 /* Disable panic signal for all active pipes */
1296 DPU_DEBUG("Disabling danger:\n");
1297 _dpu_plane_set_danger_state(kms, false);
1298 kms->has_danger_ctrl = false;
1300 /* Enable panic signal for all active pipes */
1301 DPU_DEBUG("Enabling danger:\n");
1302 kms->has_danger_ctrl = true;
1303 _dpu_plane_set_danger_state(kms, true);
1309 static const struct file_operations dpu_plane_danger_enable = {
1310 .open = simple_open,
1311 .read = _dpu_plane_danger_read,
1312 .write = _dpu_plane_danger_write,
1315 static int _dpu_plane_init_debugfs(struct drm_plane *plane)
1317 struct dpu_plane *pdpu = to_dpu_plane(plane);
1318 struct dpu_kms *kms = _dpu_plane_get_kms(plane);
1319 const struct dpu_sspp_cfg *cfg = pdpu->pipe_hw->cap;
1320 const struct dpu_sspp_sub_blks *sblk = cfg->sblk;
1322 /* create overall sub-directory for the pipe */
1323 pdpu->debugfs_root =
1324 debugfs_create_dir(pdpu->pipe_name,
1325 plane->dev->primary->debugfs_root);
1327 if (!pdpu->debugfs_root)
1330 /* don't error check these */
1331 debugfs_create_x32("features", 0600,
1332 pdpu->debugfs_root, &pdpu->features);
1334 /* add register dump support */
1335 dpu_debugfs_setup_regset32(&pdpu->debugfs_src,
1336 sblk->src_blk.base + cfg->base,
1339 dpu_debugfs_create_regset32("src_blk", 0400,
1340 pdpu->debugfs_root, &pdpu->debugfs_src);
1342 if (cfg->features & BIT(DPU_SSPP_SCALER_QSEED3) ||
1343 cfg->features & BIT(DPU_SSPP_SCALER_QSEED2)) {
1344 dpu_debugfs_setup_regset32(&pdpu->debugfs_scaler,
1345 sblk->scaler_blk.base + cfg->base,
1346 sblk->scaler_blk.len,
1348 dpu_debugfs_create_regset32("scaler_blk", 0400,
1350 &pdpu->debugfs_scaler);
1351 debugfs_create_bool("default_scaling",
1354 &pdpu->debugfs_default_scale);
1357 if (cfg->features & BIT(DPU_SSPP_CSC) ||
1358 cfg->features & BIT(DPU_SSPP_CSC_10BIT)) {
1359 dpu_debugfs_setup_regset32(&pdpu->debugfs_csc,
1360 sblk->csc_blk.base + cfg->base,
1363 dpu_debugfs_create_regset32("csc_blk", 0400,
1364 pdpu->debugfs_root, &pdpu->debugfs_csc);
1367 debugfs_create_u32("xin_id",
1370 (u32 *) &cfg->xin_id);
1371 debugfs_create_u32("clk_ctrl",
1374 (u32 *) &cfg->clk_ctrl);
1375 debugfs_create_x32("creq_vblank",
1378 (u32 *) &sblk->creq_vblank);
1379 debugfs_create_x32("danger_vblank",
1382 (u32 *) &sblk->danger_vblank);
1384 debugfs_create_file("disable_danger",
1387 kms, &dpu_plane_danger_enable);
1392 static int _dpu_plane_init_debugfs(struct drm_plane *plane)
1398 static int dpu_plane_late_register(struct drm_plane *plane)
1400 return _dpu_plane_init_debugfs(plane);
1403 static void dpu_plane_early_unregister(struct drm_plane *plane)
1405 struct dpu_plane *pdpu = to_dpu_plane(plane);
1407 debugfs_remove_recursive(pdpu->debugfs_root);
1410 static bool dpu_plane_format_mod_supported(struct drm_plane *plane,
1411 uint32_t format, uint64_t modifier)
1413 if (modifier == DRM_FORMAT_MOD_LINEAR)
1416 if (modifier == DRM_FORMAT_MOD_QCOM_COMPRESSED) {
1418 for (i = 0; i < ARRAY_SIZE(qcom_compressed_supported_formats); i++) {
1419 if (format == qcom_compressed_supported_formats[i])
1427 static const struct drm_plane_funcs dpu_plane_funcs = {
1428 .update_plane = drm_atomic_helper_update_plane,
1429 .disable_plane = drm_atomic_helper_disable_plane,
1430 .destroy = dpu_plane_destroy,
1431 .reset = dpu_plane_reset,
1432 .atomic_duplicate_state = dpu_plane_duplicate_state,
1433 .atomic_destroy_state = dpu_plane_destroy_state,
1434 .late_register = dpu_plane_late_register,
1435 .early_unregister = dpu_plane_early_unregister,
1436 .format_mod_supported = dpu_plane_format_mod_supported,
1439 static const struct drm_plane_helper_funcs dpu_plane_helper_funcs = {
1440 .prepare_fb = dpu_plane_prepare_fb,
1441 .cleanup_fb = dpu_plane_cleanup_fb,
1442 .atomic_check = dpu_plane_atomic_check,
1443 .atomic_update = dpu_plane_atomic_update,
1446 enum dpu_sspp dpu_plane_pipe(struct drm_plane *plane)
1448 return plane ? to_dpu_plane(plane)->pipe : SSPP_NONE;
1451 bool is_dpu_plane_virtual(struct drm_plane *plane)
1453 return plane ? to_dpu_plane(plane)->is_virtual : false;
1456 /* initialize plane */
1457 struct drm_plane *dpu_plane_init(struct drm_device *dev,
1458 uint32_t pipe, enum drm_plane_type type,
1459 unsigned long possible_crtcs, u32 master_plane_id)
1461 struct drm_plane *plane = NULL, *master_plane = NULL;
1462 const uint32_t *format_list;
1463 struct dpu_plane *pdpu;
1464 struct msm_drm_private *priv = dev->dev_private;
1465 struct dpu_kms *kms = to_dpu_kms(priv->kms);
1466 int zpos_max = DPU_ZPOS_MAX;
1467 uint32_t num_formats;
1470 /* create and zero local structure */
1471 pdpu = kzalloc(sizeof(*pdpu), GFP_KERNEL);
1473 DPU_ERROR("[%u]failed to allocate local plane struct\n", pipe);
1475 return ERR_PTR(ret);
1478 /* cache local stuff for later */
1479 plane = &pdpu->base;
1481 pdpu->is_virtual = (master_plane_id != 0);
1482 INIT_LIST_HEAD(&pdpu->mplane_list);
1483 master_plane = drm_plane_find(dev, NULL, master_plane_id);
1485 struct dpu_plane *mpdpu = to_dpu_plane(master_plane);
1487 list_add_tail(&pdpu->mplane_list, &mpdpu->mplane_list);
1490 /* initialize underlying h/w driver */
1491 pdpu->pipe_hw = dpu_hw_sspp_init(pipe, kms->mmio, kms->catalog,
1492 master_plane_id != 0);
1493 if (IS_ERR(pdpu->pipe_hw)) {
1494 DPU_ERROR("[%u]SSPP init failed\n", pipe);
1495 ret = PTR_ERR(pdpu->pipe_hw);
1497 } else if (!pdpu->pipe_hw->cap || !pdpu->pipe_hw->cap->sblk) {
1498 DPU_ERROR("[%u]SSPP init returned invalid cfg\n", pipe);
1502 /* cache features mask for later */
1503 pdpu->features = pdpu->pipe_hw->cap->features;
1504 pdpu->pipe_sblk = pdpu->pipe_hw->cap->sblk;
1505 if (!pdpu->pipe_sblk) {
1506 DPU_ERROR("[%u]invalid sblk\n", pipe);
1510 if (pdpu->is_virtual) {
1511 format_list = pdpu->pipe_sblk->virt_format_list;
1512 num_formats = pdpu->pipe_sblk->virt_num_formats;
1515 format_list = pdpu->pipe_sblk->format_list;
1516 num_formats = pdpu->pipe_sblk->num_formats;
1519 ret = drm_universal_plane_init(dev, plane, 0xff, &dpu_plane_funcs,
1520 format_list, num_formats,
1521 supported_format_modifiers, type, NULL);
1525 pdpu->catalog = kms->catalog;
1527 if (kms->catalog->mixer_count &&
1528 kms->catalog->mixer[0].sblk->maxblendstages) {
1529 zpos_max = kms->catalog->mixer[0].sblk->maxblendstages - 1;
1530 if (zpos_max > DPU_STAGE_MAX - DPU_STAGE_0 - 1)
1531 zpos_max = DPU_STAGE_MAX - DPU_STAGE_0 - 1;
1534 ret = drm_plane_create_zpos_property(plane, 0, 0, zpos_max);
1536 DPU_ERROR("failed to install zpos property, rc = %d\n", ret);
1538 /* success! finalize initialization */
1539 drm_plane_helper_add(plane, &dpu_plane_helper_funcs);
1541 /* save user friendly pipe name for later */
1542 snprintf(pdpu->pipe_name, DPU_NAME_SIZE, "plane%u", plane->base.id);
1544 mutex_init(&pdpu->lock);
1546 DPU_DEBUG("%s created for pipe:%u id:%u virtual:%u\n", pdpu->pipe_name,
1547 pipe, plane->base.id, master_plane_id);
1551 if (pdpu && pdpu->pipe_hw)
1552 dpu_hw_sspp_destroy(pdpu->pipe_hw);
1555 return ERR_PTR(ret);