drivers/gpu/drm/msm/adreno/adreno_gpu.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2013 Red Hat
   4  * Author: Rob Clark <robdclark@gmail.com>
   5  *
   6  * Copyright (c) 2014 The Linux Foundation. All rights reserved.
   7  */
   8
   9 #include <linux/ascii85.h>
  10 #include <linux/interconnect.h>
  11 #include <linux/qcom_scm.h>
  12 #include <linux/kernel.h>
  13 #include <linux/of_address.h>
  14 #include <linux/pm_opp.h>
  15 #include <linux/slab.h>
  16 #include <linux/soc/qcom/mdt_loader.h>
  17 #include <linux/nvmem-consumer.h>
  18 #include <soc/qcom/ocmem.h>
  19 #include "adreno_gpu.h"
  20 #include "a6xx_gpu.h"
  21 #include "msm_gem.h"
  22 #include "msm_mmu.h"
  23
  24 static bool zap_available = true;
  25
  26 static int zap_shader_load_mdt(struct msm_gpu *gpu, const char *fwname,
  27                 u32 pasid)
  28 {
  29         struct device *dev = &gpu->pdev->dev;
  30         const struct firmware *fw;
  31         const char *signed_fwname = NULL;
  32         struct device_node *np, *mem_np;
  33         struct resource r;
  34         phys_addr_t mem_phys;
  35         ssize_t mem_size;
  36         void *mem_region = NULL;
  37         int ret;
  38
  39         if (!IS_ENABLED(CONFIG_ARCH_QCOM)) {
  40                 zap_available = false;
  41                 return -EINVAL;
  42         }
  43
  44         np = of_get_child_by_name(dev->of_node, "zap-shader");
  45         if (!np) {
  46                 zap_available = false;
  47                 return -ENODEV;
  48         }
  49
  50         mem_np = of_parse_phandle(np, "memory-region", 0);
  51         of_node_put(np);
  52         if (!mem_np) {
  53                 zap_available = false;
  54                 return -EINVAL;
  55         }
  56
  57         ret = of_address_to_resource(mem_np, 0, &r);
  58         of_node_put(mem_np);
  59         if (ret)
  60                 return ret;
  61
  62         mem_phys = r.start;
  63
  64         /*
  65          * Check for a firmware-name property.  This is the new scheme
  66          * to handle firmware that may be signed with device specific
  67          * keys, allowing us to have a different zap fw path for different
  68          * devices.
  69          *
  70          * If the firmware-name property is found, we bypass the
  71          * adreno_request_fw() mechanism, because we don't need to handle
  72          * the /lib/firmware/qcom/... vs /lib/firmware/... case.
  73          *
  74          * If the firmware-name property is not found, for backwards
  75          * compatibility we fall back to the fwname from the gpulist
  76          * table.
  77          */
  78         of_property_read_string_index(np, "firmware-name", 0, &signed_fwname);
  79         if (signed_fwname) {
  80                 fwname = signed_fwname;
  81                 ret = request_firmware_direct(&fw, fwname, gpu->dev->dev);
  82                 if (ret)
  83                         fw = ERR_PTR(ret);
  84         } else if (fwname) {
  85                 /* Request the MDT file from the default location: */
  86                 fw = adreno_request_fw(to_adreno_gpu(gpu), fwname);
  87         } else {
  88                 /*
  89                  * For new targets, we require the firmware-name property,
  90                  * if a zap-shader is required, rather than falling back
  91                  * to a firmware name specified in gpulist.
  92                  *
  93                  * Because the firmware is signed with a (potentially)
  94                  * device specific key, having the name come from gpulist
  95                  * was a bad idea, and is only provided for backwards
  96                  * compatibility for older targets.
  97                  */
  98                 return -ENODEV;
  99         }
 100
 101         if (IS_ERR(fw)) {
 102                 DRM_DEV_ERROR(dev, "Unable to load %s\n", fwname);
 103                 return PTR_ERR(fw);
 104         }
 105
 106         /* Figure out how much memory we need */
 107         mem_size = qcom_mdt_get_size(fw);
 108         if (mem_size < 0) {
 109                 ret = mem_size;
 110                 goto out;
 111         }
 112
 113         if (mem_size > resource_size(&r)) {
 114                 DRM_DEV_ERROR(dev,
 115                         "memory region is too small to load the MDT\n");
 116                 ret = -E2BIG;
 117                 goto out;
 118         }
 119
 120         /* Allocate memory for the firmware image */
 121         mem_region = memremap(mem_phys, mem_size,  MEMREMAP_WC);
 122         if (!mem_region) {
 123                 ret = -ENOMEM;
 124                 goto out;
 125         }
 126
 127         /*
 128          * Load the rest of the MDT
 129          *
 130          * Note that we could be dealing with two different paths, since
 131          * with upstream linux-firmware it would be in a qcom/ subdir..
 132          * adreno_request_fw() handles this, but qcom_mdt_load() does
 133          * not.  But since we've already gotten through adreno_request_fw()
 134          * we know which of the two cases it is:
 135          */
 136         if (signed_fwname || (to_adreno_gpu(gpu)->fwloc == FW_LOCATION_LEGACY)) {
 137                 ret = qcom_mdt_load(dev, fw, fwname, pasid,
 138                                 mem_region, mem_phys, mem_size, NULL);
 139         } else {
 140                 char *newname;
 141
 142                 newname = kasprintf(GFP_KERNEL, "qcom/%s", fwname);
 143
 144                 ret = qcom_mdt_load(dev, fw, newname, pasid,
 145                                 mem_region, mem_phys, mem_size, NULL);
 146                 kfree(newname);
 147         }
 148         if (ret)
 149                 goto out;
 150
 151         /* Send the image to the secure world */
 152         ret = qcom_scm_pas_auth_and_reset(pasid);
 153
 154         /*
 155          * If the scm call returns -EOPNOTSUPP we assume that this target
 156          * doesn't need/support the zap shader so quietly fail
 157          */
 158         if (ret == -EOPNOTSUPP)
 159                 zap_available = false;
 160         else if (ret)
 161                 DRM_DEV_ERROR(dev, "Unable to authorize the image\n");
 162
 163 out:
 164         if (mem_region)
 165                 memunmap(mem_region);
 166
 167         release_firmware(fw);
 168
 169         return ret;
 170 }
 171
 172 int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid)
 173 {
 174         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 175         struct platform_device *pdev = gpu->pdev;
 176
 177         /* Short cut if we determine the zap shader isn't available/needed */
 178         if (!zap_available)
 179                 return -ENODEV;
 180
 181         /* We need SCM to be able to load the firmware */
 182         if (!qcom_scm_is_available()) {
 183                 DRM_DEV_ERROR(&pdev->dev, "SCM is not available\n");
 184                 return -EPROBE_DEFER;
 185         }
 186
 187         return zap_shader_load_mdt(gpu, adreno_gpu->info->zapfw, pasid);
 188 }
 189
 190 void adreno_set_llc_attributes(struct iommu_domain *iommu)
 191 {
 192         iommu_set_pgtable_quirks(iommu, IO_PGTABLE_QUIRK_ARM_OUTER_WBWA);
 193 }
 194
 195 struct msm_gem_address_space *
 196 adreno_iommu_create_address_space(struct msm_gpu *gpu,
 197                 struct platform_device *pdev)
 198 {
 199         struct iommu_domain *iommu;
 200         struct msm_mmu *mmu;
 201         struct msm_gem_address_space *aspace;
 202         u64 start, size;
 203
 204         iommu = iommu_domain_alloc(&platform_bus_type);
 205         if (!iommu)
 206                 return NULL;
 207
 208         mmu = msm_iommu_new(&pdev->dev, iommu);
 209         if (IS_ERR(mmu)) {
 210                 iommu_domain_free(iommu);
 211                 return ERR_CAST(mmu);
 212         }
 213
 214         /*
 215          * Use the aperture start or SZ_16M, whichever is greater. This will
 216          * ensure that we align with the allocated pagetable range while still
 217          * allowing room in the lower 32 bits for GMEM and whatnot
 218          */
 219         start = max_t(u64, SZ_16M, iommu->geometry.aperture_start);
 220         size = iommu->geometry.aperture_end - start + 1;
 221
 222         aspace = msm_gem_address_space_create(mmu, "gpu",
 223                 start & GENMASK_ULL(48, 0), size);
 224
 225         if (IS_ERR(aspace) && !IS_ERR(mmu))
 226                 mmu->funcs->destroy(mmu);
 227
 228         return aspace;
 229 }
 230
 231 int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx,
 232                      uint32_t param, uint64_t *value, uint32_t *len)
 233 {
 234         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 235
 236         /* No pointer params yet */
 237         if (*len != 0)
 238                 return -EINVAL;
 239
 240         switch (param) {
 241         case MSM_PARAM_GPU_ID:
 242                 *value = adreno_gpu->info->revn;
 243                 return 0;
 244         case MSM_PARAM_GMEM_SIZE:
 245                 *value = adreno_gpu->gmem;
 246                 return 0;
 247         case MSM_PARAM_GMEM_BASE:
 248                 *value = !adreno_is_a650_family(adreno_gpu) ? 0x100000 : 0;
 249                 return 0;
 250         case MSM_PARAM_CHIP_ID:
 251                 *value =  (uint64_t)adreno_gpu->rev.patchid |
 252                          ((uint64_t)adreno_gpu->rev.minor << 8) |
 253                          ((uint64_t)adreno_gpu->rev.major << 16) |
 254                          ((uint64_t)adreno_gpu->rev.core  << 24);
 255                 if (!adreno_gpu->info->revn)
 256                         *value |= ((uint64_t) adreno_gpu->speedbin) << 32;
 257                 return 0;
 258         case MSM_PARAM_MAX_FREQ:
 259                 *value = adreno_gpu->base.fast_rate;
 260                 return 0;
 261         case MSM_PARAM_TIMESTAMP:
 262                 if (adreno_gpu->funcs->get_timestamp) {
 263                         int ret;
 264
 265                         pm_runtime_get_sync(&gpu->pdev->dev);
 266                         ret = adreno_gpu->funcs->get_timestamp(gpu, value);
 267                         pm_runtime_put_autosuspend(&gpu->pdev->dev);
 268
 269                         return ret;
 270                 }
 271                 return -EINVAL;
 272         case MSM_PARAM_PRIORITIES:
 273                 *value = gpu->nr_rings * NR_SCHED_PRIORITIES;
 274                 return 0;
 275         case MSM_PARAM_PP_PGTABLE:
 276                 *value = 0;
 277                 return 0;
 278         case MSM_PARAM_FAULTS:
 279                 if (ctx->aspace)
 280                         *value = gpu->global_faults + ctx->aspace->faults;
 281                 else
 282                         *value = gpu->global_faults;
 283                 return 0;
 284         case MSM_PARAM_SUSPENDS:
 285                 *value = gpu->suspend_count;
 286                 return 0;
 287         case MSM_PARAM_VA_START:
 288                 if (ctx->aspace == gpu->aspace)
 289                         return -EINVAL;
 290                 *value = ctx->aspace->va_start;
 291                 return 0;
 292         case MSM_PARAM_VA_SIZE:
 293                 if (ctx->aspace == gpu->aspace)
 294                         return -EINVAL;
 295                 *value = ctx->aspace->va_size;
 296                 return 0;
 297         default:
 298                 DBG("%s: invalid param: %u", gpu->name, param);
 299                 return -EINVAL;
 300         }
 301 }
 302
 303 int adreno_set_param(struct msm_gpu *gpu, struct msm_file_private *ctx,
 304                      uint32_t param, uint64_t value, uint32_t len)
 305 {
 306         switch (param) {
 307         case MSM_PARAM_COMM:
 308         case MSM_PARAM_CMDLINE:
 309                 /* kstrdup_quotable_cmdline() limits to PAGE_SIZE, so
 310                  * that should be a reasonable upper bound
 311                  */
 312                 if (len > PAGE_SIZE)
 313                         return -EINVAL;
 314                 break;
 315         default:
 316                 if (len != 0)
 317                         return -EINVAL;
 318         }
 319
 320         switch (param) {
 321         case MSM_PARAM_COMM:
 322         case MSM_PARAM_CMDLINE: {
 323                 char *str, **paramp;
 324
 325                 str = kmalloc(len + 1, GFP_KERNEL);
 326                 if (!str)
 327                         return -ENOMEM;
 328
 329                 if (copy_from_user(str, u64_to_user_ptr(value), len)) {
 330                         kfree(str);
 331                         return -EFAULT;
 332                 }
 333
 334                 /* Ensure string is null terminated: */
 335                 str[len] = '\0';
 336
 337                 if (param == MSM_PARAM_COMM) {
 338                         paramp = &ctx->comm;
 339                 } else {
 340                         paramp = &ctx->cmdline;
 341                 }
 342
 343                 kfree(*paramp);
 344                 *paramp = str;
 345
 346                 return 0;
 347         }
 348         case MSM_PARAM_SYSPROF:
 349                 if (!capable(CAP_SYS_ADMIN))
 350                         return -EPERM;
 351                 return msm_file_private_set_sysprof(ctx, gpu, value);
 352         default:
 353                 DBG("%s: invalid param: %u", gpu->name, param);
 354                 return -EINVAL;
 355         }
 356 }
 357
 358 const struct firmware *
 359 adreno_request_fw(struct adreno_gpu *adreno_gpu, const char *fwname)
 360 {
 361         struct drm_device *drm = adreno_gpu->base.dev;
 362         const struct firmware *fw = NULL;
 363         char *newname;
 364         int ret;
 365
 366         newname = kasprintf(GFP_KERNEL, "qcom/%s", fwname);
 367         if (!newname)
 368                 return ERR_PTR(-ENOMEM);
 369
 370         /*
 371          * Try first to load from qcom/$fwfile using a direct load (to avoid
 372          * a potential timeout waiting for usermode helper)
 373          */
 374         if ((adreno_gpu->fwloc == FW_LOCATION_UNKNOWN) ||
 375             (adreno_gpu->fwloc == FW_LOCATION_NEW)) {
 376
 377                 ret = request_firmware_direct(&fw, newname, drm->dev);
 378                 if (!ret) {
 379                         DRM_DEV_INFO(drm->dev, "loaded %s from new location\n",
 380                                 newname);
 381                         adreno_gpu->fwloc = FW_LOCATION_NEW;
 382                         goto out;
 383                 } else if (adreno_gpu->fwloc != FW_LOCATION_UNKNOWN) {
 384                         DRM_DEV_ERROR(drm->dev, "failed to load %s: %d\n",
 385                                 newname, ret);
 386                         fw = ERR_PTR(ret);
 387                         goto out;
 388                 }
 389         }
 390
 391         /*
 392          * Then try the legacy location without qcom/ prefix
 393          */
 394         if ((adreno_gpu->fwloc == FW_LOCATION_UNKNOWN) ||
 395             (adreno_gpu->fwloc == FW_LOCATION_LEGACY)) {
 396
 397                 ret = request_firmware_direct(&fw, fwname, drm->dev);
 398                 if (!ret) {
 399                         DRM_DEV_INFO(drm->dev, "loaded %s from legacy location\n",
 400                                 newname);
 401                         adreno_gpu->fwloc = FW_LOCATION_LEGACY;
 402                         goto out;
 403                 } else if (adreno_gpu->fwloc != FW_LOCATION_UNKNOWN) {
 404                         DRM_DEV_ERROR(drm->dev, "failed to load %s: %d\n",
 405                                 fwname, ret);
 406                         fw = ERR_PTR(ret);
 407                         goto out;
 408                 }
 409         }
 410
 411         /*
 412          * Finally fall back to request_firmware() for cases where the
 413          * usermode helper is needed (I think mainly android)
 414          */
 415         if ((adreno_gpu->fwloc == FW_LOCATION_UNKNOWN) ||
 416             (adreno_gpu->fwloc == FW_LOCATION_HELPER)) {
 417
 418                 ret = request_firmware(&fw, newname, drm->dev);
 419                 if (!ret) {
 420                         DRM_DEV_INFO(drm->dev, "loaded %s with helper\n",
 421                                 newname);
 422                         adreno_gpu->fwloc = FW_LOCATION_HELPER;
 423                         goto out;
 424                 } else if (adreno_gpu->fwloc != FW_LOCATION_UNKNOWN) {
 425                         DRM_DEV_ERROR(drm->dev, "failed to load %s: %d\n",
 426                                 newname, ret);
 427                         fw = ERR_PTR(ret);
 428                         goto out;
 429                 }
 430         }
 431
 432         DRM_DEV_ERROR(drm->dev, "failed to load %s\n", fwname);
 433         fw = ERR_PTR(-ENOENT);
 434 out:
 435         kfree(newname);
 436         return fw;
 437 }
 438
 439 int adreno_load_fw(struct adreno_gpu *adreno_gpu)
 440 {
 441         int i;
 442
 443         for (i = 0; i < ARRAY_SIZE(adreno_gpu->info->fw); i++) {
 444                 const struct firmware *fw;
 445
 446                 if (!adreno_gpu->info->fw[i])
 447                         continue;
 448
 449                 /* Skip if the firmware has already been loaded */
 450                 if (adreno_gpu->fw[i])
 451                         continue;
 452
 453                 fw = adreno_request_fw(adreno_gpu, adreno_gpu->info->fw[i]);
 454                 if (IS_ERR(fw))
 455                         return PTR_ERR(fw);
 456
 457                 adreno_gpu->fw[i] = fw;
 458         }
 459
 460         return 0;
 461 }
 462
 463 struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu,
 464                 const struct firmware *fw, u64 *iova)
 465 {
 466         struct drm_gem_object *bo;
 467         void *ptr;
 468
 469         ptr = msm_gem_kernel_new(gpu->dev, fw->size - 4,
 470                 MSM_BO_WC | MSM_BO_GPU_READONLY, gpu->aspace, &bo, iova);
 471
 472         if (IS_ERR(ptr))
 473                 return ERR_CAST(ptr);
 474
 475         memcpy(ptr, &fw->data[4], fw->size - 4);
 476
 477         msm_gem_put_vaddr(bo);
 478
 479         return bo;
 480 }
 481
 482 int adreno_hw_init(struct msm_gpu *gpu)
 483 {
 484         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 485         int ret, i;
 486
 487         VERB("%s", gpu->name);
 488
 489         ret = adreno_load_fw(adreno_gpu);
 490         if (ret)
 491                 return ret;
 492
 493         for (i = 0; i < gpu->nr_rings; i++) {
 494                 struct msm_ringbuffer *ring = gpu->rb[i];
 495
 496                 if (!ring)
 497                         continue;
 498
 499                 ring->cur = ring->start;
 500                 ring->next = ring->start;
 501                 ring->memptrs->rptr = 0;
 502
 503                 /* Detect and clean up an impossible fence, ie. if GPU managed
 504                  * to scribble something invalid, we don't want that to confuse
 505                  * us into mistakingly believing that submits have completed.
 506                  */
 507                 if (fence_before(ring->fctx->last_fence, ring->memptrs->fence)) {
 508                         ring->memptrs->fence = ring->fctx->last_fence;
 509                 }
 510         }
 511
 512         return 0;
 513 }
 514
 515 /* Use this helper to read rptr, since a430 doesn't update rptr in memory */
 516 static uint32_t get_rptr(struct adreno_gpu *adreno_gpu,
 517                 struct msm_ringbuffer *ring)
 518 {
 519         struct msm_gpu *gpu = &adreno_gpu->base;
 520
 521         return gpu->funcs->get_rptr(gpu, ring);
 522 }
 523
 524 struct msm_ringbuffer *adreno_active_ring(struct msm_gpu *gpu)
 525 {
 526         return gpu->rb[0];
 527 }
 528
 529 void adreno_recover(struct msm_gpu *gpu)
 530 {
 531         struct drm_device *dev = gpu->dev;
 532         int ret;
 533
 534         // XXX pm-runtime??  we *need* the device to be off after this
 535         // so maybe continuing to call ->pm_suspend/resume() is better?
 536
 537         gpu->funcs->pm_suspend(gpu);
 538         gpu->funcs->pm_resume(gpu);
 539
 540         ret = msm_gpu_hw_init(gpu);
 541         if (ret) {
 542                 DRM_DEV_ERROR(dev->dev, "gpu hw init failed: %d\n", ret);
 543                 /* hmm, oh well? */
 544         }
 545 }
 546
 547 void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring, u32 reg)
 548 {
 549         uint32_t wptr;
 550
 551         /* Copy the shadow to the actual register */
 552         ring->cur = ring->next;
 553
 554         /*
 555          * Mask wptr value that we calculate to fit in the HW range. This is
 556          * to account for the possibility that the last command fit exactly into
 557          * the ringbuffer and rb->next hasn't wrapped to zero yet
 558          */
 559         wptr = get_wptr(ring);
 560
 561         /* ensure writes to ringbuffer have hit system memory: */
 562         mb();
 563
 564         gpu_write(gpu, reg, wptr);
 565 }
 566
 567 bool adreno_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
 568 {
 569         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 570         uint32_t wptr = get_wptr(ring);
 571
 572         /* wait for CP to drain ringbuffer: */
 573         if (!spin_until(get_rptr(adreno_gpu, ring) == wptr))
 574                 return true;
 575
 576         /* TODO maybe we need to reset GPU here to recover from hang? */
 577         DRM_ERROR("%s: timeout waiting to drain ringbuffer %d rptr/wptr = %X/%X\n",
 578                 gpu->name, ring->id, get_rptr(adreno_gpu, ring), wptr);
 579
 580         return false;
 581 }
 582
 583 int adreno_gpu_state_get(struct msm_gpu *gpu, struct msm_gpu_state *state)
 584 {
 585         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 586         int i, count = 0;
 587
 588         WARN_ON(!mutex_is_locked(&gpu->lock));
 589
 590         kref_init(&state->ref);
 591
 592         ktime_get_real_ts64(&state->time);
 593
 594         for (i = 0; i < gpu->nr_rings; i++) {
 595                 int size = 0, j;
 596
 597                 state->ring[i].fence = gpu->rb[i]->memptrs->fence;
 598                 state->ring[i].iova = gpu->rb[i]->iova;
 599                 state->ring[i].seqno = gpu->rb[i]->fctx->last_fence;
 600                 state->ring[i].rptr = get_rptr(adreno_gpu, gpu->rb[i]);
 601                 state->ring[i].wptr = get_wptr(gpu->rb[i]);
 602
 603                 /* Copy at least 'wptr' dwords of the data */
 604                 size = state->ring[i].wptr;
 605
 606                 /* After wptr find the last non zero dword to save space */
 607                 for (j = state->ring[i].wptr; j < MSM_GPU_RINGBUFFER_SZ >> 2; j++)
 608                         if (gpu->rb[i]->start[j])
 609                                 size = j + 1;
 610
 611                 if (size) {
 612                         state->ring[i].data = kvmalloc(size << 2, GFP_KERNEL);
 613                         if (state->ring[i].data) {
 614                                 memcpy(state->ring[i].data, gpu->rb[i]->start, size << 2);
 615                                 state->ring[i].data_size = size << 2;
 616                         }
 617                 }
 618         }
 619
 620         /* Some targets prefer to collect their own registers */
 621         if (!adreno_gpu->registers)
 622                 return 0;
 623
 624         /* Count the number of registers */
 625         for (i = 0; adreno_gpu->registers[i] != ~0; i += 2)
 626                 count += adreno_gpu->registers[i + 1] -
 627                         adreno_gpu->registers[i] + 1;
 628
 629         state->registers = kcalloc(count * 2, sizeof(u32), GFP_KERNEL);
 630         if (state->registers) {
 631                 int pos = 0;
 632
 633                 for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) {
 634                         u32 start = adreno_gpu->registers[i];
 635                         u32 end   = adreno_gpu->registers[i + 1];
 636                         u32 addr;
 637
 638                         for (addr = start; addr <= end; addr++) {
 639                                 state->registers[pos++] = addr;
 640                                 state->registers[pos++] = gpu_read(gpu, addr);
 641                         }
 642                 }
 643
 644                 state->nr_registers = count;
 645         }
 646
 647         return 0;
 648 }
 649
 650 void adreno_gpu_state_destroy(struct msm_gpu_state *state)
 651 {
 652         int i;
 653
 654         for (i = 0; i < ARRAY_SIZE(state->ring); i++)
 655                 kvfree(state->ring[i].data);
 656
 657         for (i = 0; state->bos && i < state->nr_bos; i++)
 658                 kvfree(state->bos[i].data);
 659
 660         kfree(state->bos);
 661         kfree(state->comm);
 662         kfree(state->cmd);
 663         kfree(state->registers);
 664 }
 665
 666 static void adreno_gpu_state_kref_destroy(struct kref *kref)
 667 {
 668         struct msm_gpu_state *state = container_of(kref,
 669                 struct msm_gpu_state, ref);
 670
 671         adreno_gpu_state_destroy(state);
 672         kfree(state);
 673 }
 674
 675 int adreno_gpu_state_put(struct msm_gpu_state *state)
 676 {
 677         if (IS_ERR_OR_NULL(state))
 678                 return 1;
 679
 680         return kref_put(&state->ref, adreno_gpu_state_kref_destroy);
 681 }
 682
 683 #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP)
 684
 685 static char *adreno_gpu_ascii85_encode(u32 *src, size_t len)
 686 {
 687         void *buf;
 688         size_t buf_itr = 0, buffer_size;
 689         char out[ASCII85_BUFSZ];
 690         long l;
 691         int i;
 692
 693         if (!src || !len)
 694                 return NULL;
 695
 696         l = ascii85_encode_len(len);
 697
 698         /*
 699          * Ascii85 outputs either a 5 byte string or a 1 byte string. So we
 700          * account for the worst case of 5 bytes per dword plus the 1 for '\0'
 701          */
 702         buffer_size = (l * 5) + 1;
 703
 704         buf = kvmalloc(buffer_size, GFP_KERNEL);
 705         if (!buf)
 706                 return NULL;
 707
 708         for (i = 0; i < l; i++)
 709                 buf_itr += scnprintf(buf + buf_itr, buffer_size - buf_itr, "%s",
 710                                 ascii85_encode(src[i], out));
 711
 712         return buf;
 713 }
 714
 715 /* len is expected to be in bytes */
 716 void adreno_show_object(struct drm_printer *p, void **ptr, int len,
 717                 bool *encoded)
 718 {
 719         if (!*ptr || !len)
 720                 return;
 721
 722         if (!*encoded) {
 723                 long datalen, i;
 724                 u32 *buf = *ptr;
 725
 726                 /*
 727                  * Only dump the non-zero part of the buffer - rarely will
 728                  * any data completely fill the entire allocated size of
 729                  * the buffer.
 730                  */
 731                 for (datalen = 0, i = 0; i < len >> 2; i++)
 732                         if (buf[i])
 733                                 datalen = ((i + 1) << 2);
 734
 735                 /*
 736                  * If we reach here, then the originally captured binary buffer
 737                  * will be replaced with the ascii85 encoded string
 738                  */
 739                 *ptr = adreno_gpu_ascii85_encode(buf, datalen);
 740
 741                 kvfree(buf);
 742
 743                 *encoded = true;
 744         }
 745
 746         if (!*ptr)
 747                 return;
 748
 749         drm_puts(p, "    data: !!ascii85 |\n");
 750         drm_puts(p, "     ");
 751
 752         drm_puts(p, *ptr);
 753
 754         drm_puts(p, "\n");
 755 }
 756
 757 void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
 758                 struct drm_printer *p)
 759 {
 760         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 761         int i;
 762
 763         if (IS_ERR_OR_NULL(state))
 764                 return;
 765
 766         drm_printf(p, "revision: %d (%d.%d.%d.%d)\n",
 767                         adreno_gpu->info->revn, adreno_gpu->rev.core,
 768                         adreno_gpu->rev.major, adreno_gpu->rev.minor,
 769                         adreno_gpu->rev.patchid);
 770         /*
 771          * If this is state collected due to iova fault, so fault related info
 772          *
 773          * TTBR0 would not be zero, so this is a good way to distinguish
 774          */
 775         if (state->fault_info.ttbr0) {
 776                 const struct msm_gpu_fault_info *info = &state->fault_info;
 777
 778                 drm_puts(p, "fault-info:\n");
 779                 drm_printf(p, "  - ttbr0=%.16llx\n", info->ttbr0);
 780                 drm_printf(p, "  - iova=%.16lx\n", info->iova);
 781                 drm_printf(p, "  - dir=%s\n", info->flags & IOMMU_FAULT_WRITE ? "WRITE" : "READ");
 782                 drm_printf(p, "  - type=%s\n", info->type);
 783                 drm_printf(p, "  - source=%s\n", info->block);
 784         }
 785
 786         drm_printf(p, "rbbm-status: 0x%08x\n", state->rbbm_status);
 787
 788         drm_puts(p, "ringbuffer:\n");
 789
 790         for (i = 0; i < gpu->nr_rings; i++) {
 791                 drm_printf(p, "  - id: %d\n", i);
 792                 drm_printf(p, "    iova: 0x%016llx\n", state->ring[i].iova);
 793                 drm_printf(p, "    last-fence: %d\n", state->ring[i].seqno);
 794                 drm_printf(p, "    retired-fence: %d\n", state->ring[i].fence);
 795                 drm_printf(p, "    rptr: %d\n", state->ring[i].rptr);
 796                 drm_printf(p, "    wptr: %d\n", state->ring[i].wptr);
 797                 drm_printf(p, "    size: %d\n", MSM_GPU_RINGBUFFER_SZ);
 798
 799                 adreno_show_object(p, &state->ring[i].data,
 800                         state->ring[i].data_size, &state->ring[i].encoded);
 801         }
 802
 803         if (state->bos) {
 804                 drm_puts(p, "bos:\n");
 805
 806                 for (i = 0; i < state->nr_bos; i++) {
 807                         drm_printf(p, "  - iova: 0x%016llx\n",
 808                                 state->bos[i].iova);
 809                         drm_printf(p, "    size: %zd\n", state->bos[i].size);
 810
 811                         adreno_show_object(p, &state->bos[i].data,
 812                                 state->bos[i].size, &state->bos[i].encoded);
 813                 }
 814         }
 815
 816         if (state->nr_registers) {
 817                 drm_puts(p, "registers:\n");
 818
 819                 for (i = 0; i < state->nr_registers; i++) {
 820                         drm_printf(p, "  - { offset: 0x%04x, value: 0x%08x }\n",
 821                                 state->registers[i * 2] << 2,
 822                                 state->registers[(i * 2) + 1]);
 823                 }
 824         }
 825 }
 826 #endif
 827
 828 /* Dump common gpu status and scratch registers on any hang, to make
 829  * the hangcheck logs more useful.  The scratch registers seem always
 830  * safe to read when GPU has hung (unlike some other regs, depending
 831  * on how the GPU hung), and they are useful to match up to cmdstream
 832  * dumps when debugging hangs:
 833  */
 834 void adreno_dump_info(struct msm_gpu *gpu)
 835 {
 836         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 837         int i;
 838
 839         printk("revision: %d (%d.%d.%d.%d)\n",
 840                         adreno_gpu->info->revn, adreno_gpu->rev.core,
 841                         adreno_gpu->rev.major, adreno_gpu->rev.minor,
 842                         adreno_gpu->rev.patchid);
 843
 844         for (i = 0; i < gpu->nr_rings; i++) {
 845                 struct msm_ringbuffer *ring = gpu->rb[i];
 846
 847                 printk("rb %d: fence:    %d/%d\n", i,
 848                         ring->memptrs->fence,
 849                         ring->fctx->last_fence);
 850
 851                 printk("rptr:     %d\n", get_rptr(adreno_gpu, ring));
 852                 printk("rb wptr:  %d\n", get_wptr(ring));
 853         }
 854 }
 855
 856 /* would be nice to not have to duplicate the _show() stuff with printk(): */
 857 void adreno_dump(struct msm_gpu *gpu)
 858 {
 859         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 860         int i;
 861
 862         if (!adreno_gpu->registers)
 863                 return;
 864
 865         /* dump these out in a form that can be parsed by demsm: */
 866         printk("IO:region %s 00000000 00020000\n", gpu->name);
 867         for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) {
 868                 uint32_t start = adreno_gpu->registers[i];
 869                 uint32_t end   = adreno_gpu->registers[i+1];
 870                 uint32_t addr;
 871
 872                 for (addr = start; addr <= end; addr++) {
 873                         uint32_t val = gpu_read(gpu, addr);
 874                         printk("IO:R %08x %08x\n", addr<<2, val);
 875                 }
 876         }
 877 }
 878
 879 static uint32_t ring_freewords(struct msm_ringbuffer *ring)
 880 {
 881         struct adreno_gpu *adreno_gpu = to_adreno_gpu(ring->gpu);
 882         uint32_t size = MSM_GPU_RINGBUFFER_SZ >> 2;
 883         /* Use ring->next to calculate free size */
 884         uint32_t wptr = ring->next - ring->start;
 885         uint32_t rptr = get_rptr(adreno_gpu, ring);
 886         return (rptr + (size - 1) - wptr) % size;
 887 }
 888
 889 void adreno_wait_ring(struct msm_ringbuffer *ring, uint32_t ndwords)
 890 {
 891         if (spin_until(ring_freewords(ring) >= ndwords))
 892                 DRM_DEV_ERROR(ring->gpu->dev->dev,
 893                         "timeout waiting for space in ringbuffer %d\n",
 894                         ring->id);
 895 }
 896
 897 /* Get legacy powerlevels from qcom,gpu-pwrlevels and populate the opp table */
 898 static int adreno_get_legacy_pwrlevels(struct device *dev)
 899 {
 900         struct device_node *child, *node;
 901         int ret;
 902
 903         node = of_get_compatible_child(dev->of_node, "qcom,gpu-pwrlevels");
 904         if (!node) {
 905                 DRM_DEV_DEBUG(dev, "Could not find the GPU powerlevels\n");
 906                 return -ENXIO;
 907         }
 908
 909         for_each_child_of_node(node, child) {
 910                 unsigned int val;
 911
 912                 ret = of_property_read_u32(child, "qcom,gpu-freq", &val);
 913                 if (ret)
 914                         continue;
 915
 916                 /*
 917                  * Skip the intentionally bogus clock value found at the bottom
 918                  * of most legacy frequency tables
 919                  */
 920                 if (val != 27000000)
 921                         dev_pm_opp_add(dev, val, 0);
 922         }
 923
 924         of_node_put(node);
 925
 926         return 0;
 927 }
 928
 929 static void adreno_get_pwrlevels(struct device *dev,
 930                 struct msm_gpu *gpu)
 931 {
 932         unsigned long freq = ULONG_MAX;
 933         struct dev_pm_opp *opp;
 934         int ret;
 935
 936         gpu->fast_rate = 0;
 937
 938         /* You down with OPP? */
 939         if (!of_find_property(dev->of_node, "operating-points-v2", NULL))
 940                 ret = adreno_get_legacy_pwrlevels(dev);
 941         else {
 942                 ret = devm_pm_opp_of_add_table(dev);
 943                 if (ret)
 944                         DRM_DEV_ERROR(dev, "Unable to set the OPP table\n");
 945         }
 946
 947         if (!ret) {
 948                 /* Find the fastest defined rate */
 949                 opp = dev_pm_opp_find_freq_floor(dev, &freq);
 950                 if (!IS_ERR(opp)) {
 951                         gpu->fast_rate = freq;
 952                         dev_pm_opp_put(opp);
 953                 }
 954         }
 955
 956         if (!gpu->fast_rate) {
 957                 dev_warn(dev,
 958                         "Could not find a clock rate. Using a reasonable default\n");
 959                 /* Pick a suitably safe clock speed for any target */
 960                 gpu->fast_rate = 200000000;
 961         }
 962
 963         DBG("fast_rate=%u, slow_rate=27000000", gpu->fast_rate);
 964 }
 965
 966 int adreno_gpu_ocmem_init(struct device *dev, struct adreno_gpu *adreno_gpu,
 967                           struct adreno_ocmem *adreno_ocmem)
 968 {
 969         struct ocmem_buf *ocmem_hdl;
 970         struct ocmem *ocmem;
 971
 972         ocmem = of_get_ocmem(dev);
 973         if (IS_ERR(ocmem)) {
 974                 if (PTR_ERR(ocmem) == -ENODEV) {
 975                         /*
 976                          * Return success since either the ocmem property was
 977                          * not specified in device tree, or ocmem support is
 978                          * not compiled into the kernel.
 979                          */
 980                         return 0;
 981                 }
 982
 983                 return PTR_ERR(ocmem);
 984         }
 985
 986         ocmem_hdl = ocmem_allocate(ocmem, OCMEM_GRAPHICS, adreno_gpu->gmem);
 987         if (IS_ERR(ocmem_hdl))
 988                 return PTR_ERR(ocmem_hdl);
 989
 990         adreno_ocmem->ocmem = ocmem;
 991         adreno_ocmem->base = ocmem_hdl->addr;
 992         adreno_ocmem->hdl = ocmem_hdl;
 993         adreno_gpu->gmem = ocmem_hdl->len;
 994
 995         return 0;
 996 }
 997
 998 void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *adreno_ocmem)
 999 {
1000         if (adreno_ocmem && adreno_ocmem->base)
1001                 ocmem_free(adreno_ocmem->ocmem, OCMEM_GRAPHICS,
1002                            adreno_ocmem->hdl);
1003 }
1004
1005 int adreno_read_speedbin(struct device *dev, u32 *speedbin)
1006 {
1007         return nvmem_cell_read_variable_le_u32(dev, "speed_bin", speedbin);
1008 }
1009
1010 int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
1011                 struct adreno_gpu *adreno_gpu,
1012                 const struct adreno_gpu_funcs *funcs, int nr_rings)
1013 {
1014         struct device *dev = &pdev->dev;
1015         struct adreno_platform_config *config = dev->platform_data;
1016         struct msm_gpu_config adreno_gpu_config  = { 0 };
1017         struct msm_gpu *gpu = &adreno_gpu->base;
1018         struct adreno_rev *rev = &config->rev;
1019         const char *gpu_name;
1020         u32 speedbin;
1021
1022         adreno_gpu->funcs = funcs;
1023         adreno_gpu->info = adreno_info(config->rev);
1024         adreno_gpu->gmem = adreno_gpu->info->gmem;
1025         adreno_gpu->revn = adreno_gpu->info->revn;
1026         adreno_gpu->rev = *rev;
1027
1028         if (adreno_read_speedbin(dev, &speedbin) || !speedbin)
1029                 speedbin = 0xffff;
1030         adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin);
1031
1032         gpu_name = adreno_gpu->info->name;
1033         if (!gpu_name) {
1034                 gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%d.%d.%d.%d",
1035                                 rev->core, rev->major, rev->minor,
1036                                 rev->patchid);
1037                 if (!gpu_name)
1038                         return -ENOMEM;
1039         }
1040
1041         adreno_gpu_config.ioname = "kgsl_3d0_reg_memory";
1042
1043         adreno_gpu_config.nr_rings = nr_rings;
1044
1045         adreno_get_pwrlevels(dev, gpu);
1046
1047         pm_runtime_set_autosuspend_delay(dev,
1048                 adreno_gpu->info->inactive_period);
1049         pm_runtime_use_autosuspend(dev);
1050         pm_runtime_enable(dev);
1051
1052         return msm_gpu_init(drm, pdev, &adreno_gpu->base, &funcs->base,
1053                         gpu_name, &adreno_gpu_config);
1054 }
1055
1056 void adreno_gpu_cleanup(struct adreno_gpu *adreno_gpu)
1057 {
1058         struct msm_gpu *gpu = &adreno_gpu->base;
1059         struct msm_drm_private *priv = gpu->dev->dev_private;
1060         unsigned int i;
1061
1062         for (i = 0; i < ARRAY_SIZE(adreno_gpu->info->fw); i++)
1063                 release_firmware(adreno_gpu->fw[i]);
1064
1065         if (pm_runtime_enabled(&priv->gpu_pdev->dev))
1066                 pm_runtime_disable(&priv->gpu_pdev->dev);
1067
1068         msm_gpu_cleanup(&adreno_gpu->base);
1069 }