drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. */
   3
   4 #ifndef _A6XX_CRASH_DUMP_H_
   5 #define _A6XX_CRASH_DUMP_H_
   6
   7 #include "a6xx.xml.h"
   8
   9 #define A6XX_NUM_CONTEXTS 2
  10 #define A6XX_NUM_SHADER_BANKS 3
  11
  12 static const u32 a6xx_gras_cluster[] = {
  13         0x8000, 0x8006, 0x8010, 0x8092, 0x8094, 0x809d, 0x80a0, 0x80a6,
  14         0x80af, 0x80f1, 0x8100, 0x8107, 0x8109, 0x8109, 0x8110, 0x8110,
  15         0x8400, 0x840b,
  16 };
  17
  18 static const u32 a6xx_ps_cluster_rac[] = {
  19         0x8800, 0x8806, 0x8809, 0x8811, 0x8818, 0x881e, 0x8820, 0x8865,
  20         0x8870, 0x8879, 0x8880, 0x8889, 0x8890, 0x8891, 0x8898, 0x8898,
  21         0x88c0, 0x88c1, 0x88d0, 0x88e3, 0x8900, 0x890c, 0x890f, 0x891a,
  22         0x8c00, 0x8c01, 0x8c08, 0x8c10, 0x8c17, 0x8c1f, 0x8c26, 0x8c33,
  23 };
  24
  25 static const u32 a6xx_ps_cluster_rbp[] = {
  26         0x88f0, 0x88f3, 0x890d, 0x890e, 0x8927, 0x8928, 0x8bf0, 0x8bf1,
  27         0x8c02, 0x8c07, 0x8c11, 0x8c16, 0x8c20, 0x8c25,
  28 };
  29
  30 static const u32 a6xx_ps_cluster[] = {
  31         0x9200, 0x9216, 0x9218, 0x9236, 0x9300, 0x9306,
  32 };
  33
  34 static const u32 a6xx_fe_cluster[] = {
  35         0x9300, 0x9306, 0x9800, 0x9806, 0x9b00, 0x9b07, 0xa000, 0xa009,
  36         0xa00e, 0xa0ef, 0xa0f8, 0xa0f8,
  37 };
  38
  39 static const u32 a660_fe_cluster[] = {
  40         0x9807, 0x9807,
  41 };
  42
  43 static const u32 a6xx_pc_vs_cluster[] = {
  44         0x9100, 0x9108, 0x9300, 0x9306, 0x9980, 0x9981, 0x9b00, 0x9b07,
  45 };
  46
  47 #define CLUSTER_FE      0
  48 #define CLUSTER_SP_VS   1
  49 #define CLUSTER_PC_VS   2
  50 #define CLUSTER_GRAS    3
  51 #define CLUSTER_SP_PS   4
  52 #define CLUSTER_PS      5
  53 #define CLUSTER_VPC_PS  6
  54
  55 #define CLUSTER(_id, _reg, _sel_reg, _sel_val) \
  56         { .id = _id, .name = #_id,\
  57                 .registers = _reg, \
  58                 .count = ARRAY_SIZE(_reg), \
  59                 .sel_reg = _sel_reg, .sel_val = _sel_val }
  60
  61 static const struct a6xx_cluster {
  62         u32 id;
  63         const char *name;
  64         const u32 *registers;
  65         size_t count;
  66         u32 sel_reg;
  67         u32 sel_val;
  68 } a6xx_clusters[] = {
  69         CLUSTER(CLUSTER_GRAS, a6xx_gras_cluster, 0, 0),
  70         CLUSTER(CLUSTER_PS, a6xx_ps_cluster_rac, REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 0x0),
  71         CLUSTER(CLUSTER_PS, a6xx_ps_cluster_rbp, REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 0x9),
  72         CLUSTER(CLUSTER_PS, a6xx_ps_cluster, 0, 0),
  73         CLUSTER(CLUSTER_FE, a6xx_fe_cluster, 0, 0),
  74         CLUSTER(CLUSTER_PC_VS, a6xx_pc_vs_cluster, 0, 0),
  75         CLUSTER(CLUSTER_FE, a660_fe_cluster, 0, 0),
  76 };
  77
  78 static const u32 a6xx_sp_vs_hlsq_cluster[] = {
  79         0xb800, 0xb803, 0xb820, 0xb822,
  80 };
  81
  82 static const u32 a6xx_sp_vs_sp_cluster[] = {
  83         0xa800, 0xa824, 0xa830, 0xa83c, 0xa840, 0xa864, 0xa870, 0xa895,
  84         0xa8a0, 0xa8af, 0xa8c0, 0xa8c3,
  85 };
  86
  87 static const u32 a6xx_hlsq_duplicate_cluster[] = {
  88         0xbb10, 0xbb11, 0xbb20, 0xbb29,
  89 };
  90
  91 static const u32 a6xx_hlsq_2d_duplicate_cluster[] = {
  92         0xbd80, 0xbd80,
  93 };
  94
  95 static const u32 a6xx_sp_duplicate_cluster[] = {
  96         0xab00, 0xab00, 0xab04, 0xab05, 0xab10, 0xab1b, 0xab20, 0xab20,
  97 };
  98
  99 static const u32 a6xx_tp_duplicate_cluster[] = {
 100         0xb300, 0xb307, 0xb309, 0xb309, 0xb380, 0xb382,
 101 };
 102
 103 static const u32 a6xx_sp_ps_hlsq_cluster[] = {
 104         0xb980, 0xb980, 0xb982, 0xb987, 0xb990, 0xb99b, 0xb9a0, 0xb9a2,
 105         0xb9c0, 0xb9c9,
 106 };
 107
 108 static const u32 a6xx_sp_ps_hlsq_2d_cluster[] = {
 109         0xbd80, 0xbd80,
 110 };
 111
 112 static const u32 a6xx_sp_ps_sp_cluster[] = {
 113         0xa980, 0xa9a8, 0xa9b0, 0xa9bc, 0xa9d0, 0xa9d3, 0xa9e0, 0xa9f3,
 114         0xaa00, 0xaa00, 0xaa30, 0xaa31, 0xaaf2, 0xaaf2,
 115 };
 116
 117 static const u32 a6xx_sp_ps_sp_2d_cluster[] = {
 118         0xacc0, 0xacc0,
 119 };
 120
 121 static const u32 a6xx_sp_ps_tp_cluster[] = {
 122         0xb180, 0xb183, 0xb190, 0xb191,
 123 };
 124
 125 static const u32 a6xx_sp_ps_tp_2d_cluster[] = {
 126         0xb4c0, 0xb4d1,
 127 };
 128
 129 #define CLUSTER_DBGAHB(_id, _base, _type, _reg) \
 130         { .name = #_id, .statetype = _type, .base = _base, \
 131                 .registers = _reg, .count = ARRAY_SIZE(_reg) }
 132
 133 static const struct a6xx_dbgahb_cluster {
 134         const char *name;
 135         u32 statetype;
 136         u32 base;
 137         const u32 *registers;
 138         size_t count;
 139 } a6xx_dbgahb_clusters[] = {
 140         CLUSTER_DBGAHB(CLUSTER_SP_VS, 0x0002e000, 0x41, a6xx_sp_vs_hlsq_cluster),
 141         CLUSTER_DBGAHB(CLUSTER_SP_VS, 0x0002a000, 0x21, a6xx_sp_vs_sp_cluster),
 142         CLUSTER_DBGAHB(CLUSTER_SP_VS, 0x0002e000, 0x41, a6xx_hlsq_duplicate_cluster),
 143         CLUSTER_DBGAHB(CLUSTER_SP_VS, 0x0002f000, 0x45, a6xx_hlsq_2d_duplicate_cluster),
 144         CLUSTER_DBGAHB(CLUSTER_SP_VS, 0x0002a000, 0x21, a6xx_sp_duplicate_cluster),
 145         CLUSTER_DBGAHB(CLUSTER_SP_VS, 0x0002c000, 0x1, a6xx_tp_duplicate_cluster),
 146         CLUSTER_DBGAHB(CLUSTER_SP_PS, 0x0002e000, 0x42, a6xx_sp_ps_hlsq_cluster),
 147         CLUSTER_DBGAHB(CLUSTER_SP_PS, 0x0002f000, 0x46, a6xx_sp_ps_hlsq_2d_cluster),
 148         CLUSTER_DBGAHB(CLUSTER_SP_PS, 0x0002a000, 0x22, a6xx_sp_ps_sp_cluster),
 149         CLUSTER_DBGAHB(CLUSTER_SP_PS, 0x0002b000, 0x26, a6xx_sp_ps_sp_2d_cluster),
 150         CLUSTER_DBGAHB(CLUSTER_SP_PS, 0x0002c000, 0x2, a6xx_sp_ps_tp_cluster),
 151         CLUSTER_DBGAHB(CLUSTER_SP_PS, 0x0002d000, 0x6, a6xx_sp_ps_tp_2d_cluster),
 152         CLUSTER_DBGAHB(CLUSTER_SP_PS, 0x0002e000, 0x42, a6xx_hlsq_duplicate_cluster),
 153         CLUSTER_DBGAHB(CLUSTER_SP_PS, 0x0002a000, 0x22, a6xx_sp_duplicate_cluster),
 154         CLUSTER_DBGAHB(CLUSTER_SP_PS, 0x0002c000, 0x2, a6xx_tp_duplicate_cluster),
 155 };
 156
 157 static const u32 a6xx_hlsq_registers[] = {
 158         0xbe00, 0xbe01, 0xbe04, 0xbe05, 0xbe08, 0xbe09, 0xbe10, 0xbe15,
 159         0xbe20, 0xbe23,
 160 };
 161
 162 static const u32 a6xx_sp_registers[] = {
 163         0xae00, 0xae04, 0xae0c, 0xae0c, 0xae0f, 0xae2b, 0xae30, 0xae32,
 164         0xae35, 0xae35, 0xae3a, 0xae3f, 0xae50, 0xae52,
 165 };
 166
 167 static const u32 a6xx_tp_registers[] = {
 168         0xb600, 0xb601, 0xb604, 0xb605, 0xb610, 0xb61b, 0xb620, 0xb623,
 169 };
 170
 171 struct a6xx_registers {
 172         const u32 *registers;
 173         size_t count;
 174         u32 val0;
 175         u32 val1;
 176 };
 177
 178 #define HLSQ_DBG_REGS(_base, _type, _array) \
 179         { .val0 = _base, .val1 = _type, .registers = _array, \
 180                 .count = ARRAY_SIZE(_array), }
 181
 182 static const struct a6xx_registers a6xx_hlsq_reglist[] = {
 183         HLSQ_DBG_REGS(0x0002F800, 0x40, a6xx_hlsq_registers),
 184         HLSQ_DBG_REGS(0x0002B800, 0x20, a6xx_sp_registers),
 185         HLSQ_DBG_REGS(0x0002D800, 0x0, a6xx_tp_registers),
 186 };
 187
 188 #define SHADER(_type, _size) \
 189         { .type = _type, .name = #_type, .size = _size }
 190
 191 static const struct a6xx_shader_block {
 192         const char *name;
 193         u32 type;
 194         u32 size;
 195 } a6xx_shader_blocks[] = {
 196         SHADER(A6XX_TP0_TMO_DATA, 0x200),
 197         SHADER(A6XX_TP0_SMO_DATA, 0x80),
 198         SHADER(A6XX_TP0_MIPMAP_BASE_DATA, 0x3c0),
 199         SHADER(A6XX_TP1_TMO_DATA, 0x200),
 200         SHADER(A6XX_TP1_SMO_DATA, 0x80),
 201         SHADER(A6XX_TP1_MIPMAP_BASE_DATA, 0x3c0),
 202         SHADER(A6XX_SP_INST_DATA, 0x800),
 203         SHADER(A6XX_SP_LB_0_DATA, 0x800),
 204         SHADER(A6XX_SP_LB_1_DATA, 0x800),
 205         SHADER(A6XX_SP_LB_2_DATA, 0x800),
 206         SHADER(A6XX_SP_LB_3_DATA, 0x800),
 207         SHADER(A6XX_SP_LB_4_DATA, 0x800),
 208         SHADER(A6XX_SP_LB_5_DATA, 0x200),
 209         SHADER(A6XX_SP_CB_BINDLESS_DATA, 0x2000),
 210         SHADER(A6XX_SP_CB_LEGACY_DATA, 0x280),
 211         SHADER(A6XX_SP_UAV_DATA, 0x80),
 212         SHADER(A6XX_SP_INST_TAG, 0x80),
 213         SHADER(A6XX_SP_CB_BINDLESS_TAG, 0x80),
 214         SHADER(A6XX_SP_TMO_UMO_TAG, 0x80),
 215         SHADER(A6XX_SP_SMO_TAG, 0x80),
 216         SHADER(A6XX_SP_STATE_DATA, 0x3f),
 217         SHADER(A6XX_HLSQ_CHUNK_CVS_RAM, 0x1c0),
 218         SHADER(A6XX_HLSQ_CHUNK_CPS_RAM, 0x280),
 219         SHADER(A6XX_HLSQ_CHUNK_CVS_RAM_TAG, 0x40),
 220         SHADER(A6XX_HLSQ_CHUNK_CPS_RAM_TAG, 0x40),
 221         SHADER(A6XX_HLSQ_ICB_CVS_CB_BASE_TAG, 0x4),
 222         SHADER(A6XX_HLSQ_ICB_CPS_CB_BASE_TAG, 0x4),
 223         SHADER(A6XX_HLSQ_CVS_MISC_RAM, 0x1c0),
 224         SHADER(A6XX_HLSQ_CPS_MISC_RAM, 0x580),
 225         SHADER(A6XX_HLSQ_INST_RAM, 0x800),
 226         SHADER(A6XX_HLSQ_GFX_CVS_CONST_RAM, 0x800),
 227         SHADER(A6XX_HLSQ_GFX_CPS_CONST_RAM, 0x800),
 228         SHADER(A6XX_HLSQ_CVS_MISC_RAM_TAG, 0x8),
 229         SHADER(A6XX_HLSQ_CPS_MISC_RAM_TAG, 0x4),
 230         SHADER(A6XX_HLSQ_INST_RAM_TAG, 0x80),
 231         SHADER(A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG, 0xc),
 232         SHADER(A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG, 0x10),
 233         SHADER(A6XX_HLSQ_PWR_REST_RAM, 0x28),
 234         SHADER(A6XX_HLSQ_PWR_REST_TAG, 0x14),
 235         SHADER(A6XX_HLSQ_DATAPATH_META, 0x40),
 236         SHADER(A6XX_HLSQ_FRONTEND_META, 0x40),
 237         SHADER(A6XX_HLSQ_INDIRECT_META, 0x40),
 238         SHADER(A6XX_SP_LB_6_DATA, 0x200),
 239         SHADER(A6XX_SP_LB_7_DATA, 0x200),
 240         SHADER(A6XX_HLSQ_INST_RAM_1, 0x200),
 241 };
 242
 243 static const u32 a6xx_rb_rac_registers[] = {
 244         0x8e04, 0x8e05, 0x8e07, 0x8e08, 0x8e10, 0x8e1c, 0x8e20, 0x8e25,
 245         0x8e28, 0x8e28, 0x8e2c, 0x8e2f, 0x8e50, 0x8e52,
 246 };
 247
 248 static const u32 a6xx_rb_rbp_registers[] = {
 249         0x8e01, 0x8e01, 0x8e0c, 0x8e0c, 0x8e3b, 0x8e3e, 0x8e40, 0x8e43,
 250         0x8e53, 0x8e5f, 0x8e70, 0x8e77,
 251 };
 252
 253 static const u32 a6xx_registers[] = {
 254         /* RBBM */
 255         0x0000, 0x0002, 0x0010, 0x0010, 0x0012, 0x0012, 0x0018, 0x001b,
 256         0x001e, 0x0032, 0x0038, 0x003c, 0x0042, 0x0042, 0x0044, 0x0044,
 257         0x0047, 0x0047, 0x0056, 0x0056, 0x00ad, 0x00ae, 0x00b0, 0x00fb,
 258         0x0100, 0x011d, 0x0200, 0x020d, 0x0218, 0x023d, 0x0400, 0x04f9,
 259         0x0500, 0x0500, 0x0505, 0x050b, 0x050e, 0x0511, 0x0533, 0x0533,
 260         0x0540, 0x0555,
 261         /* CP */
 262         0x0800, 0x0808, 0x0810, 0x0813, 0x0820, 0x0821, 0x0823, 0x0824,
 263         0x0826, 0x0827, 0x0830, 0x0833, 0x0840, 0x0845, 0x084f, 0x086f,
 264         0x0880, 0x088a, 0x08a0, 0x08ab, 0x08c0, 0x08c4, 0x08d0, 0x08dd,
 265         0x08f0, 0x08f3, 0x0900, 0x0903, 0x0908, 0x0911, 0x0928, 0x093e,
 266         0x0942, 0x094d, 0x0980, 0x0984, 0x098d, 0x0996, 0x0998, 0x099e,
 267         0x09a0, 0x09a6, 0x09a8, 0x09ae, 0x09b0, 0x09b1, 0x09c2, 0x09c8,
 268         0x0a00, 0x0a03,
 269         /* VSC */
 270         0x0c00, 0x0c04, 0x0c06, 0x0c06, 0x0c10, 0x0cd9, 0x0e00, 0x0e0e,
 271         /* UCHE */
 272         0x0e10, 0x0e13, 0x0e17, 0x0e19, 0x0e1c, 0x0e2b, 0x0e30, 0x0e32,
 273         0x0e38, 0x0e39,
 274         /* GRAS */
 275         0x8600, 0x8601, 0x8610, 0x861b, 0x8620, 0x8620, 0x8628, 0x862b,
 276         0x8630, 0x8637,
 277         /* VPC */
 278         0x9600, 0x9604, 0x9624, 0x9637,
 279         /* PC */
 280         0x9e00, 0x9e01, 0x9e03, 0x9e0e, 0x9e11, 0x9e16, 0x9e19, 0x9e19,
 281         0x9e1c, 0x9e1c, 0x9e20, 0x9e23, 0x9e30, 0x9e31, 0x9e34, 0x9e34,
 282         0x9e70, 0x9e72, 0x9e78, 0x9e79, 0x9e80, 0x9fff,
 283         /* VFD */
 284         0xa600, 0xa601, 0xa603, 0xa603, 0xa60a, 0xa60a, 0xa610, 0xa617,
 285         0xa630, 0xa630,
 286         /* HLSQ */
 287         0xd002, 0xd003,
 288 };
 289
 290 static const u32 a660_registers[] = {
 291         /* UCHE */
 292         0x0e3c, 0x0e3c,
 293 };
 294
 295 #define REGS(_array, _sel_reg, _sel_val) \
 296         { .registers = _array, .count = ARRAY_SIZE(_array), \
 297                 .val0 = _sel_reg, .val1 = _sel_val }
 298
 299 static const struct a6xx_registers a6xx_reglist[] = {
 300         REGS(a6xx_registers, 0, 0),
 301         REGS(a660_registers, 0, 0),
 302         REGS(a6xx_rb_rac_registers, REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 0),
 303         REGS(a6xx_rb_rbp_registers, REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 9),
 304 };
 305
 306 static const u32 a6xx_ahb_registers[] = {
 307         /* RBBM_STATUS - RBBM_STATUS3 */
 308         0x210, 0x213,
 309         /* CP_STATUS_1 */
 310         0x825, 0x825,
 311 };
 312
 313 static const u32 a6xx_vbif_registers[] = {
 314         0x3000, 0x3007, 0x300c, 0x3014, 0x3018, 0x302d, 0x3030, 0x3031,
 315         0x3034, 0x3036, 0x303c, 0x303d, 0x3040, 0x3040, 0x3042, 0x3042,
 316         0x3049, 0x3049, 0x3058, 0x3058, 0x305a, 0x3061, 0x3064, 0x3068,
 317         0x306c, 0x306d, 0x3080, 0x3088, 0x308b, 0x308c, 0x3090, 0x3094,
 318         0x3098, 0x3098, 0x309c, 0x309c, 0x30c0, 0x30c0, 0x30c8, 0x30c8,
 319         0x30d0, 0x30d0, 0x30d8, 0x30d8, 0x30e0, 0x30e0, 0x3100, 0x3100,
 320         0x3108, 0x3108, 0x3110, 0x3110, 0x3118, 0x3118, 0x3120, 0x3120,
 321         0x3124, 0x3125, 0x3129, 0x3129, 0x3131, 0x3131, 0x3154, 0x3154,
 322         0x3156, 0x3156, 0x3158, 0x3158, 0x315a, 0x315a, 0x315c, 0x315c,
 323         0x315e, 0x315e, 0x3160, 0x3160, 0x3162, 0x3162, 0x340c, 0x340c,
 324         0x3410, 0x3410, 0x3800, 0x3801,
 325 };
 326
 327 static const u32 a6xx_gbif_registers[] = {
 328         0x3C00, 0X3C0B, 0X3C40, 0X3C47, 0X3CC0, 0X3CD1, 0xE3A, 0xE3A,
 329 };
 330
 331 static const struct a6xx_registers a6xx_ahb_reglist[] = {
 332         REGS(a6xx_ahb_registers, 0, 0),
 333 };
 334
 335 static const struct a6xx_registers a6xx_vbif_reglist =
 336                         REGS(a6xx_vbif_registers, 0, 0);
 337
 338 static const struct a6xx_registers a6xx_gbif_reglist =
 339                         REGS(a6xx_gbif_registers, 0, 0);
 340
 341 static const u32 a6xx_gmu_gx_registers[] = {
 342         /* GMU GX */
 343         0x0000, 0x0000, 0x0010, 0x0013, 0x0016, 0x0016, 0x0018, 0x001b,
 344         0x001e, 0x001e, 0x0020, 0x0023, 0x0026, 0x0026, 0x0028, 0x002b,
 345         0x002e, 0x002e, 0x0030, 0x0033, 0x0036, 0x0036, 0x0038, 0x003b,
 346         0x003e, 0x003e, 0x0040, 0x0043, 0x0046, 0x0046, 0x0080, 0x0084,
 347         0x0100, 0x012b, 0x0140, 0x0140,
 348 };
 349
 350 static const u32 a6xx_gmu_cx_registers[] = {
 351         /* GMU CX */
 352         0x4c00, 0x4c07, 0x4c10, 0x4c12, 0x4d00, 0x4d00, 0x4d07, 0x4d0a,
 353         0x5000, 0x5004, 0x5007, 0x5008, 0x500b, 0x500c, 0x500f, 0x501c,
 354         0x5024, 0x502a, 0x502d, 0x5030, 0x5040, 0x5053, 0x5087, 0x5089,
 355         0x50a0, 0x50a2, 0x50a4, 0x50af, 0x50c0, 0x50c3, 0x50d0, 0x50d0,
 356         0x50e4, 0x50e4, 0x50e8, 0x50ec, 0x5100, 0x5103, 0x5140, 0x5140,
 357         0x5142, 0x5144, 0x514c, 0x514d, 0x514f, 0x5151, 0x5154, 0x5154,
 358         0x5157, 0x5158, 0x515d, 0x515d, 0x5162, 0x5162, 0x5164, 0x5165,
 359         0x5180, 0x5186, 0x5190, 0x519e, 0x51c0, 0x51c0, 0x51c5, 0x51cc,
 360         0x51e0, 0x51e2, 0x51f0, 0x51f0, 0x5200, 0x5201,
 361         /* GMU AO */
 362         0x9300, 0x9316, 0x9400, 0x9400,
 363         /* GPU CC */
 364         0x9800, 0x9812, 0x9840, 0x9852, 0x9c00, 0x9c04, 0x9c07, 0x9c0b,
 365         0x9c15, 0x9c1c, 0x9c1e, 0x9c2d, 0x9c3c, 0x9c3d, 0x9c3f, 0x9c40,
 366         0x9c42, 0x9c49, 0x9c58, 0x9c5a, 0x9d40, 0x9d5e, 0xa000, 0xa002,
 367         0xa400, 0xa402, 0xac00, 0xac02, 0xb000, 0xb002, 0xb400, 0xb402,
 368         0xb800, 0xb802,
 369         /* GPU CC ACD */
 370         0xbc00, 0xbc16, 0xbc20, 0xbc27,
 371 };
 372
 373 static const u32 a6xx_gmu_cx_rscc_registers[] = {
 374         /* GPU RSCC */
 375         0x008c, 0x008c, 0x0101, 0x0102, 0x0340, 0x0342, 0x0344, 0x0347,
 376         0x034c, 0x0387, 0x03ec, 0x03ef, 0x03f4, 0x042f, 0x0494, 0x0497,
 377         0x049c, 0x04d7, 0x053c, 0x053f, 0x0544, 0x057f,
 378 };
 379
 380 static const struct a6xx_registers a6xx_gmu_reglist[] = {
 381         REGS(a6xx_gmu_cx_registers, 0, 0),
 382         REGS(a6xx_gmu_cx_rscc_registers, 0, 0),
 383         REGS(a6xx_gmu_gx_registers, 0, 0),
 384 };
 385
 386 static u32 a6xx_get_cp_roq_size(struct msm_gpu *gpu);
 387
 388 static struct a6xx_indexed_registers {
 389         const char *name;
 390         u32 addr;
 391         u32 data;
 392         u32 count;
 393         u32 (*count_fn)(struct msm_gpu *gpu);
 394 } a6xx_indexed_reglist[] = {
 395         { "CP_SQE_STAT", REG_A6XX_CP_SQE_STAT_ADDR,
 396                 REG_A6XX_CP_SQE_STAT_DATA, 0x33, NULL },
 397         { "CP_DRAW_STATE", REG_A6XX_CP_DRAW_STATE_ADDR,
 398                 REG_A6XX_CP_DRAW_STATE_DATA, 0x100, NULL },
 399         { "CP_UCODE_DBG_DATA", REG_A6XX_CP_SQE_UCODE_DBG_ADDR,
 400                 REG_A6XX_CP_SQE_UCODE_DBG_DATA, 0x8000, NULL },
 401         { "CP_ROQ", REG_A6XX_CP_ROQ_DBG_ADDR,
 402                 REG_A6XX_CP_ROQ_DBG_DATA, 0, a6xx_get_cp_roq_size},
 403 };
 404
 405 static struct a6xx_indexed_registers a6xx_cp_mempool_indexed = {
 406         "CP_MEMPOOL", REG_A6XX_CP_MEM_POOL_DBG_ADDR,
 407                 REG_A6XX_CP_MEM_POOL_DBG_DATA, 0x2060, NULL,
 408 };
 409
 410 #define DEBUGBUS(_id, _count) { .id = _id, .name = #_id, .count = _count }
 411
 412 static const struct a6xx_debugbus_block {
 413         const char *name;
 414         u32 id;
 415         u32 count;
 416 } a6xx_debugbus_blocks[] = {
 417         DEBUGBUS(A6XX_DBGBUS_CP, 0x100),
 418         DEBUGBUS(A6XX_DBGBUS_RBBM, 0x100),
 419         DEBUGBUS(A6XX_DBGBUS_HLSQ, 0x100),
 420         DEBUGBUS(A6XX_DBGBUS_UCHE, 0x100),
 421         DEBUGBUS(A6XX_DBGBUS_DPM, 0x100),
 422         DEBUGBUS(A6XX_DBGBUS_TESS, 0x100),
 423         DEBUGBUS(A6XX_DBGBUS_PC, 0x100),
 424         DEBUGBUS(A6XX_DBGBUS_VFDP, 0x100),
 425         DEBUGBUS(A6XX_DBGBUS_VPC, 0x100),
 426         DEBUGBUS(A6XX_DBGBUS_TSE, 0x100),
 427         DEBUGBUS(A6XX_DBGBUS_RAS, 0x100),
 428         DEBUGBUS(A6XX_DBGBUS_VSC, 0x100),
 429         DEBUGBUS(A6XX_DBGBUS_COM, 0x100),
 430         DEBUGBUS(A6XX_DBGBUS_LRZ, 0x100),
 431         DEBUGBUS(A6XX_DBGBUS_A2D, 0x100),
 432         DEBUGBUS(A6XX_DBGBUS_CCUFCHE, 0x100),
 433         DEBUGBUS(A6XX_DBGBUS_RBP, 0x100),
 434         DEBUGBUS(A6XX_DBGBUS_DCS, 0x100),
 435         DEBUGBUS(A6XX_DBGBUS_DBGC, 0x100),
 436         DEBUGBUS(A6XX_DBGBUS_GMU_GX, 0x100),
 437         DEBUGBUS(A6XX_DBGBUS_TPFCHE, 0x100),
 438         DEBUGBUS(A6XX_DBGBUS_GPC, 0x100),
 439         DEBUGBUS(A6XX_DBGBUS_LARC, 0x100),
 440         DEBUGBUS(A6XX_DBGBUS_HLSQ_SPTP, 0x100),
 441         DEBUGBUS(A6XX_DBGBUS_RB_0, 0x100),
 442         DEBUGBUS(A6XX_DBGBUS_RB_1, 0x100),
 443         DEBUGBUS(A6XX_DBGBUS_UCHE_WRAPPER, 0x100),
 444         DEBUGBUS(A6XX_DBGBUS_CCU_0, 0x100),
 445         DEBUGBUS(A6XX_DBGBUS_CCU_1, 0x100),
 446         DEBUGBUS(A6XX_DBGBUS_VFD_0, 0x100),
 447         DEBUGBUS(A6XX_DBGBUS_VFD_1, 0x100),
 448         DEBUGBUS(A6XX_DBGBUS_VFD_2, 0x100),
 449         DEBUGBUS(A6XX_DBGBUS_VFD_3, 0x100),
 450         DEBUGBUS(A6XX_DBGBUS_SP_0, 0x100),
 451         DEBUGBUS(A6XX_DBGBUS_SP_1, 0x100),
 452         DEBUGBUS(A6XX_DBGBUS_TPL1_0, 0x100),
 453         DEBUGBUS(A6XX_DBGBUS_TPL1_1, 0x100),
 454         DEBUGBUS(A6XX_DBGBUS_TPL1_2, 0x100),
 455         DEBUGBUS(A6XX_DBGBUS_TPL1_3, 0x100),
 456 };
 457
 458 static const struct a6xx_debugbus_block a6xx_gbif_debugbus_block =
 459                         DEBUGBUS(A6XX_DBGBUS_VBIF, 0x100);
 460
 461 static const struct a6xx_debugbus_block a6xx_cx_debugbus_blocks[] = {
 462         DEBUGBUS(A6XX_DBGBUS_GMU_CX, 0x100),
 463         DEBUGBUS(A6XX_DBGBUS_CX, 0x100),
 464 };
 465
 466 static const struct a6xx_debugbus_block a650_debugbus_blocks[] = {
 467         DEBUGBUS(A6XX_DBGBUS_RB_2, 0x100),
 468         DEBUGBUS(A6XX_DBGBUS_CCU_2, 0x100),
 469         DEBUGBUS(A6XX_DBGBUS_VFD_4, 0x100),
 470         DEBUGBUS(A6XX_DBGBUS_VFD_5, 0x100),
 471         DEBUGBUS(A6XX_DBGBUS_SP_2, 0x100),
 472         DEBUGBUS(A6XX_DBGBUS_TPL1_4, 0x100),
 473         DEBUGBUS(A6XX_DBGBUS_TPL1_5, 0x100),
 474         DEBUGBUS(A6XX_DBGBUS_SPTP_0, 0x100),
 475         DEBUGBUS(A6XX_DBGBUS_SPTP_1, 0x100),
 476         DEBUGBUS(A6XX_DBGBUS_SPTP_2, 0x100),
 477         DEBUGBUS(A6XX_DBGBUS_SPTP_3, 0x100),
 478         DEBUGBUS(A6XX_DBGBUS_SPTP_4, 0x100),
 479         DEBUGBUS(A6XX_DBGBUS_SPTP_5, 0x100),
 480 };
 481
 482 #endif