1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. */
5 #include <linux/interconnect.h>
6 #include <linux/pm_domain.h>
7 #include <linux/pm_opp.h>
8 #include <soc/qcom/cmd-db.h>
9 #include <drm/drm_gem.h>
12 #include "a6xx_gmu.xml.h"
14 #include "msm_gpu_trace.h"
17 static void a6xx_gmu_fault(struct a6xx_gmu *gmu)
19 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
20 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
21 struct msm_gpu *gpu = &adreno_gpu->base;
23 /* FIXME: add a banner here */
26 /* Turn off the hangcheck timer while we are resetting */
27 del_timer(&gpu->hangcheck_timer);
29 /* Queue the GPU handler because we need to treat this as a recovery */
30 kthread_queue_work(gpu->worker, &gpu->recover_work);
33 static irqreturn_t a6xx_gmu_irq(int irq, void *data)
35 struct a6xx_gmu *gmu = data;
38 status = gmu_read(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_STATUS);
39 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, status);
41 if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_WDOG_BITE) {
42 dev_err_ratelimited(gmu->dev, "GMU watchdog expired\n");
47 if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_HOST_AHB_BUS_ERROR)
48 dev_err_ratelimited(gmu->dev, "GMU AHB bus error\n");
50 if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_FENCE_ERR)
51 dev_err_ratelimited(gmu->dev, "GMU fence error: 0x%x\n",
52 gmu_read(gmu, REG_A6XX_GMU_AHB_FENCE_STATUS));
57 static irqreturn_t a6xx_hfi_irq(int irq, void *data)
59 struct a6xx_gmu *gmu = data;
62 status = gmu_read(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO);
63 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, status);
65 if (status & A6XX_GMU_GMU2HOST_INTR_INFO_CM3_FAULT) {
66 dev_err_ratelimited(gmu->dev, "GMU firmware fault\n");
74 bool a6xx_gmu_sptprac_is_on(struct a6xx_gmu *gmu)
78 /* This can be called from gpu state code so make sure GMU is valid */
79 if (!gmu->initialized)
82 val = gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS);
85 (A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWER_OFF |
86 A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SP_CLOCK_OFF));
89 /* Check to see if the GX rail is still powered */
90 bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu)
94 /* This can be called from gpu state code so make sure GMU is valid */
95 if (!gmu->initialized)
98 val = gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS);
101 (A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_GDSC_POWER_OFF |
102 A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_CLK_OFF));
105 void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp)
107 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
108 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
109 struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
111 unsigned long gpu_freq;
114 gpu_freq = dev_pm_opp_get_freq(opp);
116 if (gpu_freq == gmu->freq)
119 for (perf_index = 0; perf_index < gmu->nr_gpu_freqs - 1; perf_index++)
120 if (gpu_freq == gmu->gpu_freqs[perf_index])
123 gmu->current_perf_index = perf_index;
124 gmu->freq = gmu->gpu_freqs[perf_index];
126 trace_msm_gmu_freq_change(gmu->freq, perf_index);
129 * This can get called from devfreq while the hardware is idle. Don't
130 * bring up the power if it isn't already active
132 if (pm_runtime_get_if_in_use(gmu->dev) == 0)
136 a6xx_hfi_set_freq(gmu, perf_index);
137 dev_pm_opp_set_opp(&gpu->pdev->dev, opp);
138 pm_runtime_put(gmu->dev);
142 gmu_write(gmu, REG_A6XX_GMU_DCVS_ACK_OPTION, 0);
144 gmu_write(gmu, REG_A6XX_GMU_DCVS_PERF_SETTING,
145 ((3 & 0xf) << 28) | perf_index);
148 * Send an invalid index as a vote for the bus bandwidth and let the
149 * firmware decide on the right vote
151 gmu_write(gmu, REG_A6XX_GMU_DCVS_BW_SETTING, 0xff);
153 /* Set and clear the OOB for DCVS to trigger the GMU */
154 a6xx_gmu_set_oob(gmu, GMU_OOB_DCVS_SET);
155 a6xx_gmu_clear_oob(gmu, GMU_OOB_DCVS_SET);
157 ret = gmu_read(gmu, REG_A6XX_GMU_DCVS_RETURN);
159 dev_err(gmu->dev, "GMU set GPU frequency error: %d\n", ret);
161 dev_pm_opp_set_opp(&gpu->pdev->dev, opp);
162 pm_runtime_put(gmu->dev);
165 unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu)
167 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
168 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
169 struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
174 static bool a6xx_gmu_check_idle_level(struct a6xx_gmu *gmu)
177 int local = gmu->idle_level;
179 /* SPTP and IFPC both report as IFPC */
180 if (gmu->idle_level == GMU_IDLE_STATE_SPTP)
181 local = GMU_IDLE_STATE_IFPC;
183 val = gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE);
186 if (gmu->idle_level != GMU_IDLE_STATE_IFPC ||
187 !a6xx_gmu_gx_is_on(gmu))
194 /* Wait for the GMU to get to its most idle state */
195 int a6xx_gmu_wait_for_idle(struct a6xx_gmu *gmu)
197 return spin_until(a6xx_gmu_check_idle_level(gmu));
200 static int a6xx_gmu_start(struct a6xx_gmu *gmu)
206 val = gmu_read(gmu, REG_A6XX_GMU_CM3_DTCM_START + 0xff8);
207 if (val <= 0x20010004) {
209 reset_val = 0xbabeface;
215 gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 1);
217 /* Set the log wptr index
218 * note: downstream saves the value in poweroff and restores it here
220 gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_RESP, 0);
222 gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 0);
224 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_CM3_FW_INIT_RESULT, val,
225 (val & mask) == reset_val, 100, 10000);
228 DRM_DEV_ERROR(gmu->dev, "GMU firmware initialization timed out\n");
233 static int a6xx_gmu_hfi_start(struct a6xx_gmu *gmu)
238 gmu_write(gmu, REG_A6XX_GMU_HFI_CTRL_INIT, 1);
240 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_HFI_CTRL_STATUS, val,
241 val & 1, 100, 10000);
243 DRM_DEV_ERROR(gmu->dev, "Unable to start the HFI queues\n");
248 struct a6xx_gmu_oob_bits {
249 int set, ack, set_new, ack_new;
253 /* These are the interrupt / ack bits for each OOB request that are set
254 * in a6xx_gmu_set_oob and a6xx_clear_oob
256 static const struct a6xx_gmu_oob_bits a6xx_gmu_oob_bits[] = {
257 [GMU_OOB_GPU_SET] = {
265 [GMU_OOB_PERFCOUNTER_SET] = {
266 .name = "PERFCOUNTER",
273 [GMU_OOB_BOOT_SLUMBER] = {
274 .name = "BOOT_SLUMBER",
279 [GMU_OOB_DCVS_SET] = {
286 /* Trigger a OOB (out of band) request to the GMU */
287 int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state)
293 if (state >= ARRAY_SIZE(a6xx_gmu_oob_bits))
297 request = a6xx_gmu_oob_bits[state].set;
298 ack = a6xx_gmu_oob_bits[state].ack;
300 request = a6xx_gmu_oob_bits[state].set_new;
301 ack = a6xx_gmu_oob_bits[state].ack_new;
302 if (!request || !ack) {
303 DRM_DEV_ERROR(gmu->dev,
304 "Invalid non-legacy GMU request %s\n",
305 a6xx_gmu_oob_bits[state].name);
310 /* Trigger the equested OOB operation */
311 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 1 << request);
313 /* Wait for the acknowledge interrupt */
314 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO, val,
315 val & (1 << ack), 100, 10000);
318 DRM_DEV_ERROR(gmu->dev,
319 "Timeout waiting for GMU OOB set %s: 0x%x\n",
320 a6xx_gmu_oob_bits[state].name,
321 gmu_read(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO));
323 /* Clear the acknowledge interrupt */
324 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, 1 << ack);
329 /* Clear a pending OOB state in the GMU */
330 void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state)
334 if (state >= ARRAY_SIZE(a6xx_gmu_oob_bits))
338 bit = a6xx_gmu_oob_bits[state].ack;
340 bit = a6xx_gmu_oob_bits[state].ack_new;
342 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 1 << bit);
345 /* Enable CPU control of SPTP power power collapse */
346 static int a6xx_sptprac_enable(struct a6xx_gmu *gmu)
354 gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778000);
356 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS, val,
357 (val & 0x38) == 0x28, 1, 100);
360 DRM_DEV_ERROR(gmu->dev, "Unable to power on SPTPRAC: 0x%x\n",
361 gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS));
367 /* Disable CPU control of SPTP power power collapse */
368 static void a6xx_sptprac_disable(struct a6xx_gmu *gmu)
376 /* Make sure retention is on */
377 gmu_rmw(gmu, REG_A6XX_GPU_CC_GX_GDSCR, 0, (1 << 11));
379 gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778001);
381 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS, val,
382 (val & 0x04), 100, 10000);
385 DRM_DEV_ERROR(gmu->dev, "failed to power off SPTPRAC: 0x%x\n",
386 gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS));
389 /* Let the GMU know we are starting a boot sequence */
390 static int a6xx_gmu_gfx_rail_on(struct a6xx_gmu *gmu)
394 /* Let the GMU know we are getting ready for boot */
395 gmu_write(gmu, REG_A6XX_GMU_BOOT_SLUMBER_OPTION, 0);
397 /* Choose the "default" power level as the highest available */
398 vote = gmu->gx_arc_votes[gmu->nr_gpu_freqs - 1];
400 gmu_write(gmu, REG_A6XX_GMU_GX_VOTE_IDX, vote & 0xff);
401 gmu_write(gmu, REG_A6XX_GMU_MX_VOTE_IDX, (vote >> 8) & 0xff);
403 /* Let the GMU know the boot sequence has started */
404 return a6xx_gmu_set_oob(gmu, GMU_OOB_BOOT_SLUMBER);
407 /* Let the GMU know that we are about to go into slumber */
408 static int a6xx_gmu_notify_slumber(struct a6xx_gmu *gmu)
412 /* Disable the power counter so the GMU isn't busy */
413 gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 0);
415 /* Disable SPTP_PC if the CPU is responsible for it */
416 if (gmu->idle_level < GMU_IDLE_STATE_SPTP)
417 a6xx_sptprac_disable(gmu);
420 ret = a6xx_hfi_send_prep_slumber(gmu);
424 /* Tell the GMU to get ready to slumber */
425 gmu_write(gmu, REG_A6XX_GMU_BOOT_SLUMBER_OPTION, 1);
427 ret = a6xx_gmu_set_oob(gmu, GMU_OOB_BOOT_SLUMBER);
428 a6xx_gmu_clear_oob(gmu, GMU_OOB_BOOT_SLUMBER);
431 /* Check to see if the GMU really did slumber */
432 if (gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE)
434 DRM_DEV_ERROR(gmu->dev, "The GMU did not go into slumber\n");
440 /* Put fence into allow mode */
441 gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0);
445 static int a6xx_rpmh_start(struct a6xx_gmu *gmu)
450 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1 << 1);
451 /* Wait for the register to finish posting */
454 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_RSCC_CONTROL_ACK, val,
455 val & (1 << 1), 100, 10000);
457 DRM_DEV_ERROR(gmu->dev, "Unable to power on the GPU RSC\n");
461 ret = gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_SEQ_BUSY_DRV0, val,
465 DRM_DEV_ERROR(gmu->dev, "GPU RSC sequence stuck while waking up the GPU\n");
469 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0);
471 /* Set up CX GMU counter 0 to count busy ticks */
472 gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK, 0xff000000);
473 gmu_rmw(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0, 0xff, 0x20);
475 /* Enable the power counter */
476 gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 1);
480 static void a6xx_rpmh_stop(struct a6xx_gmu *gmu)
485 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1);
487 ret = gmu_poll_timeout_rscc(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0,
488 val, val & (1 << 16), 100, 10000);
490 DRM_DEV_ERROR(gmu->dev, "Unable to power off the GPU RSC\n");
492 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0);
495 static inline void pdc_write(void __iomem *ptr, u32 offset, u32 value)
497 return msm_writel(value, ptr + (offset << 2));
500 static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev,
503 static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu)
505 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
506 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
507 struct platform_device *pdev = to_platform_device(gmu->dev);
508 void __iomem *pdcptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc");
509 void __iomem *seqptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc_seq");
510 uint32_t pdc_address_offset;
512 if (!pdcptr || !seqptr)
515 if (adreno_is_a618(adreno_gpu) || adreno_is_a640(adreno_gpu))
516 pdc_address_offset = 0x30090;
517 else if (adreno_is_a650(adreno_gpu))
518 pdc_address_offset = 0x300a0;
520 pdc_address_offset = 0x30080;
522 /* Disable SDE clock gating */
523 gmu_write_rscc(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0, BIT(24));
525 /* Setup RSC PDC handshake for sleep and wakeup */
526 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_SLAVE_ID_DRV0, 1);
527 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA, 0);
528 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR, 0);
529 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 2, 0);
530 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 2, 0);
531 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 4, 0x80000000);
532 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 4, 0);
533 gmu_write_rscc(gmu, REG_A6XX_RSCC_OVERRIDE_START_ADDR, 0);
534 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_SEQ_START_ADDR, 0x4520);
535 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_LO, 0x4510);
536 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_HI, 0x4514);
538 /* Load RSC sequencer uCode for sleep and wakeup */
539 if (adreno_is_a650(adreno_gpu)) {
540 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xeaaae5a0);
541 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xe1a1ebab);
542 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e0a581);
543 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xecac82e2);
544 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020edad);
546 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xa7a506a0);
547 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xa1e6a6e7);
548 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e081e1);
549 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xe9a982e2);
550 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020e8a8);
553 /* Load PDC sequencer uCode for power up and power down sequence */
554 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0, 0xfebea1e1);
555 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 1, 0xa5a4a3a2);
556 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 2, 0x8382a6e0);
557 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 3, 0xbce3e284);
558 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 4, 0x002081fc);
560 /* Set TCS commands used by PDC sequence for low power modes */
561 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK, 7);
562 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK, 0);
563 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CONTROL, 0);
564 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID, 0x10108);
565 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR, 0x30010);
566 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA, 1);
567 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 4, 0x10108);
568 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 4, 0x30000);
569 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 4, 0x0);
571 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 8, 0x10108);
572 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 8, pdc_address_offset);
573 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 8, 0x0);
575 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK, 7);
576 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK, 0);
577 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CONTROL, 0);
578 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID, 0x10108);
579 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR, 0x30010);
580 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA, 2);
582 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 4, 0x10108);
583 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 4, 0x30000);
584 if (adreno_is_a618(adreno_gpu) || adreno_is_a650(adreno_gpu))
585 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x2);
587 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x3);
588 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 8, 0x10108);
589 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 8, pdc_address_offset);
590 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 8, 0x3);
593 pdc_write(pdcptr, REG_A6XX_PDC_GPU_SEQ_START_ADDR, 0);
594 pdc_write(pdcptr, REG_A6XX_PDC_GPU_ENABLE_PDC, 0x80000001);
596 /* ensure no writes happen before the uCode is fully written */
600 if (!IS_ERR_OR_NULL(pdcptr))
602 if (!IS_ERR_OR_NULL(seqptr))
607 * The lowest 16 bits of this value are the number of XO clock cycles for main
608 * hysteresis which is set at 0x1680 cycles (300 us). The higher 16 bits are
609 * for the shorter hysteresis that happens after main - this is 0xa (.5 us)
612 #define GMU_PWR_COL_HYST 0x000a1680
614 /* Set up the idle state for the GMU */
615 static void a6xx_gmu_power_config(struct a6xx_gmu *gmu)
617 /* Disable GMU WB/RB buffer */
618 gmu_write(gmu, REG_A6XX_GMU_SYS_BUS_CONFIG, 0x1);
619 gmu_write(gmu, REG_A6XX_GMU_ICACHE_CONFIG, 0x1);
620 gmu_write(gmu, REG_A6XX_GMU_DCACHE_CONFIG, 0x1);
622 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0x9c40400);
624 switch (gmu->idle_level) {
625 case GMU_IDLE_STATE_IFPC:
626 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_HYST,
628 gmu_rmw(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0,
629 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_IFPC_ENABLE |
630 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_HM_POWER_COLLAPSE_ENABLE);
632 case GMU_IDLE_STATE_SPTP:
633 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_SPTPRAC_HYST,
635 gmu_rmw(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0,
636 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_IFPC_ENABLE |
637 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_SPTPRAC_POWER_CONTROL_ENABLE);
640 /* Enable RPMh GPU client */
641 gmu_rmw(gmu, REG_A6XX_GMU_RPMH_CTRL, 0,
642 A6XX_GMU_RPMH_CTRL_RPMH_INTERFACE_ENABLE |
643 A6XX_GMU_RPMH_CTRL_LLC_VOTE_ENABLE |
644 A6XX_GMU_RPMH_CTRL_DDR_VOTE_ENABLE |
645 A6XX_GMU_RPMH_CTRL_MX_VOTE_ENABLE |
646 A6XX_GMU_RPMH_CTRL_CX_VOTE_ENABLE |
647 A6XX_GMU_RPMH_CTRL_GFX_VOTE_ENABLE);
650 struct block_header {
658 /* this should be a general kernel helper */
659 static int in_range(u32 addr, u32 start, u32 size)
661 return addr >= start && addr < start + size;
664 static bool fw_block_mem(struct a6xx_gmu_bo *bo, const struct block_header *blk)
666 if (!in_range(blk->addr, bo->iova, bo->size))
669 memcpy(bo->virt + blk->addr - bo->iova, blk->data, blk->size);
673 static int a6xx_gmu_fw_load(struct a6xx_gmu *gmu)
675 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
676 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
677 const struct firmware *fw_image = adreno_gpu->fw[ADRENO_FW_GMU];
678 const struct block_header *blk;
681 u32 itcm_base = 0x00000000;
682 u32 dtcm_base = 0x00040000;
684 if (adreno_is_a650(adreno_gpu))
685 dtcm_base = 0x10004000;
688 /* Sanity check the size of the firmware that was loaded */
689 if (fw_image->size > 0x8000) {
690 DRM_DEV_ERROR(gmu->dev,
691 "GMU firmware is bigger than the available region\n");
695 gmu_write_bulk(gmu, REG_A6XX_GMU_CM3_ITCM_START,
696 (u32*) fw_image->data, fw_image->size);
701 for (blk = (const struct block_header *) fw_image->data;
702 (const u8*) blk < fw_image->data + fw_image->size;
703 blk = (const struct block_header *) &blk->data[blk->size >> 2]) {
707 if (in_range(blk->addr, itcm_base, SZ_16K)) {
708 reg_offset = (blk->addr - itcm_base) >> 2;
710 REG_A6XX_GMU_CM3_ITCM_START + reg_offset,
711 blk->data, blk->size);
712 } else if (in_range(blk->addr, dtcm_base, SZ_16K)) {
713 reg_offset = (blk->addr - dtcm_base) >> 2;
715 REG_A6XX_GMU_CM3_DTCM_START + reg_offset,
716 blk->data, blk->size);
717 } else if (!fw_block_mem(&gmu->icache, blk) &&
718 !fw_block_mem(&gmu->dcache, blk) &&
719 !fw_block_mem(&gmu->dummy, blk)) {
720 DRM_DEV_ERROR(gmu->dev,
721 "failed to match fw block (addr=%.8x size=%d data[0]=%.8x)\n",
722 blk->addr, blk->size, blk->data[0]);
729 static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state)
731 static bool rpmh_init;
732 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
733 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
737 if (adreno_is_a650(adreno_gpu))
738 gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FAL_INTF, 1);
740 if (state == GMU_WARM_BOOT) {
741 ret = a6xx_rpmh_start(gmu);
745 if (WARN(!adreno_gpu->fw[ADRENO_FW_GMU],
746 "GMU firmware is not loaded\n"))
749 /* Turn on register retention */
750 gmu_write(gmu, REG_A6XX_GMU_GENERAL_7, 1);
752 /* We only need to load the RPMh microcode once */
754 a6xx_gmu_rpmh_init(gmu);
757 ret = a6xx_rpmh_start(gmu);
762 ret = a6xx_gmu_fw_load(gmu);
767 gmu_write(gmu, REG_A6XX_GMU_CM3_FW_INIT_RESULT, 0);
768 gmu_write(gmu, REG_A6XX_GMU_CM3_BOOT_CONFIG, 0x02);
770 /* Write the iova of the HFI table */
771 gmu_write(gmu, REG_A6XX_GMU_HFI_QTBL_ADDR, gmu->hfi.iova);
772 gmu_write(gmu, REG_A6XX_GMU_HFI_QTBL_INFO, 1);
774 gmu_write(gmu, REG_A6XX_GMU_AHB_FENCE_RANGE_0,
775 (1 << 31) | (0xa << 18) | (0xa0));
777 chipid = adreno_gpu->rev.core << 24;
778 chipid |= adreno_gpu->rev.major << 16;
779 chipid |= adreno_gpu->rev.minor << 12;
780 chipid |= adreno_gpu->rev.patchid << 8;
782 gmu_write(gmu, REG_A6XX_GMU_HFI_SFR_ADDR, chipid);
784 gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_MSG,
785 gmu->log.iova | (gmu->log.size / SZ_4K - 1));
787 /* Set up the lowest idle level on the GMU */
788 a6xx_gmu_power_config(gmu);
790 ret = a6xx_gmu_start(gmu);
795 ret = a6xx_gmu_gfx_rail_on(gmu);
800 /* Enable SPTP_PC if the CPU is responsible for it */
801 if (gmu->idle_level < GMU_IDLE_STATE_SPTP) {
802 ret = a6xx_sptprac_enable(gmu);
807 ret = a6xx_gmu_hfi_start(gmu);
811 /* FIXME: Do we need this wmb() here? */
817 #define A6XX_HFI_IRQ_MASK \
818 (A6XX_GMU_GMU2HOST_INTR_INFO_CM3_FAULT)
820 #define A6XX_GMU_IRQ_MASK \
821 (A6XX_GMU_AO_HOST_INTERRUPT_STATUS_WDOG_BITE | \
822 A6XX_GMU_AO_HOST_INTERRUPT_STATUS_HOST_AHB_BUS_ERROR | \
823 A6XX_GMU_AO_HOST_INTERRUPT_STATUS_FENCE_ERR)
825 static void a6xx_gmu_irq_disable(struct a6xx_gmu *gmu)
827 disable_irq(gmu->gmu_irq);
828 disable_irq(gmu->hfi_irq);
830 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK, ~0);
831 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, ~0);
834 static void a6xx_gmu_rpmh_off(struct a6xx_gmu *gmu)
838 /* Make sure there are no outstanding RPMh votes */
839 gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS0_DRV0_STATUS, val,
840 (val & 1), 100, 10000);
841 gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS1_DRV0_STATUS, val,
842 (val & 1), 100, 10000);
843 gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS2_DRV0_STATUS, val,
844 (val & 1), 100, 10000);
845 gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS3_DRV0_STATUS, val,
846 (val & 1), 100, 1000);
849 /* Force the GMU off in case it isn't responsive */
850 static void a6xx_gmu_force_off(struct a6xx_gmu *gmu)
852 /* Flush all the queues */
855 /* Stop the interrupts */
856 a6xx_gmu_irq_disable(gmu);
858 /* Force off SPTP in case the GMU is managing it */
859 a6xx_sptprac_disable(gmu);
861 /* Make sure there are no outstanding RPMh votes */
862 a6xx_gmu_rpmh_off(gmu);
865 static void a6xx_gmu_set_initial_freq(struct msm_gpu *gpu, struct a6xx_gmu *gmu)
867 struct dev_pm_opp *gpu_opp;
868 unsigned long gpu_freq = gmu->gpu_freqs[gmu->current_perf_index];
870 gpu_opp = dev_pm_opp_find_freq_exact(&gpu->pdev->dev, gpu_freq, true);
871 if (IS_ERR_OR_NULL(gpu_opp))
874 gmu->freq = 0; /* so a6xx_gmu_set_freq() doesn't exit early */
875 a6xx_gmu_set_freq(gpu, gpu_opp);
876 dev_pm_opp_put(gpu_opp);
879 static void a6xx_gmu_set_initial_bw(struct msm_gpu *gpu, struct a6xx_gmu *gmu)
881 struct dev_pm_opp *gpu_opp;
882 unsigned long gpu_freq = gmu->gpu_freqs[gmu->current_perf_index];
884 gpu_opp = dev_pm_opp_find_freq_exact(&gpu->pdev->dev, gpu_freq, true);
885 if (IS_ERR_OR_NULL(gpu_opp))
888 dev_pm_opp_set_opp(&gpu->pdev->dev, gpu_opp);
889 dev_pm_opp_put(gpu_opp);
892 int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu)
894 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
895 struct msm_gpu *gpu = &adreno_gpu->base;
896 struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
899 if (WARN(!gmu->initialized, "The GMU is not set up yet\n"))
904 /* Turn on the resources */
905 pm_runtime_get_sync(gmu->dev);
908 * "enable" the GX power domain which won't actually do anything but it
909 * will make sure that the refcounting is correct in case we need to
910 * bring down the GX after a GMU failure
912 if (!IS_ERR_OR_NULL(gmu->gxpd))
913 pm_runtime_get_sync(gmu->gxpd);
915 /* Use a known rate to bring up the GMU */
916 clk_set_rate(gmu->core_clk, 200000000);
917 ret = clk_bulk_prepare_enable(gmu->nr_clocks, gmu->clocks);
919 pm_runtime_put(gmu->gxpd);
920 pm_runtime_put(gmu->dev);
924 /* Set the bus quota to a reasonable value for boot */
925 a6xx_gmu_set_initial_bw(gpu, gmu);
927 /* Enable the GMU interrupt */
928 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, ~0);
929 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK, ~A6XX_GMU_IRQ_MASK);
930 enable_irq(gmu->gmu_irq);
932 /* Check to see if we are doing a cold or warm boot */
933 status = gmu_read(gmu, REG_A6XX_GMU_GENERAL_7) == 1 ?
934 GMU_WARM_BOOT : GMU_COLD_BOOT;
937 * Warm boot path does not work on newer GPUs
938 * Presumably this is because icache/dcache regions must be restored
941 status = GMU_COLD_BOOT;
943 ret = a6xx_gmu_fw_start(gmu, status);
947 ret = a6xx_hfi_start(gmu, status);
952 * Turn on the GMU firmware fault interrupt after we know the boot
953 * sequence is successful
955 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, ~0);
956 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, ~A6XX_HFI_IRQ_MASK);
957 enable_irq(gmu->hfi_irq);
959 /* Set the GPU to the current freq */
960 a6xx_gmu_set_initial_freq(gpu, gmu);
963 /* On failure, shut down the GMU to leave it in a good state */
965 disable_irq(gmu->gmu_irq);
967 pm_runtime_put(gmu->gxpd);
968 pm_runtime_put(gmu->dev);
974 bool a6xx_gmu_isidle(struct a6xx_gmu *gmu)
978 if (!gmu->initialized)
981 reg = gmu_read(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS);
983 if (reg & A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS_GPUBUSYIGNAHB)
989 #define GBIF_CLIENT_HALT_MASK BIT(0)
990 #define GBIF_ARB_HALT_MASK BIT(1)
992 static void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu)
994 struct msm_gpu *gpu = &adreno_gpu->base;
996 if (!a6xx_has_gbif(adreno_gpu)) {
997 gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0xf);
998 spin_until((gpu_read(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL1) &
1000 gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0);
1005 /* Halt new client requests on GBIF */
1006 gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_CLIENT_HALT_MASK);
1007 spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) &
1008 (GBIF_CLIENT_HALT_MASK)) == GBIF_CLIENT_HALT_MASK);
1010 /* Halt all AXI requests on GBIF */
1011 gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_ARB_HALT_MASK);
1012 spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) &
1013 (GBIF_ARB_HALT_MASK)) == GBIF_ARB_HALT_MASK);
1015 /* The GBIF halt needs to be explicitly cleared */
1016 gpu_write(gpu, REG_A6XX_GBIF_HALT, 0x0);
1019 /* Gracefully try to shut down the GMU and by extension the GPU */
1020 static void a6xx_gmu_shutdown(struct a6xx_gmu *gmu)
1022 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
1023 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
1027 * The GMU may still be in slumber unless the GPU started so check and
1028 * skip putting it back into slumber if so
1030 val = gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE);
1033 int ret = a6xx_gmu_wait_for_idle(gmu);
1035 /* If the GMU isn't responding assume it is hung */
1037 a6xx_gmu_force_off(gmu);
1041 a6xx_bus_clear_pending_transactions(adreno_gpu);
1043 /* tell the GMU we want to slumber */
1044 a6xx_gmu_notify_slumber(gmu);
1046 ret = gmu_poll_timeout(gmu,
1047 REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS, val,
1048 !(val & A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS_GPUBUSYIGNAHB),
1052 * Let the user know we failed to slumber but don't worry too
1053 * much because we are powering down anyway
1057 DRM_DEV_ERROR(gmu->dev,
1058 "Unable to slumber GMU: status = 0%x/0%x\n",
1060 REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS),
1062 REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS2));
1068 /* Stop the interrupts and mask the hardware */
1069 a6xx_gmu_irq_disable(gmu);
1071 /* Tell RPMh to power off the GPU */
1072 a6xx_rpmh_stop(gmu);
1076 int a6xx_gmu_stop(struct a6xx_gpu *a6xx_gpu)
1078 struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
1079 struct msm_gpu *gpu = &a6xx_gpu->base.base;
1081 if (!pm_runtime_active(gmu->dev))
1085 * Force the GMU off if we detected a hang, otherwise try to shut it
1089 a6xx_gmu_force_off(gmu);
1091 a6xx_gmu_shutdown(gmu);
1093 /* Remove the bus vote */
1094 dev_pm_opp_set_opp(&gpu->pdev->dev, NULL);
1097 * Make sure the GX domain is off before turning off the GMU (CX)
1098 * domain. Usually the GMU does this but only if the shutdown sequence
1101 if (!IS_ERR_OR_NULL(gmu->gxpd))
1102 pm_runtime_put_sync(gmu->gxpd);
1104 clk_bulk_disable_unprepare(gmu->nr_clocks, gmu->clocks);
1106 pm_runtime_put_sync(gmu->dev);
1111 static void a6xx_gmu_memory_free(struct a6xx_gmu *gmu)
1113 msm_gem_kernel_put(gmu->hfi.obj, gmu->aspace, false);
1114 msm_gem_kernel_put(gmu->debug.obj, gmu->aspace, false);
1115 msm_gem_kernel_put(gmu->icache.obj, gmu->aspace, false);
1116 msm_gem_kernel_put(gmu->dcache.obj, gmu->aspace, false);
1117 msm_gem_kernel_put(gmu->dummy.obj, gmu->aspace, false);
1118 msm_gem_kernel_put(gmu->log.obj, gmu->aspace, false);
1120 gmu->aspace->mmu->funcs->detach(gmu->aspace->mmu);
1121 msm_gem_address_space_put(gmu->aspace);
1124 static int a6xx_gmu_memory_alloc(struct a6xx_gmu *gmu, struct a6xx_gmu_bo *bo,
1125 size_t size, u64 iova)
1127 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
1128 struct drm_device *dev = a6xx_gpu->base.base.dev;
1129 uint32_t flags = MSM_BO_WC;
1130 u64 range_start, range_end;
1133 size = PAGE_ALIGN(size);
1135 /* no fixed address - use GMU's uncached range */
1136 range_start = 0x60000000 + PAGE_SIZE; /* skip dummy page */
1137 range_end = 0x80000000;
1139 /* range for fixed address */
1141 range_end = iova + size;
1142 /* use IOMMU_PRIV for icache/dcache */
1143 flags |= MSM_BO_MAP_PRIV;
1146 bo->obj = msm_gem_new(dev, size, flags);
1147 if (IS_ERR(bo->obj))
1148 return PTR_ERR(bo->obj);
1150 ret = msm_gem_get_and_pin_iova_range(bo->obj, gmu->aspace, &bo->iova,
1151 range_start >> PAGE_SHIFT, range_end >> PAGE_SHIFT);
1153 drm_gem_object_put(bo->obj);
1157 bo->virt = msm_gem_get_vaddr(bo->obj);
1163 static int a6xx_gmu_memory_probe(struct a6xx_gmu *gmu)
1165 struct iommu_domain *domain;
1166 struct msm_mmu *mmu;
1168 domain = iommu_domain_alloc(&platform_bus_type);
1172 mmu = msm_iommu_new(gmu->dev, domain);
1173 gmu->aspace = msm_gem_address_space_create(mmu, "gmu", 0x0, 0x80000000);
1174 if (IS_ERR(gmu->aspace)) {
1175 iommu_domain_free(domain);
1176 return PTR_ERR(gmu->aspace);
1182 /* Return the 'arc-level' for the given frequency */
1183 static unsigned int a6xx_gmu_get_arc_level(struct device *dev,
1186 struct dev_pm_opp *opp;
1192 opp = dev_pm_opp_find_freq_exact(dev, freq, true);
1196 val = dev_pm_opp_get_level(opp);
1198 dev_pm_opp_put(opp);
1203 static int a6xx_gmu_rpmh_arc_votes_init(struct device *dev, u32 *votes,
1204 unsigned long *freqs, int freqs_count, const char *id)
1207 const u16 *pri, *sec;
1208 size_t pri_count, sec_count;
1210 pri = cmd_db_read_aux_data(id, &pri_count);
1212 return PTR_ERR(pri);
1214 * The data comes back as an array of unsigned shorts so adjust the
1221 sec = cmd_db_read_aux_data("mx.lvl", &sec_count);
1223 return PTR_ERR(sec);
1229 /* Construct a vote for each frequency */
1230 for (i = 0; i < freqs_count; i++) {
1231 u8 pindex = 0, sindex = 0;
1232 unsigned int level = a6xx_gmu_get_arc_level(dev, freqs[i]);
1234 /* Get the primary index that matches the arc level */
1235 for (j = 0; j < pri_count; j++) {
1236 if (pri[j] >= level) {
1242 if (j == pri_count) {
1244 "Level %u not found in the RPMh list\n",
1246 DRM_DEV_ERROR(dev, "Available levels:\n");
1247 for (j = 0; j < pri_count; j++)
1248 DRM_DEV_ERROR(dev, " %u\n", pri[j]);
1254 * Look for a level in in the secondary list that matches. If
1255 * nothing fits, use the maximum non zero vote
1258 for (j = 0; j < sec_count; j++) {
1259 if (sec[j] >= level) {
1262 } else if (sec[j]) {
1267 /* Construct the vote */
1268 votes[i] = ((pri[pindex] & 0xffff) << 16) |
1269 (sindex << 8) | pindex;
1276 * The GMU votes with the RPMh for itself and on behalf of the GPU but we need
1277 * to construct the list of votes on the CPU and send it over. Query the RPMh
1278 * voltage levels and build the votes
1281 static int a6xx_gmu_rpmh_votes_init(struct a6xx_gmu *gmu)
1283 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
1284 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
1285 struct msm_gpu *gpu = &adreno_gpu->base;
1288 /* Build the GX votes */
1289 ret = a6xx_gmu_rpmh_arc_votes_init(&gpu->pdev->dev, gmu->gx_arc_votes,
1290 gmu->gpu_freqs, gmu->nr_gpu_freqs, "gfx.lvl");
1292 /* Build the CX votes */
1293 ret |= a6xx_gmu_rpmh_arc_votes_init(gmu->dev, gmu->cx_arc_votes,
1294 gmu->gmu_freqs, gmu->nr_gmu_freqs, "cx.lvl");
1299 static int a6xx_gmu_build_freq_table(struct device *dev, unsigned long *freqs,
1302 int count = dev_pm_opp_get_opp_count(dev);
1303 struct dev_pm_opp *opp;
1305 unsigned long freq = 1;
1308 * The OPP table doesn't contain the "off" frequency level so we need to
1309 * add 1 to the table size to account for it
1312 if (WARN(count + 1 > size,
1313 "The GMU frequency table is being truncated\n"))
1316 /* Set the "off" frequency */
1319 for (i = 0; i < count; i++) {
1320 opp = dev_pm_opp_find_freq_ceil(dev, &freq);
1324 dev_pm_opp_put(opp);
1325 freqs[index++] = freq++;
1331 static int a6xx_gmu_pwrlevels_probe(struct a6xx_gmu *gmu)
1333 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
1334 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
1335 struct msm_gpu *gpu = &adreno_gpu->base;
1340 * The GMU handles its own frequency switching so build a list of
1341 * available frequencies to send during initialization
1343 ret = dev_pm_opp_of_add_table(gmu->dev);
1345 DRM_DEV_ERROR(gmu->dev, "Unable to set the OPP table for the GMU\n");
1349 gmu->nr_gmu_freqs = a6xx_gmu_build_freq_table(gmu->dev,
1350 gmu->gmu_freqs, ARRAY_SIZE(gmu->gmu_freqs));
1353 * The GMU also handles GPU frequency switching so build a list
1354 * from the GPU OPP table
1356 gmu->nr_gpu_freqs = a6xx_gmu_build_freq_table(&gpu->pdev->dev,
1357 gmu->gpu_freqs, ARRAY_SIZE(gmu->gpu_freqs));
1359 gmu->current_perf_index = gmu->nr_gpu_freqs - 1;
1361 /* Build the list of RPMh votes that we'll send to the GMU */
1362 return a6xx_gmu_rpmh_votes_init(gmu);
1365 static int a6xx_gmu_clocks_probe(struct a6xx_gmu *gmu)
1367 int ret = devm_clk_bulk_get_all(gmu->dev, &gmu->clocks);
1372 gmu->nr_clocks = ret;
1374 gmu->core_clk = msm_clk_bulk_get_clock(gmu->clocks,
1375 gmu->nr_clocks, "gmu");
1380 static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev,
1384 struct resource *res = platform_get_resource_byname(pdev,
1385 IORESOURCE_MEM, name);
1388 DRM_DEV_ERROR(&pdev->dev, "Unable to find the %s registers\n", name);
1389 return ERR_PTR(-EINVAL);
1392 ret = ioremap(res->start, resource_size(res));
1394 DRM_DEV_ERROR(&pdev->dev, "Unable to map the %s registers\n", name);
1395 return ERR_PTR(-EINVAL);
1401 static int a6xx_gmu_get_irq(struct a6xx_gmu *gmu, struct platform_device *pdev,
1402 const char *name, irq_handler_t handler)
1406 irq = platform_get_irq_byname(pdev, name);
1408 ret = request_irq(irq, handler, IRQF_TRIGGER_HIGH, name, gmu);
1410 DRM_DEV_ERROR(&pdev->dev, "Unable to get interrupt %s %d\n",
1420 void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu)
1422 struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
1423 struct platform_device *pdev = to_platform_device(gmu->dev);
1425 if (!gmu->initialized)
1428 pm_runtime_force_suspend(gmu->dev);
1430 if (!IS_ERR_OR_NULL(gmu->gxpd)) {
1431 pm_runtime_disable(gmu->gxpd);
1432 dev_pm_domain_detach(gmu->gxpd, false);
1436 if (platform_get_resource_byname(pdev, IORESOURCE_MEM, "rscc"))
1441 a6xx_gmu_memory_free(gmu);
1443 free_irq(gmu->gmu_irq, gmu);
1444 free_irq(gmu->hfi_irq, gmu);
1446 /* Drop reference taken in of_find_device_by_node */
1447 put_device(gmu->dev);
1449 gmu->initialized = false;
1452 int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
1454 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
1455 struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
1456 struct platform_device *pdev = of_find_device_by_node(node);
1462 gmu->dev = &pdev->dev;
1464 of_dma_configure(gmu->dev, node, true);
1466 /* Fow now, don't do anything fancy until we get our feet under us */
1467 gmu->idle_level = GMU_IDLE_STATE_ACTIVE;
1469 pm_runtime_enable(gmu->dev);
1471 /* Get the list of clocks */
1472 ret = a6xx_gmu_clocks_probe(gmu);
1474 goto err_put_device;
1476 ret = a6xx_gmu_memory_probe(gmu);
1478 goto err_put_device;
1480 /* Allocate memory for the GMU dummy page */
1481 ret = a6xx_gmu_memory_alloc(gmu, &gmu->dummy, SZ_4K, 0x60000000);
1485 if (adreno_is_a650(adreno_gpu)) {
1486 ret = a6xx_gmu_memory_alloc(gmu, &gmu->icache,
1487 SZ_16M - SZ_16K, 0x04000);
1490 } else if (adreno_is_a640(adreno_gpu)) {
1491 ret = a6xx_gmu_memory_alloc(gmu, &gmu->icache,
1492 SZ_256K - SZ_16K, 0x04000);
1496 ret = a6xx_gmu_memory_alloc(gmu, &gmu->dcache,
1497 SZ_256K - SZ_16K, 0x44000);
1501 /* HFI v1, has sptprac */
1504 /* Allocate memory for the GMU debug region */
1505 ret = a6xx_gmu_memory_alloc(gmu, &gmu->debug, SZ_16K, 0);
1510 /* Allocate memory for for the HFI queues */
1511 ret = a6xx_gmu_memory_alloc(gmu, &gmu->hfi, SZ_16K, 0);
1515 /* Allocate memory for the GMU log region */
1516 ret = a6xx_gmu_memory_alloc(gmu, &gmu->log, SZ_4K, 0);
1520 /* Map the GMU registers */
1521 gmu->mmio = a6xx_gmu_get_mmio(pdev, "gmu");
1522 if (IS_ERR(gmu->mmio)) {
1523 ret = PTR_ERR(gmu->mmio);
1527 if (adreno_is_a650(adreno_gpu)) {
1528 gmu->rscc = a6xx_gmu_get_mmio(pdev, "rscc");
1529 if (IS_ERR(gmu->rscc))
1532 gmu->rscc = gmu->mmio + 0x23000;
1535 /* Get the HFI and GMU interrupts */
1536 gmu->hfi_irq = a6xx_gmu_get_irq(gmu, pdev, "hfi", a6xx_hfi_irq);
1537 gmu->gmu_irq = a6xx_gmu_get_irq(gmu, pdev, "gmu", a6xx_gmu_irq);
1539 if (gmu->hfi_irq < 0 || gmu->gmu_irq < 0)
1543 * Get a link to the GX power domain to reset the GPU in case of GMU
1546 gmu->gxpd = dev_pm_domain_attach_by_name(gmu->dev, "gx");
1548 /* Get the power levels for the GMU and GPU */
1549 a6xx_gmu_pwrlevels_probe(gmu);
1551 /* Set up the HFI queues */
1554 gmu->initialized = true;
1560 if (platform_get_resource_byname(pdev, IORESOURCE_MEM, "rscc"))
1562 free_irq(gmu->gmu_irq, gmu);
1563 free_irq(gmu->hfi_irq, gmu);
1568 a6xx_gmu_memory_free(gmu);
1570 /* Drop reference taken in of_find_device_by_node */
1571 put_device(gmu->dev);