drivers/gpu/drm/mediatek/mtk_hdmi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2014 MediaTek Inc.
   4  * Author: Jie Qiu <jie.qiu@mediatek.com>
   5  */
   6
   7 #include <linux/arm-smccc.h>
   8 #include <linux/clk.h>
   9 #include <linux/delay.h>
  10 #include <linux/hdmi.h>
  11 #include <linux/i2c.h>
  12 #include <linux/io.h>
  13 #include <linux/kernel.h>
  14 #include <linux/mfd/syscon.h>
  15 #include <linux/of_platform.h>
  16 #include <linux/of.h>
  17 #include <linux/of_gpio.h>
  18 #include <linux/of_graph.h>
  19 #include <linux/phy/phy.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/regmap.h>
  22
  23 #include <sound/hdmi-codec.h>
  24
  25 #include <drm/drm_atomic_helper.h>
  26 #include <drm/drm_bridge.h>
  27 #include <drm/drm_crtc.h>
  28 #include <drm/drm_edid.h>
  29 #include <drm/drm_print.h>
  30 #include <drm/drm_probe_helper.h>
  31
  32 #include "mtk_cec.h"
  33 #include "mtk_hdmi.h"
  34 #include "mtk_hdmi_regs.h"
  35
  36 #define NCTS_BYTES      7
  37
  38 enum mtk_hdmi_clk_id {
  39         MTK_HDMI_CLK_HDMI_PIXEL,
  40         MTK_HDMI_CLK_HDMI_PLL,
  41         MTK_HDMI_CLK_AUD_BCLK,
  42         MTK_HDMI_CLK_AUD_SPDIF,
  43         MTK_HDMI_CLK_COUNT
  44 };
  45
  46 enum hdmi_aud_input_type {
  47         HDMI_AUD_INPUT_I2S = 0,
  48         HDMI_AUD_INPUT_SPDIF,
  49 };
  50
  51 enum hdmi_aud_i2s_fmt {
  52         HDMI_I2S_MODE_RJT_24BIT = 0,
  53         HDMI_I2S_MODE_RJT_16BIT,
  54         HDMI_I2S_MODE_LJT_24BIT,
  55         HDMI_I2S_MODE_LJT_16BIT,
  56         HDMI_I2S_MODE_I2S_24BIT,
  57         HDMI_I2S_MODE_I2S_16BIT
  58 };
  59
  60 enum hdmi_aud_mclk {
  61         HDMI_AUD_MCLK_128FS,
  62         HDMI_AUD_MCLK_192FS,
  63         HDMI_AUD_MCLK_256FS,
  64         HDMI_AUD_MCLK_384FS,
  65         HDMI_AUD_MCLK_512FS,
  66         HDMI_AUD_MCLK_768FS,
  67         HDMI_AUD_MCLK_1152FS,
  68 };
  69
  70 enum hdmi_aud_channel_type {
  71         HDMI_AUD_CHAN_TYPE_1_0 = 0,
  72         HDMI_AUD_CHAN_TYPE_1_1,
  73         HDMI_AUD_CHAN_TYPE_2_0,
  74         HDMI_AUD_CHAN_TYPE_2_1,
  75         HDMI_AUD_CHAN_TYPE_3_0,
  76         HDMI_AUD_CHAN_TYPE_3_1,
  77         HDMI_AUD_CHAN_TYPE_4_0,
  78         HDMI_AUD_CHAN_TYPE_4_1,
  79         HDMI_AUD_CHAN_TYPE_5_0,
  80         HDMI_AUD_CHAN_TYPE_5_1,
  81         HDMI_AUD_CHAN_TYPE_6_0,
  82         HDMI_AUD_CHAN_TYPE_6_1,
  83         HDMI_AUD_CHAN_TYPE_7_0,
  84         HDMI_AUD_CHAN_TYPE_7_1,
  85         HDMI_AUD_CHAN_TYPE_3_0_LRS,
  86         HDMI_AUD_CHAN_TYPE_3_1_LRS,
  87         HDMI_AUD_CHAN_TYPE_4_0_CLRS,
  88         HDMI_AUD_CHAN_TYPE_4_1_CLRS,
  89         HDMI_AUD_CHAN_TYPE_6_1_CS,
  90         HDMI_AUD_CHAN_TYPE_6_1_CH,
  91         HDMI_AUD_CHAN_TYPE_6_1_OH,
  92         HDMI_AUD_CHAN_TYPE_6_1_CHR,
  93         HDMI_AUD_CHAN_TYPE_7_1_LH_RH,
  94         HDMI_AUD_CHAN_TYPE_7_1_LSR_RSR,
  95         HDMI_AUD_CHAN_TYPE_7_1_LC_RC,
  96         HDMI_AUD_CHAN_TYPE_7_1_LW_RW,
  97         HDMI_AUD_CHAN_TYPE_7_1_LSD_RSD,
  98         HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS,
  99         HDMI_AUD_CHAN_TYPE_7_1_LHS_RHS,
 100         HDMI_AUD_CHAN_TYPE_7_1_CS_CH,
 101         HDMI_AUD_CHAN_TYPE_7_1_CS_OH,
 102         HDMI_AUD_CHAN_TYPE_7_1_CS_CHR,
 103         HDMI_AUD_CHAN_TYPE_7_1_CH_OH,
 104         HDMI_AUD_CHAN_TYPE_7_1_CH_CHR,
 105         HDMI_AUD_CHAN_TYPE_7_1_OH_CHR,
 106         HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS_LSR_RSR,
 107         HDMI_AUD_CHAN_TYPE_6_0_CS,
 108         HDMI_AUD_CHAN_TYPE_6_0_CH,
 109         HDMI_AUD_CHAN_TYPE_6_0_OH,
 110         HDMI_AUD_CHAN_TYPE_6_0_CHR,
 111         HDMI_AUD_CHAN_TYPE_7_0_LH_RH,
 112         HDMI_AUD_CHAN_TYPE_7_0_LSR_RSR,
 113         HDMI_AUD_CHAN_TYPE_7_0_LC_RC,
 114         HDMI_AUD_CHAN_TYPE_7_0_LW_RW,
 115         HDMI_AUD_CHAN_TYPE_7_0_LSD_RSD,
 116         HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS,
 117         HDMI_AUD_CHAN_TYPE_7_0_LHS_RHS,
 118         HDMI_AUD_CHAN_TYPE_7_0_CS_CH,
 119         HDMI_AUD_CHAN_TYPE_7_0_CS_OH,
 120         HDMI_AUD_CHAN_TYPE_7_0_CS_CHR,
 121         HDMI_AUD_CHAN_TYPE_7_0_CH_OH,
 122         HDMI_AUD_CHAN_TYPE_7_0_CH_CHR,
 123         HDMI_AUD_CHAN_TYPE_7_0_OH_CHR,
 124         HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS_LSR_RSR,
 125         HDMI_AUD_CHAN_TYPE_8_0_LH_RH_CS,
 126         HDMI_AUD_CHAN_TYPE_UNKNOWN = 0xFF
 127 };
 128
 129 enum hdmi_aud_channel_swap_type {
 130         HDMI_AUD_SWAP_LR,
 131         HDMI_AUD_SWAP_LFE_CC,
 132         HDMI_AUD_SWAP_LSRS,
 133         HDMI_AUD_SWAP_RLS_RRS,
 134         HDMI_AUD_SWAP_LR_STATUS,
 135 };
 136
 137 struct hdmi_audio_param {
 138         enum hdmi_audio_coding_type aud_codec;
 139         enum hdmi_audio_sample_size aud_sampe_size;
 140         enum hdmi_aud_input_type aud_input_type;
 141         enum hdmi_aud_i2s_fmt aud_i2s_fmt;
 142         enum hdmi_aud_mclk aud_mclk;
 143         enum hdmi_aud_channel_type aud_input_chan_type;
 144         struct hdmi_codec_params codec_params;
 145 };
 146
 147 struct mtk_hdmi {
 148         struct drm_bridge bridge;
 149         struct drm_bridge *next_bridge;
 150         struct drm_connector conn;
 151         struct device *dev;
 152         struct phy *phy;
 153         struct device *cec_dev;
 154         struct i2c_adapter *ddc_adpt;
 155         struct clk *clk[MTK_HDMI_CLK_COUNT];
 156         struct drm_display_mode mode;
 157         bool dvi_mode;
 158         u32 min_clock;
 159         u32 max_clock;
 160         u32 max_hdisplay;
 161         u32 max_vdisplay;
 162         u32 ibias;
 163         u32 ibias_up;
 164         struct regmap *sys_regmap;
 165         unsigned int sys_offset;
 166         void __iomem *regs;
 167         enum hdmi_colorspace csp;
 168         struct hdmi_audio_param aud_param;
 169         bool audio_enable;
 170         bool powered;
 171         bool enabled;
 172 };
 173
 174 static inline struct mtk_hdmi *hdmi_ctx_from_bridge(struct drm_bridge *b)
 175 {
 176         return container_of(b, struct mtk_hdmi, bridge);
 177 }
 178
 179 static inline struct mtk_hdmi *hdmi_ctx_from_conn(struct drm_connector *c)
 180 {
 181         return container_of(c, struct mtk_hdmi, conn);
 182 }
 183
 184 static u32 mtk_hdmi_read(struct mtk_hdmi *hdmi, u32 offset)
 185 {
 186         return readl(hdmi->regs + offset);
 187 }
 188
 189 static void mtk_hdmi_write(struct mtk_hdmi *hdmi, u32 offset, u32 val)
 190 {
 191         writel(val, hdmi->regs + offset);
 192 }
 193
 194 static void mtk_hdmi_clear_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits)
 195 {
 196         void __iomem *reg = hdmi->regs + offset;
 197         u32 tmp;
 198
 199         tmp = readl(reg);
 200         tmp &= ~bits;
 201         writel(tmp, reg);
 202 }
 203
 204 static void mtk_hdmi_set_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits)
 205 {
 206         void __iomem *reg = hdmi->regs + offset;
 207         u32 tmp;
 208
 209         tmp = readl(reg);
 210         tmp |= bits;
 211         writel(tmp, reg);
 212 }
 213
 214 static void mtk_hdmi_mask(struct mtk_hdmi *hdmi, u32 offset, u32 val, u32 mask)
 215 {
 216         void __iomem *reg = hdmi->regs + offset;
 217         u32 tmp;
 218
 219         tmp = readl(reg);
 220         tmp = (tmp & ~mask) | (val & mask);
 221         writel(tmp, reg);
 222 }
 223
 224 static void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi, bool black)
 225 {
 226         mtk_hdmi_mask(hdmi, VIDEO_CFG_4, black ? GEN_RGB : NORMAL_PATH,
 227                       VIDEO_SOURCE_SEL);
 228 }
 229
 230 static void mtk_hdmi_hw_make_reg_writable(struct mtk_hdmi *hdmi, bool enable)
 231 {
 232         struct arm_smccc_res res;
 233         struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(hdmi->phy);
 234
 235         /*
 236          * MT8173 HDMI hardware has an output control bit to enable/disable HDMI
 237          * output. This bit can only be controlled in ARM supervisor mode.
 238          * The ARM trusted firmware provides an API for the HDMI driver to set
 239          * this control bit to enable HDMI output in supervisor mode.
 240          */
 241         if (hdmi_phy->conf && hdmi_phy->conf->tz_disabled)
 242                 regmap_update_bits(hdmi->sys_regmap,
 243                                    hdmi->sys_offset + HDMI_SYS_CFG20,
 244                                    0x80008005, enable ? 0x80000005 : 0x8000);
 245         else
 246                 arm_smccc_smc(MTK_SIP_SET_AUTHORIZED_SECURE_REG, 0x14000904,
 247                               0x80000000, 0, 0, 0, 0, 0, &res);
 248
 249         regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
 250                            HDMI_PCLK_FREE_RUN, enable ? HDMI_PCLK_FREE_RUN : 0);
 251         regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
 252                            HDMI_ON | ANLG_ON, enable ? (HDMI_ON | ANLG_ON) : 0);
 253 }
 254
 255 static void mtk_hdmi_hw_1p4_version_enable(struct mtk_hdmi *hdmi, bool enable)
 256 {
 257         regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
 258                            HDMI2P0_EN, enable ? 0 : HDMI2P0_EN);
 259 }
 260
 261 static void mtk_hdmi_hw_aud_mute(struct mtk_hdmi *hdmi)
 262 {
 263         mtk_hdmi_set_bits(hdmi, GRL_AUDIO_CFG, AUDIO_ZERO);
 264 }
 265
 266 static void mtk_hdmi_hw_aud_unmute(struct mtk_hdmi *hdmi)
 267 {
 268         mtk_hdmi_clear_bits(hdmi, GRL_AUDIO_CFG, AUDIO_ZERO);
 269 }
 270
 271 static void mtk_hdmi_hw_reset(struct mtk_hdmi *hdmi)
 272 {
 273         regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
 274                            HDMI_RST, HDMI_RST);
 275         regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
 276                            HDMI_RST, 0);
 277         mtk_hdmi_clear_bits(hdmi, GRL_CFG3, CFG3_CONTROL_PACKET_DELAY);
 278         regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
 279                            ANLG_ON, ANLG_ON);
 280 }
 281
 282 static void mtk_hdmi_hw_enable_notice(struct mtk_hdmi *hdmi, bool enable_notice)
 283 {
 284         mtk_hdmi_mask(hdmi, GRL_CFG2, enable_notice ? CFG2_NOTICE_EN : 0,
 285                       CFG2_NOTICE_EN);
 286 }
 287
 288 static void mtk_hdmi_hw_write_int_mask(struct mtk_hdmi *hdmi, u32 int_mask)
 289 {
 290         mtk_hdmi_write(hdmi, GRL_INT_MASK, int_mask);
 291 }
 292
 293 static void mtk_hdmi_hw_enable_dvi_mode(struct mtk_hdmi *hdmi, bool enable)
 294 {
 295         mtk_hdmi_mask(hdmi, GRL_CFG1, enable ? CFG1_DVI : 0, CFG1_DVI);
 296 }
 297
 298 static void mtk_hdmi_hw_send_info_frame(struct mtk_hdmi *hdmi, u8 *buffer,
 299                                         u8 len)
 300 {
 301         u32 ctrl_reg = GRL_CTRL;
 302         int i;
 303         u8 *frame_data;
 304         enum hdmi_infoframe_type frame_type;
 305         u8 frame_ver;
 306         u8 frame_len;
 307         u8 checksum;
 308         int ctrl_frame_en = 0;
 309
 310         frame_type = *buffer;
 311         buffer += 1;
 312         frame_ver = *buffer;
 313         buffer += 1;
 314         frame_len = *buffer;
 315         buffer += 1;
 316         checksum = *buffer;
 317         buffer += 1;
 318         frame_data = buffer;
 319
 320         dev_dbg(hdmi->dev,
 321                 "frame_type:0x%x,frame_ver:0x%x,frame_len:0x%x,checksum:0x%x\n",
 322                 frame_type, frame_ver, frame_len, checksum);
 323
 324         switch (frame_type) {
 325         case HDMI_INFOFRAME_TYPE_AVI:
 326                 ctrl_frame_en = CTRL_AVI_EN;
 327                 ctrl_reg = GRL_CTRL;
 328                 break;
 329         case HDMI_INFOFRAME_TYPE_SPD:
 330                 ctrl_frame_en = CTRL_SPD_EN;
 331                 ctrl_reg = GRL_CTRL;
 332                 break;
 333         case HDMI_INFOFRAME_TYPE_AUDIO:
 334                 ctrl_frame_en = CTRL_AUDIO_EN;
 335                 ctrl_reg = GRL_CTRL;
 336                 break;
 337         case HDMI_INFOFRAME_TYPE_VENDOR:
 338                 ctrl_frame_en = VS_EN;
 339                 ctrl_reg = GRL_ACP_ISRC_CTRL;
 340                 break;
 341         default:
 342                 dev_err(hdmi->dev, "Unknown infoframe type %d\n", frame_type);
 343                 return;
 344         }
 345         mtk_hdmi_clear_bits(hdmi, ctrl_reg, ctrl_frame_en);
 346         mtk_hdmi_write(hdmi, GRL_INFOFRM_TYPE, frame_type);
 347         mtk_hdmi_write(hdmi, GRL_INFOFRM_VER, frame_ver);
 348         mtk_hdmi_write(hdmi, GRL_INFOFRM_LNG, frame_len);
 349
 350         mtk_hdmi_write(hdmi, GRL_IFM_PORT, checksum);
 351         for (i = 0; i < frame_len; i++)
 352                 mtk_hdmi_write(hdmi, GRL_IFM_PORT, frame_data[i]);
 353
 354         mtk_hdmi_set_bits(hdmi, ctrl_reg, ctrl_frame_en);
 355 }
 356
 357 static void mtk_hdmi_hw_send_aud_packet(struct mtk_hdmi *hdmi, bool enable)
 358 {
 359         mtk_hdmi_mask(hdmi, GRL_SHIFT_R2, enable ? 0 : AUDIO_PACKET_OFF,
 360                       AUDIO_PACKET_OFF);
 361 }
 362
 363 static void mtk_hdmi_hw_config_sys(struct mtk_hdmi *hdmi)
 364 {
 365         regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
 366                            HDMI_OUT_FIFO_EN | MHL_MODE_ON, 0);
 367         usleep_range(2000, 4000);
 368         regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
 369                            HDMI_OUT_FIFO_EN | MHL_MODE_ON, HDMI_OUT_FIFO_EN);
 370 }
 371
 372 static void mtk_hdmi_hw_set_deep_color_mode(struct mtk_hdmi *hdmi)
 373 {
 374         regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
 375                            DEEP_COLOR_MODE_MASK | DEEP_COLOR_EN,
 376                            COLOR_8BIT_MODE);
 377 }
 378
 379 static void mtk_hdmi_hw_send_av_mute(struct mtk_hdmi *hdmi)
 380 {
 381         mtk_hdmi_clear_bits(hdmi, GRL_CFG4, CTRL_AVMUTE);
 382         usleep_range(2000, 4000);
 383         mtk_hdmi_set_bits(hdmi, GRL_CFG4, CTRL_AVMUTE);
 384 }
 385
 386 static void mtk_hdmi_hw_send_av_unmute(struct mtk_hdmi *hdmi)
 387 {
 388         mtk_hdmi_mask(hdmi, GRL_CFG4, CFG4_AV_UNMUTE_EN,
 389                       CFG4_AV_UNMUTE_EN | CFG4_AV_UNMUTE_SET);
 390         usleep_range(2000, 4000);
 391         mtk_hdmi_mask(hdmi, GRL_CFG4, CFG4_AV_UNMUTE_SET,
 392                       CFG4_AV_UNMUTE_EN | CFG4_AV_UNMUTE_SET);
 393 }
 394
 395 static void mtk_hdmi_hw_ncts_enable(struct mtk_hdmi *hdmi, bool on)
 396 {
 397         mtk_hdmi_mask(hdmi, GRL_CTS_CTRL, on ? 0 : CTS_CTRL_SOFT,
 398                       CTS_CTRL_SOFT);
 399 }
 400
 401 static void mtk_hdmi_hw_ncts_auto_write_enable(struct mtk_hdmi *hdmi,
 402                                                bool enable)
 403 {
 404         mtk_hdmi_mask(hdmi, GRL_CTS_CTRL, enable ? NCTS_WRI_ANYTIME : 0,
 405                       NCTS_WRI_ANYTIME);
 406 }
 407
 408 static void mtk_hdmi_hw_msic_setting(struct mtk_hdmi *hdmi,
 409                                      struct drm_display_mode *mode)
 410 {
 411         mtk_hdmi_clear_bits(hdmi, GRL_CFG4, CFG4_MHL_MODE);
 412
 413         if (mode->flags & DRM_MODE_FLAG_INTERLACE &&
 414             mode->clock == 74250 &&
 415             mode->vdisplay == 1080)
 416                 mtk_hdmi_clear_bits(hdmi, GRL_CFG2, CFG2_MHL_DE_SEL);
 417         else
 418                 mtk_hdmi_set_bits(hdmi, GRL_CFG2, CFG2_MHL_DE_SEL);
 419 }
 420
 421 static void mtk_hdmi_hw_aud_set_channel_swap(struct mtk_hdmi *hdmi,
 422                                         enum hdmi_aud_channel_swap_type swap)
 423 {
 424         u8 swap_bit;
 425
 426         switch (swap) {
 427         case HDMI_AUD_SWAP_LR:
 428                 swap_bit = LR_SWAP;
 429                 break;
 430         case HDMI_AUD_SWAP_LFE_CC:
 431                 swap_bit = LFE_CC_SWAP;
 432                 break;
 433         case HDMI_AUD_SWAP_LSRS:
 434                 swap_bit = LSRS_SWAP;
 435                 break;
 436         case HDMI_AUD_SWAP_RLS_RRS:
 437                 swap_bit = RLS_RRS_SWAP;
 438                 break;
 439         case HDMI_AUD_SWAP_LR_STATUS:
 440                 swap_bit = LR_STATUS_SWAP;
 441                 break;
 442         default:
 443                 swap_bit = LFE_CC_SWAP;
 444                 break;
 445         }
 446         mtk_hdmi_mask(hdmi, GRL_CH_SWAP, swap_bit, 0xff);
 447 }
 448
 449 static void mtk_hdmi_hw_aud_set_bit_num(struct mtk_hdmi *hdmi,
 450                                         enum hdmi_audio_sample_size bit_num)
 451 {
 452         u32 val;
 453
 454         switch (bit_num) {
 455         case HDMI_AUDIO_SAMPLE_SIZE_16:
 456                 val = AOUT_16BIT;
 457                 break;
 458         case HDMI_AUDIO_SAMPLE_SIZE_20:
 459                 val = AOUT_20BIT;
 460                 break;
 461         case HDMI_AUDIO_SAMPLE_SIZE_24:
 462         case HDMI_AUDIO_SAMPLE_SIZE_STREAM:
 463                 val = AOUT_24BIT;
 464                 break;
 465         }
 466
 467         mtk_hdmi_mask(hdmi, GRL_AOUT_CFG, val, AOUT_BNUM_SEL_MASK);
 468 }
 469
 470 static void mtk_hdmi_hw_aud_set_i2s_fmt(struct mtk_hdmi *hdmi,
 471                                         enum hdmi_aud_i2s_fmt i2s_fmt)
 472 {
 473         u32 val;
 474
 475         val = mtk_hdmi_read(hdmi, GRL_CFG0);
 476         val &= ~(CFG0_W_LENGTH_MASK | CFG0_I2S_MODE_MASK);
 477
 478         switch (i2s_fmt) {
 479         case HDMI_I2S_MODE_RJT_24BIT:
 480                 val |= CFG0_I2S_MODE_RTJ | CFG0_W_LENGTH_24BIT;
 481                 break;
 482         case HDMI_I2S_MODE_RJT_16BIT:
 483                 val |= CFG0_I2S_MODE_RTJ | CFG0_W_LENGTH_16BIT;
 484                 break;
 485         case HDMI_I2S_MODE_LJT_24BIT:
 486         default:
 487                 val |= CFG0_I2S_MODE_LTJ | CFG0_W_LENGTH_24BIT;
 488                 break;
 489         case HDMI_I2S_MODE_LJT_16BIT:
 490                 val |= CFG0_I2S_MODE_LTJ | CFG0_W_LENGTH_16BIT;
 491                 break;
 492         case HDMI_I2S_MODE_I2S_24BIT:
 493                 val |= CFG0_I2S_MODE_I2S | CFG0_W_LENGTH_24BIT;
 494                 break;
 495         case HDMI_I2S_MODE_I2S_16BIT:
 496                 val |= CFG0_I2S_MODE_I2S | CFG0_W_LENGTH_16BIT;
 497                 break;
 498         }
 499         mtk_hdmi_write(hdmi, GRL_CFG0, val);
 500 }
 501
 502 static void mtk_hdmi_hw_audio_config(struct mtk_hdmi *hdmi, bool dst)
 503 {
 504         const u8 mask = HIGH_BIT_RATE | DST_NORMAL_DOUBLE | SACD_DST | DSD_SEL;
 505         u8 val;
 506
 507         /* Disable high bitrate, set DST packet normal/double */
 508         mtk_hdmi_clear_bits(hdmi, GRL_AOUT_CFG, HIGH_BIT_RATE_PACKET_ALIGN);
 509
 510         if (dst)
 511                 val = DST_NORMAL_DOUBLE | SACD_DST;
 512         else
 513                 val = 0;
 514
 515         mtk_hdmi_mask(hdmi, GRL_AUDIO_CFG, val, mask);
 516 }
 517
 518 static void mtk_hdmi_hw_aud_set_i2s_chan_num(struct mtk_hdmi *hdmi,
 519                                         enum hdmi_aud_channel_type channel_type,
 520                                         u8 channel_count)
 521 {
 522         unsigned int ch_switch;
 523         u8 i2s_uv;
 524
 525         ch_switch = CH_SWITCH(7, 7) | CH_SWITCH(6, 6) |
 526                     CH_SWITCH(5, 5) | CH_SWITCH(4, 4) |
 527                     CH_SWITCH(3, 3) | CH_SWITCH(1, 2) |
 528                     CH_SWITCH(2, 1) | CH_SWITCH(0, 0);
 529
 530         if (channel_count == 2) {
 531                 i2s_uv = I2S_UV_CH_EN(0);
 532         } else if (channel_count == 3 || channel_count == 4) {
 533                 if (channel_count == 4 &&
 534                     (channel_type == HDMI_AUD_CHAN_TYPE_3_0_LRS ||
 535                     channel_type == HDMI_AUD_CHAN_TYPE_4_0))
 536                         i2s_uv = I2S_UV_CH_EN(2) | I2S_UV_CH_EN(0);
 537                 else
 538                         i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2);
 539         } else if (channel_count == 6 || channel_count == 5) {
 540                 if (channel_count == 6 &&
 541                     channel_type != HDMI_AUD_CHAN_TYPE_5_1 &&
 542                     channel_type != HDMI_AUD_CHAN_TYPE_4_1_CLRS) {
 543                         i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2) |
 544                                  I2S_UV_CH_EN(1) | I2S_UV_CH_EN(0);
 545                 } else {
 546                         i2s_uv = I2S_UV_CH_EN(2) | I2S_UV_CH_EN(1) |
 547                                  I2S_UV_CH_EN(0);
 548                 }
 549         } else if (channel_count == 8 || channel_count == 7) {
 550                 i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2) |
 551                          I2S_UV_CH_EN(1) | I2S_UV_CH_EN(0);
 552         } else {
 553                 i2s_uv = I2S_UV_CH_EN(0);
 554         }
 555
 556         mtk_hdmi_write(hdmi, GRL_CH_SW0, ch_switch & 0xff);
 557         mtk_hdmi_write(hdmi, GRL_CH_SW1, (ch_switch >> 8) & 0xff);
 558         mtk_hdmi_write(hdmi, GRL_CH_SW2, (ch_switch >> 16) & 0xff);
 559         mtk_hdmi_write(hdmi, GRL_I2S_UV, i2s_uv);
 560 }
 561
 562 static void mtk_hdmi_hw_aud_set_input_type(struct mtk_hdmi *hdmi,
 563                                            enum hdmi_aud_input_type input_type)
 564 {
 565         u32 val;
 566
 567         val = mtk_hdmi_read(hdmi, GRL_CFG1);
 568         if (input_type == HDMI_AUD_INPUT_I2S &&
 569             (val & CFG1_SPDIF) == CFG1_SPDIF) {
 570                 val &= ~CFG1_SPDIF;
 571         } else if (input_type == HDMI_AUD_INPUT_SPDIF &&
 572                 (val & CFG1_SPDIF) == 0) {
 573                 val |= CFG1_SPDIF;
 574         }
 575         mtk_hdmi_write(hdmi, GRL_CFG1, val);
 576 }
 577
 578 static void mtk_hdmi_hw_aud_set_channel_status(struct mtk_hdmi *hdmi,
 579                                                u8 *channel_status)
 580 {
 581         int i;
 582
 583         for (i = 0; i < 5; i++) {
 584                 mtk_hdmi_write(hdmi, GRL_I2S_C_STA0 + i * 4, channel_status[i]);
 585                 mtk_hdmi_write(hdmi, GRL_L_STATUS_0 + i * 4, channel_status[i]);
 586                 mtk_hdmi_write(hdmi, GRL_R_STATUS_0 + i * 4, channel_status[i]);
 587         }
 588         for (; i < 24; i++) {
 589                 mtk_hdmi_write(hdmi, GRL_L_STATUS_0 + i * 4, 0);
 590                 mtk_hdmi_write(hdmi, GRL_R_STATUS_0 + i * 4, 0);
 591         }
 592 }
 593
 594 static void mtk_hdmi_hw_aud_src_reenable(struct mtk_hdmi *hdmi)
 595 {
 596         u32 val;
 597
 598         val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL);
 599         if (val & MIX_CTRL_SRC_EN) {
 600                 val &= ~MIX_CTRL_SRC_EN;
 601                 mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val);
 602                 usleep_range(255, 512);
 603                 val |= MIX_CTRL_SRC_EN;
 604                 mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val);
 605         }
 606 }
 607
 608 static void mtk_hdmi_hw_aud_src_disable(struct mtk_hdmi *hdmi)
 609 {
 610         u32 val;
 611
 612         val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL);
 613         val &= ~MIX_CTRL_SRC_EN;
 614         mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val);
 615         mtk_hdmi_write(hdmi, GRL_SHIFT_L1, 0x00);
 616 }
 617
 618 static void mtk_hdmi_hw_aud_set_mclk(struct mtk_hdmi *hdmi,
 619                                      enum hdmi_aud_mclk mclk)
 620 {
 621         u32 val;
 622
 623         val = mtk_hdmi_read(hdmi, GRL_CFG5);
 624         val &= CFG5_CD_RATIO_MASK;
 625
 626         switch (mclk) {
 627         case HDMI_AUD_MCLK_128FS:
 628                 val |= CFG5_FS128;
 629                 break;
 630         case HDMI_AUD_MCLK_256FS:
 631                 val |= CFG5_FS256;
 632                 break;
 633         case HDMI_AUD_MCLK_384FS:
 634                 val |= CFG5_FS384;
 635                 break;
 636         case HDMI_AUD_MCLK_512FS:
 637                 val |= CFG5_FS512;
 638                 break;
 639         case HDMI_AUD_MCLK_768FS:
 640                 val |= CFG5_FS768;
 641                 break;
 642         default:
 643                 val |= CFG5_FS256;
 644                 break;
 645         }
 646         mtk_hdmi_write(hdmi, GRL_CFG5, val);
 647 }
 648
 649 struct hdmi_acr_n {
 650         unsigned int clock;
 651         unsigned int n[3];
 652 };
 653
 654 /* Recommended N values from HDMI specification, tables 7-1 to 7-3 */
 655 static const struct hdmi_acr_n hdmi_rec_n_table[] = {
 656         /* Clock, N: 32kHz 44.1kHz 48kHz */
 657         {  25175, {  4576,  7007,  6864 } },
 658         {  74176, { 11648, 17836, 11648 } },
 659         { 148352, { 11648,  8918,  5824 } },
 660         { 296703, {  5824,  4459,  5824 } },
 661         { 297000, {  3072,  4704,  5120 } },
 662         {      0, {  4096,  6272,  6144 } }, /* all other TMDS clocks */
 663 };
 664
 665 /**
 666  * hdmi_recommended_n() - Return N value recommended by HDMI specification
 667  * @freq: audio sample rate in Hz
 668  * @clock: rounded TMDS clock in kHz
 669  */
 670 static unsigned int hdmi_recommended_n(unsigned int freq, unsigned int clock)
 671 {
 672         const struct hdmi_acr_n *recommended;
 673         unsigned int i;
 674
 675         for (i = 0; i < ARRAY_SIZE(hdmi_rec_n_table) - 1; i++) {
 676                 if (clock == hdmi_rec_n_table[i].clock)
 677                         break;
 678         }
 679         recommended = hdmi_rec_n_table + i;
 680
 681         switch (freq) {
 682         case 32000:
 683                 return recommended->n[0];
 684         case 44100:
 685                 return recommended->n[1];
 686         case 48000:
 687                 return recommended->n[2];
 688         case 88200:
 689                 return recommended->n[1] * 2;
 690         case 96000:
 691                 return recommended->n[2] * 2;
 692         case 176400:
 693                 return recommended->n[1] * 4;
 694         case 192000:
 695                 return recommended->n[2] * 4;
 696         default:
 697                 return (128 * freq) / 1000;
 698         }
 699 }
 700
 701 static unsigned int hdmi_mode_clock_to_hz(unsigned int clock)
 702 {
 703         switch (clock) {
 704         case 25175:
 705                 return 25174825;        /* 25.2/1.001 MHz */
 706         case 74176:
 707                 return 74175824;        /* 74.25/1.001 MHz */
 708         case 148352:
 709                 return 148351648;       /* 148.5/1.001 MHz */
 710         case 296703:
 711                 return 296703297;       /* 297/1.001 MHz */
 712         default:
 713                 return clock * 1000;
 714         }
 715 }
 716
 717 static unsigned int hdmi_expected_cts(unsigned int audio_sample_rate,
 718                                       unsigned int tmds_clock, unsigned int n)
 719 {
 720         return DIV_ROUND_CLOSEST_ULL((u64)hdmi_mode_clock_to_hz(tmds_clock) * n,
 721                                      128 * audio_sample_rate);
 722 }
 723
 724 static void do_hdmi_hw_aud_set_ncts(struct mtk_hdmi *hdmi, unsigned int n,
 725                                     unsigned int cts)
 726 {
 727         unsigned char val[NCTS_BYTES];
 728         int i;
 729
 730         mtk_hdmi_write(hdmi, GRL_NCTS, 0);
 731         mtk_hdmi_write(hdmi, GRL_NCTS, 0);
 732         mtk_hdmi_write(hdmi, GRL_NCTS, 0);
 733         memset(val, 0, sizeof(val));
 734
 735         val[0] = (cts >> 24) & 0xff;
 736         val[1] = (cts >> 16) & 0xff;
 737         val[2] = (cts >> 8) & 0xff;
 738         val[3] = cts & 0xff;
 739
 740         val[4] = (n >> 16) & 0xff;
 741         val[5] = (n >> 8) & 0xff;
 742         val[6] = n & 0xff;
 743
 744         for (i = 0; i < NCTS_BYTES; i++)
 745                 mtk_hdmi_write(hdmi, GRL_NCTS, val[i]);
 746 }
 747
 748 static void mtk_hdmi_hw_aud_set_ncts(struct mtk_hdmi *hdmi,
 749                                      unsigned int sample_rate,
 750                                      unsigned int clock)
 751 {
 752         unsigned int n, cts;
 753
 754         n = hdmi_recommended_n(sample_rate, clock);
 755         cts = hdmi_expected_cts(sample_rate, clock, n);
 756
 757         dev_dbg(hdmi->dev, "%s: sample_rate=%u, clock=%d, cts=%u, n=%u\n",
 758                 __func__, sample_rate, clock, n, cts);
 759
 760         mtk_hdmi_mask(hdmi, DUMMY_304, AUDIO_I2S_NCTS_SEL_64,
 761                       AUDIO_I2S_NCTS_SEL);
 762         do_hdmi_hw_aud_set_ncts(hdmi, n, cts);
 763 }
 764
 765 static u8 mtk_hdmi_aud_get_chnl_count(enum hdmi_aud_channel_type channel_type)
 766 {
 767         switch (channel_type) {
 768         case HDMI_AUD_CHAN_TYPE_1_0:
 769         case HDMI_AUD_CHAN_TYPE_1_1:
 770         case HDMI_AUD_CHAN_TYPE_2_0:
 771                 return 2;
 772         case HDMI_AUD_CHAN_TYPE_2_1:
 773         case HDMI_AUD_CHAN_TYPE_3_0:
 774                 return 3;
 775         case HDMI_AUD_CHAN_TYPE_3_1:
 776         case HDMI_AUD_CHAN_TYPE_4_0:
 777         case HDMI_AUD_CHAN_TYPE_3_0_LRS:
 778                 return 4;
 779         case HDMI_AUD_CHAN_TYPE_4_1:
 780         case HDMI_AUD_CHAN_TYPE_5_0:
 781         case HDMI_AUD_CHAN_TYPE_3_1_LRS:
 782         case HDMI_AUD_CHAN_TYPE_4_0_CLRS:
 783                 return 5;
 784         case HDMI_AUD_CHAN_TYPE_5_1:
 785         case HDMI_AUD_CHAN_TYPE_6_0:
 786         case HDMI_AUD_CHAN_TYPE_4_1_CLRS:
 787         case HDMI_AUD_CHAN_TYPE_6_0_CS:
 788         case HDMI_AUD_CHAN_TYPE_6_0_CH:
 789         case HDMI_AUD_CHAN_TYPE_6_0_OH:
 790         case HDMI_AUD_CHAN_TYPE_6_0_CHR:
 791                 return 6;
 792         case HDMI_AUD_CHAN_TYPE_6_1:
 793         case HDMI_AUD_CHAN_TYPE_6_1_CS:
 794         case HDMI_AUD_CHAN_TYPE_6_1_CH:
 795         case HDMI_AUD_CHAN_TYPE_6_1_OH:
 796         case HDMI_AUD_CHAN_TYPE_6_1_CHR:
 797         case HDMI_AUD_CHAN_TYPE_7_0:
 798         case HDMI_AUD_CHAN_TYPE_7_0_LH_RH:
 799         case HDMI_AUD_CHAN_TYPE_7_0_LSR_RSR:
 800         case HDMI_AUD_CHAN_TYPE_7_0_LC_RC:
 801         case HDMI_AUD_CHAN_TYPE_7_0_LW_RW:
 802         case HDMI_AUD_CHAN_TYPE_7_0_LSD_RSD:
 803         case HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS:
 804         case HDMI_AUD_CHAN_TYPE_7_0_LHS_RHS:
 805         case HDMI_AUD_CHAN_TYPE_7_0_CS_CH:
 806         case HDMI_AUD_CHAN_TYPE_7_0_CS_OH:
 807         case HDMI_AUD_CHAN_TYPE_7_0_CS_CHR:
 808         case HDMI_AUD_CHAN_TYPE_7_0_CH_OH:
 809         case HDMI_AUD_CHAN_TYPE_7_0_CH_CHR:
 810         case HDMI_AUD_CHAN_TYPE_7_0_OH_CHR:
 811         case HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS_LSR_RSR:
 812         case HDMI_AUD_CHAN_TYPE_8_0_LH_RH_CS:
 813                 return 7;
 814         case HDMI_AUD_CHAN_TYPE_7_1:
 815         case HDMI_AUD_CHAN_TYPE_7_1_LH_RH:
 816         case HDMI_AUD_CHAN_TYPE_7_1_LSR_RSR:
 817         case HDMI_AUD_CHAN_TYPE_7_1_LC_RC:
 818         case HDMI_AUD_CHAN_TYPE_7_1_LW_RW:
 819         case HDMI_AUD_CHAN_TYPE_7_1_LSD_RSD:
 820         case HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS:
 821         case HDMI_AUD_CHAN_TYPE_7_1_LHS_RHS:
 822         case HDMI_AUD_CHAN_TYPE_7_1_CS_CH:
 823         case HDMI_AUD_CHAN_TYPE_7_1_CS_OH:
 824         case HDMI_AUD_CHAN_TYPE_7_1_CS_CHR:
 825         case HDMI_AUD_CHAN_TYPE_7_1_CH_OH:
 826         case HDMI_AUD_CHAN_TYPE_7_1_CH_CHR:
 827         case HDMI_AUD_CHAN_TYPE_7_1_OH_CHR:
 828         case HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS_LSR_RSR:
 829                 return 8;
 830         default:
 831                 return 2;
 832         }
 833 }
 834
 835 static int mtk_hdmi_video_change_vpll(struct mtk_hdmi *hdmi, u32 clock)
 836 {
 837         unsigned long rate;
 838         int ret;
 839
 840         /* The DPI driver already should have set TVDPLL to the correct rate */
 841         ret = clk_set_rate(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL], clock);
 842         if (ret) {
 843                 dev_err(hdmi->dev, "Failed to set PLL to %u Hz: %d\n", clock,
 844                         ret);
 845                 return ret;
 846         }
 847
 848         rate = clk_get_rate(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]);
 849
 850         if (DIV_ROUND_CLOSEST(rate, 1000) != DIV_ROUND_CLOSEST(clock, 1000))
 851                 dev_warn(hdmi->dev, "Want PLL %u Hz, got %lu Hz\n", clock,
 852                          rate);
 853         else
 854                 dev_dbg(hdmi->dev, "Want PLL %u Hz, got %lu Hz\n", clock, rate);
 855
 856         mtk_hdmi_hw_config_sys(hdmi);
 857         mtk_hdmi_hw_set_deep_color_mode(hdmi);
 858         return 0;
 859 }
 860
 861 static void mtk_hdmi_video_set_display_mode(struct mtk_hdmi *hdmi,
 862                                             struct drm_display_mode *mode)
 863 {
 864         mtk_hdmi_hw_reset(hdmi);
 865         mtk_hdmi_hw_enable_notice(hdmi, true);
 866         mtk_hdmi_hw_write_int_mask(hdmi, 0xff);
 867         mtk_hdmi_hw_enable_dvi_mode(hdmi, hdmi->dvi_mode);
 868         mtk_hdmi_hw_ncts_auto_write_enable(hdmi, true);
 869
 870         mtk_hdmi_hw_msic_setting(hdmi, mode);
 871 }
 872
 873 static int mtk_hdmi_aud_enable_packet(struct mtk_hdmi *hdmi, bool enable)
 874 {
 875         mtk_hdmi_hw_send_aud_packet(hdmi, enable);
 876         return 0;
 877 }
 878
 879 static int mtk_hdmi_aud_on_off_hw_ncts(struct mtk_hdmi *hdmi, bool on)
 880 {
 881         mtk_hdmi_hw_ncts_enable(hdmi, on);
 882         return 0;
 883 }
 884
 885 static int mtk_hdmi_aud_set_input(struct mtk_hdmi *hdmi)
 886 {
 887         enum hdmi_aud_channel_type chan_type;
 888         u8 chan_count;
 889         bool dst;
 890
 891         mtk_hdmi_hw_aud_set_channel_swap(hdmi, HDMI_AUD_SWAP_LFE_CC);
 892         mtk_hdmi_set_bits(hdmi, GRL_MIX_CTRL, MIX_CTRL_FLAT);
 893
 894         if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF &&
 895             hdmi->aud_param.aud_codec == HDMI_AUDIO_CODING_TYPE_DST) {
 896                 mtk_hdmi_hw_aud_set_bit_num(hdmi, HDMI_AUDIO_SAMPLE_SIZE_24);
 897         } else if (hdmi->aud_param.aud_i2s_fmt == HDMI_I2S_MODE_LJT_24BIT) {
 898                 hdmi->aud_param.aud_i2s_fmt = HDMI_I2S_MODE_LJT_16BIT;
 899         }
 900
 901         mtk_hdmi_hw_aud_set_i2s_fmt(hdmi, hdmi->aud_param.aud_i2s_fmt);
 902         mtk_hdmi_hw_aud_set_bit_num(hdmi, HDMI_AUDIO_SAMPLE_SIZE_24);
 903
 904         dst = ((hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF) &&
 905                (hdmi->aud_param.aud_codec == HDMI_AUDIO_CODING_TYPE_DST));
 906         mtk_hdmi_hw_audio_config(hdmi, dst);
 907
 908         if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF)
 909                 chan_type = HDMI_AUD_CHAN_TYPE_2_0;
 910         else
 911                 chan_type = hdmi->aud_param.aud_input_chan_type;
 912         chan_count = mtk_hdmi_aud_get_chnl_count(chan_type);
 913         mtk_hdmi_hw_aud_set_i2s_chan_num(hdmi, chan_type, chan_count);
 914         mtk_hdmi_hw_aud_set_input_type(hdmi, hdmi->aud_param.aud_input_type);
 915
 916         return 0;
 917 }
 918
 919 static int mtk_hdmi_aud_set_src(struct mtk_hdmi *hdmi,
 920                                 struct drm_display_mode *display_mode)
 921 {
 922         unsigned int sample_rate = hdmi->aud_param.codec_params.sample_rate;
 923
 924         mtk_hdmi_aud_on_off_hw_ncts(hdmi, false);
 925         mtk_hdmi_hw_aud_src_disable(hdmi);
 926         mtk_hdmi_clear_bits(hdmi, GRL_CFG2, CFG2_ACLK_INV);
 927
 928         if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_I2S) {
 929                 switch (sample_rate) {
 930                 case 32000:
 931                 case 44100:
 932                 case 48000:
 933                 case 88200:
 934                 case 96000:
 935                         break;
 936                 default:
 937                         return -EINVAL;
 938                 }
 939                 mtk_hdmi_hw_aud_set_mclk(hdmi, hdmi->aud_param.aud_mclk);
 940         } else {
 941                 switch (sample_rate) {
 942                 case 32000:
 943                 case 44100:
 944                 case 48000:
 945                         break;
 946                 default:
 947                         return -EINVAL;
 948                 }
 949                 mtk_hdmi_hw_aud_set_mclk(hdmi, HDMI_AUD_MCLK_128FS);
 950         }
 951
 952         mtk_hdmi_hw_aud_set_ncts(hdmi, sample_rate, display_mode->clock);
 953
 954         mtk_hdmi_hw_aud_src_reenable(hdmi);
 955         return 0;
 956 }
 957
 958 static int mtk_hdmi_aud_output_config(struct mtk_hdmi *hdmi,
 959                                       struct drm_display_mode *display_mode)
 960 {
 961         mtk_hdmi_hw_aud_mute(hdmi);
 962         mtk_hdmi_aud_enable_packet(hdmi, false);
 963
 964         mtk_hdmi_aud_set_input(hdmi);
 965         mtk_hdmi_aud_set_src(hdmi, display_mode);
 966         mtk_hdmi_hw_aud_set_channel_status(hdmi,
 967                         hdmi->aud_param.codec_params.iec.status);
 968
 969         usleep_range(50, 100);
 970
 971         mtk_hdmi_aud_on_off_hw_ncts(hdmi, true);
 972         mtk_hdmi_aud_enable_packet(hdmi, true);
 973         mtk_hdmi_hw_aud_unmute(hdmi);
 974         return 0;
 975 }
 976
 977 static int mtk_hdmi_setup_avi_infoframe(struct mtk_hdmi *hdmi,
 978                                         struct drm_display_mode *mode)
 979 {
 980         struct hdmi_avi_infoframe frame;
 981         u8 buffer[17];
 982         ssize_t err;
 983
 984         err = drm_hdmi_avi_infoframe_from_display_mode(&frame,
 985                                                        &hdmi->conn, mode);
 986         if (err < 0) {
 987                 dev_err(hdmi->dev,
 988                         "Failed to get AVI infoframe from mode: %zd\n", err);
 989                 return err;
 990         }
 991
 992         err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
 993         if (err < 0) {
 994                 dev_err(hdmi->dev, "Failed to pack AVI infoframe: %zd\n", err);
 995                 return err;
 996         }
 997
 998         mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer));
 999         return 0;
1000 }
1001
1002 static int mtk_hdmi_setup_spd_infoframe(struct mtk_hdmi *hdmi,
1003                                         const char *vendor,
1004                                         const char *product)
1005 {
1006         struct hdmi_spd_infoframe frame;
1007         u8 buffer[29];
1008         ssize_t err;
1009
1010         err = hdmi_spd_infoframe_init(&frame, vendor, product);
1011         if (err < 0) {
1012                 dev_err(hdmi->dev, "Failed to initialize SPD infoframe: %zd\n",
1013                         err);
1014                 return err;
1015         }
1016
1017         err = hdmi_spd_infoframe_pack(&frame, buffer, sizeof(buffer));
1018         if (err < 0) {
1019                 dev_err(hdmi->dev, "Failed to pack SDP infoframe: %zd\n", err);
1020                 return err;
1021         }
1022
1023         mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer));
1024         return 0;
1025 }
1026
1027 static int mtk_hdmi_setup_audio_infoframe(struct mtk_hdmi *hdmi)
1028 {
1029         struct hdmi_audio_infoframe frame;
1030         u8 buffer[14];
1031         ssize_t err;
1032
1033         err = hdmi_audio_infoframe_init(&frame);
1034         if (err < 0) {
1035                 dev_err(hdmi->dev, "Failed to setup audio infoframe: %zd\n",
1036                         err);
1037                 return err;
1038         }
1039
1040         frame.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM;
1041         frame.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM;
1042         frame.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM;
1043         frame.channels = mtk_hdmi_aud_get_chnl_count(
1044                                         hdmi->aud_param.aud_input_chan_type);
1045
1046         err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
1047         if (err < 0) {
1048                 dev_err(hdmi->dev, "Failed to pack audio infoframe: %zd\n",
1049                         err);
1050                 return err;
1051         }
1052
1053         mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer));
1054         return 0;
1055 }
1056
1057 static int mtk_hdmi_setup_vendor_specific_infoframe(struct mtk_hdmi *hdmi,
1058                                                 struct drm_display_mode *mode)
1059 {
1060         struct hdmi_vendor_infoframe frame;
1061         u8 buffer[10];
1062         ssize_t err;
1063
1064         err = drm_hdmi_vendor_infoframe_from_display_mode(&frame,
1065                                                           &hdmi->conn, mode);
1066         if (err) {
1067                 dev_err(hdmi->dev,
1068                         "Failed to get vendor infoframe from mode: %zd\n", err);
1069                 return err;
1070         }
1071
1072         err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
1073         if (err < 0) {
1074                 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n",
1075                         err);
1076                 return err;
1077         }
1078
1079         mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer));
1080         return 0;
1081 }
1082
1083 static int mtk_hdmi_output_init(struct mtk_hdmi *hdmi)
1084 {
1085         struct hdmi_audio_param *aud_param = &hdmi->aud_param;
1086
1087         hdmi->csp = HDMI_COLORSPACE_RGB;
1088         aud_param->aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
1089         aud_param->aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16;
1090         aud_param->aud_input_type = HDMI_AUD_INPUT_I2S;
1091         aud_param->aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT;
1092         aud_param->aud_mclk = HDMI_AUD_MCLK_128FS;
1093         aud_param->aud_input_chan_type = HDMI_AUD_CHAN_TYPE_2_0;
1094
1095         return 0;
1096 }
1097
1098 static void mtk_hdmi_audio_enable(struct mtk_hdmi *hdmi)
1099 {
1100         mtk_hdmi_aud_enable_packet(hdmi, true);
1101         hdmi->audio_enable = true;
1102 }
1103
1104 static void mtk_hdmi_audio_disable(struct mtk_hdmi *hdmi)
1105 {
1106         mtk_hdmi_aud_enable_packet(hdmi, false);
1107         hdmi->audio_enable = false;
1108 }
1109
1110 static int mtk_hdmi_audio_set_param(struct mtk_hdmi *hdmi,
1111                                     struct hdmi_audio_param *param)
1112 {
1113         if (!hdmi->audio_enable) {
1114                 dev_err(hdmi->dev, "hdmi audio is in disable state!\n");
1115                 return -EINVAL;
1116         }
1117         dev_dbg(hdmi->dev, "codec:%d, input:%d, channel:%d, fs:%d\n",
1118                 param->aud_codec, param->aud_input_type,
1119                 param->aud_input_chan_type, param->codec_params.sample_rate);
1120         memcpy(&hdmi->aud_param, param, sizeof(*param));
1121         return mtk_hdmi_aud_output_config(hdmi, &hdmi->mode);
1122 }
1123
1124 static int mtk_hdmi_output_set_display_mode(struct mtk_hdmi *hdmi,
1125                                             struct drm_display_mode *mode)
1126 {
1127         int ret;
1128
1129         mtk_hdmi_hw_vid_black(hdmi, true);
1130         mtk_hdmi_hw_aud_mute(hdmi);
1131         mtk_hdmi_hw_send_av_mute(hdmi);
1132         phy_power_off(hdmi->phy);
1133
1134         ret = mtk_hdmi_video_change_vpll(hdmi,
1135                                          mode->clock * 1000);
1136         if (ret) {
1137                 dev_err(hdmi->dev, "Failed to set vpll: %d\n", ret);
1138                 return ret;
1139         }
1140         mtk_hdmi_video_set_display_mode(hdmi, mode);
1141
1142         phy_power_on(hdmi->phy);
1143         mtk_hdmi_aud_output_config(hdmi, mode);
1144
1145         mtk_hdmi_hw_vid_black(hdmi, false);
1146         mtk_hdmi_hw_aud_unmute(hdmi);
1147         mtk_hdmi_hw_send_av_unmute(hdmi);
1148
1149         return 0;
1150 }
1151
1152 static const char * const mtk_hdmi_clk_names[MTK_HDMI_CLK_COUNT] = {
1153         [MTK_HDMI_CLK_HDMI_PIXEL] = "pixel",
1154         [MTK_HDMI_CLK_HDMI_PLL] = "pll",
1155         [MTK_HDMI_CLK_AUD_BCLK] = "bclk",
1156         [MTK_HDMI_CLK_AUD_SPDIF] = "spdif",
1157 };
1158
1159 static int mtk_hdmi_get_all_clk(struct mtk_hdmi *hdmi,
1160                                 struct device_node *np)
1161 {
1162         int i;
1163
1164         for (i = 0; i < ARRAY_SIZE(mtk_hdmi_clk_names); i++) {
1165                 hdmi->clk[i] = of_clk_get_by_name(np,
1166                                                   mtk_hdmi_clk_names[i]);
1167                 if (IS_ERR(hdmi->clk[i]))
1168                         return PTR_ERR(hdmi->clk[i]);
1169         }
1170         return 0;
1171 }
1172
1173 static int mtk_hdmi_clk_enable_audio(struct mtk_hdmi *hdmi)
1174 {
1175         int ret;
1176
1177         ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]);
1178         if (ret)
1179                 return ret;
1180
1181         ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_AUD_SPDIF]);
1182         if (ret)
1183                 goto err;
1184
1185         return 0;
1186 err:
1187         clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]);
1188         return ret;
1189 }
1190
1191 static void mtk_hdmi_clk_disable_audio(struct mtk_hdmi *hdmi)
1192 {
1193         clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]);
1194         clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_SPDIF]);
1195 }
1196
1197 static enum drm_connector_status hdmi_conn_detect(struct drm_connector *conn,
1198                                                   bool force)
1199 {
1200         struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn);
1201
1202         return mtk_cec_hpd_high(hdmi->cec_dev) ?
1203                connector_status_connected : connector_status_disconnected;
1204 }
1205
1206 static void hdmi_conn_destroy(struct drm_connector *conn)
1207 {
1208         struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn);
1209
1210         mtk_cec_set_hpd_event(hdmi->cec_dev, NULL, NULL);
1211
1212         drm_connector_cleanup(conn);
1213 }
1214
1215 static int mtk_hdmi_conn_get_modes(struct drm_connector *conn)
1216 {
1217         struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn);
1218         struct edid *edid;
1219         int ret;
1220
1221         if (!hdmi->ddc_adpt)
1222                 return -ENODEV;
1223
1224         edid = drm_get_edid(conn, hdmi->ddc_adpt);
1225         if (!edid)
1226                 return -ENODEV;
1227
1228         hdmi->dvi_mode = !drm_detect_monitor_audio(edid);
1229
1230         drm_connector_update_edid_property(conn, edid);
1231
1232         ret = drm_add_edid_modes(conn, edid);
1233         kfree(edid);
1234         return ret;
1235 }
1236
1237 static int mtk_hdmi_conn_mode_valid(struct drm_connector *conn,
1238                                     struct drm_display_mode *mode)
1239 {
1240         struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn);
1241
1242         dev_dbg(hdmi->dev, "xres=%d, yres=%d, refresh=%d, intl=%d clock=%d\n",
1243                 mode->hdisplay, mode->vdisplay, mode->vrefresh,
1244                 !!(mode->flags & DRM_MODE_FLAG_INTERLACE), mode->clock * 1000);
1245
1246         if (hdmi->bridge.next) {
1247                 struct drm_display_mode adjusted_mode;
1248
1249                 drm_mode_copy(&adjusted_mode, mode);
1250                 if (!drm_bridge_mode_fixup(hdmi->bridge.next, mode,
1251                                            &adjusted_mode))
1252                         return MODE_BAD;
1253         }
1254
1255         if (mode->clock < 27000)
1256                 return MODE_CLOCK_LOW;
1257         if (mode->clock > 297000)
1258                 return MODE_CLOCK_HIGH;
1259
1260         return drm_mode_validate_size(mode, 0x1fff, 0x1fff);
1261 }
1262
1263 static struct drm_encoder *mtk_hdmi_conn_best_enc(struct drm_connector *conn)
1264 {
1265         struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn);
1266
1267         return hdmi->bridge.encoder;
1268 }
1269
1270 static const struct drm_connector_funcs mtk_hdmi_connector_funcs = {
1271         .detect = hdmi_conn_detect,
1272         .fill_modes = drm_helper_probe_single_connector_modes,
1273         .destroy = hdmi_conn_destroy,
1274         .reset = drm_atomic_helper_connector_reset,
1275         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1276         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1277 };
1278
1279 static const struct drm_connector_helper_funcs
1280                 mtk_hdmi_connector_helper_funcs = {
1281         .get_modes = mtk_hdmi_conn_get_modes,
1282         .mode_valid = mtk_hdmi_conn_mode_valid,
1283         .best_encoder = mtk_hdmi_conn_best_enc,
1284 };
1285
1286 static void mtk_hdmi_hpd_event(bool hpd, struct device *dev)
1287 {
1288         struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1289
1290         if (hdmi && hdmi->bridge.encoder && hdmi->bridge.encoder->dev)
1291                 drm_helper_hpd_irq_event(hdmi->bridge.encoder->dev);
1292 }
1293
1294 /*
1295  * Bridge callbacks
1296  */
1297
1298 static int mtk_hdmi_bridge_attach(struct drm_bridge *bridge)
1299 {
1300         struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1301         int ret;
1302
1303         ret = drm_connector_init(bridge->encoder->dev, &hdmi->conn,
1304                                  &mtk_hdmi_connector_funcs,
1305                                  DRM_MODE_CONNECTOR_HDMIA);
1306         if (ret) {
1307                 dev_err(hdmi->dev, "Failed to initialize connector: %d\n", ret);
1308                 return ret;
1309         }
1310         drm_connector_helper_add(&hdmi->conn, &mtk_hdmi_connector_helper_funcs);
1311
1312         hdmi->conn.polled = DRM_CONNECTOR_POLL_HPD;
1313         hdmi->conn.interlace_allowed = true;
1314         hdmi->conn.doublescan_allowed = false;
1315
1316         ret = drm_connector_attach_encoder(&hdmi->conn,
1317                                                 bridge->encoder);
1318         if (ret) {
1319                 dev_err(hdmi->dev,
1320                         "Failed to attach connector to encoder: %d\n", ret);
1321                 return ret;
1322         }
1323
1324         if (hdmi->next_bridge) {
1325                 ret = drm_bridge_attach(bridge->encoder, hdmi->next_bridge,
1326                                         bridge);
1327                 if (ret) {
1328                         dev_err(hdmi->dev,
1329                                 "Failed to attach external bridge: %d\n", ret);
1330                         return ret;
1331                 }
1332         }
1333
1334         mtk_cec_set_hpd_event(hdmi->cec_dev, mtk_hdmi_hpd_event, hdmi->dev);
1335
1336         return 0;
1337 }
1338
1339 static bool mtk_hdmi_bridge_mode_fixup(struct drm_bridge *bridge,
1340                                        const struct drm_display_mode *mode,
1341                                        struct drm_display_mode *adjusted_mode)
1342 {
1343         return true;
1344 }
1345
1346 static void mtk_hdmi_bridge_disable(struct drm_bridge *bridge)
1347 {
1348         struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1349
1350         if (!hdmi->enabled)
1351                 return;
1352
1353         phy_power_off(hdmi->phy);
1354         clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_HDMI_PIXEL]);
1355         clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]);
1356
1357         hdmi->enabled = false;
1358 }
1359
1360 static void mtk_hdmi_bridge_post_disable(struct drm_bridge *bridge)
1361 {
1362         struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1363
1364         if (!hdmi->powered)
1365                 return;
1366
1367         mtk_hdmi_hw_1p4_version_enable(hdmi, true);
1368         mtk_hdmi_hw_make_reg_writable(hdmi, false);
1369
1370         hdmi->powered = false;
1371 }
1372
1373 static void mtk_hdmi_bridge_mode_set(struct drm_bridge *bridge,
1374                                 const struct drm_display_mode *mode,
1375                                 const struct drm_display_mode *adjusted_mode)
1376 {
1377         struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1378
1379         dev_dbg(hdmi->dev, "cur info: name:%s, hdisplay:%d\n",
1380                 adjusted_mode->name, adjusted_mode->hdisplay);
1381         dev_dbg(hdmi->dev, "hsync_start:%d,hsync_end:%d, htotal:%d",
1382                 adjusted_mode->hsync_start, adjusted_mode->hsync_end,
1383                 adjusted_mode->htotal);
1384         dev_dbg(hdmi->dev, "hskew:%d, vdisplay:%d\n",
1385                 adjusted_mode->hskew, adjusted_mode->vdisplay);
1386         dev_dbg(hdmi->dev, "vsync_start:%d, vsync_end:%d, vtotal:%d",
1387                 adjusted_mode->vsync_start, adjusted_mode->vsync_end,
1388                 adjusted_mode->vtotal);
1389         dev_dbg(hdmi->dev, "vscan:%d, flag:%d\n",
1390                 adjusted_mode->vscan, adjusted_mode->flags);
1391
1392         drm_mode_copy(&hdmi->mode, adjusted_mode);
1393 }
1394
1395 static void mtk_hdmi_bridge_pre_enable(struct drm_bridge *bridge)
1396 {
1397         struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1398
1399         mtk_hdmi_hw_make_reg_writable(hdmi, true);
1400         mtk_hdmi_hw_1p4_version_enable(hdmi, true);
1401
1402         hdmi->powered = true;
1403 }
1404
1405 static void mtk_hdmi_send_infoframe(struct mtk_hdmi *hdmi,
1406                                     struct drm_display_mode *mode)
1407 {
1408         mtk_hdmi_setup_audio_infoframe(hdmi);
1409         mtk_hdmi_setup_avi_infoframe(hdmi, mode);
1410         mtk_hdmi_setup_spd_infoframe(hdmi, "mediatek", "On-chip HDMI");
1411         if (mode->flags & DRM_MODE_FLAG_3D_MASK)
1412                 mtk_hdmi_setup_vendor_specific_infoframe(hdmi, mode);
1413 }
1414
1415 static void mtk_hdmi_bridge_enable(struct drm_bridge *bridge)
1416 {
1417         struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1418
1419         mtk_hdmi_output_set_display_mode(hdmi, &hdmi->mode);
1420         clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]);
1421         clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PIXEL]);
1422         phy_power_on(hdmi->phy);
1423         mtk_hdmi_send_infoframe(hdmi, &hdmi->mode);
1424
1425         hdmi->enabled = true;
1426 }
1427
1428 static const struct drm_bridge_funcs mtk_hdmi_bridge_funcs = {
1429         .attach = mtk_hdmi_bridge_attach,
1430         .mode_fixup = mtk_hdmi_bridge_mode_fixup,
1431         .disable = mtk_hdmi_bridge_disable,
1432         .post_disable = mtk_hdmi_bridge_post_disable,
1433         .mode_set = mtk_hdmi_bridge_mode_set,
1434         .pre_enable = mtk_hdmi_bridge_pre_enable,
1435         .enable = mtk_hdmi_bridge_enable,
1436 };
1437
1438 static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
1439                                    struct platform_device *pdev)
1440 {
1441         struct device *dev = &pdev->dev;
1442         struct device_node *np = dev->of_node;
1443         struct device_node *cec_np, *remote, *i2c_np;
1444         struct platform_device *cec_pdev;
1445         struct regmap *regmap;
1446         struct resource *mem;
1447         int ret;
1448
1449         ret = mtk_hdmi_get_all_clk(hdmi, np);
1450         if (ret) {
1451                 dev_err(dev, "Failed to get clocks: %d\n", ret);
1452                 return ret;
1453         }
1454
1455         /* The CEC module handles HDMI hotplug detection */
1456         cec_np = of_get_compatible_child(np->parent, "mediatek,mt8173-cec");
1457         if (!cec_np) {
1458                 dev_err(dev, "Failed to find CEC node\n");
1459                 return -EINVAL;
1460         }
1461
1462         cec_pdev = of_find_device_by_node(cec_np);
1463         if (!cec_pdev) {
1464                 dev_err(hdmi->dev, "Waiting for CEC device %pOF\n",
1465                         cec_np);
1466                 of_node_put(cec_np);
1467                 return -EPROBE_DEFER;
1468         }
1469         of_node_put(cec_np);
1470         hdmi->cec_dev = &cec_pdev->dev;
1471
1472         /*
1473          * The mediatek,syscon-hdmi property contains a phandle link to the
1474          * MMSYS_CONFIG device and the register offset of the HDMI_SYS_CFG
1475          * registers it contains.
1476          */
1477         regmap = syscon_regmap_lookup_by_phandle(np, "mediatek,syscon-hdmi");
1478         ret = of_property_read_u32_index(np, "mediatek,syscon-hdmi", 1,
1479                                          &hdmi->sys_offset);
1480         if (IS_ERR(regmap))
1481                 ret = PTR_ERR(regmap);
1482         if (ret) {
1483                 dev_err(dev,
1484                         "Failed to get system configuration registers: %d\n",
1485                         ret);
1486                 return ret;
1487         }
1488         hdmi->sys_regmap = regmap;
1489
1490         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1491         hdmi->regs = devm_ioremap_resource(dev, mem);
1492         if (IS_ERR(hdmi->regs))
1493                 return PTR_ERR(hdmi->regs);
1494
1495         remote = of_graph_get_remote_node(np, 1, 0);
1496         if (!remote)
1497                 return -EINVAL;
1498
1499         if (!of_device_is_compatible(remote, "hdmi-connector")) {
1500                 hdmi->next_bridge = of_drm_find_bridge(remote);
1501                 if (!hdmi->next_bridge) {
1502                         dev_err(dev, "Waiting for external bridge\n");
1503                         of_node_put(remote);
1504                         return -EPROBE_DEFER;
1505                 }
1506         }
1507
1508         i2c_np = of_parse_phandle(remote, "ddc-i2c-bus", 0);
1509         if (!i2c_np) {
1510                 dev_err(dev, "Failed to find ddc-i2c-bus node in %pOF\n",
1511                         remote);
1512                 of_node_put(remote);
1513                 return -EINVAL;
1514         }
1515         of_node_put(remote);
1516
1517         hdmi->ddc_adpt = of_find_i2c_adapter_by_node(i2c_np);
1518         of_node_put(i2c_np);
1519         if (!hdmi->ddc_adpt) {
1520                 dev_err(dev, "Failed to get ddc i2c adapter by node\n");
1521                 return -EINVAL;
1522         }
1523
1524         return 0;
1525 }
1526
1527 /*
1528  * HDMI audio codec callbacks
1529  */
1530
1531 static int mtk_hdmi_audio_hw_params(struct device *dev, void *data,
1532                                     struct hdmi_codec_daifmt *daifmt,
1533                                     struct hdmi_codec_params *params)
1534 {
1535         struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1536         struct hdmi_audio_param hdmi_params;
1537         unsigned int chan = params->cea.channels;
1538
1539         dev_dbg(hdmi->dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
1540                 params->sample_rate, params->sample_width, chan);
1541
1542         if (!hdmi->bridge.encoder)
1543                 return -ENODEV;
1544
1545         switch (chan) {
1546         case 2:
1547                 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_2_0;
1548                 break;
1549         case 4:
1550                 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_4_0;
1551                 break;
1552         case 6:
1553                 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_5_1;
1554                 break;
1555         case 8:
1556                 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_7_1;
1557                 break;
1558         default:
1559                 dev_err(hdmi->dev, "channel[%d] not supported!\n", chan);
1560                 return -EINVAL;
1561         }
1562
1563         switch (params->sample_rate) {
1564         case 32000:
1565         case 44100:
1566         case 48000:
1567         case 88200:
1568         case 96000:
1569         case 176400:
1570         case 192000:
1571                 break;
1572         default:
1573                 dev_err(hdmi->dev, "rate[%d] not supported!\n",
1574                         params->sample_rate);
1575                 return -EINVAL;
1576         }
1577
1578         switch (daifmt->fmt) {
1579         case HDMI_I2S:
1580                 hdmi_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
1581                 hdmi_params.aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16;
1582                 hdmi_params.aud_input_type = HDMI_AUD_INPUT_I2S;
1583                 hdmi_params.aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT;
1584                 hdmi_params.aud_mclk = HDMI_AUD_MCLK_128FS;
1585                 break;
1586         case HDMI_SPDIF:
1587                 hdmi_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
1588                 hdmi_params.aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16;
1589                 hdmi_params.aud_input_type = HDMI_AUD_INPUT_SPDIF;
1590                 break;
1591         default:
1592                 dev_err(hdmi->dev, "%s: Invalid DAI format %d\n", __func__,
1593                         daifmt->fmt);
1594                 return -EINVAL;
1595         }
1596
1597         memcpy(&hdmi_params.codec_params, params,
1598                sizeof(hdmi_params.codec_params));
1599
1600         mtk_hdmi_audio_set_param(hdmi, &hdmi_params);
1601
1602         return 0;
1603 }
1604
1605 static int mtk_hdmi_audio_startup(struct device *dev, void *data)
1606 {
1607         struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1608
1609         dev_dbg(dev, "%s\n", __func__);
1610
1611         mtk_hdmi_audio_enable(hdmi);
1612
1613         return 0;
1614 }
1615
1616 static void mtk_hdmi_audio_shutdown(struct device *dev, void *data)
1617 {
1618         struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1619
1620         dev_dbg(dev, "%s\n", __func__);
1621
1622         mtk_hdmi_audio_disable(hdmi);
1623 }
1624
1625 static int
1626 mtk_hdmi_audio_digital_mute(struct device *dev, void *data, bool enable)
1627 {
1628         struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1629
1630         dev_dbg(dev, "%s(%d)\n", __func__, enable);
1631
1632         if (enable)
1633                 mtk_hdmi_hw_aud_mute(hdmi);
1634         else
1635                 mtk_hdmi_hw_aud_unmute(hdmi);
1636
1637         return 0;
1638 }
1639
1640 static int mtk_hdmi_audio_get_eld(struct device *dev, void *data, uint8_t *buf, size_t len)
1641 {
1642         struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1643
1644         dev_dbg(dev, "%s\n", __func__);
1645
1646         memcpy(buf, hdmi->conn.eld, min(sizeof(hdmi->conn.eld), len));
1647
1648         return 0;
1649 }
1650
1651 static const struct hdmi_codec_ops mtk_hdmi_audio_codec_ops = {
1652         .hw_params = mtk_hdmi_audio_hw_params,
1653         .audio_startup = mtk_hdmi_audio_startup,
1654         .audio_shutdown = mtk_hdmi_audio_shutdown,
1655         .digital_mute = mtk_hdmi_audio_digital_mute,
1656         .get_eld = mtk_hdmi_audio_get_eld,
1657 };
1658
1659 static void mtk_hdmi_register_audio_driver(struct device *dev)
1660 {
1661         struct hdmi_codec_pdata codec_data = {
1662                 .ops = &mtk_hdmi_audio_codec_ops,
1663                 .max_i2s_channels = 2,
1664                 .i2s = 1,
1665         };
1666         struct platform_device *pdev;
1667
1668         pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
1669                                              PLATFORM_DEVID_AUTO, &codec_data,
1670                                              sizeof(codec_data));
1671         if (IS_ERR(pdev))
1672                 return;
1673
1674         DRM_INFO("%s driver bound to HDMI\n", HDMI_CODEC_DRV_NAME);
1675 }
1676
1677 static int mtk_drm_hdmi_probe(struct platform_device *pdev)
1678 {
1679         struct mtk_hdmi *hdmi;
1680         struct device *dev = &pdev->dev;
1681         int ret;
1682
1683         hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
1684         if (!hdmi)
1685                 return -ENOMEM;
1686
1687         hdmi->dev = dev;
1688
1689         ret = mtk_hdmi_dt_parse_pdata(hdmi, pdev);
1690         if (ret)
1691                 return ret;
1692
1693         hdmi->phy = devm_phy_get(dev, "hdmi");
1694         if (IS_ERR(hdmi->phy)) {
1695                 ret = PTR_ERR(hdmi->phy);
1696                 dev_err(dev, "Failed to get HDMI PHY: %d\n", ret);
1697                 return ret;
1698         }
1699
1700         platform_set_drvdata(pdev, hdmi);
1701
1702         ret = mtk_hdmi_output_init(hdmi);
1703         if (ret) {
1704                 dev_err(dev, "Failed to initialize hdmi output\n");
1705                 return ret;
1706         }
1707
1708         mtk_hdmi_register_audio_driver(dev);
1709
1710         hdmi->bridge.funcs = &mtk_hdmi_bridge_funcs;
1711         hdmi->bridge.of_node = pdev->dev.of_node;
1712         drm_bridge_add(&hdmi->bridge);
1713
1714         ret = mtk_hdmi_clk_enable_audio(hdmi);
1715         if (ret) {
1716                 dev_err(dev, "Failed to enable audio clocks: %d\n", ret);
1717                 goto err_bridge_remove;
1718         }
1719
1720         dev_dbg(dev, "mediatek hdmi probe success\n");
1721         return 0;
1722
1723 err_bridge_remove:
1724         drm_bridge_remove(&hdmi->bridge);
1725         return ret;
1726 }
1727
1728 static int mtk_drm_hdmi_remove(struct platform_device *pdev)
1729 {
1730         struct mtk_hdmi *hdmi = platform_get_drvdata(pdev);
1731
1732         drm_bridge_remove(&hdmi->bridge);
1733         mtk_hdmi_clk_disable_audio(hdmi);
1734         return 0;
1735 }
1736
1737 #ifdef CONFIG_PM_SLEEP
1738 static int mtk_hdmi_suspend(struct device *dev)
1739 {
1740         struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1741
1742         mtk_hdmi_clk_disable_audio(hdmi);
1743         dev_dbg(dev, "hdmi suspend success!\n");
1744         return 0;
1745 }
1746
1747 static int mtk_hdmi_resume(struct device *dev)
1748 {
1749         struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1750         int ret = 0;
1751
1752         ret = mtk_hdmi_clk_enable_audio(hdmi);
1753         if (ret) {
1754                 dev_err(dev, "hdmi resume failed!\n");
1755                 return ret;
1756         }
1757
1758         dev_dbg(dev, "hdmi resume success!\n");
1759         return 0;
1760 }
1761 #endif
1762 static SIMPLE_DEV_PM_OPS(mtk_hdmi_pm_ops,
1763                          mtk_hdmi_suspend, mtk_hdmi_resume);
1764
1765 static const struct of_device_id mtk_drm_hdmi_of_ids[] = {
1766         { .compatible = "mediatek,mt8173-hdmi", },
1767         {}
1768 };
1769
1770 static struct platform_driver mtk_hdmi_driver = {
1771         .probe = mtk_drm_hdmi_probe,
1772         .remove = mtk_drm_hdmi_remove,
1773         .driver = {
1774                 .name = "mediatek-drm-hdmi",
1775                 .of_match_table = mtk_drm_hdmi_of_ids,
1776                 .pm = &mtk_hdmi_pm_ops,
1777         },
1778 };
1779
1780 static struct platform_driver * const mtk_hdmi_drivers[] = {
1781         &mtk_hdmi_phy_driver,
1782         &mtk_hdmi_ddc_driver,
1783         &mtk_cec_driver,
1784         &mtk_hdmi_driver,
1785 };
1786
1787 static int __init mtk_hdmitx_init(void)
1788 {
1789         return platform_register_drivers(mtk_hdmi_drivers,
1790                                          ARRAY_SIZE(mtk_hdmi_drivers));
1791 }
1792
1793 static void __exit mtk_hdmitx_exit(void)
1794 {
1795         platform_unregister_drivers(mtk_hdmi_drivers,
1796                                     ARRAY_SIZE(mtk_hdmi_drivers));
1797 }
1798
1799 module_init(mtk_hdmitx_init);
1800 module_exit(mtk_hdmitx_exit);
1801
1802 MODULE_AUTHOR("Jie Qiu <jie.qiu@mediatek.com>");
1803 MODULE_DESCRIPTION("MediaTek HDMI Driver");
1804 MODULE_LICENSE("GPL v2");