1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014 MediaTek Inc.
4 * Author: Jie Qiu <jie.qiu@mediatek.com>
7 #include <linux/arm-smccc.h>
9 #include <linux/delay.h>
10 #include <linux/hdmi.h>
11 #include <linux/i2c.h>
13 #include <linux/kernel.h>
14 #include <linux/mfd/syscon.h>
15 #include <linux/module.h>
16 #include <linux/mutex.h>
17 #include <linux/of_platform.h>
19 #include <linux/of_gpio.h>
20 #include <linux/of_graph.h>
21 #include <linux/phy/phy.h>
22 #include <linux/platform_device.h>
23 #include <linux/regmap.h>
25 #include <sound/hdmi-codec.h>
27 #include <drm/drm_atomic_helper.h>
28 #include <drm/drm_bridge.h>
29 #include <drm/drm_crtc.h>
30 #include <drm/drm_edid.h>
31 #include <drm/drm_print.h>
32 #include <drm/drm_probe_helper.h>
36 #include "mtk_hdmi_regs.h"
40 enum mtk_hdmi_clk_id {
41 MTK_HDMI_CLK_HDMI_PIXEL,
42 MTK_HDMI_CLK_HDMI_PLL,
43 MTK_HDMI_CLK_AUD_BCLK,
44 MTK_HDMI_CLK_AUD_SPDIF,
48 enum hdmi_aud_input_type {
49 HDMI_AUD_INPUT_I2S = 0,
53 enum hdmi_aud_i2s_fmt {
54 HDMI_I2S_MODE_RJT_24BIT = 0,
55 HDMI_I2S_MODE_RJT_16BIT,
56 HDMI_I2S_MODE_LJT_24BIT,
57 HDMI_I2S_MODE_LJT_16BIT,
58 HDMI_I2S_MODE_I2S_24BIT,
59 HDMI_I2S_MODE_I2S_16BIT
72 enum hdmi_aud_channel_type {
73 HDMI_AUD_CHAN_TYPE_1_0 = 0,
74 HDMI_AUD_CHAN_TYPE_1_1,
75 HDMI_AUD_CHAN_TYPE_2_0,
76 HDMI_AUD_CHAN_TYPE_2_1,
77 HDMI_AUD_CHAN_TYPE_3_0,
78 HDMI_AUD_CHAN_TYPE_3_1,
79 HDMI_AUD_CHAN_TYPE_4_0,
80 HDMI_AUD_CHAN_TYPE_4_1,
81 HDMI_AUD_CHAN_TYPE_5_0,
82 HDMI_AUD_CHAN_TYPE_5_1,
83 HDMI_AUD_CHAN_TYPE_6_0,
84 HDMI_AUD_CHAN_TYPE_6_1,
85 HDMI_AUD_CHAN_TYPE_7_0,
86 HDMI_AUD_CHAN_TYPE_7_1,
87 HDMI_AUD_CHAN_TYPE_3_0_LRS,
88 HDMI_AUD_CHAN_TYPE_3_1_LRS,
89 HDMI_AUD_CHAN_TYPE_4_0_CLRS,
90 HDMI_AUD_CHAN_TYPE_4_1_CLRS,
91 HDMI_AUD_CHAN_TYPE_6_1_CS,
92 HDMI_AUD_CHAN_TYPE_6_1_CH,
93 HDMI_AUD_CHAN_TYPE_6_1_OH,
94 HDMI_AUD_CHAN_TYPE_6_1_CHR,
95 HDMI_AUD_CHAN_TYPE_7_1_LH_RH,
96 HDMI_AUD_CHAN_TYPE_7_1_LSR_RSR,
97 HDMI_AUD_CHAN_TYPE_7_1_LC_RC,
98 HDMI_AUD_CHAN_TYPE_7_1_LW_RW,
99 HDMI_AUD_CHAN_TYPE_7_1_LSD_RSD,
100 HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS,
101 HDMI_AUD_CHAN_TYPE_7_1_LHS_RHS,
102 HDMI_AUD_CHAN_TYPE_7_1_CS_CH,
103 HDMI_AUD_CHAN_TYPE_7_1_CS_OH,
104 HDMI_AUD_CHAN_TYPE_7_1_CS_CHR,
105 HDMI_AUD_CHAN_TYPE_7_1_CH_OH,
106 HDMI_AUD_CHAN_TYPE_7_1_CH_CHR,
107 HDMI_AUD_CHAN_TYPE_7_1_OH_CHR,
108 HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS_LSR_RSR,
109 HDMI_AUD_CHAN_TYPE_6_0_CS,
110 HDMI_AUD_CHAN_TYPE_6_0_CH,
111 HDMI_AUD_CHAN_TYPE_6_0_OH,
112 HDMI_AUD_CHAN_TYPE_6_0_CHR,
113 HDMI_AUD_CHAN_TYPE_7_0_LH_RH,
114 HDMI_AUD_CHAN_TYPE_7_0_LSR_RSR,
115 HDMI_AUD_CHAN_TYPE_7_0_LC_RC,
116 HDMI_AUD_CHAN_TYPE_7_0_LW_RW,
117 HDMI_AUD_CHAN_TYPE_7_0_LSD_RSD,
118 HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS,
119 HDMI_AUD_CHAN_TYPE_7_0_LHS_RHS,
120 HDMI_AUD_CHAN_TYPE_7_0_CS_CH,
121 HDMI_AUD_CHAN_TYPE_7_0_CS_OH,
122 HDMI_AUD_CHAN_TYPE_7_0_CS_CHR,
123 HDMI_AUD_CHAN_TYPE_7_0_CH_OH,
124 HDMI_AUD_CHAN_TYPE_7_0_CH_CHR,
125 HDMI_AUD_CHAN_TYPE_7_0_OH_CHR,
126 HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS_LSR_RSR,
127 HDMI_AUD_CHAN_TYPE_8_0_LH_RH_CS,
128 HDMI_AUD_CHAN_TYPE_UNKNOWN = 0xFF
131 enum hdmi_aud_channel_swap_type {
133 HDMI_AUD_SWAP_LFE_CC,
135 HDMI_AUD_SWAP_RLS_RRS,
136 HDMI_AUD_SWAP_LR_STATUS,
139 struct hdmi_audio_param {
140 enum hdmi_audio_coding_type aud_codec;
141 enum hdmi_audio_sample_size aud_sampe_size;
142 enum hdmi_aud_input_type aud_input_type;
143 enum hdmi_aud_i2s_fmt aud_i2s_fmt;
144 enum hdmi_aud_mclk aud_mclk;
145 enum hdmi_aud_channel_type aud_input_chan_type;
146 struct hdmi_codec_params codec_params;
149 struct mtk_hdmi_conf {
154 struct drm_bridge bridge;
155 struct drm_bridge *next_bridge;
156 struct drm_connector conn;
158 const struct mtk_hdmi_conf *conf;
160 struct device *cec_dev;
161 struct i2c_adapter *ddc_adpt;
162 struct clk *clk[MTK_HDMI_CLK_COUNT];
163 struct drm_display_mode mode;
171 struct regmap *sys_regmap;
172 unsigned int sys_offset;
174 enum hdmi_colorspace csp;
175 struct hdmi_audio_param aud_param;
179 hdmi_codec_plugged_cb plugged_cb;
180 struct device *codec_dev;
181 struct mutex update_plugged_status_lock;
184 static inline struct mtk_hdmi *hdmi_ctx_from_bridge(struct drm_bridge *b)
186 return container_of(b, struct mtk_hdmi, bridge);
189 static inline struct mtk_hdmi *hdmi_ctx_from_conn(struct drm_connector *c)
191 return container_of(c, struct mtk_hdmi, conn);
194 static u32 mtk_hdmi_read(struct mtk_hdmi *hdmi, u32 offset)
196 return readl(hdmi->regs + offset);
199 static void mtk_hdmi_write(struct mtk_hdmi *hdmi, u32 offset, u32 val)
201 writel(val, hdmi->regs + offset);
204 static void mtk_hdmi_clear_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits)
206 void __iomem *reg = hdmi->regs + offset;
214 static void mtk_hdmi_set_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits)
216 void __iomem *reg = hdmi->regs + offset;
224 static void mtk_hdmi_mask(struct mtk_hdmi *hdmi, u32 offset, u32 val, u32 mask)
226 void __iomem *reg = hdmi->regs + offset;
230 tmp = (tmp & ~mask) | (val & mask);
234 static void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi, bool black)
236 mtk_hdmi_mask(hdmi, VIDEO_CFG_4, black ? GEN_RGB : NORMAL_PATH,
240 static void mtk_hdmi_hw_make_reg_writable(struct mtk_hdmi *hdmi, bool enable)
242 struct arm_smccc_res res;
245 * MT8173 HDMI hardware has an output control bit to enable/disable HDMI
246 * output. This bit can only be controlled in ARM supervisor mode.
247 * The ARM trusted firmware provides an API for the HDMI driver to set
248 * this control bit to enable HDMI output in supervisor mode.
250 if (hdmi->conf && hdmi->conf->tz_disabled)
251 regmap_update_bits(hdmi->sys_regmap,
252 hdmi->sys_offset + HDMI_SYS_CFG20,
253 0x80008005, enable ? 0x80000005 : 0x8000);
255 arm_smccc_smc(MTK_SIP_SET_AUTHORIZED_SECURE_REG, 0x14000904,
256 0x80000000, 0, 0, 0, 0, 0, &res);
258 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
259 HDMI_PCLK_FREE_RUN, enable ? HDMI_PCLK_FREE_RUN : 0);
260 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
261 HDMI_ON | ANLG_ON, enable ? (HDMI_ON | ANLG_ON) : 0);
264 static void mtk_hdmi_hw_1p4_version_enable(struct mtk_hdmi *hdmi, bool enable)
266 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
267 HDMI2P0_EN, enable ? 0 : HDMI2P0_EN);
270 static void mtk_hdmi_hw_aud_mute(struct mtk_hdmi *hdmi)
272 mtk_hdmi_set_bits(hdmi, GRL_AUDIO_CFG, AUDIO_ZERO);
275 static void mtk_hdmi_hw_aud_unmute(struct mtk_hdmi *hdmi)
277 mtk_hdmi_clear_bits(hdmi, GRL_AUDIO_CFG, AUDIO_ZERO);
280 static void mtk_hdmi_hw_reset(struct mtk_hdmi *hdmi)
282 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
284 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
286 mtk_hdmi_clear_bits(hdmi, GRL_CFG3, CFG3_CONTROL_PACKET_DELAY);
287 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
291 static void mtk_hdmi_hw_enable_notice(struct mtk_hdmi *hdmi, bool enable_notice)
293 mtk_hdmi_mask(hdmi, GRL_CFG2, enable_notice ? CFG2_NOTICE_EN : 0,
297 static void mtk_hdmi_hw_write_int_mask(struct mtk_hdmi *hdmi, u32 int_mask)
299 mtk_hdmi_write(hdmi, GRL_INT_MASK, int_mask);
302 static void mtk_hdmi_hw_enable_dvi_mode(struct mtk_hdmi *hdmi, bool enable)
304 mtk_hdmi_mask(hdmi, GRL_CFG1, enable ? CFG1_DVI : 0, CFG1_DVI);
307 static void mtk_hdmi_hw_send_info_frame(struct mtk_hdmi *hdmi, u8 *buffer,
310 u32 ctrl_reg = GRL_CTRL;
313 enum hdmi_infoframe_type frame_type;
317 int ctrl_frame_en = 0;
319 frame_type = *buffer++;
320 frame_ver = *buffer++;
321 frame_len = *buffer++;
322 checksum = *buffer++;
326 "frame_type:0x%x,frame_ver:0x%x,frame_len:0x%x,checksum:0x%x\n",
327 frame_type, frame_ver, frame_len, checksum);
329 switch (frame_type) {
330 case HDMI_INFOFRAME_TYPE_AVI:
331 ctrl_frame_en = CTRL_AVI_EN;
334 case HDMI_INFOFRAME_TYPE_SPD:
335 ctrl_frame_en = CTRL_SPD_EN;
338 case HDMI_INFOFRAME_TYPE_AUDIO:
339 ctrl_frame_en = CTRL_AUDIO_EN;
342 case HDMI_INFOFRAME_TYPE_VENDOR:
343 ctrl_frame_en = VS_EN;
344 ctrl_reg = GRL_ACP_ISRC_CTRL;
347 dev_err(hdmi->dev, "Unknown infoframe type %d\n", frame_type);
350 mtk_hdmi_clear_bits(hdmi, ctrl_reg, ctrl_frame_en);
351 mtk_hdmi_write(hdmi, GRL_INFOFRM_TYPE, frame_type);
352 mtk_hdmi_write(hdmi, GRL_INFOFRM_VER, frame_ver);
353 mtk_hdmi_write(hdmi, GRL_INFOFRM_LNG, frame_len);
355 mtk_hdmi_write(hdmi, GRL_IFM_PORT, checksum);
356 for (i = 0; i < frame_len; i++)
357 mtk_hdmi_write(hdmi, GRL_IFM_PORT, frame_data[i]);
359 mtk_hdmi_set_bits(hdmi, ctrl_reg, ctrl_frame_en);
362 static void mtk_hdmi_hw_send_aud_packet(struct mtk_hdmi *hdmi, bool enable)
364 mtk_hdmi_mask(hdmi, GRL_SHIFT_R2, enable ? 0 : AUDIO_PACKET_OFF,
368 static void mtk_hdmi_hw_config_sys(struct mtk_hdmi *hdmi)
370 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
371 HDMI_OUT_FIFO_EN | MHL_MODE_ON, 0);
372 usleep_range(2000, 4000);
373 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
374 HDMI_OUT_FIFO_EN | MHL_MODE_ON, HDMI_OUT_FIFO_EN);
377 static void mtk_hdmi_hw_set_deep_color_mode(struct mtk_hdmi *hdmi)
379 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
380 DEEP_COLOR_MODE_MASK | DEEP_COLOR_EN,
384 static void mtk_hdmi_hw_send_av_mute(struct mtk_hdmi *hdmi)
386 mtk_hdmi_clear_bits(hdmi, GRL_CFG4, CTRL_AVMUTE);
387 usleep_range(2000, 4000);
388 mtk_hdmi_set_bits(hdmi, GRL_CFG4, CTRL_AVMUTE);
391 static void mtk_hdmi_hw_send_av_unmute(struct mtk_hdmi *hdmi)
393 mtk_hdmi_mask(hdmi, GRL_CFG4, CFG4_AV_UNMUTE_EN,
394 CFG4_AV_UNMUTE_EN | CFG4_AV_UNMUTE_SET);
395 usleep_range(2000, 4000);
396 mtk_hdmi_mask(hdmi, GRL_CFG4, CFG4_AV_UNMUTE_SET,
397 CFG4_AV_UNMUTE_EN | CFG4_AV_UNMUTE_SET);
400 static void mtk_hdmi_hw_ncts_enable(struct mtk_hdmi *hdmi, bool on)
402 mtk_hdmi_mask(hdmi, GRL_CTS_CTRL, on ? 0 : CTS_CTRL_SOFT,
406 static void mtk_hdmi_hw_ncts_auto_write_enable(struct mtk_hdmi *hdmi,
409 mtk_hdmi_mask(hdmi, GRL_CTS_CTRL, enable ? NCTS_WRI_ANYTIME : 0,
413 static void mtk_hdmi_hw_msic_setting(struct mtk_hdmi *hdmi,
414 struct drm_display_mode *mode)
416 mtk_hdmi_clear_bits(hdmi, GRL_CFG4, CFG4_MHL_MODE);
418 if (mode->flags & DRM_MODE_FLAG_INTERLACE &&
419 mode->clock == 74250 &&
420 mode->vdisplay == 1080)
421 mtk_hdmi_clear_bits(hdmi, GRL_CFG2, CFG2_MHL_DE_SEL);
423 mtk_hdmi_set_bits(hdmi, GRL_CFG2, CFG2_MHL_DE_SEL);
426 static void mtk_hdmi_hw_aud_set_channel_swap(struct mtk_hdmi *hdmi,
427 enum hdmi_aud_channel_swap_type swap)
432 case HDMI_AUD_SWAP_LR:
435 case HDMI_AUD_SWAP_LFE_CC:
436 swap_bit = LFE_CC_SWAP;
438 case HDMI_AUD_SWAP_LSRS:
439 swap_bit = LSRS_SWAP;
441 case HDMI_AUD_SWAP_RLS_RRS:
442 swap_bit = RLS_RRS_SWAP;
444 case HDMI_AUD_SWAP_LR_STATUS:
445 swap_bit = LR_STATUS_SWAP;
448 swap_bit = LFE_CC_SWAP;
451 mtk_hdmi_mask(hdmi, GRL_CH_SWAP, swap_bit, 0xff);
454 static void mtk_hdmi_hw_aud_set_bit_num(struct mtk_hdmi *hdmi,
455 enum hdmi_audio_sample_size bit_num)
460 case HDMI_AUDIO_SAMPLE_SIZE_16:
463 case HDMI_AUDIO_SAMPLE_SIZE_20:
466 case HDMI_AUDIO_SAMPLE_SIZE_24:
467 case HDMI_AUDIO_SAMPLE_SIZE_STREAM:
472 mtk_hdmi_mask(hdmi, GRL_AOUT_CFG, val, AOUT_BNUM_SEL_MASK);
475 static void mtk_hdmi_hw_aud_set_i2s_fmt(struct mtk_hdmi *hdmi,
476 enum hdmi_aud_i2s_fmt i2s_fmt)
480 val = mtk_hdmi_read(hdmi, GRL_CFG0);
481 val &= ~(CFG0_W_LENGTH_MASK | CFG0_I2S_MODE_MASK);
484 case HDMI_I2S_MODE_RJT_24BIT:
485 val |= CFG0_I2S_MODE_RTJ | CFG0_W_LENGTH_24BIT;
487 case HDMI_I2S_MODE_RJT_16BIT:
488 val |= CFG0_I2S_MODE_RTJ | CFG0_W_LENGTH_16BIT;
490 case HDMI_I2S_MODE_LJT_24BIT:
492 val |= CFG0_I2S_MODE_LTJ | CFG0_W_LENGTH_24BIT;
494 case HDMI_I2S_MODE_LJT_16BIT:
495 val |= CFG0_I2S_MODE_LTJ | CFG0_W_LENGTH_16BIT;
497 case HDMI_I2S_MODE_I2S_24BIT:
498 val |= CFG0_I2S_MODE_I2S | CFG0_W_LENGTH_24BIT;
500 case HDMI_I2S_MODE_I2S_16BIT:
501 val |= CFG0_I2S_MODE_I2S | CFG0_W_LENGTH_16BIT;
504 mtk_hdmi_write(hdmi, GRL_CFG0, val);
507 static void mtk_hdmi_hw_audio_config(struct mtk_hdmi *hdmi, bool dst)
509 const u8 mask = HIGH_BIT_RATE | DST_NORMAL_DOUBLE | SACD_DST | DSD_SEL;
512 /* Disable high bitrate, set DST packet normal/double */
513 mtk_hdmi_clear_bits(hdmi, GRL_AOUT_CFG, HIGH_BIT_RATE_PACKET_ALIGN);
516 val = DST_NORMAL_DOUBLE | SACD_DST;
520 mtk_hdmi_mask(hdmi, GRL_AUDIO_CFG, val, mask);
523 static void mtk_hdmi_hw_aud_set_i2s_chan_num(struct mtk_hdmi *hdmi,
524 enum hdmi_aud_channel_type channel_type,
527 unsigned int ch_switch;
530 ch_switch = CH_SWITCH(7, 7) | CH_SWITCH(6, 6) |
531 CH_SWITCH(5, 5) | CH_SWITCH(4, 4) |
532 CH_SWITCH(3, 3) | CH_SWITCH(1, 2) |
533 CH_SWITCH(2, 1) | CH_SWITCH(0, 0);
535 if (channel_count == 2) {
536 i2s_uv = I2S_UV_CH_EN(0);
537 } else if (channel_count == 3 || channel_count == 4) {
538 if (channel_count == 4 &&
539 (channel_type == HDMI_AUD_CHAN_TYPE_3_0_LRS ||
540 channel_type == HDMI_AUD_CHAN_TYPE_4_0))
541 i2s_uv = I2S_UV_CH_EN(2) | I2S_UV_CH_EN(0);
543 i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2);
544 } else if (channel_count == 6 || channel_count == 5) {
545 if (channel_count == 6 &&
546 channel_type != HDMI_AUD_CHAN_TYPE_5_1 &&
547 channel_type != HDMI_AUD_CHAN_TYPE_4_1_CLRS) {
548 i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2) |
549 I2S_UV_CH_EN(1) | I2S_UV_CH_EN(0);
551 i2s_uv = I2S_UV_CH_EN(2) | I2S_UV_CH_EN(1) |
554 } else if (channel_count == 8 || channel_count == 7) {
555 i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2) |
556 I2S_UV_CH_EN(1) | I2S_UV_CH_EN(0);
558 i2s_uv = I2S_UV_CH_EN(0);
561 mtk_hdmi_write(hdmi, GRL_CH_SW0, ch_switch & 0xff);
562 mtk_hdmi_write(hdmi, GRL_CH_SW1, (ch_switch >> 8) & 0xff);
563 mtk_hdmi_write(hdmi, GRL_CH_SW2, (ch_switch >> 16) & 0xff);
564 mtk_hdmi_write(hdmi, GRL_I2S_UV, i2s_uv);
567 static void mtk_hdmi_hw_aud_set_input_type(struct mtk_hdmi *hdmi,
568 enum hdmi_aud_input_type input_type)
572 val = mtk_hdmi_read(hdmi, GRL_CFG1);
573 if (input_type == HDMI_AUD_INPUT_I2S &&
574 (val & CFG1_SPDIF) == CFG1_SPDIF) {
576 } else if (input_type == HDMI_AUD_INPUT_SPDIF &&
577 (val & CFG1_SPDIF) == 0) {
580 mtk_hdmi_write(hdmi, GRL_CFG1, val);
583 static void mtk_hdmi_hw_aud_set_channel_status(struct mtk_hdmi *hdmi,
588 for (i = 0; i < 5; i++) {
589 mtk_hdmi_write(hdmi, GRL_I2S_C_STA0 + i * 4, channel_status[i]);
590 mtk_hdmi_write(hdmi, GRL_L_STATUS_0 + i * 4, channel_status[i]);
591 mtk_hdmi_write(hdmi, GRL_R_STATUS_0 + i * 4, channel_status[i]);
593 for (; i < 24; i++) {
594 mtk_hdmi_write(hdmi, GRL_L_STATUS_0 + i * 4, 0);
595 mtk_hdmi_write(hdmi, GRL_R_STATUS_0 + i * 4, 0);
599 static void mtk_hdmi_hw_aud_src_reenable(struct mtk_hdmi *hdmi)
603 val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL);
604 if (val & MIX_CTRL_SRC_EN) {
605 val &= ~MIX_CTRL_SRC_EN;
606 mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val);
607 usleep_range(255, 512);
608 val |= MIX_CTRL_SRC_EN;
609 mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val);
613 static void mtk_hdmi_hw_aud_src_disable(struct mtk_hdmi *hdmi)
617 val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL);
618 val &= ~MIX_CTRL_SRC_EN;
619 mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val);
620 mtk_hdmi_write(hdmi, GRL_SHIFT_L1, 0x00);
623 static void mtk_hdmi_hw_aud_set_mclk(struct mtk_hdmi *hdmi,
624 enum hdmi_aud_mclk mclk)
628 val = mtk_hdmi_read(hdmi, GRL_CFG5);
629 val &= CFG5_CD_RATIO_MASK;
632 case HDMI_AUD_MCLK_128FS:
635 case HDMI_AUD_MCLK_256FS:
638 case HDMI_AUD_MCLK_384FS:
641 case HDMI_AUD_MCLK_512FS:
644 case HDMI_AUD_MCLK_768FS:
651 mtk_hdmi_write(hdmi, GRL_CFG5, val);
659 /* Recommended N values from HDMI specification, tables 7-1 to 7-3 */
660 static const struct hdmi_acr_n hdmi_rec_n_table[] = {
661 /* Clock, N: 32kHz 44.1kHz 48kHz */
662 { 25175, { 4576, 7007, 6864 } },
663 { 74176, { 11648, 17836, 11648 } },
664 { 148352, { 11648, 8918, 5824 } },
665 { 296703, { 5824, 4459, 5824 } },
666 { 297000, { 3072, 4704, 5120 } },
667 { 0, { 4096, 6272, 6144 } }, /* all other TMDS clocks */
671 * hdmi_recommended_n() - Return N value recommended by HDMI specification
672 * @freq: audio sample rate in Hz
673 * @clock: rounded TMDS clock in kHz
675 static unsigned int hdmi_recommended_n(unsigned int freq, unsigned int clock)
677 const struct hdmi_acr_n *recommended;
680 for (i = 0; i < ARRAY_SIZE(hdmi_rec_n_table) - 1; i++) {
681 if (clock == hdmi_rec_n_table[i].clock)
684 recommended = hdmi_rec_n_table + i;
688 return recommended->n[0];
690 return recommended->n[1];
692 return recommended->n[2];
694 return recommended->n[1] * 2;
696 return recommended->n[2] * 2;
698 return recommended->n[1] * 4;
700 return recommended->n[2] * 4;
702 return (128 * freq) / 1000;
706 static unsigned int hdmi_mode_clock_to_hz(unsigned int clock)
710 return 25174825; /* 25.2/1.001 MHz */
712 return 74175824; /* 74.25/1.001 MHz */
714 return 148351648; /* 148.5/1.001 MHz */
716 return 296703297; /* 297/1.001 MHz */
722 static unsigned int hdmi_expected_cts(unsigned int audio_sample_rate,
723 unsigned int tmds_clock, unsigned int n)
725 return DIV_ROUND_CLOSEST_ULL((u64)hdmi_mode_clock_to_hz(tmds_clock) * n,
726 128 * audio_sample_rate);
729 static void do_hdmi_hw_aud_set_ncts(struct mtk_hdmi *hdmi, unsigned int n,
732 unsigned char val[NCTS_BYTES];
735 mtk_hdmi_write(hdmi, GRL_NCTS, 0);
736 mtk_hdmi_write(hdmi, GRL_NCTS, 0);
737 mtk_hdmi_write(hdmi, GRL_NCTS, 0);
738 memset(val, 0, sizeof(val));
740 val[0] = (cts >> 24) & 0xff;
741 val[1] = (cts >> 16) & 0xff;
742 val[2] = (cts >> 8) & 0xff;
745 val[4] = (n >> 16) & 0xff;
746 val[5] = (n >> 8) & 0xff;
749 for (i = 0; i < NCTS_BYTES; i++)
750 mtk_hdmi_write(hdmi, GRL_NCTS, val[i]);
753 static void mtk_hdmi_hw_aud_set_ncts(struct mtk_hdmi *hdmi,
754 unsigned int sample_rate,
759 n = hdmi_recommended_n(sample_rate, clock);
760 cts = hdmi_expected_cts(sample_rate, clock, n);
762 dev_dbg(hdmi->dev, "%s: sample_rate=%u, clock=%d, cts=%u, n=%u\n",
763 __func__, sample_rate, clock, n, cts);
765 mtk_hdmi_mask(hdmi, DUMMY_304, AUDIO_I2S_NCTS_SEL_64,
767 do_hdmi_hw_aud_set_ncts(hdmi, n, cts);
770 static u8 mtk_hdmi_aud_get_chnl_count(enum hdmi_aud_channel_type channel_type)
772 switch (channel_type) {
773 case HDMI_AUD_CHAN_TYPE_1_0:
774 case HDMI_AUD_CHAN_TYPE_1_1:
775 case HDMI_AUD_CHAN_TYPE_2_0:
777 case HDMI_AUD_CHAN_TYPE_2_1:
778 case HDMI_AUD_CHAN_TYPE_3_0:
780 case HDMI_AUD_CHAN_TYPE_3_1:
781 case HDMI_AUD_CHAN_TYPE_4_0:
782 case HDMI_AUD_CHAN_TYPE_3_0_LRS:
784 case HDMI_AUD_CHAN_TYPE_4_1:
785 case HDMI_AUD_CHAN_TYPE_5_0:
786 case HDMI_AUD_CHAN_TYPE_3_1_LRS:
787 case HDMI_AUD_CHAN_TYPE_4_0_CLRS:
789 case HDMI_AUD_CHAN_TYPE_5_1:
790 case HDMI_AUD_CHAN_TYPE_6_0:
791 case HDMI_AUD_CHAN_TYPE_4_1_CLRS:
792 case HDMI_AUD_CHAN_TYPE_6_0_CS:
793 case HDMI_AUD_CHAN_TYPE_6_0_CH:
794 case HDMI_AUD_CHAN_TYPE_6_0_OH:
795 case HDMI_AUD_CHAN_TYPE_6_0_CHR:
797 case HDMI_AUD_CHAN_TYPE_6_1:
798 case HDMI_AUD_CHAN_TYPE_6_1_CS:
799 case HDMI_AUD_CHAN_TYPE_6_1_CH:
800 case HDMI_AUD_CHAN_TYPE_6_1_OH:
801 case HDMI_AUD_CHAN_TYPE_6_1_CHR:
802 case HDMI_AUD_CHAN_TYPE_7_0:
803 case HDMI_AUD_CHAN_TYPE_7_0_LH_RH:
804 case HDMI_AUD_CHAN_TYPE_7_0_LSR_RSR:
805 case HDMI_AUD_CHAN_TYPE_7_0_LC_RC:
806 case HDMI_AUD_CHAN_TYPE_7_0_LW_RW:
807 case HDMI_AUD_CHAN_TYPE_7_0_LSD_RSD:
808 case HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS:
809 case HDMI_AUD_CHAN_TYPE_7_0_LHS_RHS:
810 case HDMI_AUD_CHAN_TYPE_7_0_CS_CH:
811 case HDMI_AUD_CHAN_TYPE_7_0_CS_OH:
812 case HDMI_AUD_CHAN_TYPE_7_0_CS_CHR:
813 case HDMI_AUD_CHAN_TYPE_7_0_CH_OH:
814 case HDMI_AUD_CHAN_TYPE_7_0_CH_CHR:
815 case HDMI_AUD_CHAN_TYPE_7_0_OH_CHR:
816 case HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS_LSR_RSR:
817 case HDMI_AUD_CHAN_TYPE_8_0_LH_RH_CS:
819 case HDMI_AUD_CHAN_TYPE_7_1:
820 case HDMI_AUD_CHAN_TYPE_7_1_LH_RH:
821 case HDMI_AUD_CHAN_TYPE_7_1_LSR_RSR:
822 case HDMI_AUD_CHAN_TYPE_7_1_LC_RC:
823 case HDMI_AUD_CHAN_TYPE_7_1_LW_RW:
824 case HDMI_AUD_CHAN_TYPE_7_1_LSD_RSD:
825 case HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS:
826 case HDMI_AUD_CHAN_TYPE_7_1_LHS_RHS:
827 case HDMI_AUD_CHAN_TYPE_7_1_CS_CH:
828 case HDMI_AUD_CHAN_TYPE_7_1_CS_OH:
829 case HDMI_AUD_CHAN_TYPE_7_1_CS_CHR:
830 case HDMI_AUD_CHAN_TYPE_7_1_CH_OH:
831 case HDMI_AUD_CHAN_TYPE_7_1_CH_CHR:
832 case HDMI_AUD_CHAN_TYPE_7_1_OH_CHR:
833 case HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS_LSR_RSR:
840 static int mtk_hdmi_video_change_vpll(struct mtk_hdmi *hdmi, u32 clock)
845 /* The DPI driver already should have set TVDPLL to the correct rate */
846 ret = clk_set_rate(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL], clock);
848 dev_err(hdmi->dev, "Failed to set PLL to %u Hz: %d\n", clock,
853 rate = clk_get_rate(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]);
855 if (DIV_ROUND_CLOSEST(rate, 1000) != DIV_ROUND_CLOSEST(clock, 1000))
856 dev_warn(hdmi->dev, "Want PLL %u Hz, got %lu Hz\n", clock,
859 dev_dbg(hdmi->dev, "Want PLL %u Hz, got %lu Hz\n", clock, rate);
861 mtk_hdmi_hw_config_sys(hdmi);
862 mtk_hdmi_hw_set_deep_color_mode(hdmi);
866 static void mtk_hdmi_video_set_display_mode(struct mtk_hdmi *hdmi,
867 struct drm_display_mode *mode)
869 mtk_hdmi_hw_reset(hdmi);
870 mtk_hdmi_hw_enable_notice(hdmi, true);
871 mtk_hdmi_hw_write_int_mask(hdmi, 0xff);
872 mtk_hdmi_hw_enable_dvi_mode(hdmi, hdmi->dvi_mode);
873 mtk_hdmi_hw_ncts_auto_write_enable(hdmi, true);
875 mtk_hdmi_hw_msic_setting(hdmi, mode);
879 static void mtk_hdmi_aud_set_input(struct mtk_hdmi *hdmi)
881 enum hdmi_aud_channel_type chan_type;
885 mtk_hdmi_hw_aud_set_channel_swap(hdmi, HDMI_AUD_SWAP_LFE_CC);
886 mtk_hdmi_set_bits(hdmi, GRL_MIX_CTRL, MIX_CTRL_FLAT);
888 if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF &&
889 hdmi->aud_param.aud_codec == HDMI_AUDIO_CODING_TYPE_DST) {
890 mtk_hdmi_hw_aud_set_bit_num(hdmi, HDMI_AUDIO_SAMPLE_SIZE_24);
891 } else if (hdmi->aud_param.aud_i2s_fmt == HDMI_I2S_MODE_LJT_24BIT) {
892 hdmi->aud_param.aud_i2s_fmt = HDMI_I2S_MODE_LJT_16BIT;
895 mtk_hdmi_hw_aud_set_i2s_fmt(hdmi, hdmi->aud_param.aud_i2s_fmt);
896 mtk_hdmi_hw_aud_set_bit_num(hdmi, HDMI_AUDIO_SAMPLE_SIZE_24);
898 dst = ((hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF) &&
899 (hdmi->aud_param.aud_codec == HDMI_AUDIO_CODING_TYPE_DST));
900 mtk_hdmi_hw_audio_config(hdmi, dst);
902 if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF)
903 chan_type = HDMI_AUD_CHAN_TYPE_2_0;
905 chan_type = hdmi->aud_param.aud_input_chan_type;
906 chan_count = mtk_hdmi_aud_get_chnl_count(chan_type);
907 mtk_hdmi_hw_aud_set_i2s_chan_num(hdmi, chan_type, chan_count);
908 mtk_hdmi_hw_aud_set_input_type(hdmi, hdmi->aud_param.aud_input_type);
911 static int mtk_hdmi_aud_set_src(struct mtk_hdmi *hdmi,
912 struct drm_display_mode *display_mode)
914 unsigned int sample_rate = hdmi->aud_param.codec_params.sample_rate;
916 mtk_hdmi_hw_ncts_enable(hdmi, false);
917 mtk_hdmi_hw_aud_src_disable(hdmi);
918 mtk_hdmi_clear_bits(hdmi, GRL_CFG2, CFG2_ACLK_INV);
920 if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_I2S) {
921 switch (sample_rate) {
931 mtk_hdmi_hw_aud_set_mclk(hdmi, hdmi->aud_param.aud_mclk);
933 switch (sample_rate) {
941 mtk_hdmi_hw_aud_set_mclk(hdmi, HDMI_AUD_MCLK_128FS);
944 mtk_hdmi_hw_aud_set_ncts(hdmi, sample_rate, display_mode->clock);
946 mtk_hdmi_hw_aud_src_reenable(hdmi);
950 static int mtk_hdmi_aud_output_config(struct mtk_hdmi *hdmi,
951 struct drm_display_mode *display_mode)
953 mtk_hdmi_hw_aud_mute(hdmi);
954 mtk_hdmi_hw_send_aud_packet(hdmi, false);
956 mtk_hdmi_aud_set_input(hdmi);
957 mtk_hdmi_aud_set_src(hdmi, display_mode);
958 mtk_hdmi_hw_aud_set_channel_status(hdmi,
959 hdmi->aud_param.codec_params.iec.status);
961 usleep_range(50, 100);
963 mtk_hdmi_hw_ncts_enable(hdmi, true);
964 mtk_hdmi_hw_send_aud_packet(hdmi, true);
965 mtk_hdmi_hw_aud_unmute(hdmi);
969 static int mtk_hdmi_setup_avi_infoframe(struct mtk_hdmi *hdmi,
970 struct drm_display_mode *mode)
972 struct hdmi_avi_infoframe frame;
973 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
976 err = drm_hdmi_avi_infoframe_from_display_mode(&frame,
980 "Failed to get AVI infoframe from mode: %zd\n", err);
984 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
986 dev_err(hdmi->dev, "Failed to pack AVI infoframe: %zd\n", err);
990 mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer));
994 static int mtk_hdmi_setup_spd_infoframe(struct mtk_hdmi *hdmi,
998 struct hdmi_spd_infoframe frame;
999 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_SPD_INFOFRAME_SIZE];
1002 err = hdmi_spd_infoframe_init(&frame, vendor, product);
1004 dev_err(hdmi->dev, "Failed to initialize SPD infoframe: %zd\n",
1009 err = hdmi_spd_infoframe_pack(&frame, buffer, sizeof(buffer));
1011 dev_err(hdmi->dev, "Failed to pack SDP infoframe: %zd\n", err);
1015 mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer));
1019 static int mtk_hdmi_setup_audio_infoframe(struct mtk_hdmi *hdmi)
1021 struct hdmi_audio_infoframe frame;
1022 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AUDIO_INFOFRAME_SIZE];
1025 err = hdmi_audio_infoframe_init(&frame);
1027 dev_err(hdmi->dev, "Failed to setup audio infoframe: %zd\n",
1032 frame.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM;
1033 frame.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM;
1034 frame.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM;
1035 frame.channels = mtk_hdmi_aud_get_chnl_count(
1036 hdmi->aud_param.aud_input_chan_type);
1038 err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
1040 dev_err(hdmi->dev, "Failed to pack audio infoframe: %zd\n",
1045 mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer));
1049 static int mtk_hdmi_setup_vendor_specific_infoframe(struct mtk_hdmi *hdmi,
1050 struct drm_display_mode *mode)
1052 struct hdmi_vendor_infoframe frame;
1056 err = drm_hdmi_vendor_infoframe_from_display_mode(&frame,
1060 "Failed to get vendor infoframe from mode: %zd\n", err);
1064 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
1066 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n",
1071 mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer));
1075 static int mtk_hdmi_output_init(struct mtk_hdmi *hdmi)
1077 struct hdmi_audio_param *aud_param = &hdmi->aud_param;
1079 hdmi->csp = HDMI_COLORSPACE_RGB;
1080 aud_param->aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
1081 aud_param->aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16;
1082 aud_param->aud_input_type = HDMI_AUD_INPUT_I2S;
1083 aud_param->aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT;
1084 aud_param->aud_mclk = HDMI_AUD_MCLK_128FS;
1085 aud_param->aud_input_chan_type = HDMI_AUD_CHAN_TYPE_2_0;
1090 static void mtk_hdmi_audio_enable(struct mtk_hdmi *hdmi)
1092 mtk_hdmi_hw_send_aud_packet(hdmi, true);
1093 hdmi->audio_enable = true;
1096 static void mtk_hdmi_audio_disable(struct mtk_hdmi *hdmi)
1098 mtk_hdmi_hw_send_aud_packet(hdmi, false);
1099 hdmi->audio_enable = false;
1102 static int mtk_hdmi_audio_set_param(struct mtk_hdmi *hdmi,
1103 struct hdmi_audio_param *param)
1105 if (!hdmi->audio_enable) {
1106 dev_err(hdmi->dev, "hdmi audio is in disable state!\n");
1109 dev_dbg(hdmi->dev, "codec:%d, input:%d, channel:%d, fs:%d\n",
1110 param->aud_codec, param->aud_input_type,
1111 param->aud_input_chan_type, param->codec_params.sample_rate);
1112 memcpy(&hdmi->aud_param, param, sizeof(*param));
1113 return mtk_hdmi_aud_output_config(hdmi, &hdmi->mode);
1116 static int mtk_hdmi_output_set_display_mode(struct mtk_hdmi *hdmi,
1117 struct drm_display_mode *mode)
1121 mtk_hdmi_hw_vid_black(hdmi, true);
1122 mtk_hdmi_hw_aud_mute(hdmi);
1123 mtk_hdmi_hw_send_av_mute(hdmi);
1124 phy_power_off(hdmi->phy);
1126 ret = mtk_hdmi_video_change_vpll(hdmi,
1127 mode->clock * 1000);
1129 dev_err(hdmi->dev, "Failed to set vpll: %d\n", ret);
1132 mtk_hdmi_video_set_display_mode(hdmi, mode);
1134 phy_power_on(hdmi->phy);
1135 mtk_hdmi_aud_output_config(hdmi, mode);
1137 mtk_hdmi_hw_vid_black(hdmi, false);
1138 mtk_hdmi_hw_aud_unmute(hdmi);
1139 mtk_hdmi_hw_send_av_unmute(hdmi);
1144 static const char * const mtk_hdmi_clk_names[MTK_HDMI_CLK_COUNT] = {
1145 [MTK_HDMI_CLK_HDMI_PIXEL] = "pixel",
1146 [MTK_HDMI_CLK_HDMI_PLL] = "pll",
1147 [MTK_HDMI_CLK_AUD_BCLK] = "bclk",
1148 [MTK_HDMI_CLK_AUD_SPDIF] = "spdif",
1151 static int mtk_hdmi_get_all_clk(struct mtk_hdmi *hdmi,
1152 struct device_node *np)
1156 for (i = 0; i < ARRAY_SIZE(mtk_hdmi_clk_names); i++) {
1157 hdmi->clk[i] = of_clk_get_by_name(np,
1158 mtk_hdmi_clk_names[i]);
1159 if (IS_ERR(hdmi->clk[i]))
1160 return PTR_ERR(hdmi->clk[i]);
1165 static int mtk_hdmi_clk_enable_audio(struct mtk_hdmi *hdmi)
1169 ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]);
1173 ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_AUD_SPDIF]);
1179 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]);
1183 static void mtk_hdmi_clk_disable_audio(struct mtk_hdmi *hdmi)
1185 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]);
1186 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_SPDIF]);
1189 static enum drm_connector_status
1190 mtk_hdmi_update_plugged_status(struct mtk_hdmi *hdmi)
1194 mutex_lock(&hdmi->update_plugged_status_lock);
1195 connected = mtk_cec_hpd_high(hdmi->cec_dev);
1196 if (hdmi->plugged_cb && hdmi->codec_dev)
1197 hdmi->plugged_cb(hdmi->codec_dev, connected);
1198 mutex_unlock(&hdmi->update_plugged_status_lock);
1201 connector_status_connected : connector_status_disconnected;
1204 static enum drm_connector_status hdmi_conn_detect(struct drm_connector *conn,
1207 struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn);
1208 return mtk_hdmi_update_plugged_status(hdmi);
1211 static void hdmi_conn_destroy(struct drm_connector *conn)
1213 struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn);
1215 mtk_cec_set_hpd_event(hdmi->cec_dev, NULL, NULL);
1217 drm_connector_cleanup(conn);
1220 static int mtk_hdmi_conn_get_modes(struct drm_connector *conn)
1222 struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn);
1226 if (!hdmi->ddc_adpt)
1229 edid = drm_get_edid(conn, hdmi->ddc_adpt);
1233 hdmi->dvi_mode = !drm_detect_monitor_audio(edid);
1235 drm_connector_update_edid_property(conn, edid);
1237 ret = drm_add_edid_modes(conn, edid);
1242 static int mtk_hdmi_conn_mode_valid(struct drm_connector *conn,
1243 struct drm_display_mode *mode)
1245 struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn);
1246 struct drm_bridge *next_bridge;
1248 dev_dbg(hdmi->dev, "xres=%d, yres=%d, refresh=%d, intl=%d clock=%d\n",
1249 mode->hdisplay, mode->vdisplay, drm_mode_vrefresh(mode),
1250 !!(mode->flags & DRM_MODE_FLAG_INTERLACE), mode->clock * 1000);
1252 next_bridge = drm_bridge_get_next_bridge(&hdmi->bridge);
1254 struct drm_display_mode adjusted_mode;
1256 drm_mode_copy(&adjusted_mode, mode);
1257 if (!drm_bridge_chain_mode_fixup(next_bridge, mode,
1262 if (mode->clock < 27000)
1263 return MODE_CLOCK_LOW;
1264 if (mode->clock > 297000)
1265 return MODE_CLOCK_HIGH;
1267 return drm_mode_validate_size(mode, 0x1fff, 0x1fff);
1270 static struct drm_encoder *mtk_hdmi_conn_best_enc(struct drm_connector *conn)
1272 struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn);
1274 return hdmi->bridge.encoder;
1277 static const struct drm_connector_funcs mtk_hdmi_connector_funcs = {
1278 .detect = hdmi_conn_detect,
1279 .fill_modes = drm_helper_probe_single_connector_modes,
1280 .destroy = hdmi_conn_destroy,
1281 .reset = drm_atomic_helper_connector_reset,
1282 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1283 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1286 static const struct drm_connector_helper_funcs
1287 mtk_hdmi_connector_helper_funcs = {
1288 .get_modes = mtk_hdmi_conn_get_modes,
1289 .mode_valid = mtk_hdmi_conn_mode_valid,
1290 .best_encoder = mtk_hdmi_conn_best_enc,
1293 static void mtk_hdmi_hpd_event(bool hpd, struct device *dev)
1295 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1297 if (hdmi && hdmi->bridge.encoder && hdmi->bridge.encoder->dev)
1298 drm_helper_hpd_irq_event(hdmi->bridge.encoder->dev);
1305 static int mtk_hdmi_bridge_attach(struct drm_bridge *bridge,
1306 enum drm_bridge_attach_flags flags)
1308 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1311 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) {
1312 DRM_ERROR("Fix bridge driver to make connector optional!");
1316 ret = drm_connector_init_with_ddc(bridge->encoder->dev, &hdmi->conn,
1317 &mtk_hdmi_connector_funcs,
1318 DRM_MODE_CONNECTOR_HDMIA,
1321 dev_err(hdmi->dev, "Failed to initialize connector: %d\n", ret);
1324 drm_connector_helper_add(&hdmi->conn, &mtk_hdmi_connector_helper_funcs);
1326 hdmi->conn.polled = DRM_CONNECTOR_POLL_HPD;
1327 hdmi->conn.interlace_allowed = true;
1328 hdmi->conn.doublescan_allowed = false;
1330 ret = drm_connector_attach_encoder(&hdmi->conn,
1334 "Failed to attach connector to encoder: %d\n", ret);
1338 if (hdmi->next_bridge) {
1339 ret = drm_bridge_attach(bridge->encoder, hdmi->next_bridge,
1343 "Failed to attach external bridge: %d\n", ret);
1348 mtk_cec_set_hpd_event(hdmi->cec_dev, mtk_hdmi_hpd_event, hdmi->dev);
1353 static bool mtk_hdmi_bridge_mode_fixup(struct drm_bridge *bridge,
1354 const struct drm_display_mode *mode,
1355 struct drm_display_mode *adjusted_mode)
1360 static void mtk_hdmi_bridge_disable(struct drm_bridge *bridge)
1362 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1367 phy_power_off(hdmi->phy);
1368 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_HDMI_PIXEL]);
1369 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]);
1371 hdmi->enabled = false;
1374 static void mtk_hdmi_bridge_post_disable(struct drm_bridge *bridge)
1376 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1381 mtk_hdmi_hw_1p4_version_enable(hdmi, true);
1382 mtk_hdmi_hw_make_reg_writable(hdmi, false);
1384 hdmi->powered = false;
1387 static void mtk_hdmi_bridge_mode_set(struct drm_bridge *bridge,
1388 const struct drm_display_mode *mode,
1389 const struct drm_display_mode *adjusted_mode)
1391 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1393 dev_dbg(hdmi->dev, "cur info: name:%s, hdisplay:%d\n",
1394 adjusted_mode->name, adjusted_mode->hdisplay);
1395 dev_dbg(hdmi->dev, "hsync_start:%d,hsync_end:%d, htotal:%d",
1396 adjusted_mode->hsync_start, adjusted_mode->hsync_end,
1397 adjusted_mode->htotal);
1398 dev_dbg(hdmi->dev, "hskew:%d, vdisplay:%d\n",
1399 adjusted_mode->hskew, adjusted_mode->vdisplay);
1400 dev_dbg(hdmi->dev, "vsync_start:%d, vsync_end:%d, vtotal:%d",
1401 adjusted_mode->vsync_start, adjusted_mode->vsync_end,
1402 adjusted_mode->vtotal);
1403 dev_dbg(hdmi->dev, "vscan:%d, flag:%d\n",
1404 adjusted_mode->vscan, adjusted_mode->flags);
1406 drm_mode_copy(&hdmi->mode, adjusted_mode);
1409 static void mtk_hdmi_bridge_pre_enable(struct drm_bridge *bridge)
1411 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1413 mtk_hdmi_hw_make_reg_writable(hdmi, true);
1414 mtk_hdmi_hw_1p4_version_enable(hdmi, true);
1416 hdmi->powered = true;
1419 static void mtk_hdmi_send_infoframe(struct mtk_hdmi *hdmi,
1420 struct drm_display_mode *mode)
1422 mtk_hdmi_setup_audio_infoframe(hdmi);
1423 mtk_hdmi_setup_avi_infoframe(hdmi, mode);
1424 mtk_hdmi_setup_spd_infoframe(hdmi, "mediatek", "On-chip HDMI");
1425 if (mode->flags & DRM_MODE_FLAG_3D_MASK)
1426 mtk_hdmi_setup_vendor_specific_infoframe(hdmi, mode);
1429 static void mtk_hdmi_bridge_enable(struct drm_bridge *bridge)
1431 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1433 mtk_hdmi_output_set_display_mode(hdmi, &hdmi->mode);
1434 clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]);
1435 clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PIXEL]);
1436 phy_power_on(hdmi->phy);
1437 mtk_hdmi_send_infoframe(hdmi, &hdmi->mode);
1439 hdmi->enabled = true;
1442 static const struct drm_bridge_funcs mtk_hdmi_bridge_funcs = {
1443 .attach = mtk_hdmi_bridge_attach,
1444 .mode_fixup = mtk_hdmi_bridge_mode_fixup,
1445 .disable = mtk_hdmi_bridge_disable,
1446 .post_disable = mtk_hdmi_bridge_post_disable,
1447 .mode_set = mtk_hdmi_bridge_mode_set,
1448 .pre_enable = mtk_hdmi_bridge_pre_enable,
1449 .enable = mtk_hdmi_bridge_enable,
1452 static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
1453 struct platform_device *pdev)
1455 struct device *dev = &pdev->dev;
1456 struct device_node *np = dev->of_node;
1457 struct device_node *cec_np, *remote, *i2c_np;
1458 struct platform_device *cec_pdev;
1459 struct regmap *regmap;
1460 struct resource *mem;
1463 ret = mtk_hdmi_get_all_clk(hdmi, np);
1465 if (ret != -EPROBE_DEFER)
1466 dev_err(dev, "Failed to get clocks: %d\n", ret);
1471 /* The CEC module handles HDMI hotplug detection */
1472 cec_np = of_get_compatible_child(np->parent, "mediatek,mt8173-cec");
1474 dev_err(dev, "Failed to find CEC node\n");
1478 cec_pdev = of_find_device_by_node(cec_np);
1480 dev_err(hdmi->dev, "Waiting for CEC device %pOF\n",
1482 of_node_put(cec_np);
1483 return -EPROBE_DEFER;
1485 of_node_put(cec_np);
1486 hdmi->cec_dev = &cec_pdev->dev;
1489 * The mediatek,syscon-hdmi property contains a phandle link to the
1490 * MMSYS_CONFIG device and the register offset of the HDMI_SYS_CFG
1491 * registers it contains.
1493 regmap = syscon_regmap_lookup_by_phandle(np, "mediatek,syscon-hdmi");
1494 ret = of_property_read_u32_index(np, "mediatek,syscon-hdmi", 1,
1497 ret = PTR_ERR(regmap);
1500 "Failed to get system configuration registers: %d\n",
1504 hdmi->sys_regmap = regmap;
1506 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1507 hdmi->regs = devm_ioremap_resource(dev, mem);
1508 if (IS_ERR(hdmi->regs)) {
1509 ret = PTR_ERR(hdmi->regs);
1513 remote = of_graph_get_remote_node(np, 1, 0);
1519 if (!of_device_is_compatible(remote, "hdmi-connector")) {
1520 hdmi->next_bridge = of_drm_find_bridge(remote);
1521 if (!hdmi->next_bridge) {
1522 dev_err(dev, "Waiting for external bridge\n");
1523 of_node_put(remote);
1524 ret = -EPROBE_DEFER;
1529 i2c_np = of_parse_phandle(remote, "ddc-i2c-bus", 0);
1531 dev_err(dev, "Failed to find ddc-i2c-bus node in %pOF\n",
1533 of_node_put(remote);
1537 of_node_put(remote);
1539 hdmi->ddc_adpt = of_find_i2c_adapter_by_node(i2c_np);
1540 of_node_put(i2c_np);
1541 if (!hdmi->ddc_adpt) {
1542 dev_err(dev, "Failed to get ddc i2c adapter by node\n");
1549 put_device(hdmi->cec_dev);
1554 * HDMI audio codec callbacks
1557 static int mtk_hdmi_audio_hw_params(struct device *dev, void *data,
1558 struct hdmi_codec_daifmt *daifmt,
1559 struct hdmi_codec_params *params)
1561 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1562 struct hdmi_audio_param hdmi_params;
1563 unsigned int chan = params->cea.channels;
1565 dev_dbg(hdmi->dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
1566 params->sample_rate, params->sample_width, chan);
1568 if (!hdmi->bridge.encoder)
1573 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_2_0;
1576 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_4_0;
1579 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_5_1;
1582 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_7_1;
1585 dev_err(hdmi->dev, "channel[%d] not supported!\n", chan);
1589 switch (params->sample_rate) {
1599 dev_err(hdmi->dev, "rate[%d] not supported!\n",
1600 params->sample_rate);
1604 switch (daifmt->fmt) {
1606 hdmi_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
1607 hdmi_params.aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16;
1608 hdmi_params.aud_input_type = HDMI_AUD_INPUT_I2S;
1609 hdmi_params.aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT;
1610 hdmi_params.aud_mclk = HDMI_AUD_MCLK_128FS;
1613 hdmi_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
1614 hdmi_params.aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16;
1615 hdmi_params.aud_input_type = HDMI_AUD_INPUT_SPDIF;
1618 dev_err(hdmi->dev, "%s: Invalid DAI format %d\n", __func__,
1623 memcpy(&hdmi_params.codec_params, params,
1624 sizeof(hdmi_params.codec_params));
1626 mtk_hdmi_audio_set_param(hdmi, &hdmi_params);
1631 static int mtk_hdmi_audio_startup(struct device *dev, void *data)
1633 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1635 mtk_hdmi_audio_enable(hdmi);
1640 static void mtk_hdmi_audio_shutdown(struct device *dev, void *data)
1642 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1644 mtk_hdmi_audio_disable(hdmi);
1648 mtk_hdmi_audio_mute(struct device *dev, void *data,
1649 bool enable, int direction)
1651 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1654 mtk_hdmi_hw_aud_mute(hdmi);
1656 mtk_hdmi_hw_aud_unmute(hdmi);
1661 static int mtk_hdmi_audio_get_eld(struct device *dev, void *data, uint8_t *buf, size_t len)
1663 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1665 memcpy(buf, hdmi->conn.eld, min(sizeof(hdmi->conn.eld), len));
1670 static int mtk_hdmi_audio_hook_plugged_cb(struct device *dev, void *data,
1671 hdmi_codec_plugged_cb fn,
1672 struct device *codec_dev)
1674 struct mtk_hdmi *hdmi = data;
1676 mutex_lock(&hdmi->update_plugged_status_lock);
1677 hdmi->plugged_cb = fn;
1678 hdmi->codec_dev = codec_dev;
1679 mutex_unlock(&hdmi->update_plugged_status_lock);
1681 mtk_hdmi_update_plugged_status(hdmi);
1686 static const struct hdmi_codec_ops mtk_hdmi_audio_codec_ops = {
1687 .hw_params = mtk_hdmi_audio_hw_params,
1688 .audio_startup = mtk_hdmi_audio_startup,
1689 .audio_shutdown = mtk_hdmi_audio_shutdown,
1690 .mute_stream = mtk_hdmi_audio_mute,
1691 .get_eld = mtk_hdmi_audio_get_eld,
1692 .hook_plugged_cb = mtk_hdmi_audio_hook_plugged_cb,
1693 .no_capture_mute = 1,
1696 static int mtk_hdmi_register_audio_driver(struct device *dev)
1698 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1699 struct hdmi_codec_pdata codec_data = {
1700 .ops = &mtk_hdmi_audio_codec_ops,
1701 .max_i2s_channels = 2,
1705 struct platform_device *pdev;
1707 pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
1708 PLATFORM_DEVID_AUTO, &codec_data,
1709 sizeof(codec_data));
1711 return PTR_ERR(pdev);
1713 DRM_INFO("%s driver bound to HDMI\n", HDMI_CODEC_DRV_NAME);
1717 static int mtk_drm_hdmi_probe(struct platform_device *pdev)
1719 struct mtk_hdmi *hdmi;
1720 struct device *dev = &pdev->dev;
1723 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
1728 hdmi->conf = of_device_get_match_data(dev);
1730 ret = mtk_hdmi_dt_parse_pdata(hdmi, pdev);
1734 hdmi->phy = devm_phy_get(dev, "hdmi");
1735 if (IS_ERR(hdmi->phy)) {
1736 ret = PTR_ERR(hdmi->phy);
1737 dev_err(dev, "Failed to get HDMI PHY: %d\n", ret);
1741 mutex_init(&hdmi->update_plugged_status_lock);
1742 platform_set_drvdata(pdev, hdmi);
1744 ret = mtk_hdmi_output_init(hdmi);
1746 dev_err(dev, "Failed to initialize hdmi output\n");
1750 ret = mtk_hdmi_register_audio_driver(dev);
1752 dev_err(dev, "Failed to register audio driver: %d\n", ret);
1756 hdmi->bridge.funcs = &mtk_hdmi_bridge_funcs;
1757 hdmi->bridge.of_node = pdev->dev.of_node;
1758 drm_bridge_add(&hdmi->bridge);
1760 ret = mtk_hdmi_clk_enable_audio(hdmi);
1762 dev_err(dev, "Failed to enable audio clocks: %d\n", ret);
1763 goto err_bridge_remove;
1769 drm_bridge_remove(&hdmi->bridge);
1773 static int mtk_drm_hdmi_remove(struct platform_device *pdev)
1775 struct mtk_hdmi *hdmi = platform_get_drvdata(pdev);
1777 drm_bridge_remove(&hdmi->bridge);
1778 mtk_hdmi_clk_disable_audio(hdmi);
1782 #ifdef CONFIG_PM_SLEEP
1783 static int mtk_hdmi_suspend(struct device *dev)
1785 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1787 mtk_hdmi_clk_disable_audio(hdmi);
1792 static int mtk_hdmi_resume(struct device *dev)
1794 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1797 ret = mtk_hdmi_clk_enable_audio(hdmi);
1799 dev_err(dev, "hdmi resume failed!\n");
1806 static SIMPLE_DEV_PM_OPS(mtk_hdmi_pm_ops,
1807 mtk_hdmi_suspend, mtk_hdmi_resume);
1809 static const struct mtk_hdmi_conf mtk_hdmi_conf_mt2701 = {
1810 .tz_disabled = true,
1813 static const struct of_device_id mtk_drm_hdmi_of_ids[] = {
1814 { .compatible = "mediatek,mt2701-hdmi",
1815 .data = &mtk_hdmi_conf_mt2701,
1817 { .compatible = "mediatek,mt8173-hdmi",
1822 static struct platform_driver mtk_hdmi_driver = {
1823 .probe = mtk_drm_hdmi_probe,
1824 .remove = mtk_drm_hdmi_remove,
1826 .name = "mediatek-drm-hdmi",
1827 .of_match_table = mtk_drm_hdmi_of_ids,
1828 .pm = &mtk_hdmi_pm_ops,
1832 static struct platform_driver * const mtk_hdmi_drivers[] = {
1833 &mtk_hdmi_ddc_driver,
1838 static int __init mtk_hdmitx_init(void)
1840 return platform_register_drivers(mtk_hdmi_drivers,
1841 ARRAY_SIZE(mtk_hdmi_drivers));
1844 static void __exit mtk_hdmitx_exit(void)
1846 platform_unregister_drivers(mtk_hdmi_drivers,
1847 ARRAY_SIZE(mtk_hdmi_drivers));
1850 module_init(mtk_hdmitx_init);
1851 module_exit(mtk_hdmitx_exit);
1853 MODULE_AUTHOR("Jie Qiu <jie.qiu@mediatek.com>");
1854 MODULE_DESCRIPTION("MediaTek HDMI Driver");
1855 MODULE_LICENSE("GPL v2");