drivers/gpu/drm/mediatek/mtk_hdmi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2014 MediaTek Inc.
   4  * Author: Jie Qiu <jie.qiu@mediatek.com>
   5  */
   6 #include <drm/drmP.h>
   7 #include <drm/drm_atomic_helper.h>
   8 #include <drm/drm_crtc.h>
   9 #include <drm/drm_probe_helper.h>
  10 #include <drm/drm_edid.h>
  11 #include <linux/arm-smccc.h>
  12 #include <linux/clk.h>
  13 #include <linux/delay.h>
  14 #include <linux/hdmi.h>
  15 #include <linux/i2c.h>
  16 #include <linux/io.h>
  17 #include <linux/kernel.h>
  18 #include <linux/mfd/syscon.h>
  19 #include <linux/of_platform.h>
  20 #include <linux/of.h>
  21 #include <linux/of_gpio.h>
  22 #include <linux/of_graph.h>
  23 #include <linux/phy/phy.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/regmap.h>
  26 #include <sound/hdmi-codec.h>
  27 #include "mtk_cec.h"
  28 #include "mtk_hdmi.h"
  29 #include "mtk_hdmi_regs.h"
  30
  31 #define NCTS_BYTES      7
  32
  33 enum mtk_hdmi_clk_id {
  34         MTK_HDMI_CLK_HDMI_PIXEL,
  35         MTK_HDMI_CLK_HDMI_PLL,
  36         MTK_HDMI_CLK_AUD_BCLK,
  37         MTK_HDMI_CLK_AUD_SPDIF,
  38         MTK_HDMI_CLK_COUNT
  39 };
  40
  41 enum hdmi_aud_input_type {
  42         HDMI_AUD_INPUT_I2S = 0,
  43         HDMI_AUD_INPUT_SPDIF,
  44 };
  45
  46 enum hdmi_aud_i2s_fmt {
  47         HDMI_I2S_MODE_RJT_24BIT = 0,
  48         HDMI_I2S_MODE_RJT_16BIT,
  49         HDMI_I2S_MODE_LJT_24BIT,
  50         HDMI_I2S_MODE_LJT_16BIT,
  51         HDMI_I2S_MODE_I2S_24BIT,
  52         HDMI_I2S_MODE_I2S_16BIT
  53 };
  54
  55 enum hdmi_aud_mclk {
  56         HDMI_AUD_MCLK_128FS,
  57         HDMI_AUD_MCLK_192FS,
  58         HDMI_AUD_MCLK_256FS,
  59         HDMI_AUD_MCLK_384FS,
  60         HDMI_AUD_MCLK_512FS,
  61         HDMI_AUD_MCLK_768FS,
  62         HDMI_AUD_MCLK_1152FS,
  63 };
  64
  65 enum hdmi_aud_channel_type {
  66         HDMI_AUD_CHAN_TYPE_1_0 = 0,
  67         HDMI_AUD_CHAN_TYPE_1_1,
  68         HDMI_AUD_CHAN_TYPE_2_0,
  69         HDMI_AUD_CHAN_TYPE_2_1,
  70         HDMI_AUD_CHAN_TYPE_3_0,
  71         HDMI_AUD_CHAN_TYPE_3_1,
  72         HDMI_AUD_CHAN_TYPE_4_0,
  73         HDMI_AUD_CHAN_TYPE_4_1,
  74         HDMI_AUD_CHAN_TYPE_5_0,
  75         HDMI_AUD_CHAN_TYPE_5_1,
  76         HDMI_AUD_CHAN_TYPE_6_0,
  77         HDMI_AUD_CHAN_TYPE_6_1,
  78         HDMI_AUD_CHAN_TYPE_7_0,
  79         HDMI_AUD_CHAN_TYPE_7_1,
  80         HDMI_AUD_CHAN_TYPE_3_0_LRS,
  81         HDMI_AUD_CHAN_TYPE_3_1_LRS,
  82         HDMI_AUD_CHAN_TYPE_4_0_CLRS,
  83         HDMI_AUD_CHAN_TYPE_4_1_CLRS,
  84         HDMI_AUD_CHAN_TYPE_6_1_CS,
  85         HDMI_AUD_CHAN_TYPE_6_1_CH,
  86         HDMI_AUD_CHAN_TYPE_6_1_OH,
  87         HDMI_AUD_CHAN_TYPE_6_1_CHR,
  88         HDMI_AUD_CHAN_TYPE_7_1_LH_RH,
  89         HDMI_AUD_CHAN_TYPE_7_1_LSR_RSR,
  90         HDMI_AUD_CHAN_TYPE_7_1_LC_RC,
  91         HDMI_AUD_CHAN_TYPE_7_1_LW_RW,
  92         HDMI_AUD_CHAN_TYPE_7_1_LSD_RSD,
  93         HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS,
  94         HDMI_AUD_CHAN_TYPE_7_1_LHS_RHS,
  95         HDMI_AUD_CHAN_TYPE_7_1_CS_CH,
  96         HDMI_AUD_CHAN_TYPE_7_1_CS_OH,
  97         HDMI_AUD_CHAN_TYPE_7_1_CS_CHR,
  98         HDMI_AUD_CHAN_TYPE_7_1_CH_OH,
  99         HDMI_AUD_CHAN_TYPE_7_1_CH_CHR,
 100         HDMI_AUD_CHAN_TYPE_7_1_OH_CHR,
 101         HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS_LSR_RSR,
 102         HDMI_AUD_CHAN_TYPE_6_0_CS,
 103         HDMI_AUD_CHAN_TYPE_6_0_CH,
 104         HDMI_AUD_CHAN_TYPE_6_0_OH,
 105         HDMI_AUD_CHAN_TYPE_6_0_CHR,
 106         HDMI_AUD_CHAN_TYPE_7_0_LH_RH,
 107         HDMI_AUD_CHAN_TYPE_7_0_LSR_RSR,
 108         HDMI_AUD_CHAN_TYPE_7_0_LC_RC,
 109         HDMI_AUD_CHAN_TYPE_7_0_LW_RW,
 110         HDMI_AUD_CHAN_TYPE_7_0_LSD_RSD,
 111         HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS,
 112         HDMI_AUD_CHAN_TYPE_7_0_LHS_RHS,
 113         HDMI_AUD_CHAN_TYPE_7_0_CS_CH,
 114         HDMI_AUD_CHAN_TYPE_7_0_CS_OH,
 115         HDMI_AUD_CHAN_TYPE_7_0_CS_CHR,
 116         HDMI_AUD_CHAN_TYPE_7_0_CH_OH,
 117         HDMI_AUD_CHAN_TYPE_7_0_CH_CHR,
 118         HDMI_AUD_CHAN_TYPE_7_0_OH_CHR,
 119         HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS_LSR_RSR,
 120         HDMI_AUD_CHAN_TYPE_8_0_LH_RH_CS,
 121         HDMI_AUD_CHAN_TYPE_UNKNOWN = 0xFF
 122 };
 123
 124 enum hdmi_aud_channel_swap_type {
 125         HDMI_AUD_SWAP_LR,
 126         HDMI_AUD_SWAP_LFE_CC,
 127         HDMI_AUD_SWAP_LSRS,
 128         HDMI_AUD_SWAP_RLS_RRS,
 129         HDMI_AUD_SWAP_LR_STATUS,
 130 };
 131
 132 struct hdmi_audio_param {
 133         enum hdmi_audio_coding_type aud_codec;
 134         enum hdmi_audio_sample_size aud_sampe_size;
 135         enum hdmi_aud_input_type aud_input_type;
 136         enum hdmi_aud_i2s_fmt aud_i2s_fmt;
 137         enum hdmi_aud_mclk aud_mclk;
 138         enum hdmi_aud_channel_type aud_input_chan_type;
 139         struct hdmi_codec_params codec_params;
 140 };
 141
 142 struct mtk_hdmi {
 143         struct drm_bridge bridge;
 144         struct drm_bridge *next_bridge;
 145         struct drm_connector conn;
 146         struct device *dev;
 147         struct phy *phy;
 148         struct device *cec_dev;
 149         struct i2c_adapter *ddc_adpt;
 150         struct clk *clk[MTK_HDMI_CLK_COUNT];
 151         struct drm_display_mode mode;
 152         bool dvi_mode;
 153         u32 min_clock;
 154         u32 max_clock;
 155         u32 max_hdisplay;
 156         u32 max_vdisplay;
 157         u32 ibias;
 158         u32 ibias_up;
 159         struct regmap *sys_regmap;
 160         unsigned int sys_offset;
 161         void __iomem *regs;
 162         enum hdmi_colorspace csp;
 163         struct hdmi_audio_param aud_param;
 164         bool audio_enable;
 165         bool powered;
 166         bool enabled;
 167 };
 168
 169 static inline struct mtk_hdmi *hdmi_ctx_from_bridge(struct drm_bridge *b)
 170 {
 171         return container_of(b, struct mtk_hdmi, bridge);
 172 }
 173
 174 static inline struct mtk_hdmi *hdmi_ctx_from_conn(struct drm_connector *c)
 175 {
 176         return container_of(c, struct mtk_hdmi, conn);
 177 }
 178
 179 static u32 mtk_hdmi_read(struct mtk_hdmi *hdmi, u32 offset)
 180 {
 181         return readl(hdmi->regs + offset);
 182 }
 183
 184 static void mtk_hdmi_write(struct mtk_hdmi *hdmi, u32 offset, u32 val)
 185 {
 186         writel(val, hdmi->regs + offset);
 187 }
 188
 189 static void mtk_hdmi_clear_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits)
 190 {
 191         void __iomem *reg = hdmi->regs + offset;
 192         u32 tmp;
 193
 194         tmp = readl(reg);
 195         tmp &= ~bits;
 196         writel(tmp, reg);
 197 }
 198
 199 static void mtk_hdmi_set_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits)
 200 {
 201         void __iomem *reg = hdmi->regs + offset;
 202         u32 tmp;
 203
 204         tmp = readl(reg);
 205         tmp |= bits;
 206         writel(tmp, reg);
 207 }
 208
 209 static void mtk_hdmi_mask(struct mtk_hdmi *hdmi, u32 offset, u32 val, u32 mask)
 210 {
 211         void __iomem *reg = hdmi->regs + offset;
 212         u32 tmp;
 213
 214         tmp = readl(reg);
 215         tmp = (tmp & ~mask) | (val & mask);
 216         writel(tmp, reg);
 217 }
 218
 219 static void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi, bool black)
 220 {
 221         mtk_hdmi_mask(hdmi, VIDEO_CFG_4, black ? GEN_RGB : NORMAL_PATH,
 222                       VIDEO_SOURCE_SEL);
 223 }
 224
 225 static void mtk_hdmi_hw_make_reg_writable(struct mtk_hdmi *hdmi, bool enable)
 226 {
 227         struct arm_smccc_res res;
 228         struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(hdmi->phy);
 229
 230         /*
 231          * MT8173 HDMI hardware has an output control bit to enable/disable HDMI
 232          * output. This bit can only be controlled in ARM supervisor mode.
 233          * The ARM trusted firmware provides an API for the HDMI driver to set
 234          * this control bit to enable HDMI output in supervisor mode.
 235          */
 236         if (hdmi_phy->conf && hdmi_phy->conf->tz_disabled)
 237                 regmap_update_bits(hdmi->sys_regmap,
 238                                    hdmi->sys_offset + HDMI_SYS_CFG20,
 239                                    0x80008005, enable ? 0x80000005 : 0x8000);
 240         else
 241                 arm_smccc_smc(MTK_SIP_SET_AUTHORIZED_SECURE_REG, 0x14000904,
 242                               0x80000000, 0, 0, 0, 0, 0, &res);
 243
 244         regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
 245                            HDMI_PCLK_FREE_RUN, enable ? HDMI_PCLK_FREE_RUN : 0);
 246         regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
 247                            HDMI_ON | ANLG_ON, enable ? (HDMI_ON | ANLG_ON) : 0);
 248 }
 249
 250 static void mtk_hdmi_hw_1p4_version_enable(struct mtk_hdmi *hdmi, bool enable)
 251 {
 252         regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
 253                            HDMI2P0_EN, enable ? 0 : HDMI2P0_EN);
 254 }
 255
 256 static void mtk_hdmi_hw_aud_mute(struct mtk_hdmi *hdmi)
 257 {
 258         mtk_hdmi_set_bits(hdmi, GRL_AUDIO_CFG, AUDIO_ZERO);
 259 }
 260
 261 static void mtk_hdmi_hw_aud_unmute(struct mtk_hdmi *hdmi)
 262 {
 263         mtk_hdmi_clear_bits(hdmi, GRL_AUDIO_CFG, AUDIO_ZERO);
 264 }
 265
 266 static void mtk_hdmi_hw_reset(struct mtk_hdmi *hdmi)
 267 {
 268         regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
 269                            HDMI_RST, HDMI_RST);
 270         regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
 271                            HDMI_RST, 0);
 272         mtk_hdmi_clear_bits(hdmi, GRL_CFG3, CFG3_CONTROL_PACKET_DELAY);
 273         regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
 274                            ANLG_ON, ANLG_ON);
 275 }
 276
 277 static void mtk_hdmi_hw_enable_notice(struct mtk_hdmi *hdmi, bool enable_notice)
 278 {
 279         mtk_hdmi_mask(hdmi, GRL_CFG2, enable_notice ? CFG2_NOTICE_EN : 0,
 280                       CFG2_NOTICE_EN);
 281 }
 282
 283 static void mtk_hdmi_hw_write_int_mask(struct mtk_hdmi *hdmi, u32 int_mask)
 284 {
 285         mtk_hdmi_write(hdmi, GRL_INT_MASK, int_mask);
 286 }
 287
 288 static void mtk_hdmi_hw_enable_dvi_mode(struct mtk_hdmi *hdmi, bool enable)
 289 {
 290         mtk_hdmi_mask(hdmi, GRL_CFG1, enable ? CFG1_DVI : 0, CFG1_DVI);
 291 }
 292
 293 static void mtk_hdmi_hw_send_info_frame(struct mtk_hdmi *hdmi, u8 *buffer,
 294                                         u8 len)
 295 {
 296         u32 ctrl_reg = GRL_CTRL;
 297         int i;
 298         u8 *frame_data;
 299         enum hdmi_infoframe_type frame_type;
 300         u8 frame_ver;
 301         u8 frame_len;
 302         u8 checksum;
 303         int ctrl_frame_en = 0;
 304
 305         frame_type = *buffer;
 306         buffer += 1;
 307         frame_ver = *buffer;
 308         buffer += 1;
 309         frame_len = *buffer;
 310         buffer += 1;
 311         checksum = *buffer;
 312         buffer += 1;
 313         frame_data = buffer;
 314
 315         dev_dbg(hdmi->dev,
 316                 "frame_type:0x%x,frame_ver:0x%x,frame_len:0x%x,checksum:0x%x\n",
 317                 frame_type, frame_ver, frame_len, checksum);
 318
 319         switch (frame_type) {
 320         case HDMI_INFOFRAME_TYPE_AVI:
 321                 ctrl_frame_en = CTRL_AVI_EN;
 322                 ctrl_reg = GRL_CTRL;
 323                 break;
 324         case HDMI_INFOFRAME_TYPE_SPD:
 325                 ctrl_frame_en = CTRL_SPD_EN;
 326                 ctrl_reg = GRL_CTRL;
 327                 break;
 328         case HDMI_INFOFRAME_TYPE_AUDIO:
 329                 ctrl_frame_en = CTRL_AUDIO_EN;
 330                 ctrl_reg = GRL_CTRL;
 331                 break;
 332         case HDMI_INFOFRAME_TYPE_VENDOR:
 333                 ctrl_frame_en = VS_EN;
 334                 ctrl_reg = GRL_ACP_ISRC_CTRL;
 335                 break;
 336         }
 337         mtk_hdmi_clear_bits(hdmi, ctrl_reg, ctrl_frame_en);
 338         mtk_hdmi_write(hdmi, GRL_INFOFRM_TYPE, frame_type);
 339         mtk_hdmi_write(hdmi, GRL_INFOFRM_VER, frame_ver);
 340         mtk_hdmi_write(hdmi, GRL_INFOFRM_LNG, frame_len);
 341
 342         mtk_hdmi_write(hdmi, GRL_IFM_PORT, checksum);
 343         for (i = 0; i < frame_len; i++)
 344                 mtk_hdmi_write(hdmi, GRL_IFM_PORT, frame_data[i]);
 345
 346         mtk_hdmi_set_bits(hdmi, ctrl_reg, ctrl_frame_en);
 347 }
 348
 349 static void mtk_hdmi_hw_send_aud_packet(struct mtk_hdmi *hdmi, bool enable)
 350 {
 351         mtk_hdmi_mask(hdmi, GRL_SHIFT_R2, enable ? 0 : AUDIO_PACKET_OFF,
 352                       AUDIO_PACKET_OFF);
 353 }
 354
 355 static void mtk_hdmi_hw_config_sys(struct mtk_hdmi *hdmi)
 356 {
 357         regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
 358                            HDMI_OUT_FIFO_EN | MHL_MODE_ON, 0);
 359         usleep_range(2000, 4000);
 360         regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
 361                            HDMI_OUT_FIFO_EN | MHL_MODE_ON, HDMI_OUT_FIFO_EN);
 362 }
 363
 364 static void mtk_hdmi_hw_set_deep_color_mode(struct mtk_hdmi *hdmi)
 365 {
 366         regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
 367                            DEEP_COLOR_MODE_MASK | DEEP_COLOR_EN,
 368                            COLOR_8BIT_MODE);
 369 }
 370
 371 static void mtk_hdmi_hw_send_av_mute(struct mtk_hdmi *hdmi)
 372 {
 373         mtk_hdmi_clear_bits(hdmi, GRL_CFG4, CTRL_AVMUTE);
 374         usleep_range(2000, 4000);
 375         mtk_hdmi_set_bits(hdmi, GRL_CFG4, CTRL_AVMUTE);
 376 }
 377
 378 static void mtk_hdmi_hw_send_av_unmute(struct mtk_hdmi *hdmi)
 379 {
 380         mtk_hdmi_mask(hdmi, GRL_CFG4, CFG4_AV_UNMUTE_EN,
 381                       CFG4_AV_UNMUTE_EN | CFG4_AV_UNMUTE_SET);
 382         usleep_range(2000, 4000);
 383         mtk_hdmi_mask(hdmi, GRL_CFG4, CFG4_AV_UNMUTE_SET,
 384                       CFG4_AV_UNMUTE_EN | CFG4_AV_UNMUTE_SET);
 385 }
 386
 387 static void mtk_hdmi_hw_ncts_enable(struct mtk_hdmi *hdmi, bool on)
 388 {
 389         mtk_hdmi_mask(hdmi, GRL_CTS_CTRL, on ? 0 : CTS_CTRL_SOFT,
 390                       CTS_CTRL_SOFT);
 391 }
 392
 393 static void mtk_hdmi_hw_ncts_auto_write_enable(struct mtk_hdmi *hdmi,
 394                                                bool enable)
 395 {
 396         mtk_hdmi_mask(hdmi, GRL_CTS_CTRL, enable ? NCTS_WRI_ANYTIME : 0,
 397                       NCTS_WRI_ANYTIME);
 398 }
 399
 400 static void mtk_hdmi_hw_msic_setting(struct mtk_hdmi *hdmi,
 401                                      struct drm_display_mode *mode)
 402 {
 403         mtk_hdmi_clear_bits(hdmi, GRL_CFG4, CFG4_MHL_MODE);
 404
 405         if (mode->flags & DRM_MODE_FLAG_INTERLACE &&
 406             mode->clock == 74250 &&
 407             mode->vdisplay == 1080)
 408                 mtk_hdmi_clear_bits(hdmi, GRL_CFG2, CFG2_MHL_DE_SEL);
 409         else
 410                 mtk_hdmi_set_bits(hdmi, GRL_CFG2, CFG2_MHL_DE_SEL);
 411 }
 412
 413 static void mtk_hdmi_hw_aud_set_channel_swap(struct mtk_hdmi *hdmi,
 414                                         enum hdmi_aud_channel_swap_type swap)
 415 {
 416         u8 swap_bit;
 417
 418         switch (swap) {
 419         case HDMI_AUD_SWAP_LR:
 420                 swap_bit = LR_SWAP;
 421                 break;
 422         case HDMI_AUD_SWAP_LFE_CC:
 423                 swap_bit = LFE_CC_SWAP;
 424                 break;
 425         case HDMI_AUD_SWAP_LSRS:
 426                 swap_bit = LSRS_SWAP;
 427                 break;
 428         case HDMI_AUD_SWAP_RLS_RRS:
 429                 swap_bit = RLS_RRS_SWAP;
 430                 break;
 431         case HDMI_AUD_SWAP_LR_STATUS:
 432                 swap_bit = LR_STATUS_SWAP;
 433                 break;
 434         default:
 435                 swap_bit = LFE_CC_SWAP;
 436                 break;
 437         }
 438         mtk_hdmi_mask(hdmi, GRL_CH_SWAP, swap_bit, 0xff);
 439 }
 440
 441 static void mtk_hdmi_hw_aud_set_bit_num(struct mtk_hdmi *hdmi,
 442                                         enum hdmi_audio_sample_size bit_num)
 443 {
 444         u32 val;
 445
 446         switch (bit_num) {
 447         case HDMI_AUDIO_SAMPLE_SIZE_16:
 448                 val = AOUT_16BIT;
 449                 break;
 450         case HDMI_AUDIO_SAMPLE_SIZE_20:
 451                 val = AOUT_20BIT;
 452                 break;
 453         case HDMI_AUDIO_SAMPLE_SIZE_24:
 454         case HDMI_AUDIO_SAMPLE_SIZE_STREAM:
 455                 val = AOUT_24BIT;
 456                 break;
 457         }
 458
 459         mtk_hdmi_mask(hdmi, GRL_AOUT_CFG, val, AOUT_BNUM_SEL_MASK);
 460 }
 461
 462 static void mtk_hdmi_hw_aud_set_i2s_fmt(struct mtk_hdmi *hdmi,
 463                                         enum hdmi_aud_i2s_fmt i2s_fmt)
 464 {
 465         u32 val;
 466
 467         val = mtk_hdmi_read(hdmi, GRL_CFG0);
 468         val &= ~(CFG0_W_LENGTH_MASK | CFG0_I2S_MODE_MASK);
 469
 470         switch (i2s_fmt) {
 471         case HDMI_I2S_MODE_RJT_24BIT:
 472                 val |= CFG0_I2S_MODE_RTJ | CFG0_W_LENGTH_24BIT;
 473                 break;
 474         case HDMI_I2S_MODE_RJT_16BIT:
 475                 val |= CFG0_I2S_MODE_RTJ | CFG0_W_LENGTH_16BIT;
 476                 break;
 477         case HDMI_I2S_MODE_LJT_24BIT:
 478         default:
 479                 val |= CFG0_I2S_MODE_LTJ | CFG0_W_LENGTH_24BIT;
 480                 break;
 481         case HDMI_I2S_MODE_LJT_16BIT:
 482                 val |= CFG0_I2S_MODE_LTJ | CFG0_W_LENGTH_16BIT;
 483                 break;
 484         case HDMI_I2S_MODE_I2S_24BIT:
 485                 val |= CFG0_I2S_MODE_I2S | CFG0_W_LENGTH_24BIT;
 486                 break;
 487         case HDMI_I2S_MODE_I2S_16BIT:
 488                 val |= CFG0_I2S_MODE_I2S | CFG0_W_LENGTH_16BIT;
 489                 break;
 490         }
 491         mtk_hdmi_write(hdmi, GRL_CFG0, val);
 492 }
 493
 494 static void mtk_hdmi_hw_audio_config(struct mtk_hdmi *hdmi, bool dst)
 495 {
 496         const u8 mask = HIGH_BIT_RATE | DST_NORMAL_DOUBLE | SACD_DST | DSD_SEL;
 497         u8 val;
 498
 499         /* Disable high bitrate, set DST packet normal/double */
 500         mtk_hdmi_clear_bits(hdmi, GRL_AOUT_CFG, HIGH_BIT_RATE_PACKET_ALIGN);
 501
 502         if (dst)
 503                 val = DST_NORMAL_DOUBLE | SACD_DST;
 504         else
 505                 val = 0;
 506
 507         mtk_hdmi_mask(hdmi, GRL_AUDIO_CFG, val, mask);
 508 }
 509
 510 static void mtk_hdmi_hw_aud_set_i2s_chan_num(struct mtk_hdmi *hdmi,
 511                                         enum hdmi_aud_channel_type channel_type,
 512                                         u8 channel_count)
 513 {
 514         unsigned int ch_switch;
 515         u8 i2s_uv;
 516
 517         ch_switch = CH_SWITCH(7, 7) | CH_SWITCH(6, 6) |
 518                     CH_SWITCH(5, 5) | CH_SWITCH(4, 4) |
 519                     CH_SWITCH(3, 3) | CH_SWITCH(1, 2) |
 520                     CH_SWITCH(2, 1) | CH_SWITCH(0, 0);
 521
 522         if (channel_count == 2) {
 523                 i2s_uv = I2S_UV_CH_EN(0);
 524         } else if (channel_count == 3 || channel_count == 4) {
 525                 if (channel_count == 4 &&
 526                     (channel_type == HDMI_AUD_CHAN_TYPE_3_0_LRS ||
 527                     channel_type == HDMI_AUD_CHAN_TYPE_4_0))
 528                         i2s_uv = I2S_UV_CH_EN(2) | I2S_UV_CH_EN(0);
 529                 else
 530                         i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2);
 531         } else if (channel_count == 6 || channel_count == 5) {
 532                 if (channel_count == 6 &&
 533                     channel_type != HDMI_AUD_CHAN_TYPE_5_1 &&
 534                     channel_type != HDMI_AUD_CHAN_TYPE_4_1_CLRS) {
 535                         i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2) |
 536                                  I2S_UV_CH_EN(1) | I2S_UV_CH_EN(0);
 537                 } else {
 538                         i2s_uv = I2S_UV_CH_EN(2) | I2S_UV_CH_EN(1) |
 539                                  I2S_UV_CH_EN(0);
 540                 }
 541         } else if (channel_count == 8 || channel_count == 7) {
 542                 i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2) |
 543                          I2S_UV_CH_EN(1) | I2S_UV_CH_EN(0);
 544         } else {
 545                 i2s_uv = I2S_UV_CH_EN(0);
 546         }
 547
 548         mtk_hdmi_write(hdmi, GRL_CH_SW0, ch_switch & 0xff);
 549         mtk_hdmi_write(hdmi, GRL_CH_SW1, (ch_switch >> 8) & 0xff);
 550         mtk_hdmi_write(hdmi, GRL_CH_SW2, (ch_switch >> 16) & 0xff);
 551         mtk_hdmi_write(hdmi, GRL_I2S_UV, i2s_uv);
 552 }
 553
 554 static void mtk_hdmi_hw_aud_set_input_type(struct mtk_hdmi *hdmi,
 555                                            enum hdmi_aud_input_type input_type)
 556 {
 557         u32 val;
 558
 559         val = mtk_hdmi_read(hdmi, GRL_CFG1);
 560         if (input_type == HDMI_AUD_INPUT_I2S &&
 561             (val & CFG1_SPDIF) == CFG1_SPDIF) {
 562                 val &= ~CFG1_SPDIF;
 563         } else if (input_type == HDMI_AUD_INPUT_SPDIF &&
 564                 (val & CFG1_SPDIF) == 0) {
 565                 val |= CFG1_SPDIF;
 566         }
 567         mtk_hdmi_write(hdmi, GRL_CFG1, val);
 568 }
 569
 570 static void mtk_hdmi_hw_aud_set_channel_status(struct mtk_hdmi *hdmi,
 571                                                u8 *channel_status)
 572 {
 573         int i;
 574
 575         for (i = 0; i < 5; i++) {
 576                 mtk_hdmi_write(hdmi, GRL_I2S_C_STA0 + i * 4, channel_status[i]);
 577                 mtk_hdmi_write(hdmi, GRL_L_STATUS_0 + i * 4, channel_status[i]);
 578                 mtk_hdmi_write(hdmi, GRL_R_STATUS_0 + i * 4, channel_status[i]);
 579         }
 580         for (; i < 24; i++) {
 581                 mtk_hdmi_write(hdmi, GRL_L_STATUS_0 + i * 4, 0);
 582                 mtk_hdmi_write(hdmi, GRL_R_STATUS_0 + i * 4, 0);
 583         }
 584 }
 585
 586 static void mtk_hdmi_hw_aud_src_reenable(struct mtk_hdmi *hdmi)
 587 {
 588         u32 val;
 589
 590         val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL);
 591         if (val & MIX_CTRL_SRC_EN) {
 592                 val &= ~MIX_CTRL_SRC_EN;
 593                 mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val);
 594                 usleep_range(255, 512);
 595                 val |= MIX_CTRL_SRC_EN;
 596                 mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val);
 597         }
 598 }
 599
 600 static void mtk_hdmi_hw_aud_src_disable(struct mtk_hdmi *hdmi)
 601 {
 602         u32 val;
 603
 604         val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL);
 605         val &= ~MIX_CTRL_SRC_EN;
 606         mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val);
 607         mtk_hdmi_write(hdmi, GRL_SHIFT_L1, 0x00);
 608 }
 609
 610 static void mtk_hdmi_hw_aud_set_mclk(struct mtk_hdmi *hdmi,
 611                                      enum hdmi_aud_mclk mclk)
 612 {
 613         u32 val;
 614
 615         val = mtk_hdmi_read(hdmi, GRL_CFG5);
 616         val &= CFG5_CD_RATIO_MASK;
 617
 618         switch (mclk) {
 619         case HDMI_AUD_MCLK_128FS:
 620                 val |= CFG5_FS128;
 621                 break;
 622         case HDMI_AUD_MCLK_256FS:
 623                 val |= CFG5_FS256;
 624                 break;
 625         case HDMI_AUD_MCLK_384FS:
 626                 val |= CFG5_FS384;
 627                 break;
 628         case HDMI_AUD_MCLK_512FS:
 629                 val |= CFG5_FS512;
 630                 break;
 631         case HDMI_AUD_MCLK_768FS:
 632                 val |= CFG5_FS768;
 633                 break;
 634         default:
 635                 val |= CFG5_FS256;
 636                 break;
 637         }
 638         mtk_hdmi_write(hdmi, GRL_CFG5, val);
 639 }
 640
 641 struct hdmi_acr_n {
 642         unsigned int clock;
 643         unsigned int n[3];
 644 };
 645
 646 /* Recommended N values from HDMI specification, tables 7-1 to 7-3 */
 647 static const struct hdmi_acr_n hdmi_rec_n_table[] = {
 648         /* Clock, N: 32kHz 44.1kHz 48kHz */
 649         {  25175, {  4576,  7007,  6864 } },
 650         {  74176, { 11648, 17836, 11648 } },
 651         { 148352, { 11648,  8918,  5824 } },
 652         { 296703, {  5824,  4459,  5824 } },
 653         { 297000, {  3072,  4704,  5120 } },
 654         {      0, {  4096,  6272,  6144 } }, /* all other TMDS clocks */
 655 };
 656
 657 /**
 658  * hdmi_recommended_n() - Return N value recommended by HDMI specification
 659  * @freq: audio sample rate in Hz
 660  * @clock: rounded TMDS clock in kHz
 661  */
 662 static unsigned int hdmi_recommended_n(unsigned int freq, unsigned int clock)
 663 {
 664         const struct hdmi_acr_n *recommended;
 665         unsigned int i;
 666
 667         for (i = 0; i < ARRAY_SIZE(hdmi_rec_n_table) - 1; i++) {
 668                 if (clock == hdmi_rec_n_table[i].clock)
 669                         break;
 670         }
 671         recommended = hdmi_rec_n_table + i;
 672
 673         switch (freq) {
 674         case 32000:
 675                 return recommended->n[0];
 676         case 44100:
 677                 return recommended->n[1];
 678         case 48000:
 679                 return recommended->n[2];
 680         case 88200:
 681                 return recommended->n[1] * 2;
 682         case 96000:
 683                 return recommended->n[2] * 2;
 684         case 176400:
 685                 return recommended->n[1] * 4;
 686         case 192000:
 687                 return recommended->n[2] * 4;
 688         default:
 689                 return (128 * freq) / 1000;
 690         }
 691 }
 692
 693 static unsigned int hdmi_mode_clock_to_hz(unsigned int clock)
 694 {
 695         switch (clock) {
 696         case 25175:
 697                 return 25174825;        /* 25.2/1.001 MHz */
 698         case 74176:
 699                 return 74175824;        /* 74.25/1.001 MHz */
 700         case 148352:
 701                 return 148351648;       /* 148.5/1.001 MHz */
 702         case 296703:
 703                 return 296703297;       /* 297/1.001 MHz */
 704         default:
 705                 return clock * 1000;
 706         }
 707 }
 708
 709 static unsigned int hdmi_expected_cts(unsigned int audio_sample_rate,
 710                                       unsigned int tmds_clock, unsigned int n)
 711 {
 712         return DIV_ROUND_CLOSEST_ULL((u64)hdmi_mode_clock_to_hz(tmds_clock) * n,
 713                                      128 * audio_sample_rate);
 714 }
 715
 716 static void do_hdmi_hw_aud_set_ncts(struct mtk_hdmi *hdmi, unsigned int n,
 717                                     unsigned int cts)
 718 {
 719         unsigned char val[NCTS_BYTES];
 720         int i;
 721
 722         mtk_hdmi_write(hdmi, GRL_NCTS, 0);
 723         mtk_hdmi_write(hdmi, GRL_NCTS, 0);
 724         mtk_hdmi_write(hdmi, GRL_NCTS, 0);
 725         memset(val, 0, sizeof(val));
 726
 727         val[0] = (cts >> 24) & 0xff;
 728         val[1] = (cts >> 16) & 0xff;
 729         val[2] = (cts >> 8) & 0xff;
 730         val[3] = cts & 0xff;
 731
 732         val[4] = (n >> 16) & 0xff;
 733         val[5] = (n >> 8) & 0xff;
 734         val[6] = n & 0xff;
 735
 736         for (i = 0; i < NCTS_BYTES; i++)
 737                 mtk_hdmi_write(hdmi, GRL_NCTS, val[i]);
 738 }
 739
 740 static void mtk_hdmi_hw_aud_set_ncts(struct mtk_hdmi *hdmi,
 741                                      unsigned int sample_rate,
 742                                      unsigned int clock)
 743 {
 744         unsigned int n, cts;
 745
 746         n = hdmi_recommended_n(sample_rate, clock);
 747         cts = hdmi_expected_cts(sample_rate, clock, n);
 748
 749         dev_dbg(hdmi->dev, "%s: sample_rate=%u, clock=%d, cts=%u, n=%u\n",
 750                 __func__, sample_rate, clock, n, cts);
 751
 752         mtk_hdmi_mask(hdmi, DUMMY_304, AUDIO_I2S_NCTS_SEL_64,
 753                       AUDIO_I2S_NCTS_SEL);
 754         do_hdmi_hw_aud_set_ncts(hdmi, n, cts);
 755 }
 756
 757 static u8 mtk_hdmi_aud_get_chnl_count(enum hdmi_aud_channel_type channel_type)
 758 {
 759         switch (channel_type) {
 760         case HDMI_AUD_CHAN_TYPE_1_0:
 761         case HDMI_AUD_CHAN_TYPE_1_1:
 762         case HDMI_AUD_CHAN_TYPE_2_0:
 763                 return 2;
 764         case HDMI_AUD_CHAN_TYPE_2_1:
 765         case HDMI_AUD_CHAN_TYPE_3_0:
 766                 return 3;
 767         case HDMI_AUD_CHAN_TYPE_3_1:
 768         case HDMI_AUD_CHAN_TYPE_4_0:
 769         case HDMI_AUD_CHAN_TYPE_3_0_LRS:
 770                 return 4;
 771         case HDMI_AUD_CHAN_TYPE_4_1:
 772         case HDMI_AUD_CHAN_TYPE_5_0:
 773         case HDMI_AUD_CHAN_TYPE_3_1_LRS:
 774         case HDMI_AUD_CHAN_TYPE_4_0_CLRS:
 775                 return 5;
 776         case HDMI_AUD_CHAN_TYPE_5_1:
 777         case HDMI_AUD_CHAN_TYPE_6_0:
 778         case HDMI_AUD_CHAN_TYPE_4_1_CLRS:
 779         case HDMI_AUD_CHAN_TYPE_6_0_CS:
 780         case HDMI_AUD_CHAN_TYPE_6_0_CH:
 781         case HDMI_AUD_CHAN_TYPE_6_0_OH:
 782         case HDMI_AUD_CHAN_TYPE_6_0_CHR:
 783                 return 6;
 784         case HDMI_AUD_CHAN_TYPE_6_1:
 785         case HDMI_AUD_CHAN_TYPE_6_1_CS:
 786         case HDMI_AUD_CHAN_TYPE_6_1_CH:
 787         case HDMI_AUD_CHAN_TYPE_6_1_OH:
 788         case HDMI_AUD_CHAN_TYPE_6_1_CHR:
 789         case HDMI_AUD_CHAN_TYPE_7_0:
 790         case HDMI_AUD_CHAN_TYPE_7_0_LH_RH:
 791         case HDMI_AUD_CHAN_TYPE_7_0_LSR_RSR:
 792         case HDMI_AUD_CHAN_TYPE_7_0_LC_RC:
 793         case HDMI_AUD_CHAN_TYPE_7_0_LW_RW:
 794         case HDMI_AUD_CHAN_TYPE_7_0_LSD_RSD:
 795         case HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS:
 796         case HDMI_AUD_CHAN_TYPE_7_0_LHS_RHS:
 797         case HDMI_AUD_CHAN_TYPE_7_0_CS_CH:
 798         case HDMI_AUD_CHAN_TYPE_7_0_CS_OH:
 799         case HDMI_AUD_CHAN_TYPE_7_0_CS_CHR:
 800         case HDMI_AUD_CHAN_TYPE_7_0_CH_OH:
 801         case HDMI_AUD_CHAN_TYPE_7_0_CH_CHR:
 802         case HDMI_AUD_CHAN_TYPE_7_0_OH_CHR:
 803         case HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS_LSR_RSR:
 804         case HDMI_AUD_CHAN_TYPE_8_0_LH_RH_CS:
 805                 return 7;
 806         case HDMI_AUD_CHAN_TYPE_7_1:
 807         case HDMI_AUD_CHAN_TYPE_7_1_LH_RH:
 808         case HDMI_AUD_CHAN_TYPE_7_1_LSR_RSR:
 809         case HDMI_AUD_CHAN_TYPE_7_1_LC_RC:
 810         case HDMI_AUD_CHAN_TYPE_7_1_LW_RW:
 811         case HDMI_AUD_CHAN_TYPE_7_1_LSD_RSD:
 812         case HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS:
 813         case HDMI_AUD_CHAN_TYPE_7_1_LHS_RHS:
 814         case HDMI_AUD_CHAN_TYPE_7_1_CS_CH:
 815         case HDMI_AUD_CHAN_TYPE_7_1_CS_OH:
 816         case HDMI_AUD_CHAN_TYPE_7_1_CS_CHR:
 817         case HDMI_AUD_CHAN_TYPE_7_1_CH_OH:
 818         case HDMI_AUD_CHAN_TYPE_7_1_CH_CHR:
 819         case HDMI_AUD_CHAN_TYPE_7_1_OH_CHR:
 820         case HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS_LSR_RSR:
 821                 return 8;
 822         default:
 823                 return 2;
 824         }
 825 }
 826
 827 static int mtk_hdmi_video_change_vpll(struct mtk_hdmi *hdmi, u32 clock)
 828 {
 829         unsigned long rate;
 830         int ret;
 831
 832         /* The DPI driver already should have set TVDPLL to the correct rate */
 833         ret = clk_set_rate(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL], clock);
 834         if (ret) {
 835                 dev_err(hdmi->dev, "Failed to set PLL to %u Hz: %d\n", clock,
 836                         ret);
 837                 return ret;
 838         }
 839
 840         rate = clk_get_rate(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]);
 841
 842         if (DIV_ROUND_CLOSEST(rate, 1000) != DIV_ROUND_CLOSEST(clock, 1000))
 843                 dev_warn(hdmi->dev, "Want PLL %u Hz, got %lu Hz\n", clock,
 844                          rate);
 845         else
 846                 dev_dbg(hdmi->dev, "Want PLL %u Hz, got %lu Hz\n", clock, rate);
 847
 848         mtk_hdmi_hw_config_sys(hdmi);
 849         mtk_hdmi_hw_set_deep_color_mode(hdmi);
 850         return 0;
 851 }
 852
 853 static void mtk_hdmi_video_set_display_mode(struct mtk_hdmi *hdmi,
 854                                             struct drm_display_mode *mode)
 855 {
 856         mtk_hdmi_hw_reset(hdmi);
 857         mtk_hdmi_hw_enable_notice(hdmi, true);
 858         mtk_hdmi_hw_write_int_mask(hdmi, 0xff);
 859         mtk_hdmi_hw_enable_dvi_mode(hdmi, hdmi->dvi_mode);
 860         mtk_hdmi_hw_ncts_auto_write_enable(hdmi, true);
 861
 862         mtk_hdmi_hw_msic_setting(hdmi, mode);
 863 }
 864
 865 static int mtk_hdmi_aud_enable_packet(struct mtk_hdmi *hdmi, bool enable)
 866 {
 867         mtk_hdmi_hw_send_aud_packet(hdmi, enable);
 868         return 0;
 869 }
 870
 871 static int mtk_hdmi_aud_on_off_hw_ncts(struct mtk_hdmi *hdmi, bool on)
 872 {
 873         mtk_hdmi_hw_ncts_enable(hdmi, on);
 874         return 0;
 875 }
 876
 877 static int mtk_hdmi_aud_set_input(struct mtk_hdmi *hdmi)
 878 {
 879         enum hdmi_aud_channel_type chan_type;
 880         u8 chan_count;
 881         bool dst;
 882
 883         mtk_hdmi_hw_aud_set_channel_swap(hdmi, HDMI_AUD_SWAP_LFE_CC);
 884         mtk_hdmi_set_bits(hdmi, GRL_MIX_CTRL, MIX_CTRL_FLAT);
 885
 886         if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF &&
 887             hdmi->aud_param.aud_codec == HDMI_AUDIO_CODING_TYPE_DST) {
 888                 mtk_hdmi_hw_aud_set_bit_num(hdmi, HDMI_AUDIO_SAMPLE_SIZE_24);
 889         } else if (hdmi->aud_param.aud_i2s_fmt == HDMI_I2S_MODE_LJT_24BIT) {
 890                 hdmi->aud_param.aud_i2s_fmt = HDMI_I2S_MODE_LJT_16BIT;
 891         }
 892
 893         mtk_hdmi_hw_aud_set_i2s_fmt(hdmi, hdmi->aud_param.aud_i2s_fmt);
 894         mtk_hdmi_hw_aud_set_bit_num(hdmi, HDMI_AUDIO_SAMPLE_SIZE_24);
 895
 896         dst = ((hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF) &&
 897                (hdmi->aud_param.aud_codec == HDMI_AUDIO_CODING_TYPE_DST));
 898         mtk_hdmi_hw_audio_config(hdmi, dst);
 899
 900         if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF)
 901                 chan_type = HDMI_AUD_CHAN_TYPE_2_0;
 902         else
 903                 chan_type = hdmi->aud_param.aud_input_chan_type;
 904         chan_count = mtk_hdmi_aud_get_chnl_count(chan_type);
 905         mtk_hdmi_hw_aud_set_i2s_chan_num(hdmi, chan_type, chan_count);
 906         mtk_hdmi_hw_aud_set_input_type(hdmi, hdmi->aud_param.aud_input_type);
 907
 908         return 0;
 909 }
 910
 911 static int mtk_hdmi_aud_set_src(struct mtk_hdmi *hdmi,
 912                                 struct drm_display_mode *display_mode)
 913 {
 914         unsigned int sample_rate = hdmi->aud_param.codec_params.sample_rate;
 915
 916         mtk_hdmi_aud_on_off_hw_ncts(hdmi, false);
 917         mtk_hdmi_hw_aud_src_disable(hdmi);
 918         mtk_hdmi_clear_bits(hdmi, GRL_CFG2, CFG2_ACLK_INV);
 919
 920         if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_I2S) {
 921                 switch (sample_rate) {
 922                 case 32000:
 923                 case 44100:
 924                 case 48000:
 925                 case 88200:
 926                 case 96000:
 927                         break;
 928                 default:
 929                         return -EINVAL;
 930                 }
 931                 mtk_hdmi_hw_aud_set_mclk(hdmi, hdmi->aud_param.aud_mclk);
 932         } else {
 933                 switch (sample_rate) {
 934                 case 32000:
 935                 case 44100:
 936                 case 48000:
 937                         break;
 938                 default:
 939                         return -EINVAL;
 940                 }
 941                 mtk_hdmi_hw_aud_set_mclk(hdmi, HDMI_AUD_MCLK_128FS);
 942         }
 943
 944         mtk_hdmi_hw_aud_set_ncts(hdmi, sample_rate, display_mode->clock);
 945
 946         mtk_hdmi_hw_aud_src_reenable(hdmi);
 947         return 0;
 948 }
 949
 950 static int mtk_hdmi_aud_output_config(struct mtk_hdmi *hdmi,
 951                                       struct drm_display_mode *display_mode)
 952 {
 953         mtk_hdmi_hw_aud_mute(hdmi);
 954         mtk_hdmi_aud_enable_packet(hdmi, false);
 955
 956         mtk_hdmi_aud_set_input(hdmi);
 957         mtk_hdmi_aud_set_src(hdmi, display_mode);
 958         mtk_hdmi_hw_aud_set_channel_status(hdmi,
 959                         hdmi->aud_param.codec_params.iec.status);
 960
 961         usleep_range(50, 100);
 962
 963         mtk_hdmi_aud_on_off_hw_ncts(hdmi, true);
 964         mtk_hdmi_aud_enable_packet(hdmi, true);
 965         mtk_hdmi_hw_aud_unmute(hdmi);
 966         return 0;
 967 }
 968
 969 static int mtk_hdmi_setup_avi_infoframe(struct mtk_hdmi *hdmi,
 970                                         struct drm_display_mode *mode)
 971 {
 972         struct hdmi_avi_infoframe frame;
 973         u8 buffer[17];
 974         ssize_t err;
 975
 976         err = drm_hdmi_avi_infoframe_from_display_mode(&frame,
 977                                                        &hdmi->conn, mode);
 978         if (err < 0) {
 979                 dev_err(hdmi->dev,
 980                         "Failed to get AVI infoframe from mode: %zd\n", err);
 981                 return err;
 982         }
 983
 984         err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
 985         if (err < 0) {
 986                 dev_err(hdmi->dev, "Failed to pack AVI infoframe: %zd\n", err);
 987                 return err;
 988         }
 989
 990         mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer));
 991         return 0;
 992 }
 993
 994 static int mtk_hdmi_setup_spd_infoframe(struct mtk_hdmi *hdmi,
 995                                         const char *vendor,
 996                                         const char *product)
 997 {
 998         struct hdmi_spd_infoframe frame;
 999         u8 buffer[29];
1000         ssize_t err;
1001
1002         err = hdmi_spd_infoframe_init(&frame, vendor, product);
1003         if (err < 0) {
1004                 dev_err(hdmi->dev, "Failed to initialize SPD infoframe: %zd\n",
1005                         err);
1006                 return err;
1007         }
1008
1009         err = hdmi_spd_infoframe_pack(&frame, buffer, sizeof(buffer));
1010         if (err < 0) {
1011                 dev_err(hdmi->dev, "Failed to pack SDP infoframe: %zd\n", err);
1012                 return err;
1013         }
1014
1015         mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer));
1016         return 0;
1017 }
1018
1019 static int mtk_hdmi_setup_audio_infoframe(struct mtk_hdmi *hdmi)
1020 {
1021         struct hdmi_audio_infoframe frame;
1022         u8 buffer[14];
1023         ssize_t err;
1024
1025         err = hdmi_audio_infoframe_init(&frame);
1026         if (err < 0) {
1027                 dev_err(hdmi->dev, "Failed to setup audio infoframe: %zd\n",
1028                         err);
1029                 return err;
1030         }
1031
1032         frame.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM;
1033         frame.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM;
1034         frame.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM;
1035         frame.channels = mtk_hdmi_aud_get_chnl_count(
1036                                         hdmi->aud_param.aud_input_chan_type);
1037
1038         err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
1039         if (err < 0) {
1040                 dev_err(hdmi->dev, "Failed to pack audio infoframe: %zd\n",
1041                         err);
1042                 return err;
1043         }
1044
1045         mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer));
1046         return 0;
1047 }
1048
1049 static int mtk_hdmi_setup_vendor_specific_infoframe(struct mtk_hdmi *hdmi,
1050                                                 struct drm_display_mode *mode)
1051 {
1052         struct hdmi_vendor_infoframe frame;
1053         u8 buffer[10];
1054         ssize_t err;
1055
1056         err = drm_hdmi_vendor_infoframe_from_display_mode(&frame,
1057                                                           &hdmi->conn, mode);
1058         if (err) {
1059                 dev_err(hdmi->dev,
1060                         "Failed to get vendor infoframe from mode: %zd\n", err);
1061                 return err;
1062         }
1063
1064         err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
1065         if (err < 0) {
1066                 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n",
1067                         err);
1068                 return err;
1069         }
1070
1071         mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer));
1072         return 0;
1073 }
1074
1075 static int mtk_hdmi_output_init(struct mtk_hdmi *hdmi)
1076 {
1077         struct hdmi_audio_param *aud_param = &hdmi->aud_param;
1078
1079         hdmi->csp = HDMI_COLORSPACE_RGB;
1080         aud_param->aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
1081         aud_param->aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16;
1082         aud_param->aud_input_type = HDMI_AUD_INPUT_I2S;
1083         aud_param->aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT;
1084         aud_param->aud_mclk = HDMI_AUD_MCLK_128FS;
1085         aud_param->aud_input_chan_type = HDMI_AUD_CHAN_TYPE_2_0;
1086
1087         return 0;
1088 }
1089
1090 static void mtk_hdmi_audio_enable(struct mtk_hdmi *hdmi)
1091 {
1092         mtk_hdmi_aud_enable_packet(hdmi, true);
1093         hdmi->audio_enable = true;
1094 }
1095
1096 static void mtk_hdmi_audio_disable(struct mtk_hdmi *hdmi)
1097 {
1098         mtk_hdmi_aud_enable_packet(hdmi, false);
1099         hdmi->audio_enable = false;
1100 }
1101
1102 static int mtk_hdmi_audio_set_param(struct mtk_hdmi *hdmi,
1103                                     struct hdmi_audio_param *param)
1104 {
1105         if (!hdmi->audio_enable) {
1106                 dev_err(hdmi->dev, "hdmi audio is in disable state!\n");
1107                 return -EINVAL;
1108         }
1109         dev_dbg(hdmi->dev, "codec:%d, input:%d, channel:%d, fs:%d\n",
1110                 param->aud_codec, param->aud_input_type,
1111                 param->aud_input_chan_type, param->codec_params.sample_rate);
1112         memcpy(&hdmi->aud_param, param, sizeof(*param));
1113         return mtk_hdmi_aud_output_config(hdmi, &hdmi->mode);
1114 }
1115
1116 static int mtk_hdmi_output_set_display_mode(struct mtk_hdmi *hdmi,
1117                                             struct drm_display_mode *mode)
1118 {
1119         int ret;
1120
1121         mtk_hdmi_hw_vid_black(hdmi, true);
1122         mtk_hdmi_hw_aud_mute(hdmi);
1123         mtk_hdmi_hw_send_av_mute(hdmi);
1124         phy_power_off(hdmi->phy);
1125
1126         ret = mtk_hdmi_video_change_vpll(hdmi,
1127                                          mode->clock * 1000);
1128         if (ret) {
1129                 dev_err(hdmi->dev, "Failed to set vpll: %d\n", ret);
1130                 return ret;
1131         }
1132         mtk_hdmi_video_set_display_mode(hdmi, mode);
1133
1134         phy_power_on(hdmi->phy);
1135         mtk_hdmi_aud_output_config(hdmi, mode);
1136
1137         mtk_hdmi_hw_vid_black(hdmi, false);
1138         mtk_hdmi_hw_aud_unmute(hdmi);
1139         mtk_hdmi_hw_send_av_unmute(hdmi);
1140
1141         return 0;
1142 }
1143
1144 static const char * const mtk_hdmi_clk_names[MTK_HDMI_CLK_COUNT] = {
1145         [MTK_HDMI_CLK_HDMI_PIXEL] = "pixel",
1146         [MTK_HDMI_CLK_HDMI_PLL] = "pll",
1147         [MTK_HDMI_CLK_AUD_BCLK] = "bclk",
1148         [MTK_HDMI_CLK_AUD_SPDIF] = "spdif",
1149 };
1150
1151 static int mtk_hdmi_get_all_clk(struct mtk_hdmi *hdmi,
1152                                 struct device_node *np)
1153 {
1154         int i;
1155
1156         for (i = 0; i < ARRAY_SIZE(mtk_hdmi_clk_names); i++) {
1157                 hdmi->clk[i] = of_clk_get_by_name(np,
1158                                                   mtk_hdmi_clk_names[i]);
1159                 if (IS_ERR(hdmi->clk[i]))
1160                         return PTR_ERR(hdmi->clk[i]);
1161         }
1162         return 0;
1163 }
1164
1165 static int mtk_hdmi_clk_enable_audio(struct mtk_hdmi *hdmi)
1166 {
1167         int ret;
1168
1169         ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]);
1170         if (ret)
1171                 return ret;
1172
1173         ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_AUD_SPDIF]);
1174         if (ret)
1175                 goto err;
1176
1177         return 0;
1178 err:
1179         clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]);
1180         return ret;
1181 }
1182
1183 static void mtk_hdmi_clk_disable_audio(struct mtk_hdmi *hdmi)
1184 {
1185         clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]);
1186         clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_SPDIF]);
1187 }
1188
1189 static enum drm_connector_status hdmi_conn_detect(struct drm_connector *conn,
1190                                                   bool force)
1191 {
1192         struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn);
1193
1194         return mtk_cec_hpd_high(hdmi->cec_dev) ?
1195                connector_status_connected : connector_status_disconnected;
1196 }
1197
1198 static void hdmi_conn_destroy(struct drm_connector *conn)
1199 {
1200         struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn);
1201
1202         mtk_cec_set_hpd_event(hdmi->cec_dev, NULL, NULL);
1203
1204         drm_connector_cleanup(conn);
1205 }
1206
1207 static int mtk_hdmi_conn_get_modes(struct drm_connector *conn)
1208 {
1209         struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn);
1210         struct edid *edid;
1211         int ret;
1212
1213         if (!hdmi->ddc_adpt)
1214                 return -ENODEV;
1215
1216         edid = drm_get_edid(conn, hdmi->ddc_adpt);
1217         if (!edid)
1218                 return -ENODEV;
1219
1220         hdmi->dvi_mode = !drm_detect_monitor_audio(edid);
1221
1222         drm_connector_update_edid_property(conn, edid);
1223
1224         ret = drm_add_edid_modes(conn, edid);
1225         kfree(edid);
1226         return ret;
1227 }
1228
1229 static int mtk_hdmi_conn_mode_valid(struct drm_connector *conn,
1230                                     struct drm_display_mode *mode)
1231 {
1232         struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn);
1233
1234         dev_dbg(hdmi->dev, "xres=%d, yres=%d, refresh=%d, intl=%d clock=%d\n",
1235                 mode->hdisplay, mode->vdisplay, mode->vrefresh,
1236                 !!(mode->flags & DRM_MODE_FLAG_INTERLACE), mode->clock * 1000);
1237
1238         if (hdmi->bridge.next) {
1239                 struct drm_display_mode adjusted_mode;
1240
1241                 drm_mode_copy(&adjusted_mode, mode);
1242                 if (!drm_bridge_mode_fixup(hdmi->bridge.next, mode,
1243                                            &adjusted_mode))
1244                         return MODE_BAD;
1245         }
1246
1247         if (mode->clock < 27000)
1248                 return MODE_CLOCK_LOW;
1249         if (mode->clock > 297000)
1250                 return MODE_CLOCK_HIGH;
1251
1252         return drm_mode_validate_size(mode, 0x1fff, 0x1fff);
1253 }
1254
1255 static struct drm_encoder *mtk_hdmi_conn_best_enc(struct drm_connector *conn)
1256 {
1257         struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn);
1258
1259         return hdmi->bridge.encoder;
1260 }
1261
1262 static const struct drm_connector_funcs mtk_hdmi_connector_funcs = {
1263         .detect = hdmi_conn_detect,
1264         .fill_modes = drm_helper_probe_single_connector_modes,
1265         .destroy = hdmi_conn_destroy,
1266         .reset = drm_atomic_helper_connector_reset,
1267         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1268         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1269 };
1270
1271 static const struct drm_connector_helper_funcs
1272                 mtk_hdmi_connector_helper_funcs = {
1273         .get_modes = mtk_hdmi_conn_get_modes,
1274         .mode_valid = mtk_hdmi_conn_mode_valid,
1275         .best_encoder = mtk_hdmi_conn_best_enc,
1276 };
1277
1278 static void mtk_hdmi_hpd_event(bool hpd, struct device *dev)
1279 {
1280         struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1281
1282         if (hdmi && hdmi->bridge.encoder && hdmi->bridge.encoder->dev)
1283                 drm_helper_hpd_irq_event(hdmi->bridge.encoder->dev);
1284 }
1285
1286 /*
1287  * Bridge callbacks
1288  */
1289
1290 static int mtk_hdmi_bridge_attach(struct drm_bridge *bridge)
1291 {
1292         struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1293         int ret;
1294
1295         ret = drm_connector_init(bridge->encoder->dev, &hdmi->conn,
1296                                  &mtk_hdmi_connector_funcs,
1297                                  DRM_MODE_CONNECTOR_HDMIA);
1298         if (ret) {
1299                 dev_err(hdmi->dev, "Failed to initialize connector: %d\n", ret);
1300                 return ret;
1301         }
1302         drm_connector_helper_add(&hdmi->conn, &mtk_hdmi_connector_helper_funcs);
1303
1304         hdmi->conn.polled = DRM_CONNECTOR_POLL_HPD;
1305         hdmi->conn.interlace_allowed = true;
1306         hdmi->conn.doublescan_allowed = false;
1307
1308         ret = drm_connector_attach_encoder(&hdmi->conn,
1309                                                 bridge->encoder);
1310         if (ret) {
1311                 dev_err(hdmi->dev,
1312                         "Failed to attach connector to encoder: %d\n", ret);
1313                 return ret;
1314         }
1315
1316         if (hdmi->next_bridge) {
1317                 ret = drm_bridge_attach(bridge->encoder, hdmi->next_bridge,
1318                                         bridge);
1319                 if (ret) {
1320                         dev_err(hdmi->dev,
1321                                 "Failed to attach external bridge: %d\n", ret);
1322                         return ret;
1323                 }
1324         }
1325
1326         mtk_cec_set_hpd_event(hdmi->cec_dev, mtk_hdmi_hpd_event, hdmi->dev);
1327
1328         return 0;
1329 }
1330
1331 static bool mtk_hdmi_bridge_mode_fixup(struct drm_bridge *bridge,
1332                                        const struct drm_display_mode *mode,
1333                                        struct drm_display_mode *adjusted_mode)
1334 {
1335         return true;
1336 }
1337
1338 static void mtk_hdmi_bridge_disable(struct drm_bridge *bridge)
1339 {
1340         struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1341
1342         if (!hdmi->enabled)
1343                 return;
1344
1345         phy_power_off(hdmi->phy);
1346         clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_HDMI_PIXEL]);
1347         clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]);
1348
1349         hdmi->enabled = false;
1350 }
1351
1352 static void mtk_hdmi_bridge_post_disable(struct drm_bridge *bridge)
1353 {
1354         struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1355
1356         if (!hdmi->powered)
1357                 return;
1358
1359         mtk_hdmi_hw_1p4_version_enable(hdmi, true);
1360         mtk_hdmi_hw_make_reg_writable(hdmi, false);
1361
1362         hdmi->powered = false;
1363 }
1364
1365 static void mtk_hdmi_bridge_mode_set(struct drm_bridge *bridge,
1366                                 const struct drm_display_mode *mode,
1367                                 const struct drm_display_mode *adjusted_mode)
1368 {
1369         struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1370
1371         dev_dbg(hdmi->dev, "cur info: name:%s, hdisplay:%d\n",
1372                 adjusted_mode->name, adjusted_mode->hdisplay);
1373         dev_dbg(hdmi->dev, "hsync_start:%d,hsync_end:%d, htotal:%d",
1374                 adjusted_mode->hsync_start, adjusted_mode->hsync_end,
1375                 adjusted_mode->htotal);
1376         dev_dbg(hdmi->dev, "hskew:%d, vdisplay:%d\n",
1377                 adjusted_mode->hskew, adjusted_mode->vdisplay);
1378         dev_dbg(hdmi->dev, "vsync_start:%d, vsync_end:%d, vtotal:%d",
1379                 adjusted_mode->vsync_start, adjusted_mode->vsync_end,
1380                 adjusted_mode->vtotal);
1381         dev_dbg(hdmi->dev, "vscan:%d, flag:%d\n",
1382                 adjusted_mode->vscan, adjusted_mode->flags);
1383
1384         drm_mode_copy(&hdmi->mode, adjusted_mode);
1385 }
1386
1387 static void mtk_hdmi_bridge_pre_enable(struct drm_bridge *bridge)
1388 {
1389         struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1390
1391         mtk_hdmi_hw_make_reg_writable(hdmi, true);
1392         mtk_hdmi_hw_1p4_version_enable(hdmi, true);
1393
1394         hdmi->powered = true;
1395 }
1396
1397 static void mtk_hdmi_send_infoframe(struct mtk_hdmi *hdmi,
1398                                     struct drm_display_mode *mode)
1399 {
1400         mtk_hdmi_setup_audio_infoframe(hdmi);
1401         mtk_hdmi_setup_avi_infoframe(hdmi, mode);
1402         mtk_hdmi_setup_spd_infoframe(hdmi, "mediatek", "On-chip HDMI");
1403         if (mode->flags & DRM_MODE_FLAG_3D_MASK)
1404                 mtk_hdmi_setup_vendor_specific_infoframe(hdmi, mode);
1405 }
1406
1407 static void mtk_hdmi_bridge_enable(struct drm_bridge *bridge)
1408 {
1409         struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1410
1411         mtk_hdmi_output_set_display_mode(hdmi, &hdmi->mode);
1412         clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]);
1413         clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PIXEL]);
1414         phy_power_on(hdmi->phy);
1415         mtk_hdmi_send_infoframe(hdmi, &hdmi->mode);
1416
1417         hdmi->enabled = true;
1418 }
1419
1420 static const struct drm_bridge_funcs mtk_hdmi_bridge_funcs = {
1421         .attach = mtk_hdmi_bridge_attach,
1422         .mode_fixup = mtk_hdmi_bridge_mode_fixup,
1423         .disable = mtk_hdmi_bridge_disable,
1424         .post_disable = mtk_hdmi_bridge_post_disable,
1425         .mode_set = mtk_hdmi_bridge_mode_set,
1426         .pre_enable = mtk_hdmi_bridge_pre_enable,
1427         .enable = mtk_hdmi_bridge_enable,
1428 };
1429
1430 static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
1431                                    struct platform_device *pdev)
1432 {
1433         struct device *dev = &pdev->dev;
1434         struct device_node *np = dev->of_node;
1435         struct device_node *cec_np, *remote, *i2c_np;
1436         struct platform_device *cec_pdev;
1437         struct regmap *regmap;
1438         struct resource *mem;
1439         int ret;
1440
1441         ret = mtk_hdmi_get_all_clk(hdmi, np);
1442         if (ret) {
1443                 dev_err(dev, "Failed to get clocks: %d\n", ret);
1444                 return ret;
1445         }
1446
1447         /* The CEC module handles HDMI hotplug detection */
1448         cec_np = of_get_compatible_child(np->parent, "mediatek,mt8173-cec");
1449         if (!cec_np) {
1450                 dev_err(dev, "Failed to find CEC node\n");
1451                 return -EINVAL;
1452         }
1453
1454         cec_pdev = of_find_device_by_node(cec_np);
1455         if (!cec_pdev) {
1456                 dev_err(hdmi->dev, "Waiting for CEC device %pOF\n",
1457                         cec_np);
1458                 of_node_put(cec_np);
1459                 return -EPROBE_DEFER;
1460         }
1461         of_node_put(cec_np);
1462         hdmi->cec_dev = &cec_pdev->dev;
1463
1464         /*
1465          * The mediatek,syscon-hdmi property contains a phandle link to the
1466          * MMSYS_CONFIG device and the register offset of the HDMI_SYS_CFG
1467          * registers it contains.
1468          */
1469         regmap = syscon_regmap_lookup_by_phandle(np, "mediatek,syscon-hdmi");
1470         ret = of_property_read_u32_index(np, "mediatek,syscon-hdmi", 1,
1471                                          &hdmi->sys_offset);
1472         if (IS_ERR(regmap))
1473                 ret = PTR_ERR(regmap);
1474         if (ret) {
1475                 dev_err(dev,
1476                         "Failed to get system configuration registers: %d\n",
1477                         ret);
1478                 return ret;
1479         }
1480         hdmi->sys_regmap = regmap;
1481
1482         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1483         hdmi->regs = devm_ioremap_resource(dev, mem);
1484         if (IS_ERR(hdmi->regs))
1485                 return PTR_ERR(hdmi->regs);
1486
1487         remote = of_graph_get_remote_node(np, 1, 0);
1488         if (!remote)
1489                 return -EINVAL;
1490
1491         if (!of_device_is_compatible(remote, "hdmi-connector")) {
1492                 hdmi->next_bridge = of_drm_find_bridge(remote);
1493                 if (!hdmi->next_bridge) {
1494                         dev_err(dev, "Waiting for external bridge\n");
1495                         of_node_put(remote);
1496                         return -EPROBE_DEFER;
1497                 }
1498         }
1499
1500         i2c_np = of_parse_phandle(remote, "ddc-i2c-bus", 0);
1501         if (!i2c_np) {
1502                 dev_err(dev, "Failed to find ddc-i2c-bus node in %pOF\n",
1503                         remote);
1504                 of_node_put(remote);
1505                 return -EINVAL;
1506         }
1507         of_node_put(remote);
1508
1509         hdmi->ddc_adpt = of_find_i2c_adapter_by_node(i2c_np);
1510         of_node_put(i2c_np);
1511         if (!hdmi->ddc_adpt) {
1512                 dev_err(dev, "Failed to get ddc i2c adapter by node\n");
1513                 return -EINVAL;
1514         }
1515
1516         return 0;
1517 }
1518
1519 /*
1520  * HDMI audio codec callbacks
1521  */
1522
1523 static int mtk_hdmi_audio_hw_params(struct device *dev, void *data,
1524                                     struct hdmi_codec_daifmt *daifmt,
1525                                     struct hdmi_codec_params *params)
1526 {
1527         struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1528         struct hdmi_audio_param hdmi_params;
1529         unsigned int chan = params->cea.channels;
1530
1531         dev_dbg(hdmi->dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
1532                 params->sample_rate, params->sample_width, chan);
1533
1534         if (!hdmi->bridge.encoder)
1535                 return -ENODEV;
1536
1537         switch (chan) {
1538         case 2:
1539                 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_2_0;
1540                 break;
1541         case 4:
1542                 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_4_0;
1543                 break;
1544         case 6:
1545                 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_5_1;
1546                 break;
1547         case 8:
1548                 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_7_1;
1549                 break;
1550         default:
1551                 dev_err(hdmi->dev, "channel[%d] not supported!\n", chan);
1552                 return -EINVAL;
1553         }
1554
1555         switch (params->sample_rate) {
1556         case 32000:
1557         case 44100:
1558         case 48000:
1559         case 88200:
1560         case 96000:
1561         case 176400:
1562         case 192000:
1563                 break;
1564         default:
1565                 dev_err(hdmi->dev, "rate[%d] not supported!\n",
1566                         params->sample_rate);
1567                 return -EINVAL;
1568         }
1569
1570         switch (daifmt->fmt) {
1571         case HDMI_I2S:
1572                 hdmi_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
1573                 hdmi_params.aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16;
1574                 hdmi_params.aud_input_type = HDMI_AUD_INPUT_I2S;
1575                 hdmi_params.aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT;
1576                 hdmi_params.aud_mclk = HDMI_AUD_MCLK_128FS;
1577                 break;
1578         case HDMI_SPDIF:
1579                 hdmi_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
1580                 hdmi_params.aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16;
1581                 hdmi_params.aud_input_type = HDMI_AUD_INPUT_SPDIF;
1582                 break;
1583         default:
1584                 dev_err(hdmi->dev, "%s: Invalid DAI format %d\n", __func__,
1585                         daifmt->fmt);
1586                 return -EINVAL;
1587         }
1588
1589         memcpy(&hdmi_params.codec_params, params,
1590                sizeof(hdmi_params.codec_params));
1591
1592         mtk_hdmi_audio_set_param(hdmi, &hdmi_params);
1593
1594         return 0;
1595 }
1596
1597 static int mtk_hdmi_audio_startup(struct device *dev, void *data)
1598 {
1599         struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1600
1601         dev_dbg(dev, "%s\n", __func__);
1602
1603         mtk_hdmi_audio_enable(hdmi);
1604
1605         return 0;
1606 }
1607
1608 static void mtk_hdmi_audio_shutdown(struct device *dev, void *data)
1609 {
1610         struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1611
1612         dev_dbg(dev, "%s\n", __func__);
1613
1614         mtk_hdmi_audio_disable(hdmi);
1615 }
1616
1617 static int
1618 mtk_hdmi_audio_digital_mute(struct device *dev, void *data, bool enable)
1619 {
1620         struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1621
1622         dev_dbg(dev, "%s(%d)\n", __func__, enable);
1623
1624         if (enable)
1625                 mtk_hdmi_hw_aud_mute(hdmi);
1626         else
1627                 mtk_hdmi_hw_aud_unmute(hdmi);
1628
1629         return 0;
1630 }
1631
1632 static int mtk_hdmi_audio_get_eld(struct device *dev, void *data, uint8_t *buf, size_t len)
1633 {
1634         struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1635
1636         dev_dbg(dev, "%s\n", __func__);
1637
1638         memcpy(buf, hdmi->conn.eld, min(sizeof(hdmi->conn.eld), len));
1639
1640         return 0;
1641 }
1642
1643 static const struct hdmi_codec_ops mtk_hdmi_audio_codec_ops = {
1644         .hw_params = mtk_hdmi_audio_hw_params,
1645         .audio_startup = mtk_hdmi_audio_startup,
1646         .audio_shutdown = mtk_hdmi_audio_shutdown,
1647         .digital_mute = mtk_hdmi_audio_digital_mute,
1648         .get_eld = mtk_hdmi_audio_get_eld,
1649 };
1650
1651 static void mtk_hdmi_register_audio_driver(struct device *dev)
1652 {
1653         struct hdmi_codec_pdata codec_data = {
1654                 .ops = &mtk_hdmi_audio_codec_ops,
1655                 .max_i2s_channels = 2,
1656                 .i2s = 1,
1657         };
1658         struct platform_device *pdev;
1659
1660         pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
1661                                              PLATFORM_DEVID_AUTO, &codec_data,
1662                                              sizeof(codec_data));
1663         if (IS_ERR(pdev))
1664                 return;
1665
1666         DRM_INFO("%s driver bound to HDMI\n", HDMI_CODEC_DRV_NAME);
1667 }
1668
1669 static int mtk_drm_hdmi_probe(struct platform_device *pdev)
1670 {
1671         struct mtk_hdmi *hdmi;
1672         struct device *dev = &pdev->dev;
1673         int ret;
1674
1675         hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
1676         if (!hdmi)
1677                 return -ENOMEM;
1678
1679         hdmi->dev = dev;
1680
1681         ret = mtk_hdmi_dt_parse_pdata(hdmi, pdev);
1682         if (ret)
1683                 return ret;
1684
1685         hdmi->phy = devm_phy_get(dev, "hdmi");
1686         if (IS_ERR(hdmi->phy)) {
1687                 ret = PTR_ERR(hdmi->phy);
1688                 dev_err(dev, "Failed to get HDMI PHY: %d\n", ret);
1689                 return ret;
1690         }
1691
1692         platform_set_drvdata(pdev, hdmi);
1693
1694         ret = mtk_hdmi_output_init(hdmi);
1695         if (ret) {
1696                 dev_err(dev, "Failed to initialize hdmi output\n");
1697                 return ret;
1698         }
1699
1700         mtk_hdmi_register_audio_driver(dev);
1701
1702         hdmi->bridge.funcs = &mtk_hdmi_bridge_funcs;
1703         hdmi->bridge.of_node = pdev->dev.of_node;
1704         drm_bridge_add(&hdmi->bridge);
1705
1706         ret = mtk_hdmi_clk_enable_audio(hdmi);
1707         if (ret) {
1708                 dev_err(dev, "Failed to enable audio clocks: %d\n", ret);
1709                 goto err_bridge_remove;
1710         }
1711
1712         dev_dbg(dev, "mediatek hdmi probe success\n");
1713         return 0;
1714
1715 err_bridge_remove:
1716         drm_bridge_remove(&hdmi->bridge);
1717         return ret;
1718 }
1719
1720 static int mtk_drm_hdmi_remove(struct platform_device *pdev)
1721 {
1722         struct mtk_hdmi *hdmi = platform_get_drvdata(pdev);
1723
1724         drm_bridge_remove(&hdmi->bridge);
1725         mtk_hdmi_clk_disable_audio(hdmi);
1726         return 0;
1727 }
1728
1729 #ifdef CONFIG_PM_SLEEP
1730 static int mtk_hdmi_suspend(struct device *dev)
1731 {
1732         struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1733
1734         mtk_hdmi_clk_disable_audio(hdmi);
1735         dev_dbg(dev, "hdmi suspend success!\n");
1736         return 0;
1737 }
1738
1739 static int mtk_hdmi_resume(struct device *dev)
1740 {
1741         struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1742         int ret = 0;
1743
1744         ret = mtk_hdmi_clk_enable_audio(hdmi);
1745         if (ret) {
1746                 dev_err(dev, "hdmi resume failed!\n");
1747                 return ret;
1748         }
1749
1750         dev_dbg(dev, "hdmi resume success!\n");
1751         return 0;
1752 }
1753 #endif
1754 static SIMPLE_DEV_PM_OPS(mtk_hdmi_pm_ops,
1755                          mtk_hdmi_suspend, mtk_hdmi_resume);
1756
1757 static const struct of_device_id mtk_drm_hdmi_of_ids[] = {
1758         { .compatible = "mediatek,mt8173-hdmi", },
1759         {}
1760 };
1761
1762 static struct platform_driver mtk_hdmi_driver = {
1763         .probe = mtk_drm_hdmi_probe,
1764         .remove = mtk_drm_hdmi_remove,
1765         .driver = {
1766                 .name = "mediatek-drm-hdmi",
1767                 .of_match_table = mtk_drm_hdmi_of_ids,
1768                 .pm = &mtk_hdmi_pm_ops,
1769         },
1770 };
1771
1772 static struct platform_driver * const mtk_hdmi_drivers[] = {
1773         &mtk_hdmi_phy_driver,
1774         &mtk_hdmi_ddc_driver,
1775         &mtk_cec_driver,
1776         &mtk_hdmi_driver,
1777 };
1778
1779 static int __init mtk_hdmitx_init(void)
1780 {
1781         return platform_register_drivers(mtk_hdmi_drivers,
1782                                          ARRAY_SIZE(mtk_hdmi_drivers));
1783 }
1784
1785 static void __exit mtk_hdmitx_exit(void)
1786 {
1787         platform_unregister_drivers(mtk_hdmi_drivers,
1788                                     ARRAY_SIZE(mtk_hdmi_drivers));
1789 }
1790
1791 module_init(mtk_hdmitx_init);
1792 module_exit(mtk_hdmitx_exit);
1793
1794 MODULE_AUTHOR("Jie Qiu <jie.qiu@mediatek.com>");
1795 MODULE_DESCRIPTION("MediaTek HDMI Driver");
1796 MODULE_LICENSE("GPL v2");