drivers/gpu/drm/imx/ipuv3-crtc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * i.MX IPUv3 Graphics driver
   4  *
   5  * Copyright (C) 2011 Sascha Hauer, Pengutronix
   6  */
   7 #include <linux/clk.h>
   8 #include <linux/component.h>
   9 #include <linux/device.h>
  10 #include <linux/errno.h>
  11 #include <linux/export.h>
  12 #include <linux/module.h>
  13 #include <linux/platform_device.h>
  14 #include <drm/drmP.h>
  15 #include <drm/drm_atomic.h>
  16 #include <drm/drm_atomic_helper.h>
  17 #include <drm/drm_fb_cma_helper.h>
  18 #include <drm/drm_gem_cma_helper.h>
  19 #include <drm/drm_probe_helper.h>
  20
  21 #include <video/imx-ipu-v3.h>
  22 #include "imx-drm.h"
  23 #include "ipuv3-plane.h"
  24
  25 #define DRIVER_DESC             "i.MX IPUv3 Graphics"
  26
  27 struct ipu_crtc {
  28         struct device           *dev;
  29         struct drm_crtc         base;
  30
  31         /* plane[0] is the full plane, plane[1] is the partial plane */
  32         struct ipu_plane        *plane[2];
  33
  34         struct ipu_dc           *dc;
  35         struct ipu_di           *di;
  36         int                     irq;
  37 };
  38
  39 static inline struct ipu_crtc *to_ipu_crtc(struct drm_crtc *crtc)
  40 {
  41         return container_of(crtc, struct ipu_crtc, base);
  42 }
  43
  44 static void ipu_crtc_atomic_enable(struct drm_crtc *crtc,
  45                                    struct drm_crtc_state *old_state)
  46 {
  47         struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
  48         struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
  49
  50         ipu_prg_enable(ipu);
  51         ipu_dc_enable(ipu);
  52         ipu_dc_enable_channel(ipu_crtc->dc);
  53         ipu_di_enable(ipu_crtc->di);
  54 }
  55
  56 static void ipu_crtc_disable_planes(struct ipu_crtc *ipu_crtc,
  57                                     struct drm_crtc_state *old_crtc_state)
  58 {
  59         bool disable_partial = false;
  60         bool disable_full = false;
  61         struct drm_plane *plane;
  62
  63         drm_atomic_crtc_state_for_each_plane(plane, old_crtc_state) {
  64                 if (plane == &ipu_crtc->plane[0]->base)
  65                         disable_full = true;
  66                 if (&ipu_crtc->plane[1] && plane == &ipu_crtc->plane[1]->base)
  67                         disable_partial = true;
  68         }
  69
  70         if (disable_partial)
  71                 ipu_plane_disable(ipu_crtc->plane[1], true);
  72         if (disable_full)
  73                 ipu_plane_disable(ipu_crtc->plane[0], false);
  74 }
  75
  76 static void ipu_crtc_atomic_disable(struct drm_crtc *crtc,
  77                                     struct drm_crtc_state *old_crtc_state)
  78 {
  79         struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
  80         struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
  81
  82         ipu_dc_disable_channel(ipu_crtc->dc);
  83         ipu_di_disable(ipu_crtc->di);
  84         /*
  85          * Planes must be disabled before DC clock is removed, as otherwise the
  86          * attached IDMACs will be left in undefined state, possibly hanging
  87          * the IPU or even system.
  88          */
  89         ipu_crtc_disable_planes(ipu_crtc, old_crtc_state);
  90         ipu_dc_disable(ipu);
  91         ipu_prg_disable(ipu);
  92
  93         spin_lock_irq(&crtc->dev->event_lock);
  94         if (crtc->state->event) {
  95                 drm_crtc_send_vblank_event(crtc, crtc->state->event);
  96                 crtc->state->event = NULL;
  97         }
  98         spin_unlock_irq(&crtc->dev->event_lock);
  99
 100         drm_crtc_vblank_off(crtc);
 101 }
 102
 103 static void imx_drm_crtc_reset(struct drm_crtc *crtc)
 104 {
 105         struct imx_crtc_state *state;
 106
 107         if (crtc->state) {
 108                 if (crtc->state->mode_blob)
 109                         drm_property_blob_put(crtc->state->mode_blob);
 110
 111                 state = to_imx_crtc_state(crtc->state);
 112                 memset(state, 0, sizeof(*state));
 113         } else {
 114                 state = kzalloc(sizeof(*state), GFP_KERNEL);
 115                 if (!state)
 116                         return;
 117                 crtc->state = &state->base;
 118         }
 119
 120         state->base.crtc = crtc;
 121 }
 122
 123 static struct drm_crtc_state *imx_drm_crtc_duplicate_state(struct drm_crtc *crtc)
 124 {
 125         struct imx_crtc_state *state;
 126
 127         state = kzalloc(sizeof(*state), GFP_KERNEL);
 128         if (!state)
 129                 return NULL;
 130
 131         __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
 132
 133         WARN_ON(state->base.crtc != crtc);
 134         state->base.crtc = crtc;
 135
 136         return &state->base;
 137 }
 138
 139 static void imx_drm_crtc_destroy_state(struct drm_crtc *crtc,
 140                                        struct drm_crtc_state *state)
 141 {
 142         __drm_atomic_helper_crtc_destroy_state(state);
 143         kfree(to_imx_crtc_state(state));
 144 }
 145
 146 static int ipu_enable_vblank(struct drm_crtc *crtc)
 147 {
 148         struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
 149
 150         enable_irq(ipu_crtc->irq);
 151
 152         return 0;
 153 }
 154
 155 static void ipu_disable_vblank(struct drm_crtc *crtc)
 156 {
 157         struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
 158
 159         disable_irq_nosync(ipu_crtc->irq);
 160 }
 161
 162 static const struct drm_crtc_funcs ipu_crtc_funcs = {
 163         .set_config = drm_atomic_helper_set_config,
 164         .destroy = drm_crtc_cleanup,
 165         .page_flip = drm_atomic_helper_page_flip,
 166         .reset = imx_drm_crtc_reset,
 167         .atomic_duplicate_state = imx_drm_crtc_duplicate_state,
 168         .atomic_destroy_state = imx_drm_crtc_destroy_state,
 169         .enable_vblank = ipu_enable_vblank,
 170         .disable_vblank = ipu_disable_vblank,
 171 };
 172
 173 static irqreturn_t ipu_irq_handler(int irq, void *dev_id)
 174 {
 175         struct ipu_crtc *ipu_crtc = dev_id;
 176
 177         drm_crtc_handle_vblank(&ipu_crtc->base);
 178
 179         return IRQ_HANDLED;
 180 }
 181
 182 static bool ipu_crtc_mode_fixup(struct drm_crtc *crtc,
 183                                   const struct drm_display_mode *mode,
 184                                   struct drm_display_mode *adjusted_mode)
 185 {
 186         struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
 187         struct videomode vm;
 188         int ret;
 189
 190         drm_display_mode_to_videomode(adjusted_mode, &vm);
 191
 192         ret = ipu_di_adjust_videomode(ipu_crtc->di, &vm);
 193         if (ret)
 194                 return false;
 195
 196         if ((vm.vsync_len == 0) || (vm.hsync_len == 0))
 197                 return false;
 198
 199         drm_display_mode_from_videomode(&vm, adjusted_mode);
 200
 201         return true;
 202 }
 203
 204 static int ipu_crtc_atomic_check(struct drm_crtc *crtc,
 205                                  struct drm_crtc_state *state)
 206 {
 207         u32 primary_plane_mask = drm_plane_mask(crtc->primary);
 208
 209         if (state->active && (primary_plane_mask & state->plane_mask) == 0)
 210                 return -EINVAL;
 211
 212         return 0;
 213 }
 214
 215 static void ipu_crtc_atomic_begin(struct drm_crtc *crtc,
 216                                   struct drm_crtc_state *old_crtc_state)
 217 {
 218         drm_crtc_vblank_on(crtc);
 219 }
 220
 221 static void ipu_crtc_atomic_flush(struct drm_crtc *crtc,
 222                                   struct drm_crtc_state *old_crtc_state)
 223 {
 224         spin_lock_irq(&crtc->dev->event_lock);
 225         if (crtc->state->event) {
 226                 WARN_ON(drm_crtc_vblank_get(crtc));
 227                 drm_crtc_arm_vblank_event(crtc, crtc->state->event);
 228                 crtc->state->event = NULL;
 229         }
 230         spin_unlock_irq(&crtc->dev->event_lock);
 231 }
 232
 233 static void ipu_crtc_mode_set_nofb(struct drm_crtc *crtc)
 234 {
 235         struct drm_device *dev = crtc->dev;
 236         struct drm_encoder *encoder;
 237         struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
 238         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
 239         struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc->state);
 240         struct ipu_di_signal_cfg sig_cfg = {};
 241         unsigned long encoder_types = 0;
 242
 243         dev_dbg(ipu_crtc->dev, "%s: mode->hdisplay: %d\n", __func__,
 244                         mode->hdisplay);
 245         dev_dbg(ipu_crtc->dev, "%s: mode->vdisplay: %d\n", __func__,
 246                         mode->vdisplay);
 247
 248         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 249                 if (encoder->crtc == crtc)
 250                         encoder_types |= BIT(encoder->encoder_type);
 251         }
 252
 253         dev_dbg(ipu_crtc->dev, "%s: attached to encoder types 0x%lx\n",
 254                 __func__, encoder_types);
 255
 256         /*
 257          * If we have DAC or LDB, then we need the IPU DI clock to be
 258          * the same as the LDB DI clock. For TVDAC, derive the IPU DI
 259          * clock from 27 MHz TVE_DI clock, but allow to divide it.
 260          */
 261         if (encoder_types & (BIT(DRM_MODE_ENCODER_DAC) |
 262                              BIT(DRM_MODE_ENCODER_LVDS)))
 263                 sig_cfg.clkflags = IPU_DI_CLKMODE_SYNC | IPU_DI_CLKMODE_EXT;
 264         else if (encoder_types & BIT(DRM_MODE_ENCODER_TVDAC))
 265                 sig_cfg.clkflags = IPU_DI_CLKMODE_EXT;
 266         else
 267                 sig_cfg.clkflags = 0;
 268
 269         sig_cfg.enable_pol = !(imx_crtc_state->bus_flags & DRM_BUS_FLAG_DE_LOW);
 270         /* Default to driving pixel data on negative clock edges */
 271         sig_cfg.clk_pol = !!(imx_crtc_state->bus_flags &
 272                              DRM_BUS_FLAG_PIXDATA_POSEDGE);
 273         sig_cfg.bus_format = imx_crtc_state->bus_format;
 274         sig_cfg.v_to_h_sync = 0;
 275         sig_cfg.hsync_pin = imx_crtc_state->di_hsync_pin;
 276         sig_cfg.vsync_pin = imx_crtc_state->di_vsync_pin;
 277
 278         drm_display_mode_to_videomode(mode, &sig_cfg.mode);
 279
 280         ipu_dc_init_sync(ipu_crtc->dc, ipu_crtc->di,
 281                          mode->flags & DRM_MODE_FLAG_INTERLACE,
 282                          imx_crtc_state->bus_format, mode->hdisplay);
 283         ipu_di_init_sync_panel(ipu_crtc->di, &sig_cfg);
 284 }
 285
 286 static const struct drm_crtc_helper_funcs ipu_helper_funcs = {
 287         .mode_fixup = ipu_crtc_mode_fixup,
 288         .mode_set_nofb = ipu_crtc_mode_set_nofb,
 289         .atomic_check = ipu_crtc_atomic_check,
 290         .atomic_begin = ipu_crtc_atomic_begin,
 291         .atomic_flush = ipu_crtc_atomic_flush,
 292         .atomic_disable = ipu_crtc_atomic_disable,
 293         .atomic_enable = ipu_crtc_atomic_enable,
 294 };
 295
 296 static void ipu_put_resources(struct ipu_crtc *ipu_crtc)
 297 {
 298         if (!IS_ERR_OR_NULL(ipu_crtc->dc))
 299                 ipu_dc_put(ipu_crtc->dc);
 300         if (!IS_ERR_OR_NULL(ipu_crtc->di))
 301                 ipu_di_put(ipu_crtc->di);
 302 }
 303
 304 static int ipu_get_resources(struct ipu_crtc *ipu_crtc,
 305                 struct ipu_client_platformdata *pdata)
 306 {
 307         struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
 308         int ret;
 309
 310         ipu_crtc->dc = ipu_dc_get(ipu, pdata->dc);
 311         if (IS_ERR(ipu_crtc->dc)) {
 312                 ret = PTR_ERR(ipu_crtc->dc);
 313                 goto err_out;
 314         }
 315
 316         ipu_crtc->di = ipu_di_get(ipu, pdata->di);
 317         if (IS_ERR(ipu_crtc->di)) {
 318                 ret = PTR_ERR(ipu_crtc->di);
 319                 goto err_out;
 320         }
 321
 322         return 0;
 323 err_out:
 324         ipu_put_resources(ipu_crtc);
 325
 326         return ret;
 327 }
 328
 329 static int ipu_crtc_init(struct ipu_crtc *ipu_crtc,
 330         struct ipu_client_platformdata *pdata, struct drm_device *drm)
 331 {
 332         struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
 333         struct drm_crtc *crtc = &ipu_crtc->base;
 334         int dp = -EINVAL;
 335         int ret;
 336
 337         ret = ipu_get_resources(ipu_crtc, pdata);
 338         if (ret) {
 339                 dev_err(ipu_crtc->dev, "getting resources failed with %d.\n",
 340                                 ret);
 341                 return ret;
 342         }
 343
 344         if (pdata->dp >= 0)
 345                 dp = IPU_DP_FLOW_SYNC_BG;
 346         ipu_crtc->plane[0] = ipu_plane_init(drm, ipu, pdata->dma[0], dp, 0,
 347                                             DRM_PLANE_TYPE_PRIMARY);
 348         if (IS_ERR(ipu_crtc->plane[0])) {
 349                 ret = PTR_ERR(ipu_crtc->plane[0]);
 350                 goto err_put_resources;
 351         }
 352
 353         crtc->port = pdata->of_node;
 354         drm_crtc_helper_add(crtc, &ipu_helper_funcs);
 355         drm_crtc_init_with_planes(drm, crtc, &ipu_crtc->plane[0]->base, NULL,
 356                                   &ipu_crtc_funcs, NULL);
 357
 358         ret = ipu_plane_get_resources(ipu_crtc->plane[0]);
 359         if (ret) {
 360                 dev_err(ipu_crtc->dev, "getting plane 0 resources failed with %d.\n",
 361                         ret);
 362                 goto err_put_resources;
 363         }
 364
 365         /* If this crtc is using the DP, add an overlay plane */
 366         if (pdata->dp >= 0 && pdata->dma[1] > 0) {
 367                 ipu_crtc->plane[1] = ipu_plane_init(drm, ipu, pdata->dma[1],
 368                                                 IPU_DP_FLOW_SYNC_FG,
 369                                                 drm_crtc_mask(&ipu_crtc->base),
 370                                                 DRM_PLANE_TYPE_OVERLAY);
 371                 if (IS_ERR(ipu_crtc->plane[1])) {
 372                         ipu_crtc->plane[1] = NULL;
 373                 } else {
 374                         ret = ipu_plane_get_resources(ipu_crtc->plane[1]);
 375                         if (ret) {
 376                                 dev_err(ipu_crtc->dev, "getting plane 1 "
 377                                         "resources failed with %d.\n", ret);
 378                                 goto err_put_plane0_res;
 379                         }
 380                 }
 381         }
 382
 383         ipu_crtc->irq = ipu_plane_irq(ipu_crtc->plane[0]);
 384         ret = devm_request_irq(ipu_crtc->dev, ipu_crtc->irq, ipu_irq_handler, 0,
 385                         "imx_drm", ipu_crtc);
 386         if (ret < 0) {
 387                 dev_err(ipu_crtc->dev, "irq request failed with %d.\n", ret);
 388                 goto err_put_plane1_res;
 389         }
 390         /* Only enable IRQ when we actually need it to trigger work. */
 391         disable_irq(ipu_crtc->irq);
 392
 393         return 0;
 394
 395 err_put_plane1_res:
 396         if (ipu_crtc->plane[1])
 397                 ipu_plane_put_resources(ipu_crtc->plane[1]);
 398 err_put_plane0_res:
 399         ipu_plane_put_resources(ipu_crtc->plane[0]);
 400 err_put_resources:
 401         ipu_put_resources(ipu_crtc);
 402
 403         return ret;
 404 }
 405
 406 static int ipu_drm_bind(struct device *dev, struct device *master, void *data)
 407 {
 408         struct ipu_client_platformdata *pdata = dev->platform_data;
 409         struct drm_device *drm = data;
 410         struct ipu_crtc *ipu_crtc;
 411         int ret;
 412
 413         ipu_crtc = devm_kzalloc(dev, sizeof(*ipu_crtc), GFP_KERNEL);
 414         if (!ipu_crtc)
 415                 return -ENOMEM;
 416
 417         ipu_crtc->dev = dev;
 418
 419         ret = ipu_crtc_init(ipu_crtc, pdata, drm);
 420         if (ret)
 421                 return ret;
 422
 423         dev_set_drvdata(dev, ipu_crtc);
 424
 425         return 0;
 426 }
 427
 428 static void ipu_drm_unbind(struct device *dev, struct device *master,
 429         void *data)
 430 {
 431         struct ipu_crtc *ipu_crtc = dev_get_drvdata(dev);
 432
 433         ipu_put_resources(ipu_crtc);
 434         if (ipu_crtc->plane[1])
 435                 ipu_plane_put_resources(ipu_crtc->plane[1]);
 436         ipu_plane_put_resources(ipu_crtc->plane[0]);
 437 }
 438
 439 static const struct component_ops ipu_crtc_ops = {
 440         .bind = ipu_drm_bind,
 441         .unbind = ipu_drm_unbind,
 442 };
 443
 444 static int ipu_drm_probe(struct platform_device *pdev)
 445 {
 446         struct device *dev = &pdev->dev;
 447         int ret;
 448
 449         if (!dev->platform_data)
 450                 return -EINVAL;
 451
 452         ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
 453         if (ret)
 454                 return ret;
 455
 456         return component_add(dev, &ipu_crtc_ops);
 457 }
 458
 459 static int ipu_drm_remove(struct platform_device *pdev)
 460 {
 461         component_del(&pdev->dev, &ipu_crtc_ops);
 462         return 0;
 463 }
 464
 465 struct platform_driver ipu_drm_driver = {
 466         .driver = {
 467                 .name = "imx-ipuv3-crtc",
 468         },
 469         .probe = ipu_drm_probe,
 470         .remove = ipu_drm_remove,
 471 };