2 * SPDX-License-Identifier: MIT
4 * Copyright © 2018 Intel Corporation
7 #include "../i915_selftest.h"
9 #include "igt_flush_test.h"
10 #include "igt_reset.h"
11 #include "igt_spinner.h"
12 #include "igt_wedge_me.h"
13 #include "mock_context.h"
15 static struct drm_i915_gem_object *
16 read_nonprivs(struct i915_gem_context *ctx, struct intel_engine_cs *engine)
18 struct drm_i915_gem_object *result;
19 struct i915_request *rq;
21 const u32 base = engine->mmio_base;
26 result = i915_gem_object_create_internal(engine->i915, PAGE_SIZE);
30 i915_gem_object_set_cache_level(result, I915_CACHE_LLC);
32 cs = i915_gem_object_pin_map(result, I915_MAP_WB);
37 memset(cs, 0xc5, PAGE_SIZE);
38 i915_gem_object_unpin_map(result);
40 vma = i915_vma_instance(result, &engine->i915->ggtt.vm, NULL);
46 err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL);
50 intel_runtime_pm_get(engine->i915);
51 rq = i915_request_alloc(engine, ctx);
52 intel_runtime_pm_put(engine->i915);
58 err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
62 srm = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
63 if (INTEL_GEN(ctx->i915) >= 8)
66 cs = intel_ring_begin(rq, 4 * RING_MAX_NONPRIV_SLOTS);
72 for (i = 0; i < RING_MAX_NONPRIV_SLOTS; i++) {
74 *cs++ = i915_mmio_reg_offset(RING_FORCE_TO_NONPRIV(base, i));
75 *cs++ = i915_ggtt_offset(vma) + sizeof(u32) * i;
78 intel_ring_advance(rq, cs);
80 i915_gem_object_get(result);
81 i915_gem_object_set_active_reference(result);
93 i915_gem_object_put(result);
98 get_whitelist_reg(const struct intel_engine_cs *engine, unsigned int i)
100 i915_reg_t reg = i < engine->whitelist.count ?
101 engine->whitelist.list[i].reg :
102 RING_NOPID(engine->mmio_base);
104 return i915_mmio_reg_offset(reg);
108 print_results(const struct intel_engine_cs *engine, const u32 *results)
112 for (i = 0; i < RING_MAX_NONPRIV_SLOTS; i++) {
113 u32 expected = get_whitelist_reg(engine, i);
114 u32 actual = results[i];
116 pr_info("RING_NONPRIV[%d]: expected 0x%08x, found 0x%08x\n",
117 i, expected, actual);
121 static int check_whitelist(struct i915_gem_context *ctx,
122 struct intel_engine_cs *engine)
124 struct drm_i915_gem_object *results;
125 struct igt_wedge_me wedge;
130 results = read_nonprivs(ctx, engine);
132 return PTR_ERR(results);
135 igt_wedge_on_timeout(&wedge, ctx->i915, HZ / 5) /* a safety net! */
136 err = i915_gem_object_set_to_cpu_domain(results, false);
137 if (i915_terminally_wedged(&ctx->i915->gpu_error))
142 vaddr = i915_gem_object_pin_map(results, I915_MAP_WB);
144 err = PTR_ERR(vaddr);
148 for (i = 0; i < RING_MAX_NONPRIV_SLOTS; i++) {
149 u32 expected = get_whitelist_reg(engine, i);
150 u32 actual = vaddr[i];
152 if (expected != actual) {
153 print_results(engine, vaddr);
154 pr_err("Invalid RING_NONPRIV[%d], expected 0x%08x, found 0x%08x\n",
155 i, expected, actual);
162 i915_gem_object_unpin_map(results);
164 i915_gem_object_put(results);
168 static int do_device_reset(struct intel_engine_cs *engine)
170 set_bit(I915_RESET_HANDOFF, &engine->i915->gpu_error.flags);
171 i915_reset(engine->i915, ENGINE_MASK(engine->id), "live_workarounds");
175 static int do_engine_reset(struct intel_engine_cs *engine)
177 return i915_reset_engine(engine, "live_workarounds");
181 switch_to_scratch_context(struct intel_engine_cs *engine,
182 struct igt_spinner *spin)
184 struct i915_gem_context *ctx;
185 struct i915_request *rq;
188 ctx = kernel_context(engine->i915);
192 intel_runtime_pm_get(engine->i915);
195 rq = igt_spinner_create_request(spin, ctx, engine, MI_NOOP);
197 rq = i915_request_alloc(engine, ctx);
199 intel_runtime_pm_put(engine->i915);
201 kernel_context_close(ctx);
209 i915_request_add(rq);
211 if (spin && !igt_wait_for_spinner(spin, rq)) {
212 pr_err("Spinner failed to start\n");
218 igt_spinner_end(spin);
223 static int check_whitelist_across_reset(struct intel_engine_cs *engine,
224 int (*reset)(struct intel_engine_cs *),
227 struct drm_i915_private *i915 = engine->i915;
228 bool want_spin = reset == do_engine_reset;
229 struct i915_gem_context *ctx;
230 struct igt_spinner spin;
233 pr_info("Checking %d whitelisted registers (RING_NONPRIV) [%s]\n",
234 engine->whitelist.count, name);
237 err = igt_spinner_init(&spin, i915);
242 ctx = kernel_context(i915);
246 err = check_whitelist(ctx, engine);
248 pr_err("Invalid whitelist *before* %s reset!\n", name);
252 err = switch_to_scratch_context(engine, want_spin ? &spin : NULL);
256 intel_runtime_pm_get(i915);
258 intel_runtime_pm_put(i915);
261 igt_spinner_end(&spin);
262 igt_spinner_fini(&spin);
266 pr_err("%s reset failed\n", name);
270 err = check_whitelist(ctx, engine);
272 pr_err("Whitelist not preserved in context across %s reset!\n",
277 kernel_context_close(ctx);
279 ctx = kernel_context(i915);
283 err = check_whitelist(ctx, engine);
285 pr_err("Invalid whitelist *after* %s reset in fresh context!\n",
291 kernel_context_close(ctx);
295 static int live_reset_whitelist(void *arg)
297 struct drm_i915_private *i915 = arg;
298 struct intel_engine_cs *engine = i915->engine[RCS];
301 /* If we reset the gpu, we should not lose the RING_NONPRIV */
303 if (!engine || engine->whitelist.count == 0)
306 igt_global_reset_lock(i915);
308 if (intel_has_reset_engine(i915)) {
309 err = check_whitelist_across_reset(engine,
316 if (intel_has_gpu_reset(i915)) {
317 err = check_whitelist_across_reset(engine,
325 igt_global_reset_unlock(i915);
329 static bool verify_gt_engine_wa(struct drm_i915_private *i915, const char *str)
331 struct intel_engine_cs *engine;
332 enum intel_engine_id id;
335 ok &= intel_gt_verify_workarounds(i915, str);
336 for_each_engine(engine, i915, id)
337 ok &= intel_engine_verify_workarounds(engine, str);
343 live_gpu_reset_gt_engine_workarounds(void *arg)
345 struct drm_i915_private *i915 = arg;
346 struct i915_gpu_error *error = &i915->gpu_error;
349 if (!intel_has_gpu_reset(i915))
352 pr_info("Verifying after GPU reset...\n");
354 igt_global_reset_lock(i915);
355 intel_runtime_pm_get(i915);
357 ok = verify_gt_engine_wa(i915, "before reset");
361 set_bit(I915_RESET_HANDOFF, &error->flags);
362 i915_reset(i915, ALL_ENGINES, "live_workarounds");
364 ok = verify_gt_engine_wa(i915, "after reset");
367 intel_runtime_pm_put(i915);
368 igt_global_reset_unlock(i915);
370 return ok ? 0 : -ESRCH;
374 live_engine_reset_gt_engine_workarounds(void *arg)
376 struct drm_i915_private *i915 = arg;
377 struct intel_engine_cs *engine;
378 struct i915_gem_context *ctx;
379 struct igt_spinner spin;
380 enum intel_engine_id id;
381 struct i915_request *rq;
384 if (!intel_has_reset_engine(i915))
387 ctx = kernel_context(i915);
391 igt_global_reset_lock(i915);
392 intel_runtime_pm_get(i915);
394 for_each_engine(engine, i915, id) {
397 pr_info("Verifying after %s reset...\n", engine->name);
399 ok = verify_gt_engine_wa(i915, "before reset");
405 i915_reset_engine(engine, "live_workarounds");
407 ok = verify_gt_engine_wa(i915, "after idle reset");
413 ret = igt_spinner_init(&spin, i915);
417 rq = igt_spinner_create_request(&spin, ctx, engine, MI_NOOP);
420 igt_spinner_fini(&spin);
424 i915_request_add(rq);
426 if (!igt_wait_for_spinner(&spin, rq)) {
427 pr_err("Spinner failed to start\n");
428 igt_spinner_fini(&spin);
433 i915_reset_engine(engine, "live_workarounds");
435 igt_spinner_end(&spin);
436 igt_spinner_fini(&spin);
438 ok = verify_gt_engine_wa(i915, "after busy reset");
446 intel_runtime_pm_put(i915);
447 igt_global_reset_unlock(i915);
448 kernel_context_close(ctx);
450 igt_flush_test(i915, I915_WAIT_LOCKED);
455 int intel_workarounds_live_selftests(struct drm_i915_private *i915)
457 static const struct i915_subtest tests[] = {
458 SUBTEST(live_reset_whitelist),
459 SUBTEST(live_gpu_reset_gt_engine_workarounds),
460 SUBTEST(live_engine_reset_gt_engine_workarounds),
464 if (i915_terminally_wedged(&i915->gpu_error))
467 mutex_lock(&i915->drm.struct_mutex);
468 err = i915_subtests(tests, i915);
469 mutex_unlock(&i915->drm.struct_mutex);