2 * SPDX-License-Identifier: MIT
4 * Copyright © 2018 Intel Corporation
7 #include "../i915_selftest.h"
9 #include "igt_flush_test.h"
10 #include "igt_reset.h"
11 #include "igt_spinner.h"
12 #include "igt_wedge_me.h"
13 #include "mock_context.h"
15 #define REF_NAME_MAX (INTEL_ENGINE_CS_MAX_NAME + 4)
17 struct i915_wa_list gt_wa_list;
19 char name[REF_NAME_MAX];
20 struct i915_wa_list wa_list;
21 } engine[I915_NUM_ENGINES];
25 reference_lists_init(struct drm_i915_private *i915, struct wa_lists *lists)
27 struct intel_engine_cs *engine;
28 enum intel_engine_id id;
30 memset(lists, 0, sizeof(*lists));
32 wa_init_start(&lists->gt_wa_list, "GT_REF");
33 gt_init_workarounds(i915, &lists->gt_wa_list);
34 wa_init_finish(&lists->gt_wa_list);
36 for_each_engine(engine, i915, id) {
37 struct i915_wa_list *wal = &lists->engine[id].wa_list;
38 char *name = lists->engine[id].name;
40 snprintf(name, REF_NAME_MAX, "%s_REF", engine->name);
42 wa_init_start(wal, name);
43 engine_init_workarounds(engine, wal);
49 reference_lists_fini(struct drm_i915_private *i915, struct wa_lists *lists)
51 struct intel_engine_cs *engine;
52 enum intel_engine_id id;
54 for_each_engine(engine, i915, id)
55 intel_wa_list_free(&lists->engine[id].wa_list);
57 intel_wa_list_free(&lists->gt_wa_list);
60 static struct drm_i915_gem_object *
61 read_nonprivs(struct i915_gem_context *ctx, struct intel_engine_cs *engine)
63 struct drm_i915_gem_object *result;
64 struct i915_request *rq;
66 const u32 base = engine->mmio_base;
71 result = i915_gem_object_create_internal(engine->i915, PAGE_SIZE);
75 i915_gem_object_set_cache_level(result, I915_CACHE_LLC);
77 cs = i915_gem_object_pin_map(result, I915_MAP_WB);
82 memset(cs, 0xc5, PAGE_SIZE);
83 i915_gem_object_unpin_map(result);
85 vma = i915_vma_instance(result, &engine->i915->ggtt.vm, NULL);
91 err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL);
95 intel_runtime_pm_get(engine->i915);
96 rq = i915_request_alloc(engine, ctx);
97 intel_runtime_pm_put_unchecked(engine->i915);
103 err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
107 srm = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
108 if (INTEL_GEN(ctx->i915) >= 8)
111 cs = intel_ring_begin(rq, 4 * RING_MAX_NONPRIV_SLOTS);
117 for (i = 0; i < RING_MAX_NONPRIV_SLOTS; i++) {
119 *cs++ = i915_mmio_reg_offset(RING_FORCE_TO_NONPRIV(base, i));
120 *cs++ = i915_ggtt_offset(vma) + sizeof(u32) * i;
123 intel_ring_advance(rq, cs);
125 i915_gem_object_get(result);
126 i915_gem_object_set_active_reference(result);
128 i915_request_add(rq);
134 i915_request_add(rq);
138 i915_gem_object_put(result);
143 get_whitelist_reg(const struct intel_engine_cs *engine, unsigned int i)
145 i915_reg_t reg = i < engine->whitelist.count ?
146 engine->whitelist.list[i].reg :
147 RING_NOPID(engine->mmio_base);
149 return i915_mmio_reg_offset(reg);
153 print_results(const struct intel_engine_cs *engine, const u32 *results)
157 for (i = 0; i < RING_MAX_NONPRIV_SLOTS; i++) {
158 u32 expected = get_whitelist_reg(engine, i);
159 u32 actual = results[i];
161 pr_info("RING_NONPRIV[%d]: expected 0x%08x, found 0x%08x\n",
162 i, expected, actual);
166 static int check_whitelist(struct i915_gem_context *ctx,
167 struct intel_engine_cs *engine)
169 struct drm_i915_gem_object *results;
170 struct igt_wedge_me wedge;
175 results = read_nonprivs(ctx, engine);
177 return PTR_ERR(results);
180 igt_wedge_on_timeout(&wedge, ctx->i915, HZ / 5) /* a safety net! */
181 err = i915_gem_object_set_to_cpu_domain(results, false);
182 if (i915_terminally_wedged(&ctx->i915->gpu_error))
187 vaddr = i915_gem_object_pin_map(results, I915_MAP_WB);
189 err = PTR_ERR(vaddr);
193 for (i = 0; i < RING_MAX_NONPRIV_SLOTS; i++) {
194 u32 expected = get_whitelist_reg(engine, i);
195 u32 actual = vaddr[i];
197 if (expected != actual) {
198 print_results(engine, vaddr);
199 pr_err("Invalid RING_NONPRIV[%d], expected 0x%08x, found 0x%08x\n",
200 i, expected, actual);
207 i915_gem_object_unpin_map(results);
209 i915_gem_object_put(results);
213 static int do_device_reset(struct intel_engine_cs *engine)
215 set_bit(I915_RESET_HANDOFF, &engine->i915->gpu_error.flags);
216 i915_reset(engine->i915, ENGINE_MASK(engine->id), "live_workarounds");
220 static int do_engine_reset(struct intel_engine_cs *engine)
222 return i915_reset_engine(engine, "live_workarounds");
226 switch_to_scratch_context(struct intel_engine_cs *engine,
227 struct igt_spinner *spin)
229 struct i915_gem_context *ctx;
230 struct i915_request *rq;
233 ctx = kernel_context(engine->i915);
237 intel_runtime_pm_get(engine->i915);
240 rq = igt_spinner_create_request(spin, ctx, engine, MI_NOOP);
242 rq = i915_request_alloc(engine, ctx);
244 intel_runtime_pm_put_unchecked(engine->i915);
246 kernel_context_close(ctx);
254 i915_request_add(rq);
256 if (spin && !igt_wait_for_spinner(spin, rq)) {
257 pr_err("Spinner failed to start\n");
263 igt_spinner_end(spin);
268 static int check_whitelist_across_reset(struct intel_engine_cs *engine,
269 int (*reset)(struct intel_engine_cs *),
272 struct drm_i915_private *i915 = engine->i915;
273 bool want_spin = reset == do_engine_reset;
274 struct i915_gem_context *ctx;
275 struct igt_spinner spin;
278 pr_info("Checking %d whitelisted registers (RING_NONPRIV) [%s]\n",
279 engine->whitelist.count, name);
282 err = igt_spinner_init(&spin, i915);
287 ctx = kernel_context(i915);
291 err = check_whitelist(ctx, engine);
293 pr_err("Invalid whitelist *before* %s reset!\n", name);
297 err = switch_to_scratch_context(engine, want_spin ? &spin : NULL);
301 intel_runtime_pm_get(i915);
303 intel_runtime_pm_put_unchecked(i915);
306 igt_spinner_end(&spin);
307 igt_spinner_fini(&spin);
311 pr_err("%s reset failed\n", name);
315 err = check_whitelist(ctx, engine);
317 pr_err("Whitelist not preserved in context across %s reset!\n",
322 kernel_context_close(ctx);
324 ctx = kernel_context(i915);
328 err = check_whitelist(ctx, engine);
330 pr_err("Invalid whitelist *after* %s reset in fresh context!\n",
336 kernel_context_close(ctx);
340 static int live_reset_whitelist(void *arg)
342 struct drm_i915_private *i915 = arg;
343 struct intel_engine_cs *engine = i915->engine[RCS];
346 /* If we reset the gpu, we should not lose the RING_NONPRIV */
348 if (!engine || engine->whitelist.count == 0)
351 igt_global_reset_lock(i915);
353 if (intel_has_reset_engine(i915)) {
354 err = check_whitelist_across_reset(engine,
361 if (intel_has_gpu_reset(i915)) {
362 err = check_whitelist_across_reset(engine,
370 igt_global_reset_unlock(i915);
374 static bool verify_gt_engine_wa(struct drm_i915_private *i915,
375 struct wa_lists *lists, const char *str)
377 struct intel_engine_cs *engine;
378 enum intel_engine_id id;
381 ok &= wa_list_verify(i915, &lists->gt_wa_list, str);
383 for_each_engine(engine, i915, id)
384 ok &= wa_list_verify(i915, &lists->engine[id].wa_list, str);
390 live_gpu_reset_gt_engine_workarounds(void *arg)
392 struct drm_i915_private *i915 = arg;
393 struct i915_gpu_error *error = &i915->gpu_error;
394 struct wa_lists lists;
397 if (!intel_has_gpu_reset(i915))
400 pr_info("Verifying after GPU reset...\n");
402 igt_global_reset_lock(i915);
403 intel_runtime_pm_get(i915);
404 reference_lists_init(i915, &lists);
406 ok = verify_gt_engine_wa(i915, &lists, "before reset");
410 set_bit(I915_RESET_HANDOFF, &error->flags);
411 i915_reset(i915, ALL_ENGINES, "live_workarounds");
413 ok = verify_gt_engine_wa(i915, &lists, "after reset");
416 reference_lists_fini(i915, &lists);
417 intel_runtime_pm_put_unchecked(i915);
418 igt_global_reset_unlock(i915);
420 return ok ? 0 : -ESRCH;
424 live_engine_reset_gt_engine_workarounds(void *arg)
426 struct drm_i915_private *i915 = arg;
427 struct intel_engine_cs *engine;
428 struct i915_gem_context *ctx;
429 struct igt_spinner spin;
430 enum intel_engine_id id;
431 struct i915_request *rq;
432 struct wa_lists lists;
435 if (!intel_has_reset_engine(i915))
438 ctx = kernel_context(i915);
442 igt_global_reset_lock(i915);
443 intel_runtime_pm_get(i915);
444 reference_lists_init(i915, &lists);
446 for_each_engine(engine, i915, id) {
449 pr_info("Verifying after %s reset...\n", engine->name);
451 ok = verify_gt_engine_wa(i915, &lists, "before reset");
457 i915_reset_engine(engine, "live_workarounds");
459 ok = verify_gt_engine_wa(i915, &lists, "after idle reset");
465 ret = igt_spinner_init(&spin, i915);
469 rq = igt_spinner_create_request(&spin, ctx, engine, MI_NOOP);
472 igt_spinner_fini(&spin);
476 i915_request_add(rq);
478 if (!igt_wait_for_spinner(&spin, rq)) {
479 pr_err("Spinner failed to start\n");
480 igt_spinner_fini(&spin);
485 i915_reset_engine(engine, "live_workarounds");
487 igt_spinner_end(&spin);
488 igt_spinner_fini(&spin);
490 ok = verify_gt_engine_wa(i915, &lists, "after busy reset");
498 reference_lists_fini(i915, &lists);
499 intel_runtime_pm_put_unchecked(i915);
500 igt_global_reset_unlock(i915);
501 kernel_context_close(ctx);
503 igt_flush_test(i915, I915_WAIT_LOCKED);
508 int intel_workarounds_live_selftests(struct drm_i915_private *i915)
510 static const struct i915_subtest tests[] = {
511 SUBTEST(live_reset_whitelist),
512 SUBTEST(live_gpu_reset_gt_engine_workarounds),
513 SUBTEST(live_engine_reset_gt_engine_workarounds),
517 if (i915_terminally_wedged(&i915->gpu_error))
520 mutex_lock(&i915->drm.struct_mutex);
521 err = i915_subtests(tests, i915);
522 mutex_unlock(&i915->drm.struct_mutex);