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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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25 #include "../i915_selftest.h"
27 static int intel_fw_table_check(const struct intel_forcewake_range *ranges,
28 unsigned int num_ranges,
34 for (i = 0, prev = -1; i < num_ranges; i++, ranges++) {
35 /* Check that the table is watertight */
36 if (is_watertight && (prev + 1) != (s32)ranges->start) {
37 pr_err("%s: entry[%d]:(%x, %x) is not watertight to previous (%x)\n",
38 __func__, i, ranges->start, ranges->end, prev);
42 /* Check that the table never goes backwards */
43 if (prev >= (s32)ranges->start) {
44 pr_err("%s: entry[%d]:(%x, %x) is less than the previous (%x)\n",
45 __func__, i, ranges->start, ranges->end, prev);
49 /* Check that the entry is valid */
50 if (ranges->start >= ranges->end) {
51 pr_err("%s: entry[%d]:(%x, %x) has negative length\n",
52 __func__, i, ranges->start, ranges->end);
62 static int intel_shadow_table_check(void)
65 const i915_reg_t *regs;
68 { gen8_shadowed_regs, ARRAY_SIZE(gen8_shadowed_regs) },
69 { gen11_shadowed_regs, ARRAY_SIZE(gen11_shadowed_regs) },
71 const i915_reg_t *reg;
75 for (j = 0; j < ARRAY_SIZE(reg_lists); ++j) {
76 reg = reg_lists[j].regs;
77 for (i = 0, prev = -1; i < reg_lists[j].size; i++, reg++) {
78 u32 offset = i915_mmio_reg_offset(*reg);
80 if (prev >= (s32)offset) {
81 pr_err("%s: entry[%d]:(%x) is before previous (%x)\n",
82 __func__, i, offset, prev);
93 int intel_uncore_mock_selftests(void)
96 const struct intel_forcewake_range *ranges;
97 unsigned int num_ranges;
100 { __vlv_fw_ranges, ARRAY_SIZE(__vlv_fw_ranges), false },
101 { __chv_fw_ranges, ARRAY_SIZE(__chv_fw_ranges), false },
102 { __gen9_fw_ranges, ARRAY_SIZE(__gen9_fw_ranges), true },
103 { __gen11_fw_ranges, ARRAY_SIZE(__gen11_fw_ranges), true },
107 for (i = 0; i < ARRAY_SIZE(fw); i++) {
108 err = intel_fw_table_check(fw[i].ranges,
110 fw[i].is_watertight);
115 err = intel_shadow_table_check();
122 static int intel_uncore_check_forcewake_domains(struct drm_i915_private *dev_priv)
124 #define FW_RANGE 0x40000
125 unsigned long *valid;
129 if (!HAS_FPGA_DBG_UNCLAIMED(dev_priv) &&
130 !IS_VALLEYVIEW(dev_priv) &&
131 !IS_CHERRYVIEW(dev_priv))
135 * This test may lockup the machine or cause GPU hangs afterwards.
137 if (!IS_ENABLED(CONFIG_DRM_I915_SELFTEST_BROKEN))
140 valid = kcalloc(BITS_TO_LONGS(FW_RANGE), sizeof(*valid),
145 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
147 check_for_unclaimed_mmio(dev_priv);
148 for (offset = 0; offset < FW_RANGE; offset += 4) {
149 i915_reg_t reg = { offset };
151 (void)I915_READ_FW(reg);
152 if (!check_for_unclaimed_mmio(dev_priv))
153 set_bit(offset, valid);
156 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
159 for_each_set_bit(offset, valid, FW_RANGE) {
160 i915_reg_t reg = { offset };
162 iosf_mbi_punit_acquire();
163 intel_uncore_forcewake_reset(dev_priv, false);
164 iosf_mbi_punit_release();
166 check_for_unclaimed_mmio(dev_priv);
168 (void)I915_READ(reg);
169 if (check_for_unclaimed_mmio(dev_priv)) {
170 pr_err("Unclaimed mmio read to register 0x%04x\n",
180 int intel_uncore_live_selftests(struct drm_i915_private *i915)
184 /* Confirm the table we load is still valid */
185 err = intel_fw_table_check(i915->uncore.fw_domains_table,
186 i915->uncore.fw_domains_table_entries,
187 INTEL_GEN(i915) >= 9);
191 err = intel_uncore_check_forcewake_domains(i915);