drivers/gpu/drm/i915/intel_uncore.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <linux/pm_runtime.h>
  25 #include <asm/iosf_mbi.h>
  26
  27 #include "i915_drv.h"
  28 #include "i915_vgpu.h"
  29 #include "intel_drv.h"
  30 #include "intel_pm.h"
  31
  32 #define FORCEWAKE_ACK_TIMEOUT_MS 50
  33 #define GT_FIFO_TIMEOUT_MS       10
  34
  35 #define __raw_posting_read(...) ((void)__raw_uncore_read32(__VA_ARGS__))
  36
  37 static const char * const forcewake_domain_names[] = {
  38         "render",
  39         "blitter",
  40         "media",
  41         "vdbox0",
  42         "vdbox1",
  43         "vdbox2",
  44         "vdbox3",
  45         "vebox0",
  46         "vebox1",
  47 };
  48
  49 const char *
  50 intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id)
  51 {
  52         BUILD_BUG_ON(ARRAY_SIZE(forcewake_domain_names) != FW_DOMAIN_ID_COUNT);
  53
  54         if (id >= 0 && id < FW_DOMAIN_ID_COUNT)
  55                 return forcewake_domain_names[id];
  56
  57         WARN_ON(id);
  58
  59         return "unknown";
  60 }
  61
  62 #define fw_ack(d) readl((d)->reg_ack)
  63 #define fw_set(d, val) writel(_MASKED_BIT_ENABLE((val)), (d)->reg_set)
  64 #define fw_clear(d, val) writel(_MASKED_BIT_DISABLE((val)), (d)->reg_set)
  65
  66 static inline void
  67 fw_domain_reset(const struct intel_uncore_forcewake_domain *d)
  68 {
  69         /*
  70          * We don't really know if the powerwell for the forcewake domain we are
  71          * trying to reset here does exist at this point (engines could be fused
  72          * off in ICL+), so no waiting for acks
  73          */
  74         /* WaRsClearFWBitsAtReset:bdw,skl */
  75         fw_clear(d, 0xffff);
  76 }
  77
  78 static inline void
  79 fw_domain_arm_timer(struct intel_uncore_forcewake_domain *d)
  80 {
  81         d->wake_count++;
  82         hrtimer_start_range_ns(&d->timer,
  83                                NSEC_PER_MSEC,
  84                                NSEC_PER_MSEC,
  85                                HRTIMER_MODE_REL);
  86 }
  87
  88 static inline int
  89 __wait_for_ack(const struct intel_uncore_forcewake_domain *d,
  90                const u32 ack,
  91                const u32 value)
  92 {
  93         return wait_for_atomic((fw_ack(d) & ack) == value,
  94                                FORCEWAKE_ACK_TIMEOUT_MS);
  95 }
  96
  97 static inline int
  98 wait_ack_clear(const struct intel_uncore_forcewake_domain *d,
  99                const u32 ack)
 100 {
 101         return __wait_for_ack(d, ack, 0);
 102 }
 103
 104 static inline int
 105 wait_ack_set(const struct intel_uncore_forcewake_domain *d,
 106              const u32 ack)
 107 {
 108         return __wait_for_ack(d, ack, ack);
 109 }
 110
 111 static inline void
 112 fw_domain_wait_ack_clear(const struct intel_uncore_forcewake_domain *d)
 113 {
 114         if (wait_ack_clear(d, FORCEWAKE_KERNEL))
 115                 DRM_ERROR("%s: timed out waiting for forcewake ack to clear.\n",
 116                           intel_uncore_forcewake_domain_to_str(d->id));
 117 }
 118
 119 enum ack_type {
 120         ACK_CLEAR = 0,
 121         ACK_SET
 122 };
 123
 124 static int
 125 fw_domain_wait_ack_with_fallback(const struct intel_uncore_forcewake_domain *d,
 126                                  const enum ack_type type)
 127 {
 128         const u32 ack_bit = FORCEWAKE_KERNEL;
 129         const u32 value = type == ACK_SET ? ack_bit : 0;
 130         unsigned int pass;
 131         bool ack_detected;
 132
 133         /*
 134          * There is a possibility of driver's wake request colliding
 135          * with hardware's own wake requests and that can cause
 136          * hardware to not deliver the driver's ack message.
 137          *
 138          * Use a fallback bit toggle to kick the gpu state machine
 139          * in the hope that the original ack will be delivered along with
 140          * the fallback ack.
 141          *
 142          * This workaround is described in HSDES #1604254524 and it's known as:
 143          * WaRsForcewakeAddDelayForAck:skl,bxt,kbl,glk,cfl,cnl,icl
 144          * although the name is a bit misleading.
 145          */
 146
 147         pass = 1;
 148         do {
 149                 wait_ack_clear(d, FORCEWAKE_KERNEL_FALLBACK);
 150
 151                 fw_set(d, FORCEWAKE_KERNEL_FALLBACK);
 152                 /* Give gt some time to relax before the polling frenzy */
 153                 udelay(10 * pass);
 154                 wait_ack_set(d, FORCEWAKE_KERNEL_FALLBACK);
 155
 156                 ack_detected = (fw_ack(d) & ack_bit) == value;
 157
 158                 fw_clear(d, FORCEWAKE_KERNEL_FALLBACK);
 159         } while (!ack_detected && pass++ < 10);
 160
 161         DRM_DEBUG_DRIVER("%s had to use fallback to %s ack, 0x%x (passes %u)\n",
 162                          intel_uncore_forcewake_domain_to_str(d->id),
 163                          type == ACK_SET ? "set" : "clear",
 164                          fw_ack(d),
 165                          pass);
 166
 167         return ack_detected ? 0 : -ETIMEDOUT;
 168 }
 169
 170 static inline void
 171 fw_domain_wait_ack_clear_fallback(const struct intel_uncore_forcewake_domain *d)
 172 {
 173         if (likely(!wait_ack_clear(d, FORCEWAKE_KERNEL)))
 174                 return;
 175
 176         if (fw_domain_wait_ack_with_fallback(d, ACK_CLEAR))
 177                 fw_domain_wait_ack_clear(d);
 178 }
 179
 180 static inline void
 181 fw_domain_get(const struct intel_uncore_forcewake_domain *d)
 182 {
 183         fw_set(d, FORCEWAKE_KERNEL);
 184 }
 185
 186 static inline void
 187 fw_domain_wait_ack_set(const struct intel_uncore_forcewake_domain *d)
 188 {
 189         if (wait_ack_set(d, FORCEWAKE_KERNEL))
 190                 DRM_ERROR("%s: timed out waiting for forcewake ack request.\n",
 191                           intel_uncore_forcewake_domain_to_str(d->id));
 192 }
 193
 194 static inline void
 195 fw_domain_wait_ack_set_fallback(const struct intel_uncore_forcewake_domain *d)
 196 {
 197         if (likely(!wait_ack_set(d, FORCEWAKE_KERNEL)))
 198                 return;
 199
 200         if (fw_domain_wait_ack_with_fallback(d, ACK_SET))
 201                 fw_domain_wait_ack_set(d);
 202 }
 203
 204 static inline void
 205 fw_domain_put(const struct intel_uncore_forcewake_domain *d)
 206 {
 207         fw_clear(d, FORCEWAKE_KERNEL);
 208 }
 209
 210 static void
 211 fw_domains_get(struct intel_uncore *uncore, enum forcewake_domains fw_domains)
 212 {
 213         struct intel_uncore_forcewake_domain *d;
 214         unsigned int tmp;
 215
 216         GEM_BUG_ON(fw_domains & ~uncore->fw_domains);
 217
 218         for_each_fw_domain_masked(d, fw_domains, uncore, tmp) {
 219                 fw_domain_wait_ack_clear(d);
 220                 fw_domain_get(d);
 221         }
 222
 223         for_each_fw_domain_masked(d, fw_domains, uncore, tmp)
 224                 fw_domain_wait_ack_set(d);
 225
 226         uncore->fw_domains_active |= fw_domains;
 227 }
 228
 229 static void
 230 fw_domains_get_with_fallback(struct intel_uncore *uncore,
 231                              enum forcewake_domains fw_domains)
 232 {
 233         struct intel_uncore_forcewake_domain *d;
 234         unsigned int tmp;
 235
 236         GEM_BUG_ON(fw_domains & ~uncore->fw_domains);
 237
 238         for_each_fw_domain_masked(d, fw_domains, uncore, tmp) {
 239                 fw_domain_wait_ack_clear_fallback(d);
 240                 fw_domain_get(d);
 241         }
 242
 243         for_each_fw_domain_masked(d, fw_domains, uncore, tmp)
 244                 fw_domain_wait_ack_set_fallback(d);
 245
 246         uncore->fw_domains_active |= fw_domains;
 247 }
 248
 249 static void
 250 fw_domains_put(struct intel_uncore *uncore, enum forcewake_domains fw_domains)
 251 {
 252         struct intel_uncore_forcewake_domain *d;
 253         unsigned int tmp;
 254
 255         GEM_BUG_ON(fw_domains & ~uncore->fw_domains);
 256
 257         for_each_fw_domain_masked(d, fw_domains, uncore, tmp)
 258                 fw_domain_put(d);
 259
 260         uncore->fw_domains_active &= ~fw_domains;
 261 }
 262
 263 static void
 264 fw_domains_reset(struct intel_uncore *uncore,
 265                  enum forcewake_domains fw_domains)
 266 {
 267         struct intel_uncore_forcewake_domain *d;
 268         unsigned int tmp;
 269
 270         if (!fw_domains)
 271                 return;
 272
 273         GEM_BUG_ON(fw_domains & ~uncore->fw_domains);
 274
 275         for_each_fw_domain_masked(d, fw_domains, uncore, tmp)
 276                 fw_domain_reset(d);
 277 }
 278
 279 static inline u32 gt_thread_status(struct intel_uncore *uncore)
 280 {
 281         u32 val;
 282
 283         val = __raw_uncore_read32(uncore, GEN6_GT_THREAD_STATUS_REG);
 284         val &= GEN6_GT_THREAD_STATUS_CORE_MASK;
 285
 286         return val;
 287 }
 288
 289 static void __gen6_gt_wait_for_thread_c0(struct intel_uncore *uncore)
 290 {
 291         /*
 292          * w/a for a sporadic read returning 0 by waiting for the GT
 293          * thread to wake up.
 294          */
 295         WARN_ONCE(wait_for_atomic_us(gt_thread_status(uncore) == 0, 5000),
 296                   "GT thread status wait timed out\n");
 297 }
 298
 299 static void fw_domains_get_with_thread_status(struct intel_uncore *uncore,
 300                                               enum forcewake_domains fw_domains)
 301 {
 302         fw_domains_get(uncore, fw_domains);
 303
 304         /* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */
 305         __gen6_gt_wait_for_thread_c0(uncore);
 306 }
 307
 308 static inline u32 fifo_free_entries(struct intel_uncore *uncore)
 309 {
 310         u32 count = __raw_uncore_read32(uncore, GTFIFOCTL);
 311
 312         return count & GT_FIFO_FREE_ENTRIES_MASK;
 313 }
 314
 315 static void __gen6_gt_wait_for_fifo(struct intel_uncore *uncore)
 316 {
 317         u32 n;
 318
 319         /* On VLV, FIFO will be shared by both SW and HW.
 320          * So, we need to read the FREE_ENTRIES everytime */
 321         if (IS_VALLEYVIEW(uncore_to_i915(uncore)))
 322                 n = fifo_free_entries(uncore);
 323         else
 324                 n = uncore->fifo_count;
 325
 326         if (n <= GT_FIFO_NUM_RESERVED_ENTRIES) {
 327                 if (wait_for_atomic((n = fifo_free_entries(uncore)) >
 328                                     GT_FIFO_NUM_RESERVED_ENTRIES,
 329                                     GT_FIFO_TIMEOUT_MS)) {
 330                         DRM_DEBUG("GT_FIFO timeout, entries: %u\n", n);
 331                         return;
 332                 }
 333         }
 334
 335         uncore->fifo_count = n - 1;
 336 }
 337
 338 static enum hrtimer_restart
 339 intel_uncore_fw_release_timer(struct hrtimer *timer)
 340 {
 341         struct intel_uncore_forcewake_domain *domain =
 342                container_of(timer, struct intel_uncore_forcewake_domain, timer);
 343         struct intel_uncore *uncore = forcewake_domain_to_uncore(domain);
 344         unsigned long irqflags;
 345
 346         assert_rpm_device_not_suspended(uncore->rpm);
 347
 348         if (xchg(&domain->active, false))
 349                 return HRTIMER_RESTART;
 350
 351         spin_lock_irqsave(&uncore->lock, irqflags);
 352         if (WARN_ON(domain->wake_count == 0))
 353                 domain->wake_count++;
 354
 355         if (--domain->wake_count == 0)
 356                 uncore->funcs.force_wake_put(uncore, domain->mask);
 357
 358         spin_unlock_irqrestore(&uncore->lock, irqflags);
 359
 360         return HRTIMER_NORESTART;
 361 }
 362
 363 /* Note callers must have acquired the PUNIT->PMIC bus, before calling this. */
 364 static unsigned int
 365 intel_uncore_forcewake_reset(struct intel_uncore *uncore)
 366 {
 367         unsigned long irqflags;
 368         struct intel_uncore_forcewake_domain *domain;
 369         int retry_count = 100;
 370         enum forcewake_domains fw, active_domains;
 371
 372         iosf_mbi_assert_punit_acquired();
 373
 374         /* Hold uncore.lock across reset to prevent any register access
 375          * with forcewake not set correctly. Wait until all pending
 376          * timers are run before holding.
 377          */
 378         while (1) {
 379                 unsigned int tmp;
 380
 381                 active_domains = 0;
 382
 383                 for_each_fw_domain(domain, uncore, tmp) {
 384                         smp_store_mb(domain->active, false);
 385                         if (hrtimer_cancel(&domain->timer) == 0)
 386                                 continue;
 387
 388                         intel_uncore_fw_release_timer(&domain->timer);
 389                 }
 390
 391                 spin_lock_irqsave(&uncore->lock, irqflags);
 392
 393                 for_each_fw_domain(domain, uncore, tmp) {
 394                         if (hrtimer_active(&domain->timer))
 395                                 active_domains |= domain->mask;
 396                 }
 397
 398                 if (active_domains == 0)
 399                         break;
 400
 401                 if (--retry_count == 0) {
 402                         DRM_ERROR("Timed out waiting for forcewake timers to finish\n");
 403                         break;
 404                 }
 405
 406                 spin_unlock_irqrestore(&uncore->lock, irqflags);
 407                 cond_resched();
 408         }
 409
 410         WARN_ON(active_domains);
 411
 412         fw = uncore->fw_domains_active;
 413         if (fw)
 414                 uncore->funcs.force_wake_put(uncore, fw);
 415
 416         fw_domains_reset(uncore, uncore->fw_domains);
 417         assert_forcewakes_inactive(uncore);
 418
 419         spin_unlock_irqrestore(&uncore->lock, irqflags);
 420
 421         return fw; /* track the lost user forcewake domains */
 422 }
 423
 424 static bool
 425 fpga_check_for_unclaimed_mmio(struct intel_uncore *uncore)
 426 {
 427         u32 dbg;
 428
 429         dbg = __raw_uncore_read32(uncore, FPGA_DBG);
 430         if (likely(!(dbg & FPGA_DBG_RM_NOCLAIM)))
 431                 return false;
 432
 433         __raw_uncore_write32(uncore, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
 434
 435         return true;
 436 }
 437
 438 static bool
 439 vlv_check_for_unclaimed_mmio(struct intel_uncore *uncore)
 440 {
 441         u32 cer;
 442
 443         cer = __raw_uncore_read32(uncore, CLAIM_ER);
 444         if (likely(!(cer & (CLAIM_ER_OVERFLOW | CLAIM_ER_CTR_MASK))))
 445                 return false;
 446
 447         __raw_uncore_write32(uncore, CLAIM_ER, CLAIM_ER_CLR);
 448
 449         return true;
 450 }
 451
 452 static bool
 453 gen6_check_for_fifo_debug(struct intel_uncore *uncore)
 454 {
 455         u32 fifodbg;
 456
 457         fifodbg = __raw_uncore_read32(uncore, GTFIFODBG);
 458
 459         if (unlikely(fifodbg)) {
 460                 DRM_DEBUG_DRIVER("GTFIFODBG = 0x08%x\n", fifodbg);
 461                 __raw_uncore_write32(uncore, GTFIFODBG, fifodbg);
 462         }
 463
 464         return fifodbg;
 465 }
 466
 467 static bool
 468 check_for_unclaimed_mmio(struct intel_uncore *uncore)
 469 {
 470         bool ret = false;
 471
 472         if (intel_uncore_has_fpga_dbg_unclaimed(uncore))
 473                 ret |= fpga_check_for_unclaimed_mmio(uncore);
 474
 475         if (intel_uncore_has_dbg_unclaimed(uncore))
 476                 ret |= vlv_check_for_unclaimed_mmio(uncore);
 477
 478         if (intel_uncore_has_fifo(uncore))
 479                 ret |= gen6_check_for_fifo_debug(uncore);
 480
 481         return ret;
 482 }
 483
 484 static void __intel_uncore_early_sanitize(struct intel_uncore *uncore,
 485                                           unsigned int restore_forcewake)
 486 {
 487         /* clear out unclaimed reg detection bit */
 488         if (check_for_unclaimed_mmio(uncore))
 489                 DRM_DEBUG("unclaimed mmio detected on uncore init, clearing\n");
 490
 491         /* WaDisableShadowRegForCpd:chv */
 492         if (IS_CHERRYVIEW(uncore_to_i915(uncore))) {
 493                 __raw_uncore_write32(uncore, GTFIFOCTL,
 494                                      __raw_uncore_read32(uncore, GTFIFOCTL) |
 495                                      GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
 496                                      GT_FIFO_CTL_RC6_POLICY_STALL);
 497         }
 498
 499         iosf_mbi_punit_acquire();
 500         intel_uncore_forcewake_reset(uncore);
 501         if (restore_forcewake) {
 502                 spin_lock_irq(&uncore->lock);
 503                 uncore->funcs.force_wake_get(uncore, restore_forcewake);
 504
 505                 if (intel_uncore_has_fifo(uncore))
 506                         uncore->fifo_count = fifo_free_entries(uncore);
 507                 spin_unlock_irq(&uncore->lock);
 508         }
 509         iosf_mbi_punit_release();
 510 }
 511
 512 void intel_uncore_suspend(struct intel_uncore *uncore)
 513 {
 514         iosf_mbi_punit_acquire();
 515         iosf_mbi_unregister_pmic_bus_access_notifier_unlocked(
 516                 &uncore->pmic_bus_access_nb);
 517         uncore->fw_domains_saved = intel_uncore_forcewake_reset(uncore);
 518         iosf_mbi_punit_release();
 519 }
 520
 521 void intel_uncore_resume_early(struct intel_uncore *uncore)
 522 {
 523         unsigned int restore_forcewake;
 524
 525         restore_forcewake = fetch_and_zero(&uncore->fw_domains_saved);
 526         __intel_uncore_early_sanitize(uncore, restore_forcewake);
 527
 528         iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb);
 529 }
 530
 531 void intel_uncore_runtime_resume(struct intel_uncore *uncore)
 532 {
 533         iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb);
 534 }
 535
 536 void intel_uncore_sanitize(struct drm_i915_private *dev_priv)
 537 {
 538         /* BIOS often leaves RC6 enabled, but disable it for hw init */
 539         intel_sanitize_gt_powersave(dev_priv);
 540 }
 541
 542 static void __intel_uncore_forcewake_get(struct intel_uncore *uncore,
 543                                          enum forcewake_domains fw_domains)
 544 {
 545         struct intel_uncore_forcewake_domain *domain;
 546         unsigned int tmp;
 547
 548         fw_domains &= uncore->fw_domains;
 549
 550         for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) {
 551                 if (domain->wake_count++) {
 552                         fw_domains &= ~domain->mask;
 553                         domain->active = true;
 554                 }
 555         }
 556
 557         if (fw_domains)
 558                 uncore->funcs.force_wake_get(uncore, fw_domains);
 559 }
 560
 561 /**
 562  * intel_uncore_forcewake_get - grab forcewake domain references
 563  * @uncore: the intel_uncore structure
 564  * @fw_domains: forcewake domains to get reference on
 565  *
 566  * This function can be used get GT's forcewake domain references.
 567  * Normal register access will handle the forcewake domains automatically.
 568  * However if some sequence requires the GT to not power down a particular
 569  * forcewake domains this function should be called at the beginning of the
 570  * sequence. And subsequently the reference should be dropped by symmetric
 571  * call to intel_unforce_forcewake_put(). Usually caller wants all the domains
 572  * to be kept awake so the @fw_domains would be then FORCEWAKE_ALL.
 573  */
 574 void intel_uncore_forcewake_get(struct intel_uncore *uncore,
 575                                 enum forcewake_domains fw_domains)
 576 {
 577         unsigned long irqflags;
 578
 579         if (!uncore->funcs.force_wake_get)
 580                 return;
 581
 582         __assert_rpm_wakelock_held(uncore->rpm);
 583
 584         spin_lock_irqsave(&uncore->lock, irqflags);
 585         __intel_uncore_forcewake_get(uncore, fw_domains);
 586         spin_unlock_irqrestore(&uncore->lock, irqflags);
 587 }
 588
 589 /**
 590  * intel_uncore_forcewake_user_get - claim forcewake on behalf of userspace
 591  * @uncore: the intel_uncore structure
 592  *
 593  * This function is a wrapper around intel_uncore_forcewake_get() to acquire
 594  * the GT powerwell and in the process disable our debugging for the
 595  * duration of userspace's bypass.
 596  */
 597 void intel_uncore_forcewake_user_get(struct intel_uncore *uncore)
 598 {
 599         spin_lock_irq(&uncore->lock);
 600         if (!uncore->user_forcewake.count++) {
 601                 intel_uncore_forcewake_get__locked(uncore, FORCEWAKE_ALL);
 602
 603                 /* Save and disable mmio debugging for the user bypass */
 604                 uncore->user_forcewake.saved_mmio_check =
 605                         uncore->unclaimed_mmio_check;
 606                 uncore->user_forcewake.saved_mmio_debug =
 607                         i915_modparams.mmio_debug;
 608
 609                 uncore->unclaimed_mmio_check = 0;
 610                 i915_modparams.mmio_debug = 0;
 611         }
 612         spin_unlock_irq(&uncore->lock);
 613 }
 614
 615 /**
 616  * intel_uncore_forcewake_user_put - release forcewake on behalf of userspace
 617  * @uncore: the intel_uncore structure
 618  *
 619  * This function complements intel_uncore_forcewake_user_get() and releases
 620  * the GT powerwell taken on behalf of the userspace bypass.
 621  */
 622 void intel_uncore_forcewake_user_put(struct intel_uncore *uncore)
 623 {
 624         spin_lock_irq(&uncore->lock);
 625         if (!--uncore->user_forcewake.count) {
 626                 if (intel_uncore_unclaimed_mmio(uncore))
 627                         dev_info(uncore_to_i915(uncore)->drm.dev,
 628                                  "Invalid mmio detected during user access\n");
 629
 630                 uncore->unclaimed_mmio_check =
 631                         uncore->user_forcewake.saved_mmio_check;
 632                 i915_modparams.mmio_debug =
 633                         uncore->user_forcewake.saved_mmio_debug;
 634
 635                 intel_uncore_forcewake_put__locked(uncore, FORCEWAKE_ALL);
 636         }
 637         spin_unlock_irq(&uncore->lock);
 638 }
 639
 640 /**
 641  * intel_uncore_forcewake_get__locked - grab forcewake domain references
 642  * @uncore: the intel_uncore structure
 643  * @fw_domains: forcewake domains to get reference on
 644  *
 645  * See intel_uncore_forcewake_get(). This variant places the onus
 646  * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
 647  */
 648 void intel_uncore_forcewake_get__locked(struct intel_uncore *uncore,
 649                                         enum forcewake_domains fw_domains)
 650 {
 651         lockdep_assert_held(&uncore->lock);
 652
 653         if (!uncore->funcs.force_wake_get)
 654                 return;
 655
 656         __intel_uncore_forcewake_get(uncore, fw_domains);
 657 }
 658
 659 static void __intel_uncore_forcewake_put(struct intel_uncore *uncore,
 660                                          enum forcewake_domains fw_domains)
 661 {
 662         struct intel_uncore_forcewake_domain *domain;
 663         unsigned int tmp;
 664
 665         fw_domains &= uncore->fw_domains;
 666
 667         for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) {
 668                 if (WARN_ON(domain->wake_count == 0))
 669                         continue;
 670
 671                 if (--domain->wake_count) {
 672                         domain->active = true;
 673                         continue;
 674                 }
 675
 676                 fw_domain_arm_timer(domain);
 677         }
 678 }
 679
 680 /**
 681  * intel_uncore_forcewake_put - release a forcewake domain reference
 682  * @uncore: the intel_uncore structure
 683  * @fw_domains: forcewake domains to put references
 684  *
 685  * This function drops the device-level forcewakes for specified
 686  * domains obtained by intel_uncore_forcewake_get().
 687  */
 688 void intel_uncore_forcewake_put(struct intel_uncore *uncore,
 689                                 enum forcewake_domains fw_domains)
 690 {
 691         unsigned long irqflags;
 692
 693         if (!uncore->funcs.force_wake_put)
 694                 return;
 695
 696         spin_lock_irqsave(&uncore->lock, irqflags);
 697         __intel_uncore_forcewake_put(uncore, fw_domains);
 698         spin_unlock_irqrestore(&uncore->lock, irqflags);
 699 }
 700
 701 /**
 702  * intel_uncore_forcewake_put__locked - grab forcewake domain references
 703  * @uncore: the intel_uncore structure
 704  * @fw_domains: forcewake domains to get reference on
 705  *
 706  * See intel_uncore_forcewake_put(). This variant places the onus
 707  * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
 708  */
 709 void intel_uncore_forcewake_put__locked(struct intel_uncore *uncore,
 710                                         enum forcewake_domains fw_domains)
 711 {
 712         lockdep_assert_held(&uncore->lock);
 713
 714         if (!uncore->funcs.force_wake_put)
 715                 return;
 716
 717         __intel_uncore_forcewake_put(uncore, fw_domains);
 718 }
 719
 720 void assert_forcewakes_inactive(struct intel_uncore *uncore)
 721 {
 722         if (!uncore->funcs.force_wake_get)
 723                 return;
 724
 725         WARN(uncore->fw_domains_active,
 726              "Expected all fw_domains to be inactive, but %08x are still on\n",
 727              uncore->fw_domains_active);
 728 }
 729
 730 void assert_forcewakes_active(struct intel_uncore *uncore,
 731                               enum forcewake_domains fw_domains)
 732 {
 733         if (!uncore->funcs.force_wake_get)
 734                 return;
 735
 736         __assert_rpm_wakelock_held(uncore->rpm);
 737
 738         fw_domains &= uncore->fw_domains;
 739         WARN(fw_domains & ~uncore->fw_domains_active,
 740              "Expected %08x fw_domains to be active, but %08x are off\n",
 741              fw_domains, fw_domains & ~uncore->fw_domains_active);
 742 }
 743
 744 /* We give fast paths for the really cool registers */
 745 #define NEEDS_FORCE_WAKE(reg) ((reg) < 0x40000)
 746
 747 #define GEN11_NEEDS_FORCE_WAKE(reg) \
 748         ((reg) < 0x40000 || ((reg) >= 0x1c0000 && (reg) < 0x1dc000))
 749
 750 #define __gen6_reg_read_fw_domains(uncore, offset) \
 751 ({ \
 752         enum forcewake_domains __fwd; \
 753         if (NEEDS_FORCE_WAKE(offset)) \
 754                 __fwd = FORCEWAKE_RENDER; \
 755         else \
 756                 __fwd = 0; \
 757         __fwd; \
 758 })
 759
 760 static int fw_range_cmp(u32 offset, const struct intel_forcewake_range *entry)
 761 {
 762         if (offset < entry->start)
 763                 return -1;
 764         else if (offset > entry->end)
 765                 return 1;
 766         else
 767                 return 0;
 768 }
 769
 770 /* Copied and "macroized" from lib/bsearch.c */
 771 #define BSEARCH(key, base, num, cmp) ({                                 \
 772         unsigned int start__ = 0, end__ = (num);                        \
 773         typeof(base) result__ = NULL;                                   \
 774         while (start__ < end__) {                                       \
 775                 unsigned int mid__ = start__ + (end__ - start__) / 2;   \
 776                 int ret__ = (cmp)((key), (base) + mid__);               \
 777                 if (ret__ < 0) {                                        \
 778                         end__ = mid__;                                  \
 779                 } else if (ret__ > 0) {                                 \
 780                         start__ = mid__ + 1;                            \
 781                 } else {                                                \
 782                         result__ = (base) + mid__;                      \
 783                         break;                                          \
 784                 }                                                       \
 785         }                                                               \
 786         result__;                                                       \
 787 })
 788
 789 static enum forcewake_domains
 790 find_fw_domain(struct intel_uncore *uncore, u32 offset)
 791 {
 792         const struct intel_forcewake_range *entry;
 793
 794         entry = BSEARCH(offset,
 795                         uncore->fw_domains_table,
 796                         uncore->fw_domains_table_entries,
 797                         fw_range_cmp);
 798
 799         if (!entry)
 800                 return 0;
 801
 802         /*
 803          * The list of FW domains depends on the SKU in gen11+ so we
 804          * can't determine it statically. We use FORCEWAKE_ALL and
 805          * translate it here to the list of available domains.
 806          */
 807         if (entry->domains == FORCEWAKE_ALL)
 808                 return uncore->fw_domains;
 809
 810         WARN(entry->domains & ~uncore->fw_domains,
 811              "Uninitialized forcewake domain(s) 0x%x accessed at 0x%x\n",
 812              entry->domains & ~uncore->fw_domains, offset);
 813
 814         return entry->domains;
 815 }
 816
 817 #define GEN_FW_RANGE(s, e, d) \
 818         { .start = (s), .end = (e), .domains = (d) }
 819
 820 #define HAS_FWTABLE(dev_priv) \
 821         (INTEL_GEN(dev_priv) >= 9 || \
 822          IS_CHERRYVIEW(dev_priv) || \
 823          IS_VALLEYVIEW(dev_priv))
 824
 825 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
 826 static const struct intel_forcewake_range __vlv_fw_ranges[] = {
 827         GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER),
 828         GEN_FW_RANGE(0x5000, 0x7fff, FORCEWAKE_RENDER),
 829         GEN_FW_RANGE(0xb000, 0x11fff, FORCEWAKE_RENDER),
 830         GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
 831         GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_MEDIA),
 832         GEN_FW_RANGE(0x2e000, 0x2ffff, FORCEWAKE_RENDER),
 833         GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA),
 834 };
 835
 836 #define __fwtable_reg_read_fw_domains(uncore, offset) \
 837 ({ \
 838         enum forcewake_domains __fwd = 0; \
 839         if (NEEDS_FORCE_WAKE((offset))) \
 840                 __fwd = find_fw_domain(uncore, offset); \
 841         __fwd; \
 842 })
 843
 844 #define __gen11_fwtable_reg_read_fw_domains(uncore, offset) \
 845 ({ \
 846         enum forcewake_domains __fwd = 0; \
 847         if (GEN11_NEEDS_FORCE_WAKE((offset))) \
 848                 __fwd = find_fw_domain(uncore, offset); \
 849         __fwd; \
 850 })
 851
 852 /* *Must* be sorted by offset! See intel_shadow_table_check(). */
 853 static const i915_reg_t gen8_shadowed_regs[] = {
 854         RING_TAIL(RENDER_RING_BASE),    /* 0x2000 (base) */
 855         GEN6_RPNSWREQ,                  /* 0xA008 */
 856         GEN6_RC_VIDEO_FREQ,             /* 0xA00C */
 857         RING_TAIL(GEN6_BSD_RING_BASE),  /* 0x12000 (base) */
 858         RING_TAIL(VEBOX_RING_BASE),     /* 0x1a000 (base) */
 859         RING_TAIL(BLT_RING_BASE),       /* 0x22000 (base) */
 860         /* TODO: Other registers are not yet used */
 861 };
 862
 863 static const i915_reg_t gen11_shadowed_regs[] = {
 864         RING_TAIL(RENDER_RING_BASE),            /* 0x2000 (base) */
 865         GEN6_RPNSWREQ,                          /* 0xA008 */
 866         GEN6_RC_VIDEO_FREQ,                     /* 0xA00C */
 867         RING_TAIL(BLT_RING_BASE),               /* 0x22000 (base) */
 868         RING_TAIL(GEN11_BSD_RING_BASE),         /* 0x1C0000 (base) */
 869         RING_TAIL(GEN11_BSD2_RING_BASE),        /* 0x1C4000 (base) */
 870         RING_TAIL(GEN11_VEBOX_RING_BASE),       /* 0x1C8000 (base) */
 871         RING_TAIL(GEN11_BSD3_RING_BASE),        /* 0x1D0000 (base) */
 872         RING_TAIL(GEN11_BSD4_RING_BASE),        /* 0x1D4000 (base) */
 873         RING_TAIL(GEN11_VEBOX2_RING_BASE),      /* 0x1D8000 (base) */
 874         /* TODO: Other registers are not yet used */
 875 };
 876
 877 static int mmio_reg_cmp(u32 key, const i915_reg_t *reg)
 878 {
 879         u32 offset = i915_mmio_reg_offset(*reg);
 880
 881         if (key < offset)
 882                 return -1;
 883         else if (key > offset)
 884                 return 1;
 885         else
 886                 return 0;
 887 }
 888
 889 #define __is_genX_shadowed(x) \
 890 static bool is_gen##x##_shadowed(u32 offset) \
 891 { \
 892         const i915_reg_t *regs = gen##x##_shadowed_regs; \
 893         return BSEARCH(offset, regs, ARRAY_SIZE(gen##x##_shadowed_regs), \
 894                        mmio_reg_cmp); \
 895 }
 896
 897 __is_genX_shadowed(8)
 898 __is_genX_shadowed(11)
 899
 900 #define __gen8_reg_write_fw_domains(uncore, offset) \
 901 ({ \
 902         enum forcewake_domains __fwd; \
 903         if (NEEDS_FORCE_WAKE(offset) && !is_gen8_shadowed(offset)) \
 904                 __fwd = FORCEWAKE_RENDER; \
 905         else \
 906                 __fwd = 0; \
 907         __fwd; \
 908 })
 909
 910 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
 911 static const struct intel_forcewake_range __chv_fw_ranges[] = {
 912         GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER),
 913         GEN_FW_RANGE(0x4000, 0x4fff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
 914         GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
 915         GEN_FW_RANGE(0x8000, 0x82ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
 916         GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
 917         GEN_FW_RANGE(0x8500, 0x85ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
 918         GEN_FW_RANGE(0x8800, 0x88ff, FORCEWAKE_MEDIA),
 919         GEN_FW_RANGE(0x9000, 0xafff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
 920         GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
 921         GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA),
 922         GEN_FW_RANGE(0xe000, 0xe7ff, FORCEWAKE_RENDER),
 923         GEN_FW_RANGE(0xf000, 0xffff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
 924         GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
 925         GEN_FW_RANGE(0x1a000, 0x1bfff, FORCEWAKE_MEDIA),
 926         GEN_FW_RANGE(0x1e800, 0x1e9ff, FORCEWAKE_MEDIA),
 927         GEN_FW_RANGE(0x30000, 0x37fff, FORCEWAKE_MEDIA),
 928 };
 929
 930 #define __fwtable_reg_write_fw_domains(uncore, offset) \
 931 ({ \
 932         enum forcewake_domains __fwd = 0; \
 933         if (NEEDS_FORCE_WAKE((offset)) && !is_gen8_shadowed(offset)) \
 934                 __fwd = find_fw_domain(uncore, offset); \
 935         __fwd; \
 936 })
 937
 938 #define __gen11_fwtable_reg_write_fw_domains(uncore, offset) \
 939 ({ \
 940         enum forcewake_domains __fwd = 0; \
 941         if (GEN11_NEEDS_FORCE_WAKE((offset)) && !is_gen11_shadowed(offset)) \
 942                 __fwd = find_fw_domain(uncore, offset); \
 943         __fwd; \
 944 })
 945
 946 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
 947 static const struct intel_forcewake_range __gen9_fw_ranges[] = {
 948         GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER),
 949         GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */
 950         GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
 951         GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER),
 952         GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
 953         GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_BLITTER),
 954         GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
 955         GEN_FW_RANGE(0x8000, 0x812f, FORCEWAKE_BLITTER),
 956         GEN_FW_RANGE(0x8130, 0x813f, FORCEWAKE_MEDIA),
 957         GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
 958         GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER),
 959         GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
 960         GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_BLITTER),
 961         GEN_FW_RANGE(0x8800, 0x89ff, FORCEWAKE_MEDIA),
 962         GEN_FW_RANGE(0x8a00, 0x8bff, FORCEWAKE_BLITTER),
 963         GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER),
 964         GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_BLITTER),
 965         GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
 966         GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_BLITTER),
 967         GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
 968         GEN_FW_RANGE(0xb480, 0xcfff, FORCEWAKE_BLITTER),
 969         GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA),
 970         GEN_FW_RANGE(0xd800, 0xdfff, FORCEWAKE_BLITTER),
 971         GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER),
 972         GEN_FW_RANGE(0xe900, 0x11fff, FORCEWAKE_BLITTER),
 973         GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
 974         GEN_FW_RANGE(0x14000, 0x19fff, FORCEWAKE_BLITTER),
 975         GEN_FW_RANGE(0x1a000, 0x1e9ff, FORCEWAKE_MEDIA),
 976         GEN_FW_RANGE(0x1ea00, 0x243ff, FORCEWAKE_BLITTER),
 977         GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER),
 978         GEN_FW_RANGE(0x24800, 0x2ffff, FORCEWAKE_BLITTER),
 979         GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA),
 980 };
 981
 982 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
 983 static const struct intel_forcewake_range __gen11_fw_ranges[] = {
 984         GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER),
 985         GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */
 986         GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
 987         GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER),
 988         GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
 989         GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_BLITTER),
 990         GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
 991         GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_BLITTER),
 992         GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
 993         GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER),
 994         GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
 995         GEN_FW_RANGE(0x8500, 0x8bff, FORCEWAKE_BLITTER),
 996         GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER),
 997         GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_BLITTER),
 998         GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_ALL),
 999         GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_BLITTER),
1000         GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
1001         GEN_FW_RANGE(0xb480, 0xdfff, FORCEWAKE_BLITTER),
1002         GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER),
1003         GEN_FW_RANGE(0xe900, 0x243ff, FORCEWAKE_BLITTER),
1004         GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER),
1005         GEN_FW_RANGE(0x24800, 0x3ffff, FORCEWAKE_BLITTER),
1006         GEN_FW_RANGE(0x40000, 0x1bffff, 0),
1007         GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0),
1008         GEN_FW_RANGE(0x1c4000, 0x1c7fff, FORCEWAKE_MEDIA_VDBOX1),
1009         GEN_FW_RANGE(0x1c8000, 0x1cbfff, FORCEWAKE_MEDIA_VEBOX0),
1010         GEN_FW_RANGE(0x1cc000, 0x1cffff, FORCEWAKE_BLITTER),
1011         GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2),
1012         GEN_FW_RANGE(0x1d4000, 0x1d7fff, FORCEWAKE_MEDIA_VDBOX3),
1013         GEN_FW_RANGE(0x1d8000, 0x1dbfff, FORCEWAKE_MEDIA_VEBOX1)
1014 };
1015
1016 static void
1017 ilk_dummy_write(struct intel_uncore *uncore)
1018 {
1019         /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
1020          * the chip from rc6 before touching it for real. MI_MODE is masked,
1021          * hence harmless to write 0 into. */
1022         __raw_uncore_write32(uncore, MI_MODE, 0);
1023 }
1024
1025 static void
1026 __unclaimed_reg_debug(struct intel_uncore *uncore,
1027                       const i915_reg_t reg,
1028                       const bool read,
1029                       const bool before)
1030 {
1031         if (WARN(check_for_unclaimed_mmio(uncore) && !before,
1032                  "Unclaimed %s register 0x%x\n",
1033                  read ? "read from" : "write to",
1034                  i915_mmio_reg_offset(reg)))
1035                 /* Only report the first N failures */
1036                 i915_modparams.mmio_debug--;
1037 }
1038
1039 static inline void
1040 unclaimed_reg_debug(struct intel_uncore *uncore,
1041                     const i915_reg_t reg,
1042                     const bool read,
1043                     const bool before)
1044 {
1045         if (likely(!i915_modparams.mmio_debug))
1046                 return;
1047
1048         __unclaimed_reg_debug(uncore, reg, read, before);
1049 }
1050
1051 #define GEN2_READ_HEADER(x) \
1052         u##x val = 0; \
1053         __assert_rpm_wakelock_held(uncore->rpm);
1054
1055 #define GEN2_READ_FOOTER \
1056         trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
1057         return val
1058
1059 #define __gen2_read(x) \
1060 static u##x \
1061 gen2_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
1062         GEN2_READ_HEADER(x); \
1063         val = __raw_uncore_read##x(uncore, reg); \
1064         GEN2_READ_FOOTER; \
1065 }
1066
1067 #define __gen5_read(x) \
1068 static u##x \
1069 gen5_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
1070         GEN2_READ_HEADER(x); \
1071         ilk_dummy_write(uncore); \
1072         val = __raw_uncore_read##x(uncore, reg); \
1073         GEN2_READ_FOOTER; \
1074 }
1075
1076 __gen5_read(8)
1077 __gen5_read(16)
1078 __gen5_read(32)
1079 __gen5_read(64)
1080 __gen2_read(8)
1081 __gen2_read(16)
1082 __gen2_read(32)
1083 __gen2_read(64)
1084
1085 #undef __gen5_read
1086 #undef __gen2_read
1087
1088 #undef GEN2_READ_FOOTER
1089 #undef GEN2_READ_HEADER
1090
1091 #define GEN6_READ_HEADER(x) \
1092         u32 offset = i915_mmio_reg_offset(reg); \
1093         unsigned long irqflags; \
1094         u##x val = 0; \
1095         __assert_rpm_wakelock_held(uncore->rpm); \
1096         spin_lock_irqsave(&uncore->lock, irqflags); \
1097         unclaimed_reg_debug(uncore, reg, true, true)
1098
1099 #define GEN6_READ_FOOTER \
1100         unclaimed_reg_debug(uncore, reg, true, false); \
1101         spin_unlock_irqrestore(&uncore->lock, irqflags); \
1102         trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
1103         return val
1104
1105 static noinline void ___force_wake_auto(struct intel_uncore *uncore,
1106                                         enum forcewake_domains fw_domains)
1107 {
1108         struct intel_uncore_forcewake_domain *domain;
1109         unsigned int tmp;
1110
1111         GEM_BUG_ON(fw_domains & ~uncore->fw_domains);
1112
1113         for_each_fw_domain_masked(domain, fw_domains, uncore, tmp)
1114                 fw_domain_arm_timer(domain);
1115
1116         uncore->funcs.force_wake_get(uncore, fw_domains);
1117 }
1118
1119 static inline void __force_wake_auto(struct intel_uncore *uncore,
1120                                      enum forcewake_domains fw_domains)
1121 {
1122         if (WARN_ON(!fw_domains))
1123                 return;
1124
1125         /* Turn on all requested but inactive supported forcewake domains. */
1126         fw_domains &= uncore->fw_domains;
1127         fw_domains &= ~uncore->fw_domains_active;
1128
1129         if (fw_domains)
1130                 ___force_wake_auto(uncore, fw_domains);
1131 }
1132
1133 #define __gen_read(func, x) \
1134 static u##x \
1135 func##_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
1136         enum forcewake_domains fw_engine; \
1137         GEN6_READ_HEADER(x); \
1138         fw_engine = __##func##_reg_read_fw_domains(uncore, offset); \
1139         if (fw_engine) \
1140                 __force_wake_auto(uncore, fw_engine); \
1141         val = __raw_uncore_read##x(uncore, reg); \
1142         GEN6_READ_FOOTER; \
1143 }
1144 #define __gen6_read(x) __gen_read(gen6, x)
1145 #define __fwtable_read(x) __gen_read(fwtable, x)
1146 #define __gen11_fwtable_read(x) __gen_read(gen11_fwtable, x)
1147
1148 __gen11_fwtable_read(8)
1149 __gen11_fwtable_read(16)
1150 __gen11_fwtable_read(32)
1151 __gen11_fwtable_read(64)
1152 __fwtable_read(8)
1153 __fwtable_read(16)
1154 __fwtable_read(32)
1155 __fwtable_read(64)
1156 __gen6_read(8)
1157 __gen6_read(16)
1158 __gen6_read(32)
1159 __gen6_read(64)
1160
1161 #undef __gen11_fwtable_read
1162 #undef __fwtable_read
1163 #undef __gen6_read
1164 #undef GEN6_READ_FOOTER
1165 #undef GEN6_READ_HEADER
1166
1167 #define GEN2_WRITE_HEADER \
1168         trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
1169         __assert_rpm_wakelock_held(uncore->rpm); \
1170
1171 #define GEN2_WRITE_FOOTER
1172
1173 #define __gen2_write(x) \
1174 static void \
1175 gen2_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
1176         GEN2_WRITE_HEADER; \
1177         __raw_uncore_write##x(uncore, reg, val); \
1178         GEN2_WRITE_FOOTER; \
1179 }
1180
1181 #define __gen5_write(x) \
1182 static void \
1183 gen5_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
1184         GEN2_WRITE_HEADER; \
1185         ilk_dummy_write(uncore); \
1186         __raw_uncore_write##x(uncore, reg, val); \
1187         GEN2_WRITE_FOOTER; \
1188 }
1189
1190 __gen5_write(8)
1191 __gen5_write(16)
1192 __gen5_write(32)
1193 __gen2_write(8)
1194 __gen2_write(16)
1195 __gen2_write(32)
1196
1197 #undef __gen5_write
1198 #undef __gen2_write
1199
1200 #undef GEN2_WRITE_FOOTER
1201 #undef GEN2_WRITE_HEADER
1202
1203 #define GEN6_WRITE_HEADER \
1204         u32 offset = i915_mmio_reg_offset(reg); \
1205         unsigned long irqflags; \
1206         trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
1207         __assert_rpm_wakelock_held(uncore->rpm); \
1208         spin_lock_irqsave(&uncore->lock, irqflags); \
1209         unclaimed_reg_debug(uncore, reg, false, true)
1210
1211 #define GEN6_WRITE_FOOTER \
1212         unclaimed_reg_debug(uncore, reg, false, false); \
1213         spin_unlock_irqrestore(&uncore->lock, irqflags)
1214
1215 #define __gen6_write(x) \
1216 static void \
1217 gen6_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
1218         GEN6_WRITE_HEADER; \
1219         if (NEEDS_FORCE_WAKE(offset)) \
1220                 __gen6_gt_wait_for_fifo(uncore); \
1221         __raw_uncore_write##x(uncore, reg, val); \
1222         GEN6_WRITE_FOOTER; \
1223 }
1224
1225 #define __gen_write(func, x) \
1226 static void \
1227 func##_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
1228         enum forcewake_domains fw_engine; \
1229         GEN6_WRITE_HEADER; \
1230         fw_engine = __##func##_reg_write_fw_domains(uncore, offset); \
1231         if (fw_engine) \
1232                 __force_wake_auto(uncore, fw_engine); \
1233         __raw_uncore_write##x(uncore, reg, val); \
1234         GEN6_WRITE_FOOTER; \
1235 }
1236 #define __gen8_write(x) __gen_write(gen8, x)
1237 #define __fwtable_write(x) __gen_write(fwtable, x)
1238 #define __gen11_fwtable_write(x) __gen_write(gen11_fwtable, x)
1239
1240 __gen11_fwtable_write(8)
1241 __gen11_fwtable_write(16)
1242 __gen11_fwtable_write(32)
1243 __fwtable_write(8)
1244 __fwtable_write(16)
1245 __fwtable_write(32)
1246 __gen8_write(8)
1247 __gen8_write(16)
1248 __gen8_write(32)
1249 __gen6_write(8)
1250 __gen6_write(16)
1251 __gen6_write(32)
1252
1253 #undef __gen11_fwtable_write
1254 #undef __fwtable_write
1255 #undef __gen8_write
1256 #undef __gen6_write
1257 #undef GEN6_WRITE_FOOTER
1258 #undef GEN6_WRITE_HEADER
1259
1260 #define ASSIGN_WRITE_MMIO_VFUNCS(uncore, x) \
1261 do { \
1262         (uncore)->funcs.mmio_writeb = x##_write8; \
1263         (uncore)->funcs.mmio_writew = x##_write16; \
1264         (uncore)->funcs.mmio_writel = x##_write32; \
1265 } while (0)
1266
1267 #define ASSIGN_READ_MMIO_VFUNCS(uncore, x) \
1268 do { \
1269         (uncore)->funcs.mmio_readb = x##_read8; \
1270         (uncore)->funcs.mmio_readw = x##_read16; \
1271         (uncore)->funcs.mmio_readl = x##_read32; \
1272         (uncore)->funcs.mmio_readq = x##_read64; \
1273 } while (0)
1274
1275
1276 static void fw_domain_init(struct intel_uncore *uncore,
1277                            enum forcewake_domain_id domain_id,
1278                            i915_reg_t reg_set,
1279                            i915_reg_t reg_ack)
1280 {
1281         struct intel_uncore_forcewake_domain *d;
1282
1283         if (WARN_ON(domain_id >= FW_DOMAIN_ID_COUNT))
1284                 return;
1285
1286         d = &uncore->fw_domain[domain_id];
1287
1288         WARN_ON(d->wake_count);
1289
1290         WARN_ON(!i915_mmio_reg_valid(reg_set));
1291         WARN_ON(!i915_mmio_reg_valid(reg_ack));
1292
1293         d->wake_count = 0;
1294         d->reg_set = uncore->regs + i915_mmio_reg_offset(reg_set);
1295         d->reg_ack = uncore->regs + i915_mmio_reg_offset(reg_ack);
1296
1297         d->id = domain_id;
1298
1299         BUILD_BUG_ON(FORCEWAKE_RENDER != (1 << FW_DOMAIN_ID_RENDER));
1300         BUILD_BUG_ON(FORCEWAKE_BLITTER != (1 << FW_DOMAIN_ID_BLITTER));
1301         BUILD_BUG_ON(FORCEWAKE_MEDIA != (1 << FW_DOMAIN_ID_MEDIA));
1302         BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX0 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX0));
1303         BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX1 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX1));
1304         BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX2 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX2));
1305         BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX3 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX3));
1306         BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX0 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX0));
1307         BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX1 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX1));
1308
1309
1310         d->mask = BIT(domain_id);
1311
1312         hrtimer_init(&d->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1313         d->timer.function = intel_uncore_fw_release_timer;
1314
1315         uncore->fw_domains |= BIT(domain_id);
1316
1317         fw_domain_reset(d);
1318 }
1319
1320 static void fw_domain_fini(struct intel_uncore *uncore,
1321                            enum forcewake_domain_id domain_id)
1322 {
1323         struct intel_uncore_forcewake_domain *d;
1324
1325         if (WARN_ON(domain_id >= FW_DOMAIN_ID_COUNT))
1326                 return;
1327
1328         d = &uncore->fw_domain[domain_id];
1329
1330         WARN_ON(d->wake_count);
1331         WARN_ON(hrtimer_cancel(&d->timer));
1332         memset(d, 0, sizeof(*d));
1333
1334         uncore->fw_domains &= ~BIT(domain_id);
1335 }
1336
1337 static void intel_uncore_fw_domains_init(struct intel_uncore *uncore)
1338 {
1339         struct drm_i915_private *i915 = uncore_to_i915(uncore);
1340
1341         if (!intel_uncore_has_forcewake(uncore))
1342                 return;
1343
1344         if (INTEL_GEN(i915) >= 11) {
1345                 int i;
1346
1347                 uncore->funcs.force_wake_get =
1348                         fw_domains_get_with_fallback;
1349                 uncore->funcs.force_wake_put = fw_domains_put;
1350                 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
1351                                FORCEWAKE_RENDER_GEN9,
1352                                FORCEWAKE_ACK_RENDER_GEN9);
1353                 fw_domain_init(uncore, FW_DOMAIN_ID_BLITTER,
1354                                FORCEWAKE_BLITTER_GEN9,
1355                                FORCEWAKE_ACK_BLITTER_GEN9);
1356                 for (i = 0; i < I915_MAX_VCS; i++) {
1357                         if (!HAS_ENGINE(i915, _VCS(i)))
1358                                 continue;
1359
1360                         fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA_VDBOX0 + i,
1361                                        FORCEWAKE_MEDIA_VDBOX_GEN11(i),
1362                                        FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(i));
1363                 }
1364                 for (i = 0; i < I915_MAX_VECS; i++) {
1365                         if (!HAS_ENGINE(i915, _VECS(i)))
1366                                 continue;
1367
1368                         fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA_VEBOX0 + i,
1369                                        FORCEWAKE_MEDIA_VEBOX_GEN11(i),
1370                                        FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(i));
1371                 }
1372         } else if (IS_GEN_RANGE(i915, 9, 10)) {
1373                 uncore->funcs.force_wake_get =
1374                         fw_domains_get_with_fallback;
1375                 uncore->funcs.force_wake_put = fw_domains_put;
1376                 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
1377                                FORCEWAKE_RENDER_GEN9,
1378                                FORCEWAKE_ACK_RENDER_GEN9);
1379                 fw_domain_init(uncore, FW_DOMAIN_ID_BLITTER,
1380                                FORCEWAKE_BLITTER_GEN9,
1381                                FORCEWAKE_ACK_BLITTER_GEN9);
1382                 fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA,
1383                                FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9);
1384         } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
1385                 uncore->funcs.force_wake_get = fw_domains_get;
1386                 uncore->funcs.force_wake_put = fw_domains_put;
1387                 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
1388                                FORCEWAKE_VLV, FORCEWAKE_ACK_VLV);
1389                 fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA,
1390                                FORCEWAKE_MEDIA_VLV, FORCEWAKE_ACK_MEDIA_VLV);
1391         } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
1392                 uncore->funcs.force_wake_get =
1393                         fw_domains_get_with_thread_status;
1394                 uncore->funcs.force_wake_put = fw_domains_put;
1395                 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
1396                                FORCEWAKE_MT, FORCEWAKE_ACK_HSW);
1397         } else if (IS_IVYBRIDGE(i915)) {
1398                 u32 ecobus;
1399
1400                 /* IVB configs may use multi-threaded forcewake */
1401
1402                 /* A small trick here - if the bios hasn't configured
1403                  * MT forcewake, and if the device is in RC6, then
1404                  * force_wake_mt_get will not wake the device and the
1405                  * ECOBUS read will return zero. Which will be
1406                  * (correctly) interpreted by the test below as MT
1407                  * forcewake being disabled.
1408                  */
1409                 uncore->funcs.force_wake_get =
1410                         fw_domains_get_with_thread_status;
1411                 uncore->funcs.force_wake_put = fw_domains_put;
1412
1413                 /* We need to init first for ECOBUS access and then
1414                  * determine later if we want to reinit, in case of MT access is
1415                  * not working. In this stage we don't know which flavour this
1416                  * ivb is, so it is better to reset also the gen6 fw registers
1417                  * before the ecobus check.
1418                  */
1419
1420                 __raw_uncore_write32(uncore, FORCEWAKE, 0);
1421                 __raw_posting_read(uncore, ECOBUS);
1422
1423                 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
1424                                FORCEWAKE_MT, FORCEWAKE_MT_ACK);
1425
1426                 spin_lock_irq(&uncore->lock);
1427                 fw_domains_get_with_thread_status(uncore, FORCEWAKE_RENDER);
1428                 ecobus = __raw_uncore_read32(uncore, ECOBUS);
1429                 fw_domains_put(uncore, FORCEWAKE_RENDER);
1430                 spin_unlock_irq(&uncore->lock);
1431
1432                 if (!(ecobus & FORCEWAKE_MT_ENABLE)) {
1433                         DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n");
1434                         DRM_INFO("when using vblank-synced partial screen updates.\n");
1435                         fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
1436                                        FORCEWAKE, FORCEWAKE_ACK);
1437                 }
1438         } else if (IS_GEN(i915, 6)) {
1439                 uncore->funcs.force_wake_get =
1440                         fw_domains_get_with_thread_status;
1441                 uncore->funcs.force_wake_put = fw_domains_put;
1442                 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
1443                                FORCEWAKE, FORCEWAKE_ACK);
1444         }
1445
1446         /* All future platforms are expected to require complex power gating */
1447         WARN_ON(uncore->fw_domains == 0);
1448 }
1449
1450 #define ASSIGN_FW_DOMAINS_TABLE(uncore, d) \
1451 { \
1452         (uncore)->fw_domains_table = \
1453                         (struct intel_forcewake_range *)(d); \
1454         (uncore)->fw_domains_table_entries = ARRAY_SIZE((d)); \
1455 }
1456
1457 static int i915_pmic_bus_access_notifier(struct notifier_block *nb,
1458                                          unsigned long action, void *data)
1459 {
1460         struct drm_i915_private *dev_priv = container_of(nb,
1461                         struct drm_i915_private, uncore.pmic_bus_access_nb);
1462
1463         switch (action) {
1464         case MBI_PMIC_BUS_ACCESS_BEGIN:
1465                 /*
1466                  * forcewake all now to make sure that we don't need to do a
1467                  * forcewake later which on systems where this notifier gets
1468                  * called requires the punit to access to the shared pmic i2c
1469                  * bus, which will be busy after this notification, leading to:
1470                  * "render: timed out waiting for forcewake ack request."
1471                  * errors.
1472                  *
1473                  * The notifier is unregistered during intel_runtime_suspend(),
1474                  * so it's ok to access the HW here without holding a RPM
1475                  * wake reference -> disable wakeref asserts for the time of
1476                  * the access.
1477                  */
1478                 disable_rpm_wakeref_asserts(dev_priv);
1479                 intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
1480                 enable_rpm_wakeref_asserts(dev_priv);
1481                 break;
1482         case MBI_PMIC_BUS_ACCESS_END:
1483                 intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
1484                 break;
1485         }
1486
1487         return NOTIFY_OK;
1488 }
1489
1490 static int uncore_mmio_setup(struct intel_uncore *uncore)
1491 {
1492         struct drm_i915_private *i915 = uncore_to_i915(uncore);
1493         struct pci_dev *pdev = i915->drm.pdev;
1494         int mmio_bar;
1495         int mmio_size;
1496
1497         mmio_bar = IS_GEN(i915, 2) ? 1 : 0;
1498         /*
1499          * Before gen4, the registers and the GTT are behind different BARs.
1500          * However, from gen4 onwards, the registers and the GTT are shared
1501          * in the same BAR, so we want to restrict this ioremap from
1502          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
1503          * the register BAR remains the same size for all the earlier
1504          * generations up to Ironlake.
1505          */
1506         if (INTEL_GEN(i915) < 5)
1507                 mmio_size = 512 * 1024;
1508         else
1509                 mmio_size = 2 * 1024 * 1024;
1510         uncore->regs = pci_iomap(pdev, mmio_bar, mmio_size);
1511         if (uncore->regs == NULL) {
1512                 DRM_ERROR("failed to map registers\n");
1513
1514                 return -EIO;
1515         }
1516
1517         return 0;
1518 }
1519
1520 static void uncore_mmio_cleanup(struct intel_uncore *uncore)
1521 {
1522         struct drm_i915_private *i915 = uncore_to_i915(uncore);
1523         struct pci_dev *pdev = i915->drm.pdev;
1524
1525         pci_iounmap(pdev, uncore->regs);
1526 }
1527
1528 void intel_uncore_init_early(struct intel_uncore *uncore)
1529 {
1530         spin_lock_init(&uncore->lock);
1531 }
1532
1533 int intel_uncore_init_mmio(struct intel_uncore *uncore)
1534 {
1535         struct drm_i915_private *i915 = uncore_to_i915(uncore);
1536         int ret;
1537
1538         ret = uncore_mmio_setup(uncore);
1539         if (ret)
1540                 return ret;
1541
1542         i915_check_vgpu(i915);
1543
1544         if (INTEL_GEN(i915) > 5 && !intel_vgpu_active(i915))
1545                 uncore->flags |= UNCORE_HAS_FORCEWAKE;
1546
1547         intel_uncore_fw_domains_init(uncore);
1548         __intel_uncore_early_sanitize(uncore, 0);
1549
1550         uncore->unclaimed_mmio_check = 1;
1551         uncore->pmic_bus_access_nb.notifier_call =
1552                 i915_pmic_bus_access_notifier;
1553
1554         uncore->rpm = &i915->runtime_pm;
1555
1556         if (!intel_uncore_has_forcewake(uncore)) {
1557                 if (IS_GEN(i915, 5)) {
1558                         ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen5);
1559                         ASSIGN_READ_MMIO_VFUNCS(uncore, gen5);
1560                 } else {
1561                         ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen2);
1562                         ASSIGN_READ_MMIO_VFUNCS(uncore, gen2);
1563                 }
1564         } else if (IS_GEN_RANGE(i915, 6, 7)) {
1565                 ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen6);
1566
1567                 if (IS_VALLEYVIEW(i915)) {
1568                         ASSIGN_FW_DOMAINS_TABLE(uncore, __vlv_fw_ranges);
1569                         ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
1570                 } else {
1571                         ASSIGN_READ_MMIO_VFUNCS(uncore, gen6);
1572                 }
1573         } else if (IS_GEN(i915, 8)) {
1574                 if (IS_CHERRYVIEW(i915)) {
1575                         ASSIGN_FW_DOMAINS_TABLE(uncore, __chv_fw_ranges);
1576                         ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
1577                         ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
1578
1579                 } else {
1580                         ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen8);
1581                         ASSIGN_READ_MMIO_VFUNCS(uncore, gen6);
1582                 }
1583         } else if (IS_GEN_RANGE(i915, 9, 10)) {
1584                 ASSIGN_FW_DOMAINS_TABLE(uncore, __gen9_fw_ranges);
1585                 ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
1586                 ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
1587         } else {
1588                 ASSIGN_FW_DOMAINS_TABLE(uncore, __gen11_fw_ranges);
1589                 ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen11_fwtable);
1590                 ASSIGN_READ_MMIO_VFUNCS(uncore, gen11_fwtable);
1591         }
1592
1593         if (HAS_FPGA_DBG_UNCLAIMED(i915))
1594                 uncore->flags |= UNCORE_HAS_FPGA_DBG_UNCLAIMED;
1595
1596         if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
1597                 uncore->flags |= UNCORE_HAS_DBG_UNCLAIMED;
1598
1599         if (IS_GEN_RANGE(i915, 6, 7))
1600                 uncore->flags |= UNCORE_HAS_FIFO;
1601
1602         iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb);
1603
1604         return 0;
1605 }
1606
1607 /*
1608  * We might have detected that some engines are fused off after we initialized
1609  * the forcewake domains. Prune them, to make sure they only reference existing
1610  * engines.
1611  */
1612 void intel_uncore_prune_mmio_domains(struct intel_uncore *uncore)
1613 {
1614         struct drm_i915_private *i915 = uncore_to_i915(uncore);
1615
1616         if (INTEL_GEN(i915) >= 11) {
1617                 enum forcewake_domains fw_domains = uncore->fw_domains;
1618                 enum forcewake_domain_id domain_id;
1619                 int i;
1620
1621                 for (i = 0; i < I915_MAX_VCS; i++) {
1622                         domain_id = FW_DOMAIN_ID_MEDIA_VDBOX0 + i;
1623
1624                         if (HAS_ENGINE(i915, _VCS(i)))
1625                                 continue;
1626
1627                         if (fw_domains & BIT(domain_id))
1628                                 fw_domain_fini(uncore, domain_id);
1629                 }
1630
1631                 for (i = 0; i < I915_MAX_VECS; i++) {
1632                         domain_id = FW_DOMAIN_ID_MEDIA_VEBOX0 + i;
1633
1634                         if (HAS_ENGINE(i915, _VECS(i)))
1635                                 continue;
1636
1637                         if (fw_domains & BIT(domain_id))
1638                                 fw_domain_fini(uncore, domain_id);
1639                 }
1640         }
1641 }
1642
1643 void intel_uncore_fini_mmio(struct intel_uncore *uncore)
1644 {
1645         /* Paranoia: make sure we have disabled everything before we exit. */
1646         intel_uncore_sanitize(uncore_to_i915(uncore));
1647
1648         iosf_mbi_punit_acquire();
1649         iosf_mbi_unregister_pmic_bus_access_notifier_unlocked(
1650                 &uncore->pmic_bus_access_nb);
1651         intel_uncore_forcewake_reset(uncore);
1652         iosf_mbi_punit_release();
1653         uncore_mmio_cleanup(uncore);
1654 }
1655
1656 static const struct reg_whitelist {
1657         i915_reg_t offset_ldw;
1658         i915_reg_t offset_udw;
1659         u16 gen_mask;
1660         u8 size;
1661 } reg_read_whitelist[] = { {
1662         .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
1663         .offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
1664         .gen_mask = INTEL_GEN_MASK(4, 11),
1665         .size = 8
1666 } };
1667
1668 int i915_reg_read_ioctl(struct drm_device *dev,
1669                         void *data, struct drm_file *file)
1670 {
1671         struct drm_i915_private *dev_priv = to_i915(dev);
1672         struct drm_i915_reg_read *reg = data;
1673         struct reg_whitelist const *entry;
1674         intel_wakeref_t wakeref;
1675         unsigned int flags;
1676         int remain;
1677         int ret = 0;
1678
1679         entry = reg_read_whitelist;
1680         remain = ARRAY_SIZE(reg_read_whitelist);
1681         while (remain) {
1682                 u32 entry_offset = i915_mmio_reg_offset(entry->offset_ldw);
1683
1684                 GEM_BUG_ON(!is_power_of_2(entry->size));
1685                 GEM_BUG_ON(entry->size > 8);
1686                 GEM_BUG_ON(entry_offset & (entry->size - 1));
1687
1688                 if (INTEL_INFO(dev_priv)->gen_mask & entry->gen_mask &&
1689                     entry_offset == (reg->offset & -entry->size))
1690                         break;
1691                 entry++;
1692                 remain--;
1693         }
1694
1695         if (!remain)
1696                 return -EINVAL;
1697
1698         flags = reg->offset & (entry->size - 1);
1699
1700         with_intel_runtime_pm(dev_priv, wakeref) {
1701                 if (entry->size == 8 && flags == I915_REG_READ_8B_WA)
1702                         reg->val = I915_READ64_2x32(entry->offset_ldw,
1703                                                     entry->offset_udw);
1704                 else if (entry->size == 8 && flags == 0)
1705                         reg->val = I915_READ64(entry->offset_ldw);
1706                 else if (entry->size == 4 && flags == 0)
1707                         reg->val = I915_READ(entry->offset_ldw);
1708                 else if (entry->size == 2 && flags == 0)
1709                         reg->val = I915_READ16(entry->offset_ldw);
1710                 else if (entry->size == 1 && flags == 0)
1711                         reg->val = I915_READ8(entry->offset_ldw);
1712                 else
1713                         ret = -EINVAL;
1714         }
1715
1716         return ret;
1717 }
1718
1719 /**
1720  * __intel_wait_for_register_fw - wait until register matches expected state
1721  * @uncore: the struct intel_uncore
1722  * @reg: the register to read
1723  * @mask: mask to apply to register value
1724  * @value: expected value
1725  * @fast_timeout_us: fast timeout in microsecond for atomic/tight wait
1726  * @slow_timeout_ms: slow timeout in millisecond
1727  * @out_value: optional placeholder to hold registry value
1728  *
1729  * This routine waits until the target register @reg contains the expected
1730  * @value after applying the @mask, i.e. it waits until ::
1731  *
1732  *     (I915_READ_FW(reg) & mask) == value
1733  *
1734  * Otherwise, the wait will timeout after @slow_timeout_ms milliseconds.
1735  * For atomic context @slow_timeout_ms must be zero and @fast_timeout_us
1736  * must be not larger than 20,0000 microseconds.
1737  *
1738  * Note that this routine assumes the caller holds forcewake asserted, it is
1739  * not suitable for very long waits. See intel_wait_for_register() if you
1740  * wish to wait without holding forcewake for the duration (i.e. you expect
1741  * the wait to be slow).
1742  *
1743  * Returns 0 if the register matches the desired condition, or -ETIMEOUT.
1744  */
1745 int __intel_wait_for_register_fw(struct intel_uncore *uncore,
1746                                  i915_reg_t reg,
1747                                  u32 mask,
1748                                  u32 value,
1749                                  unsigned int fast_timeout_us,
1750                                  unsigned int slow_timeout_ms,
1751                                  u32 *out_value)
1752 {
1753         u32 uninitialized_var(reg_value);
1754 #define done (((reg_value = intel_uncore_read_fw(uncore, reg)) & mask) == value)
1755         int ret;
1756
1757         /* Catch any overuse of this function */
1758         might_sleep_if(slow_timeout_ms);
1759         GEM_BUG_ON(fast_timeout_us > 20000);
1760
1761         ret = -ETIMEDOUT;
1762         if (fast_timeout_us && fast_timeout_us <= 20000)
1763                 ret = _wait_for_atomic(done, fast_timeout_us, 0);
1764         if (ret && slow_timeout_ms)
1765                 ret = wait_for(done, slow_timeout_ms);
1766
1767         if (out_value)
1768                 *out_value = reg_value;
1769
1770         return ret;
1771 #undef done
1772 }
1773
1774 /**
1775  * __intel_wait_for_register - wait until register matches expected state
1776  * @uncore: the struct intel_uncore
1777  * @reg: the register to read
1778  * @mask: mask to apply to register value
1779  * @value: expected value
1780  * @fast_timeout_us: fast timeout in microsecond for atomic/tight wait
1781  * @slow_timeout_ms: slow timeout in millisecond
1782  * @out_value: optional placeholder to hold registry value
1783  *
1784  * This routine waits until the target register @reg contains the expected
1785  * @value after applying the @mask, i.e. it waits until ::
1786  *
1787  *     (I915_READ(reg) & mask) == value
1788  *
1789  * Otherwise, the wait will timeout after @timeout_ms milliseconds.
1790  *
1791  * Returns 0 if the register matches the desired condition, or -ETIMEOUT.
1792  */
1793 int __intel_wait_for_register(struct intel_uncore *uncore,
1794                               i915_reg_t reg,
1795                               u32 mask,
1796                               u32 value,
1797                               unsigned int fast_timeout_us,
1798                               unsigned int slow_timeout_ms,
1799                               u32 *out_value)
1800 {
1801         unsigned fw =
1802                 intel_uncore_forcewake_for_reg(uncore, reg, FW_REG_READ);
1803         u32 reg_value;
1804         int ret;
1805
1806         might_sleep_if(slow_timeout_ms);
1807
1808         spin_lock_irq(&uncore->lock);
1809         intel_uncore_forcewake_get__locked(uncore, fw);
1810
1811         ret = __intel_wait_for_register_fw(uncore,
1812                                            reg, mask, value,
1813                                            fast_timeout_us, 0, &reg_value);
1814
1815         intel_uncore_forcewake_put__locked(uncore, fw);
1816         spin_unlock_irq(&uncore->lock);
1817
1818         if (ret && slow_timeout_ms)
1819                 ret = __wait_for(reg_value = intel_uncore_read_notrace(uncore,
1820                                                                        reg),
1821                                  (reg_value & mask) == value,
1822                                  slow_timeout_ms * 1000, 10, 1000);
1823
1824         /* just trace the final value */
1825         trace_i915_reg_rw(false, reg, reg_value, sizeof(reg_value), true);
1826
1827         if (out_value)
1828                 *out_value = reg_value;
1829
1830         return ret;
1831 }
1832
1833 bool intel_uncore_unclaimed_mmio(struct intel_uncore *uncore)
1834 {
1835         return check_for_unclaimed_mmio(uncore);
1836 }
1837
1838 bool
1839 intel_uncore_arm_unclaimed_mmio_detection(struct intel_uncore *uncore)
1840 {
1841         bool ret = false;
1842
1843         spin_lock_irq(&uncore->lock);
1844
1845         if (unlikely(uncore->unclaimed_mmio_check <= 0))
1846                 goto out;
1847
1848         if (unlikely(intel_uncore_unclaimed_mmio(uncore))) {
1849                 if (!i915_modparams.mmio_debug) {
1850                         DRM_DEBUG("Unclaimed register detected, "
1851                                   "enabling oneshot unclaimed register reporting. "
1852                                   "Please use i915.mmio_debug=N for more information.\n");
1853                         i915_modparams.mmio_debug++;
1854                 }
1855                 uncore->unclaimed_mmio_check--;
1856                 ret = true;
1857         }
1858
1859 out:
1860         spin_unlock_irq(&uncore->lock);
1861
1862         return ret;
1863 }
1864
1865 static enum forcewake_domains
1866 intel_uncore_forcewake_for_read(struct intel_uncore *uncore,
1867                                 i915_reg_t reg)
1868 {
1869         struct drm_i915_private *i915 = uncore_to_i915(uncore);
1870         u32 offset = i915_mmio_reg_offset(reg);
1871         enum forcewake_domains fw_domains;
1872
1873         if (INTEL_GEN(i915) >= 11) {
1874                 fw_domains = __gen11_fwtable_reg_read_fw_domains(uncore, offset);
1875         } else if (HAS_FWTABLE(i915)) {
1876                 fw_domains = __fwtable_reg_read_fw_domains(uncore, offset);
1877         } else if (INTEL_GEN(i915) >= 6) {
1878                 fw_domains = __gen6_reg_read_fw_domains(uncore, offset);
1879         } else {
1880                 /* on devices with FW we expect to hit one of the above cases */
1881                 if (intel_uncore_has_forcewake(uncore))
1882                         MISSING_CASE(INTEL_GEN(i915));
1883
1884                 fw_domains = 0;
1885         }
1886
1887         WARN_ON(fw_domains & ~uncore->fw_domains);
1888
1889         return fw_domains;
1890 }
1891
1892 static enum forcewake_domains
1893 intel_uncore_forcewake_for_write(struct intel_uncore *uncore,
1894                                  i915_reg_t reg)
1895 {
1896         struct drm_i915_private *i915 = uncore_to_i915(uncore);
1897         u32 offset = i915_mmio_reg_offset(reg);
1898         enum forcewake_domains fw_domains;
1899
1900         if (INTEL_GEN(i915) >= 11) {
1901                 fw_domains = __gen11_fwtable_reg_write_fw_domains(uncore, offset);
1902         } else if (HAS_FWTABLE(i915) && !IS_VALLEYVIEW(i915)) {
1903                 fw_domains = __fwtable_reg_write_fw_domains(uncore, offset);
1904         } else if (IS_GEN(i915, 8)) {
1905                 fw_domains = __gen8_reg_write_fw_domains(uncore, offset);
1906         } else if (IS_GEN_RANGE(i915, 6, 7)) {
1907                 fw_domains = FORCEWAKE_RENDER;
1908         } else {
1909                 /* on devices with FW we expect to hit one of the above cases */
1910                 if (intel_uncore_has_forcewake(uncore))
1911                         MISSING_CASE(INTEL_GEN(i915));
1912
1913                 fw_domains = 0;
1914         }
1915
1916         WARN_ON(fw_domains & ~uncore->fw_domains);
1917
1918         return fw_domains;
1919 }
1920
1921 /**
1922  * intel_uncore_forcewake_for_reg - which forcewake domains are needed to access
1923  *                                  a register
1924  * @uncore: pointer to struct intel_uncore
1925  * @reg: register in question
1926  * @op: operation bitmask of FW_REG_READ and/or FW_REG_WRITE
1927  *
1928  * Returns a set of forcewake domains required to be taken with for example
1929  * intel_uncore_forcewake_get for the specified register to be accessible in the
1930  * specified mode (read, write or read/write) with raw mmio accessors.
1931  *
1932  * NOTE: On Gen6 and Gen7 write forcewake domain (FORCEWAKE_RENDER) requires the
1933  * callers to do FIFO management on their own or risk losing writes.
1934  */
1935 enum forcewake_domains
1936 intel_uncore_forcewake_for_reg(struct intel_uncore *uncore,
1937                                i915_reg_t reg, unsigned int op)
1938 {
1939         enum forcewake_domains fw_domains = 0;
1940
1941         WARN_ON(!op);
1942
1943         if (!intel_uncore_has_forcewake(uncore))
1944                 return 0;
1945
1946         if (op & FW_REG_READ)
1947                 fw_domains = intel_uncore_forcewake_for_read(uncore, reg);
1948
1949         if (op & FW_REG_WRITE)
1950                 fw_domains |= intel_uncore_forcewake_for_write(uncore, reg);
1951
1952         return fw_domains;
1953 }
1954
1955 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1956 #include "selftests/mock_uncore.c"
1957 #include "selftests/intel_uncore.c"
1958 #endif