drivers/gpu/drm/i915/intel_uncore.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "i915_drv.h"
  25 #include "intel_drv.h"
  26 #include "i915_vgpu.h"
  27
  28 #include <asm/iosf_mbi.h>
  29 #include <linux/pm_runtime.h>
  30
  31 #define FORCEWAKE_ACK_TIMEOUT_MS 50
  32 #define GT_FIFO_TIMEOUT_MS       10
  33
  34 #define __raw_posting_read(...) ((void)__raw_uncore_read32(__VA_ARGS__))
  35
  36 static const char * const forcewake_domain_names[] = {
  37         "render",
  38         "blitter",
  39         "media",
  40         "vdbox0",
  41         "vdbox1",
  42         "vdbox2",
  43         "vdbox3",
  44         "vebox0",
  45         "vebox1",
  46 };
  47
  48 const char *
  49 intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id)
  50 {
  51         BUILD_BUG_ON(ARRAY_SIZE(forcewake_domain_names) != FW_DOMAIN_ID_COUNT);
  52
  53         if (id >= 0 && id < FW_DOMAIN_ID_COUNT)
  54                 return forcewake_domain_names[id];
  55
  56         WARN_ON(id);
  57
  58         return "unknown";
  59 }
  60
  61 #define fw_ack(d) readl((d)->reg_ack)
  62 #define fw_set(d, val) writel(_MASKED_BIT_ENABLE((val)), (d)->reg_set)
  63 #define fw_clear(d, val) writel(_MASKED_BIT_DISABLE((val)), (d)->reg_set)
  64
  65 static inline void
  66 fw_domain_reset(const struct intel_uncore_forcewake_domain *d)
  67 {
  68         /*
  69          * We don't really know if the powerwell for the forcewake domain we are
  70          * trying to reset here does exist at this point (engines could be fused
  71          * off in ICL+), so no waiting for acks
  72          */
  73         /* WaRsClearFWBitsAtReset:bdw,skl */
  74         fw_clear(d, 0xffff);
  75 }
  76
  77 static inline void
  78 fw_domain_arm_timer(struct intel_uncore_forcewake_domain *d)
  79 {
  80         d->wake_count++;
  81         hrtimer_start_range_ns(&d->timer,
  82                                NSEC_PER_MSEC,
  83                                NSEC_PER_MSEC,
  84                                HRTIMER_MODE_REL);
  85 }
  86
  87 static inline int
  88 __wait_for_ack(const struct intel_uncore_forcewake_domain *d,
  89                const u32 ack,
  90                const u32 value)
  91 {
  92         return wait_for_atomic((fw_ack(d) & ack) == value,
  93                                FORCEWAKE_ACK_TIMEOUT_MS);
  94 }
  95
  96 static inline int
  97 wait_ack_clear(const struct intel_uncore_forcewake_domain *d,
  98                const u32 ack)
  99 {
 100         return __wait_for_ack(d, ack, 0);
 101 }
 102
 103 static inline int
 104 wait_ack_set(const struct intel_uncore_forcewake_domain *d,
 105              const u32 ack)
 106 {
 107         return __wait_for_ack(d, ack, ack);
 108 }
 109
 110 static inline void
 111 fw_domain_wait_ack_clear(const struct intel_uncore_forcewake_domain *d)
 112 {
 113         if (wait_ack_clear(d, FORCEWAKE_KERNEL))
 114                 DRM_ERROR("%s: timed out waiting for forcewake ack to clear.\n",
 115                           intel_uncore_forcewake_domain_to_str(d->id));
 116 }
 117
 118 enum ack_type {
 119         ACK_CLEAR = 0,
 120         ACK_SET
 121 };
 122
 123 static int
 124 fw_domain_wait_ack_with_fallback(const struct intel_uncore_forcewake_domain *d,
 125                                  const enum ack_type type)
 126 {
 127         const u32 ack_bit = FORCEWAKE_KERNEL;
 128         const u32 value = type == ACK_SET ? ack_bit : 0;
 129         unsigned int pass;
 130         bool ack_detected;
 131
 132         /*
 133          * There is a possibility of driver's wake request colliding
 134          * with hardware's own wake requests and that can cause
 135          * hardware to not deliver the driver's ack message.
 136          *
 137          * Use a fallback bit toggle to kick the gpu state machine
 138          * in the hope that the original ack will be delivered along with
 139          * the fallback ack.
 140          *
 141          * This workaround is described in HSDES #1604254524 and it's known as:
 142          * WaRsForcewakeAddDelayForAck:skl,bxt,kbl,glk,cfl,cnl,icl
 143          * although the name is a bit misleading.
 144          */
 145
 146         pass = 1;
 147         do {
 148                 wait_ack_clear(d, FORCEWAKE_KERNEL_FALLBACK);
 149
 150                 fw_set(d, FORCEWAKE_KERNEL_FALLBACK);
 151                 /* Give gt some time to relax before the polling frenzy */
 152                 udelay(10 * pass);
 153                 wait_ack_set(d, FORCEWAKE_KERNEL_FALLBACK);
 154
 155                 ack_detected = (fw_ack(d) & ack_bit) == value;
 156
 157                 fw_clear(d, FORCEWAKE_KERNEL_FALLBACK);
 158         } while (!ack_detected && pass++ < 10);
 159
 160         DRM_DEBUG_DRIVER("%s had to use fallback to %s ack, 0x%x (passes %u)\n",
 161                          intel_uncore_forcewake_domain_to_str(d->id),
 162                          type == ACK_SET ? "set" : "clear",
 163                          fw_ack(d),
 164                          pass);
 165
 166         return ack_detected ? 0 : -ETIMEDOUT;
 167 }
 168
 169 static inline void
 170 fw_domain_wait_ack_clear_fallback(const struct intel_uncore_forcewake_domain *d)
 171 {
 172         if (likely(!wait_ack_clear(d, FORCEWAKE_KERNEL)))
 173                 return;
 174
 175         if (fw_domain_wait_ack_with_fallback(d, ACK_CLEAR))
 176                 fw_domain_wait_ack_clear(d);
 177 }
 178
 179 static inline void
 180 fw_domain_get(const struct intel_uncore_forcewake_domain *d)
 181 {
 182         fw_set(d, FORCEWAKE_KERNEL);
 183 }
 184
 185 static inline void
 186 fw_domain_wait_ack_set(const struct intel_uncore_forcewake_domain *d)
 187 {
 188         if (wait_ack_set(d, FORCEWAKE_KERNEL))
 189                 DRM_ERROR("%s: timed out waiting for forcewake ack request.\n",
 190                           intel_uncore_forcewake_domain_to_str(d->id));
 191 }
 192
 193 static inline void
 194 fw_domain_wait_ack_set_fallback(const struct intel_uncore_forcewake_domain *d)
 195 {
 196         if (likely(!wait_ack_set(d, FORCEWAKE_KERNEL)))
 197                 return;
 198
 199         if (fw_domain_wait_ack_with_fallback(d, ACK_SET))
 200                 fw_domain_wait_ack_set(d);
 201 }
 202
 203 static inline void
 204 fw_domain_put(const struct intel_uncore_forcewake_domain *d)
 205 {
 206         fw_clear(d, FORCEWAKE_KERNEL);
 207 }
 208
 209 static void
 210 fw_domains_get(struct intel_uncore *uncore, enum forcewake_domains fw_domains)
 211 {
 212         struct intel_uncore_forcewake_domain *d;
 213         unsigned int tmp;
 214
 215         GEM_BUG_ON(fw_domains & ~uncore->fw_domains);
 216
 217         for_each_fw_domain_masked(d, fw_domains, uncore, tmp) {
 218                 fw_domain_wait_ack_clear(d);
 219                 fw_domain_get(d);
 220         }
 221
 222         for_each_fw_domain_masked(d, fw_domains, uncore, tmp)
 223                 fw_domain_wait_ack_set(d);
 224
 225         uncore->fw_domains_active |= fw_domains;
 226 }
 227
 228 static void
 229 fw_domains_get_with_fallback(struct intel_uncore *uncore,
 230                              enum forcewake_domains fw_domains)
 231 {
 232         struct intel_uncore_forcewake_domain *d;
 233         unsigned int tmp;
 234
 235         GEM_BUG_ON(fw_domains & ~uncore->fw_domains);
 236
 237         for_each_fw_domain_masked(d, fw_domains, uncore, tmp) {
 238                 fw_domain_wait_ack_clear_fallback(d);
 239                 fw_domain_get(d);
 240         }
 241
 242         for_each_fw_domain_masked(d, fw_domains, uncore, tmp)
 243                 fw_domain_wait_ack_set_fallback(d);
 244
 245         uncore->fw_domains_active |= fw_domains;
 246 }
 247
 248 static void
 249 fw_domains_put(struct intel_uncore *uncore, enum forcewake_domains fw_domains)
 250 {
 251         struct intel_uncore_forcewake_domain *d;
 252         unsigned int tmp;
 253
 254         GEM_BUG_ON(fw_domains & ~uncore->fw_domains);
 255
 256         for_each_fw_domain_masked(d, fw_domains, uncore, tmp)
 257                 fw_domain_put(d);
 258
 259         uncore->fw_domains_active &= ~fw_domains;
 260 }
 261
 262 static void
 263 fw_domains_reset(struct intel_uncore *uncore,
 264                  enum forcewake_domains fw_domains)
 265 {
 266         struct intel_uncore_forcewake_domain *d;
 267         unsigned int tmp;
 268
 269         if (!fw_domains)
 270                 return;
 271
 272         GEM_BUG_ON(fw_domains & ~uncore->fw_domains);
 273
 274         for_each_fw_domain_masked(d, fw_domains, uncore, tmp)
 275                 fw_domain_reset(d);
 276 }
 277
 278 static inline u32 gt_thread_status(struct intel_uncore *uncore)
 279 {
 280         u32 val;
 281
 282         val = __raw_uncore_read32(uncore, GEN6_GT_THREAD_STATUS_REG);
 283         val &= GEN6_GT_THREAD_STATUS_CORE_MASK;
 284
 285         return val;
 286 }
 287
 288 static void __gen6_gt_wait_for_thread_c0(struct intel_uncore *uncore)
 289 {
 290         /*
 291          * w/a for a sporadic read returning 0 by waiting for the GT
 292          * thread to wake up.
 293          */
 294         WARN_ONCE(wait_for_atomic_us(gt_thread_status(uncore) == 0, 5000),
 295                   "GT thread status wait timed out\n");
 296 }
 297
 298 static void fw_domains_get_with_thread_status(struct intel_uncore *uncore,
 299                                               enum forcewake_domains fw_domains)
 300 {
 301         fw_domains_get(uncore, fw_domains);
 302
 303         /* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */
 304         __gen6_gt_wait_for_thread_c0(uncore);
 305 }
 306
 307 static inline u32 fifo_free_entries(struct intel_uncore *uncore)
 308 {
 309         u32 count = __raw_uncore_read32(uncore, GTFIFOCTL);
 310
 311         return count & GT_FIFO_FREE_ENTRIES_MASK;
 312 }
 313
 314 static void __gen6_gt_wait_for_fifo(struct intel_uncore *uncore)
 315 {
 316         u32 n;
 317
 318         /* On VLV, FIFO will be shared by both SW and HW.
 319          * So, we need to read the FREE_ENTRIES everytime */
 320         if (IS_VALLEYVIEW(uncore_to_i915(uncore)))
 321                 n = fifo_free_entries(uncore);
 322         else
 323                 n = uncore->fifo_count;
 324
 325         if (n <= GT_FIFO_NUM_RESERVED_ENTRIES) {
 326                 if (wait_for_atomic((n = fifo_free_entries(uncore)) >
 327                                     GT_FIFO_NUM_RESERVED_ENTRIES,
 328                                     GT_FIFO_TIMEOUT_MS)) {
 329                         DRM_DEBUG("GT_FIFO timeout, entries: %u\n", n);
 330                         return;
 331                 }
 332         }
 333
 334         uncore->fifo_count = n - 1;
 335 }
 336
 337 static enum hrtimer_restart
 338 intel_uncore_fw_release_timer(struct hrtimer *timer)
 339 {
 340         struct intel_uncore_forcewake_domain *domain =
 341                container_of(timer, struct intel_uncore_forcewake_domain, timer);
 342         struct intel_uncore *uncore = forcewake_domain_to_uncore(domain);
 343         unsigned long irqflags;
 344
 345         assert_rpm_device_not_suspended(uncore->rpm);
 346
 347         if (xchg(&domain->active, false))
 348                 return HRTIMER_RESTART;
 349
 350         spin_lock_irqsave(&uncore->lock, irqflags);
 351         if (WARN_ON(domain->wake_count == 0))
 352                 domain->wake_count++;
 353
 354         if (--domain->wake_count == 0)
 355                 uncore->funcs.force_wake_put(uncore, domain->mask);
 356
 357         spin_unlock_irqrestore(&uncore->lock, irqflags);
 358
 359         return HRTIMER_NORESTART;
 360 }
 361
 362 /* Note callers must have acquired the PUNIT->PMIC bus, before calling this. */
 363 static unsigned int
 364 intel_uncore_forcewake_reset(struct intel_uncore *uncore)
 365 {
 366         unsigned long irqflags;
 367         struct intel_uncore_forcewake_domain *domain;
 368         int retry_count = 100;
 369         enum forcewake_domains fw, active_domains;
 370
 371         iosf_mbi_assert_punit_acquired();
 372
 373         /* Hold uncore.lock across reset to prevent any register access
 374          * with forcewake not set correctly. Wait until all pending
 375          * timers are run before holding.
 376          */
 377         while (1) {
 378                 unsigned int tmp;
 379
 380                 active_domains = 0;
 381
 382                 for_each_fw_domain(domain, uncore, tmp) {
 383                         smp_store_mb(domain->active, false);
 384                         if (hrtimer_cancel(&domain->timer) == 0)
 385                                 continue;
 386
 387                         intel_uncore_fw_release_timer(&domain->timer);
 388                 }
 389
 390                 spin_lock_irqsave(&uncore->lock, irqflags);
 391
 392                 for_each_fw_domain(domain, uncore, tmp) {
 393                         if (hrtimer_active(&domain->timer))
 394                                 active_domains |= domain->mask;
 395                 }
 396
 397                 if (active_domains == 0)
 398                         break;
 399
 400                 if (--retry_count == 0) {
 401                         DRM_ERROR("Timed out waiting for forcewake timers to finish\n");
 402                         break;
 403                 }
 404
 405                 spin_unlock_irqrestore(&uncore->lock, irqflags);
 406                 cond_resched();
 407         }
 408
 409         WARN_ON(active_domains);
 410
 411         fw = uncore->fw_domains_active;
 412         if (fw)
 413                 uncore->funcs.force_wake_put(uncore, fw);
 414
 415         fw_domains_reset(uncore, uncore->fw_domains);
 416         assert_forcewakes_inactive(uncore);
 417
 418         spin_unlock_irqrestore(&uncore->lock, irqflags);
 419
 420         return fw; /* track the lost user forcewake domains */
 421 }
 422
 423 static bool
 424 fpga_check_for_unclaimed_mmio(struct intel_uncore *uncore)
 425 {
 426         u32 dbg;
 427
 428         dbg = __raw_uncore_read32(uncore, FPGA_DBG);
 429         if (likely(!(dbg & FPGA_DBG_RM_NOCLAIM)))
 430                 return false;
 431
 432         __raw_uncore_write32(uncore, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
 433
 434         return true;
 435 }
 436
 437 static bool
 438 vlv_check_for_unclaimed_mmio(struct intel_uncore *uncore)
 439 {
 440         u32 cer;
 441
 442         cer = __raw_uncore_read32(uncore, CLAIM_ER);
 443         if (likely(!(cer & (CLAIM_ER_OVERFLOW | CLAIM_ER_CTR_MASK))))
 444                 return false;
 445
 446         __raw_uncore_write32(uncore, CLAIM_ER, CLAIM_ER_CLR);
 447
 448         return true;
 449 }
 450
 451 static bool
 452 gen6_check_for_fifo_debug(struct intel_uncore *uncore)
 453 {
 454         u32 fifodbg;
 455
 456         fifodbg = __raw_uncore_read32(uncore, GTFIFODBG);
 457
 458         if (unlikely(fifodbg)) {
 459                 DRM_DEBUG_DRIVER("GTFIFODBG = 0x08%x\n", fifodbg);
 460                 __raw_uncore_write32(uncore, GTFIFODBG, fifodbg);
 461         }
 462
 463         return fifodbg;
 464 }
 465
 466 static bool
 467 check_for_unclaimed_mmio(struct intel_uncore *uncore)
 468 {
 469         bool ret = false;
 470
 471         if (intel_uncore_has_fpga_dbg_unclaimed(uncore))
 472                 ret |= fpga_check_for_unclaimed_mmio(uncore);
 473
 474         if (intel_uncore_has_dbg_unclaimed(uncore))
 475                 ret |= vlv_check_for_unclaimed_mmio(uncore);
 476
 477         if (intel_uncore_has_fifo(uncore))
 478                 ret |= gen6_check_for_fifo_debug(uncore);
 479
 480         return ret;
 481 }
 482
 483 static void __intel_uncore_early_sanitize(struct intel_uncore *uncore,
 484                                           unsigned int restore_forcewake)
 485 {
 486         /* clear out unclaimed reg detection bit */
 487         if (check_for_unclaimed_mmio(uncore))
 488                 DRM_DEBUG("unclaimed mmio detected on uncore init, clearing\n");
 489
 490         /* WaDisableShadowRegForCpd:chv */
 491         if (IS_CHERRYVIEW(uncore_to_i915(uncore))) {
 492                 __raw_uncore_write32(uncore, GTFIFOCTL,
 493                                      __raw_uncore_read32(uncore, GTFIFOCTL) |
 494                                      GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
 495                                      GT_FIFO_CTL_RC6_POLICY_STALL);
 496         }
 497
 498         iosf_mbi_punit_acquire();
 499         intel_uncore_forcewake_reset(uncore);
 500         if (restore_forcewake) {
 501                 spin_lock_irq(&uncore->lock);
 502                 uncore->funcs.force_wake_get(uncore, restore_forcewake);
 503
 504                 if (intel_uncore_has_fifo(uncore))
 505                         uncore->fifo_count = fifo_free_entries(uncore);
 506                 spin_unlock_irq(&uncore->lock);
 507         }
 508         iosf_mbi_punit_release();
 509 }
 510
 511 void intel_uncore_suspend(struct intel_uncore *uncore)
 512 {
 513         iosf_mbi_punit_acquire();
 514         iosf_mbi_unregister_pmic_bus_access_notifier_unlocked(
 515                 &uncore->pmic_bus_access_nb);
 516         uncore->fw_domains_saved = intel_uncore_forcewake_reset(uncore);
 517         iosf_mbi_punit_release();
 518 }
 519
 520 void intel_uncore_resume_early(struct intel_uncore *uncore)
 521 {
 522         unsigned int restore_forcewake;
 523
 524         restore_forcewake = fetch_and_zero(&uncore->fw_domains_saved);
 525         __intel_uncore_early_sanitize(uncore, restore_forcewake);
 526
 527         iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb);
 528 }
 529
 530 void intel_uncore_runtime_resume(struct intel_uncore *uncore)
 531 {
 532         iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb);
 533 }
 534
 535 void intel_uncore_sanitize(struct drm_i915_private *dev_priv)
 536 {
 537         /* BIOS often leaves RC6 enabled, but disable it for hw init */
 538         intel_sanitize_gt_powersave(dev_priv);
 539 }
 540
 541 static void __intel_uncore_forcewake_get(struct intel_uncore *uncore,
 542                                          enum forcewake_domains fw_domains)
 543 {
 544         struct intel_uncore_forcewake_domain *domain;
 545         unsigned int tmp;
 546
 547         fw_domains &= uncore->fw_domains;
 548
 549         for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) {
 550                 if (domain->wake_count++) {
 551                         fw_domains &= ~domain->mask;
 552                         domain->active = true;
 553                 }
 554         }
 555
 556         if (fw_domains)
 557                 uncore->funcs.force_wake_get(uncore, fw_domains);
 558 }
 559
 560 /**
 561  * intel_uncore_forcewake_get - grab forcewake domain references
 562  * @uncore: the intel_uncore structure
 563  * @fw_domains: forcewake domains to get reference on
 564  *
 565  * This function can be used get GT's forcewake domain references.
 566  * Normal register access will handle the forcewake domains automatically.
 567  * However if some sequence requires the GT to not power down a particular
 568  * forcewake domains this function should be called at the beginning of the
 569  * sequence. And subsequently the reference should be dropped by symmetric
 570  * call to intel_unforce_forcewake_put(). Usually caller wants all the domains
 571  * to be kept awake so the @fw_domains would be then FORCEWAKE_ALL.
 572  */
 573 void intel_uncore_forcewake_get(struct intel_uncore *uncore,
 574                                 enum forcewake_domains fw_domains)
 575 {
 576         unsigned long irqflags;
 577
 578         if (!uncore->funcs.force_wake_get)
 579                 return;
 580
 581         __assert_rpm_wakelock_held(uncore->rpm);
 582
 583         spin_lock_irqsave(&uncore->lock, irqflags);
 584         __intel_uncore_forcewake_get(uncore, fw_domains);
 585         spin_unlock_irqrestore(&uncore->lock, irqflags);
 586 }
 587
 588 /**
 589  * intel_uncore_forcewake_user_get - claim forcewake on behalf of userspace
 590  * @uncore: the intel_uncore structure
 591  *
 592  * This function is a wrapper around intel_uncore_forcewake_get() to acquire
 593  * the GT powerwell and in the process disable our debugging for the
 594  * duration of userspace's bypass.
 595  */
 596 void intel_uncore_forcewake_user_get(struct intel_uncore *uncore)
 597 {
 598         spin_lock_irq(&uncore->lock);
 599         if (!uncore->user_forcewake.count++) {
 600                 intel_uncore_forcewake_get__locked(uncore, FORCEWAKE_ALL);
 601
 602                 /* Save and disable mmio debugging for the user bypass */
 603                 uncore->user_forcewake.saved_mmio_check =
 604                         uncore->unclaimed_mmio_check;
 605                 uncore->user_forcewake.saved_mmio_debug =
 606                         i915_modparams.mmio_debug;
 607
 608                 uncore->unclaimed_mmio_check = 0;
 609                 i915_modparams.mmio_debug = 0;
 610         }
 611         spin_unlock_irq(&uncore->lock);
 612 }
 613
 614 /**
 615  * intel_uncore_forcewake_user_put - release forcewake on behalf of userspace
 616  * @uncore: the intel_uncore structure
 617  *
 618  * This function complements intel_uncore_forcewake_user_get() and releases
 619  * the GT powerwell taken on behalf of the userspace bypass.
 620  */
 621 void intel_uncore_forcewake_user_put(struct intel_uncore *uncore)
 622 {
 623         spin_lock_irq(&uncore->lock);
 624         if (!--uncore->user_forcewake.count) {
 625                 if (intel_uncore_unclaimed_mmio(uncore))
 626                         dev_info(uncore_to_i915(uncore)->drm.dev,
 627                                  "Invalid mmio detected during user access\n");
 628
 629                 uncore->unclaimed_mmio_check =
 630                         uncore->user_forcewake.saved_mmio_check;
 631                 i915_modparams.mmio_debug =
 632                         uncore->user_forcewake.saved_mmio_debug;
 633
 634                 intel_uncore_forcewake_put__locked(uncore, FORCEWAKE_ALL);
 635         }
 636         spin_unlock_irq(&uncore->lock);
 637 }
 638
 639 /**
 640  * intel_uncore_forcewake_get__locked - grab forcewake domain references
 641  * @uncore: the intel_uncore structure
 642  * @fw_domains: forcewake domains to get reference on
 643  *
 644  * See intel_uncore_forcewake_get(). This variant places the onus
 645  * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
 646  */
 647 void intel_uncore_forcewake_get__locked(struct intel_uncore *uncore,
 648                                         enum forcewake_domains fw_domains)
 649 {
 650         lockdep_assert_held(&uncore->lock);
 651
 652         if (!uncore->funcs.force_wake_get)
 653                 return;
 654
 655         __intel_uncore_forcewake_get(uncore, fw_domains);
 656 }
 657
 658 static void __intel_uncore_forcewake_put(struct intel_uncore *uncore,
 659                                          enum forcewake_domains fw_domains)
 660 {
 661         struct intel_uncore_forcewake_domain *domain;
 662         unsigned int tmp;
 663
 664         fw_domains &= uncore->fw_domains;
 665
 666         for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) {
 667                 if (WARN_ON(domain->wake_count == 0))
 668                         continue;
 669
 670                 if (--domain->wake_count) {
 671                         domain->active = true;
 672                         continue;
 673                 }
 674
 675                 fw_domain_arm_timer(domain);
 676         }
 677 }
 678
 679 /**
 680  * intel_uncore_forcewake_put - release a forcewake domain reference
 681  * @uncore: the intel_uncore structure
 682  * @fw_domains: forcewake domains to put references
 683  *
 684  * This function drops the device-level forcewakes for specified
 685  * domains obtained by intel_uncore_forcewake_get().
 686  */
 687 void intel_uncore_forcewake_put(struct intel_uncore *uncore,
 688                                 enum forcewake_domains fw_domains)
 689 {
 690         unsigned long irqflags;
 691
 692         if (!uncore->funcs.force_wake_put)
 693                 return;
 694
 695         spin_lock_irqsave(&uncore->lock, irqflags);
 696         __intel_uncore_forcewake_put(uncore, fw_domains);
 697         spin_unlock_irqrestore(&uncore->lock, irqflags);
 698 }
 699
 700 /**
 701  * intel_uncore_forcewake_put__locked - grab forcewake domain references
 702  * @uncore: the intel_uncore structure
 703  * @fw_domains: forcewake domains to get reference on
 704  *
 705  * See intel_uncore_forcewake_put(). This variant places the onus
 706  * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
 707  */
 708 void intel_uncore_forcewake_put__locked(struct intel_uncore *uncore,
 709                                         enum forcewake_domains fw_domains)
 710 {
 711         lockdep_assert_held(&uncore->lock);
 712
 713         if (!uncore->funcs.force_wake_put)
 714                 return;
 715
 716         __intel_uncore_forcewake_put(uncore, fw_domains);
 717 }
 718
 719 void assert_forcewakes_inactive(struct intel_uncore *uncore)
 720 {
 721         if (!uncore->funcs.force_wake_get)
 722                 return;
 723
 724         WARN(uncore->fw_domains_active,
 725              "Expected all fw_domains to be inactive, but %08x are still on\n",
 726              uncore->fw_domains_active);
 727 }
 728
 729 void assert_forcewakes_active(struct intel_uncore *uncore,
 730                               enum forcewake_domains fw_domains)
 731 {
 732         if (!uncore->funcs.force_wake_get)
 733                 return;
 734
 735         __assert_rpm_wakelock_held(uncore->rpm);
 736
 737         fw_domains &= uncore->fw_domains;
 738         WARN(fw_domains & ~uncore->fw_domains_active,
 739              "Expected %08x fw_domains to be active, but %08x are off\n",
 740              fw_domains, fw_domains & ~uncore->fw_domains_active);
 741 }
 742
 743 /* We give fast paths for the really cool registers */
 744 #define NEEDS_FORCE_WAKE(reg) ((reg) < 0x40000)
 745
 746 #define GEN11_NEEDS_FORCE_WAKE(reg) \
 747         ((reg) < 0x40000 || ((reg) >= 0x1c0000 && (reg) < 0x1dc000))
 748
 749 #define __gen6_reg_read_fw_domains(uncore, offset) \
 750 ({ \
 751         enum forcewake_domains __fwd; \
 752         if (NEEDS_FORCE_WAKE(offset)) \
 753                 __fwd = FORCEWAKE_RENDER; \
 754         else \
 755                 __fwd = 0; \
 756         __fwd; \
 757 })
 758
 759 static int fw_range_cmp(u32 offset, const struct intel_forcewake_range *entry)
 760 {
 761         if (offset < entry->start)
 762                 return -1;
 763         else if (offset > entry->end)
 764                 return 1;
 765         else
 766                 return 0;
 767 }
 768
 769 /* Copied and "macroized" from lib/bsearch.c */
 770 #define BSEARCH(key, base, num, cmp) ({                                 \
 771         unsigned int start__ = 0, end__ = (num);                        \
 772         typeof(base) result__ = NULL;                                   \
 773         while (start__ < end__) {                                       \
 774                 unsigned int mid__ = start__ + (end__ - start__) / 2;   \
 775                 int ret__ = (cmp)((key), (base) + mid__);               \
 776                 if (ret__ < 0) {                                        \
 777                         end__ = mid__;                                  \
 778                 } else if (ret__ > 0) {                                 \
 779                         start__ = mid__ + 1;                            \
 780                 } else {                                                \
 781                         result__ = (base) + mid__;                      \
 782                         break;                                          \
 783                 }                                                       \
 784         }                                                               \
 785         result__;                                                       \
 786 })
 787
 788 static enum forcewake_domains
 789 find_fw_domain(struct intel_uncore *uncore, u32 offset)
 790 {
 791         const struct intel_forcewake_range *entry;
 792
 793         entry = BSEARCH(offset,
 794                         uncore->fw_domains_table,
 795                         uncore->fw_domains_table_entries,
 796                         fw_range_cmp);
 797
 798         if (!entry)
 799                 return 0;
 800
 801         /*
 802          * The list of FW domains depends on the SKU in gen11+ so we
 803          * can't determine it statically. We use FORCEWAKE_ALL and
 804          * translate it here to the list of available domains.
 805          */
 806         if (entry->domains == FORCEWAKE_ALL)
 807                 return uncore->fw_domains;
 808
 809         WARN(entry->domains & ~uncore->fw_domains,
 810              "Uninitialized forcewake domain(s) 0x%x accessed at 0x%x\n",
 811              entry->domains & ~uncore->fw_domains, offset);
 812
 813         return entry->domains;
 814 }
 815
 816 #define GEN_FW_RANGE(s, e, d) \
 817         { .start = (s), .end = (e), .domains = (d) }
 818
 819 #define HAS_FWTABLE(dev_priv) \
 820         (INTEL_GEN(dev_priv) >= 9 || \
 821          IS_CHERRYVIEW(dev_priv) || \
 822          IS_VALLEYVIEW(dev_priv))
 823
 824 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
 825 static const struct intel_forcewake_range __vlv_fw_ranges[] = {
 826         GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER),
 827         GEN_FW_RANGE(0x5000, 0x7fff, FORCEWAKE_RENDER),
 828         GEN_FW_RANGE(0xb000, 0x11fff, FORCEWAKE_RENDER),
 829         GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
 830         GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_MEDIA),
 831         GEN_FW_RANGE(0x2e000, 0x2ffff, FORCEWAKE_RENDER),
 832         GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA),
 833 };
 834
 835 #define __fwtable_reg_read_fw_domains(uncore, offset) \
 836 ({ \
 837         enum forcewake_domains __fwd = 0; \
 838         if (NEEDS_FORCE_WAKE((offset))) \
 839                 __fwd = find_fw_domain(uncore, offset); \
 840         __fwd; \
 841 })
 842
 843 #define __gen11_fwtable_reg_read_fw_domains(uncore, offset) \
 844 ({ \
 845         enum forcewake_domains __fwd = 0; \
 846         if (GEN11_NEEDS_FORCE_WAKE((offset))) \
 847                 __fwd = find_fw_domain(uncore, offset); \
 848         __fwd; \
 849 })
 850
 851 /* *Must* be sorted by offset! See intel_shadow_table_check(). */
 852 static const i915_reg_t gen8_shadowed_regs[] = {
 853         RING_TAIL(RENDER_RING_BASE),    /* 0x2000 (base) */
 854         GEN6_RPNSWREQ,                  /* 0xA008 */
 855         GEN6_RC_VIDEO_FREQ,             /* 0xA00C */
 856         RING_TAIL(GEN6_BSD_RING_BASE),  /* 0x12000 (base) */
 857         RING_TAIL(VEBOX_RING_BASE),     /* 0x1a000 (base) */
 858         RING_TAIL(BLT_RING_BASE),       /* 0x22000 (base) */
 859         /* TODO: Other registers are not yet used */
 860 };
 861
 862 static const i915_reg_t gen11_shadowed_regs[] = {
 863         RING_TAIL(RENDER_RING_BASE),            /* 0x2000 (base) */
 864         GEN6_RPNSWREQ,                          /* 0xA008 */
 865         GEN6_RC_VIDEO_FREQ,                     /* 0xA00C */
 866         RING_TAIL(BLT_RING_BASE),               /* 0x22000 (base) */
 867         RING_TAIL(GEN11_BSD_RING_BASE),         /* 0x1C0000 (base) */
 868         RING_TAIL(GEN11_BSD2_RING_BASE),        /* 0x1C4000 (base) */
 869         RING_TAIL(GEN11_VEBOX_RING_BASE),       /* 0x1C8000 (base) */
 870         RING_TAIL(GEN11_BSD3_RING_BASE),        /* 0x1D0000 (base) */
 871         RING_TAIL(GEN11_BSD4_RING_BASE),        /* 0x1D4000 (base) */
 872         RING_TAIL(GEN11_VEBOX2_RING_BASE),      /* 0x1D8000 (base) */
 873         /* TODO: Other registers are not yet used */
 874 };
 875
 876 static int mmio_reg_cmp(u32 key, const i915_reg_t *reg)
 877 {
 878         u32 offset = i915_mmio_reg_offset(*reg);
 879
 880         if (key < offset)
 881                 return -1;
 882         else if (key > offset)
 883                 return 1;
 884         else
 885                 return 0;
 886 }
 887
 888 #define __is_genX_shadowed(x) \
 889 static bool is_gen##x##_shadowed(u32 offset) \
 890 { \
 891         const i915_reg_t *regs = gen##x##_shadowed_regs; \
 892         return BSEARCH(offset, regs, ARRAY_SIZE(gen##x##_shadowed_regs), \
 893                        mmio_reg_cmp); \
 894 }
 895
 896 __is_genX_shadowed(8)
 897 __is_genX_shadowed(11)
 898
 899 #define __gen8_reg_write_fw_domains(uncore, offset) \
 900 ({ \
 901         enum forcewake_domains __fwd; \
 902         if (NEEDS_FORCE_WAKE(offset) && !is_gen8_shadowed(offset)) \
 903                 __fwd = FORCEWAKE_RENDER; \
 904         else \
 905                 __fwd = 0; \
 906         __fwd; \
 907 })
 908
 909 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
 910 static const struct intel_forcewake_range __chv_fw_ranges[] = {
 911         GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER),
 912         GEN_FW_RANGE(0x4000, 0x4fff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
 913         GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
 914         GEN_FW_RANGE(0x8000, 0x82ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
 915         GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
 916         GEN_FW_RANGE(0x8500, 0x85ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
 917         GEN_FW_RANGE(0x8800, 0x88ff, FORCEWAKE_MEDIA),
 918         GEN_FW_RANGE(0x9000, 0xafff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
 919         GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
 920         GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA),
 921         GEN_FW_RANGE(0xe000, 0xe7ff, FORCEWAKE_RENDER),
 922         GEN_FW_RANGE(0xf000, 0xffff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
 923         GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
 924         GEN_FW_RANGE(0x1a000, 0x1bfff, FORCEWAKE_MEDIA),
 925         GEN_FW_RANGE(0x1e800, 0x1e9ff, FORCEWAKE_MEDIA),
 926         GEN_FW_RANGE(0x30000, 0x37fff, FORCEWAKE_MEDIA),
 927 };
 928
 929 #define __fwtable_reg_write_fw_domains(uncore, offset) \
 930 ({ \
 931         enum forcewake_domains __fwd = 0; \
 932         if (NEEDS_FORCE_WAKE((offset)) && !is_gen8_shadowed(offset)) \
 933                 __fwd = find_fw_domain(uncore, offset); \
 934         __fwd; \
 935 })
 936
 937 #define __gen11_fwtable_reg_write_fw_domains(uncore, offset) \
 938 ({ \
 939         enum forcewake_domains __fwd = 0; \
 940         if (GEN11_NEEDS_FORCE_WAKE((offset)) && !is_gen11_shadowed(offset)) \
 941                 __fwd = find_fw_domain(uncore, offset); \
 942         __fwd; \
 943 })
 944
 945 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
 946 static const struct intel_forcewake_range __gen9_fw_ranges[] = {
 947         GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER),
 948         GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */
 949         GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
 950         GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER),
 951         GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
 952         GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_BLITTER),
 953         GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
 954         GEN_FW_RANGE(0x8000, 0x812f, FORCEWAKE_BLITTER),
 955         GEN_FW_RANGE(0x8130, 0x813f, FORCEWAKE_MEDIA),
 956         GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
 957         GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER),
 958         GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
 959         GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_BLITTER),
 960         GEN_FW_RANGE(0x8800, 0x89ff, FORCEWAKE_MEDIA),
 961         GEN_FW_RANGE(0x8a00, 0x8bff, FORCEWAKE_BLITTER),
 962         GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER),
 963         GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_BLITTER),
 964         GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
 965         GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_BLITTER),
 966         GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
 967         GEN_FW_RANGE(0xb480, 0xcfff, FORCEWAKE_BLITTER),
 968         GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA),
 969         GEN_FW_RANGE(0xd800, 0xdfff, FORCEWAKE_BLITTER),
 970         GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER),
 971         GEN_FW_RANGE(0xe900, 0x11fff, FORCEWAKE_BLITTER),
 972         GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
 973         GEN_FW_RANGE(0x14000, 0x19fff, FORCEWAKE_BLITTER),
 974         GEN_FW_RANGE(0x1a000, 0x1e9ff, FORCEWAKE_MEDIA),
 975         GEN_FW_RANGE(0x1ea00, 0x243ff, FORCEWAKE_BLITTER),
 976         GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER),
 977         GEN_FW_RANGE(0x24800, 0x2ffff, FORCEWAKE_BLITTER),
 978         GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA),
 979 };
 980
 981 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
 982 static const struct intel_forcewake_range __gen11_fw_ranges[] = {
 983         GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER),
 984         GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */
 985         GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
 986         GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER),
 987         GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
 988         GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_BLITTER),
 989         GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
 990         GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_BLITTER),
 991         GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
 992         GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER),
 993         GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
 994         GEN_FW_RANGE(0x8500, 0x8bff, FORCEWAKE_BLITTER),
 995         GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER),
 996         GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_BLITTER),
 997         GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_ALL),
 998         GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_BLITTER),
 999         GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
1000         GEN_FW_RANGE(0xb480, 0xdfff, FORCEWAKE_BLITTER),
1001         GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER),
1002         GEN_FW_RANGE(0xe900, 0x243ff, FORCEWAKE_BLITTER),
1003         GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER),
1004         GEN_FW_RANGE(0x24800, 0x3ffff, FORCEWAKE_BLITTER),
1005         GEN_FW_RANGE(0x40000, 0x1bffff, 0),
1006         GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0),
1007         GEN_FW_RANGE(0x1c4000, 0x1c7fff, FORCEWAKE_MEDIA_VDBOX1),
1008         GEN_FW_RANGE(0x1c8000, 0x1cbfff, FORCEWAKE_MEDIA_VEBOX0),
1009         GEN_FW_RANGE(0x1cc000, 0x1cffff, FORCEWAKE_BLITTER),
1010         GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2),
1011         GEN_FW_RANGE(0x1d4000, 0x1d7fff, FORCEWAKE_MEDIA_VDBOX3),
1012         GEN_FW_RANGE(0x1d8000, 0x1dbfff, FORCEWAKE_MEDIA_VEBOX1)
1013 };
1014
1015 static void
1016 ilk_dummy_write(struct intel_uncore *uncore)
1017 {
1018         /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
1019          * the chip from rc6 before touching it for real. MI_MODE is masked,
1020          * hence harmless to write 0 into. */
1021         __raw_uncore_write32(uncore, MI_MODE, 0);
1022 }
1023
1024 static void
1025 __unclaimed_reg_debug(struct intel_uncore *uncore,
1026                       const i915_reg_t reg,
1027                       const bool read,
1028                       const bool before)
1029 {
1030         if (WARN(check_for_unclaimed_mmio(uncore) && !before,
1031                  "Unclaimed %s register 0x%x\n",
1032                  read ? "read from" : "write to",
1033                  i915_mmio_reg_offset(reg)))
1034                 /* Only report the first N failures */
1035                 i915_modparams.mmio_debug--;
1036 }
1037
1038 static inline void
1039 unclaimed_reg_debug(struct intel_uncore *uncore,
1040                     const i915_reg_t reg,
1041                     const bool read,
1042                     const bool before)
1043 {
1044         if (likely(!i915_modparams.mmio_debug))
1045                 return;
1046
1047         __unclaimed_reg_debug(uncore, reg, read, before);
1048 }
1049
1050 #define GEN2_READ_HEADER(x) \
1051         u##x val = 0; \
1052         __assert_rpm_wakelock_held(uncore->rpm);
1053
1054 #define GEN2_READ_FOOTER \
1055         trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
1056         return val
1057
1058 #define __gen2_read(x) \
1059 static u##x \
1060 gen2_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
1061         GEN2_READ_HEADER(x); \
1062         val = __raw_uncore_read##x(uncore, reg); \
1063         GEN2_READ_FOOTER; \
1064 }
1065
1066 #define __gen5_read(x) \
1067 static u##x \
1068 gen5_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
1069         GEN2_READ_HEADER(x); \
1070         ilk_dummy_write(uncore); \
1071         val = __raw_uncore_read##x(uncore, reg); \
1072         GEN2_READ_FOOTER; \
1073 }
1074
1075 __gen5_read(8)
1076 __gen5_read(16)
1077 __gen5_read(32)
1078 __gen5_read(64)
1079 __gen2_read(8)
1080 __gen2_read(16)
1081 __gen2_read(32)
1082 __gen2_read(64)
1083
1084 #undef __gen5_read
1085 #undef __gen2_read
1086
1087 #undef GEN2_READ_FOOTER
1088 #undef GEN2_READ_HEADER
1089
1090 #define GEN6_READ_HEADER(x) \
1091         u32 offset = i915_mmio_reg_offset(reg); \
1092         unsigned long irqflags; \
1093         u##x val = 0; \
1094         __assert_rpm_wakelock_held(uncore->rpm); \
1095         spin_lock_irqsave(&uncore->lock, irqflags); \
1096         unclaimed_reg_debug(uncore, reg, true, true)
1097
1098 #define GEN6_READ_FOOTER \
1099         unclaimed_reg_debug(uncore, reg, true, false); \
1100         spin_unlock_irqrestore(&uncore->lock, irqflags); \
1101         trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
1102         return val
1103
1104 static noinline void ___force_wake_auto(struct intel_uncore *uncore,
1105                                         enum forcewake_domains fw_domains)
1106 {
1107         struct intel_uncore_forcewake_domain *domain;
1108         unsigned int tmp;
1109
1110         GEM_BUG_ON(fw_domains & ~uncore->fw_domains);
1111
1112         for_each_fw_domain_masked(domain, fw_domains, uncore, tmp)
1113                 fw_domain_arm_timer(domain);
1114
1115         uncore->funcs.force_wake_get(uncore, fw_domains);
1116 }
1117
1118 static inline void __force_wake_auto(struct intel_uncore *uncore,
1119                                      enum forcewake_domains fw_domains)
1120 {
1121         if (WARN_ON(!fw_domains))
1122                 return;
1123
1124         /* Turn on all requested but inactive supported forcewake domains. */
1125         fw_domains &= uncore->fw_domains;
1126         fw_domains &= ~uncore->fw_domains_active;
1127
1128         if (fw_domains)
1129                 ___force_wake_auto(uncore, fw_domains);
1130 }
1131
1132 #define __gen_read(func, x) \
1133 static u##x \
1134 func##_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
1135         enum forcewake_domains fw_engine; \
1136         GEN6_READ_HEADER(x); \
1137         fw_engine = __##func##_reg_read_fw_domains(uncore, offset); \
1138         if (fw_engine) \
1139                 __force_wake_auto(uncore, fw_engine); \
1140         val = __raw_uncore_read##x(uncore, reg); \
1141         GEN6_READ_FOOTER; \
1142 }
1143 #define __gen6_read(x) __gen_read(gen6, x)
1144 #define __fwtable_read(x) __gen_read(fwtable, x)
1145 #define __gen11_fwtable_read(x) __gen_read(gen11_fwtable, x)
1146
1147 __gen11_fwtable_read(8)
1148 __gen11_fwtable_read(16)
1149 __gen11_fwtable_read(32)
1150 __gen11_fwtable_read(64)
1151 __fwtable_read(8)
1152 __fwtable_read(16)
1153 __fwtable_read(32)
1154 __fwtable_read(64)
1155 __gen6_read(8)
1156 __gen6_read(16)
1157 __gen6_read(32)
1158 __gen6_read(64)
1159
1160 #undef __gen11_fwtable_read
1161 #undef __fwtable_read
1162 #undef __gen6_read
1163 #undef GEN6_READ_FOOTER
1164 #undef GEN6_READ_HEADER
1165
1166 #define GEN2_WRITE_HEADER \
1167         trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
1168         __assert_rpm_wakelock_held(uncore->rpm); \
1169
1170 #define GEN2_WRITE_FOOTER
1171
1172 #define __gen2_write(x) \
1173 static void \
1174 gen2_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
1175         GEN2_WRITE_HEADER; \
1176         __raw_uncore_write##x(uncore, reg, val); \
1177         GEN2_WRITE_FOOTER; \
1178 }
1179
1180 #define __gen5_write(x) \
1181 static void \
1182 gen5_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
1183         GEN2_WRITE_HEADER; \
1184         ilk_dummy_write(uncore); \
1185         __raw_uncore_write##x(uncore, reg, val); \
1186         GEN2_WRITE_FOOTER; \
1187 }
1188
1189 __gen5_write(8)
1190 __gen5_write(16)
1191 __gen5_write(32)
1192 __gen2_write(8)
1193 __gen2_write(16)
1194 __gen2_write(32)
1195
1196 #undef __gen5_write
1197 #undef __gen2_write
1198
1199 #undef GEN2_WRITE_FOOTER
1200 #undef GEN2_WRITE_HEADER
1201
1202 #define GEN6_WRITE_HEADER \
1203         u32 offset = i915_mmio_reg_offset(reg); \
1204         unsigned long irqflags; \
1205         trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
1206         __assert_rpm_wakelock_held(uncore->rpm); \
1207         spin_lock_irqsave(&uncore->lock, irqflags); \
1208         unclaimed_reg_debug(uncore, reg, false, true)
1209
1210 #define GEN6_WRITE_FOOTER \
1211         unclaimed_reg_debug(uncore, reg, false, false); \
1212         spin_unlock_irqrestore(&uncore->lock, irqflags)
1213
1214 #define __gen6_write(x) \
1215 static void \
1216 gen6_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
1217         GEN6_WRITE_HEADER; \
1218         if (NEEDS_FORCE_WAKE(offset)) \
1219                 __gen6_gt_wait_for_fifo(uncore); \
1220         __raw_uncore_write##x(uncore, reg, val); \
1221         GEN6_WRITE_FOOTER; \
1222 }
1223
1224 #define __gen_write(func, x) \
1225 static void \
1226 func##_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
1227         enum forcewake_domains fw_engine; \
1228         GEN6_WRITE_HEADER; \
1229         fw_engine = __##func##_reg_write_fw_domains(uncore, offset); \
1230         if (fw_engine) \
1231                 __force_wake_auto(uncore, fw_engine); \
1232         __raw_uncore_write##x(uncore, reg, val); \
1233         GEN6_WRITE_FOOTER; \
1234 }
1235 #define __gen8_write(x) __gen_write(gen8, x)
1236 #define __fwtable_write(x) __gen_write(fwtable, x)
1237 #define __gen11_fwtable_write(x) __gen_write(gen11_fwtable, x)
1238
1239 __gen11_fwtable_write(8)
1240 __gen11_fwtable_write(16)
1241 __gen11_fwtable_write(32)
1242 __fwtable_write(8)
1243 __fwtable_write(16)
1244 __fwtable_write(32)
1245 __gen8_write(8)
1246 __gen8_write(16)
1247 __gen8_write(32)
1248 __gen6_write(8)
1249 __gen6_write(16)
1250 __gen6_write(32)
1251
1252 #undef __gen11_fwtable_write
1253 #undef __fwtable_write
1254 #undef __gen8_write
1255 #undef __gen6_write
1256 #undef GEN6_WRITE_FOOTER
1257 #undef GEN6_WRITE_HEADER
1258
1259 #define ASSIGN_WRITE_MMIO_VFUNCS(uncore, x) \
1260 do { \
1261         (uncore)->funcs.mmio_writeb = x##_write8; \
1262         (uncore)->funcs.mmio_writew = x##_write16; \
1263         (uncore)->funcs.mmio_writel = x##_write32; \
1264 } while (0)
1265
1266 #define ASSIGN_READ_MMIO_VFUNCS(uncore, x) \
1267 do { \
1268         (uncore)->funcs.mmio_readb = x##_read8; \
1269         (uncore)->funcs.mmio_readw = x##_read16; \
1270         (uncore)->funcs.mmio_readl = x##_read32; \
1271         (uncore)->funcs.mmio_readq = x##_read64; \
1272 } while (0)
1273
1274
1275 static void fw_domain_init(struct intel_uncore *uncore,
1276                            enum forcewake_domain_id domain_id,
1277                            i915_reg_t reg_set,
1278                            i915_reg_t reg_ack)
1279 {
1280         struct intel_uncore_forcewake_domain *d;
1281
1282         if (WARN_ON(domain_id >= FW_DOMAIN_ID_COUNT))
1283                 return;
1284
1285         d = &uncore->fw_domain[domain_id];
1286
1287         WARN_ON(d->wake_count);
1288
1289         WARN_ON(!i915_mmio_reg_valid(reg_set));
1290         WARN_ON(!i915_mmio_reg_valid(reg_ack));
1291
1292         d->wake_count = 0;
1293         d->reg_set = uncore->regs + i915_mmio_reg_offset(reg_set);
1294         d->reg_ack = uncore->regs + i915_mmio_reg_offset(reg_ack);
1295
1296         d->id = domain_id;
1297
1298         BUILD_BUG_ON(FORCEWAKE_RENDER != (1 << FW_DOMAIN_ID_RENDER));
1299         BUILD_BUG_ON(FORCEWAKE_BLITTER != (1 << FW_DOMAIN_ID_BLITTER));
1300         BUILD_BUG_ON(FORCEWAKE_MEDIA != (1 << FW_DOMAIN_ID_MEDIA));
1301         BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX0 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX0));
1302         BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX1 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX1));
1303         BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX2 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX2));
1304         BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX3 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX3));
1305         BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX0 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX0));
1306         BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX1 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX1));
1307
1308
1309         d->mask = BIT(domain_id);
1310
1311         hrtimer_init(&d->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1312         d->timer.function = intel_uncore_fw_release_timer;
1313
1314         uncore->fw_domains |= BIT(domain_id);
1315
1316         fw_domain_reset(d);
1317 }
1318
1319 static void fw_domain_fini(struct intel_uncore *uncore,
1320                            enum forcewake_domain_id domain_id)
1321 {
1322         struct intel_uncore_forcewake_domain *d;
1323
1324         if (WARN_ON(domain_id >= FW_DOMAIN_ID_COUNT))
1325                 return;
1326
1327         d = &uncore->fw_domain[domain_id];
1328
1329         WARN_ON(d->wake_count);
1330         WARN_ON(hrtimer_cancel(&d->timer));
1331         memset(d, 0, sizeof(*d));
1332
1333         uncore->fw_domains &= ~BIT(domain_id);
1334 }
1335
1336 static void intel_uncore_fw_domains_init(struct intel_uncore *uncore)
1337 {
1338         struct drm_i915_private *i915 = uncore_to_i915(uncore);
1339
1340         if (!intel_uncore_has_forcewake(uncore))
1341                 return;
1342
1343         if (INTEL_GEN(i915) >= 11) {
1344                 int i;
1345
1346                 uncore->funcs.force_wake_get =
1347                         fw_domains_get_with_fallback;
1348                 uncore->funcs.force_wake_put = fw_domains_put;
1349                 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
1350                                FORCEWAKE_RENDER_GEN9,
1351                                FORCEWAKE_ACK_RENDER_GEN9);
1352                 fw_domain_init(uncore, FW_DOMAIN_ID_BLITTER,
1353                                FORCEWAKE_BLITTER_GEN9,
1354                                FORCEWAKE_ACK_BLITTER_GEN9);
1355                 for (i = 0; i < I915_MAX_VCS; i++) {
1356                         if (!HAS_ENGINE(i915, _VCS(i)))
1357                                 continue;
1358
1359                         fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA_VDBOX0 + i,
1360                                        FORCEWAKE_MEDIA_VDBOX_GEN11(i),
1361                                        FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(i));
1362                 }
1363                 for (i = 0; i < I915_MAX_VECS; i++) {
1364                         if (!HAS_ENGINE(i915, _VECS(i)))
1365                                 continue;
1366
1367                         fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA_VEBOX0 + i,
1368                                        FORCEWAKE_MEDIA_VEBOX_GEN11(i),
1369                                        FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(i));
1370                 }
1371         } else if (IS_GEN_RANGE(i915, 9, 10)) {
1372                 uncore->funcs.force_wake_get =
1373                         fw_domains_get_with_fallback;
1374                 uncore->funcs.force_wake_put = fw_domains_put;
1375                 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
1376                                FORCEWAKE_RENDER_GEN9,
1377                                FORCEWAKE_ACK_RENDER_GEN9);
1378                 fw_domain_init(uncore, FW_DOMAIN_ID_BLITTER,
1379                                FORCEWAKE_BLITTER_GEN9,
1380                                FORCEWAKE_ACK_BLITTER_GEN9);
1381                 fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA,
1382                                FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9);
1383         } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
1384                 uncore->funcs.force_wake_get = fw_domains_get;
1385                 uncore->funcs.force_wake_put = fw_domains_put;
1386                 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
1387                                FORCEWAKE_VLV, FORCEWAKE_ACK_VLV);
1388                 fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA,
1389                                FORCEWAKE_MEDIA_VLV, FORCEWAKE_ACK_MEDIA_VLV);
1390         } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
1391                 uncore->funcs.force_wake_get =
1392                         fw_domains_get_with_thread_status;
1393                 uncore->funcs.force_wake_put = fw_domains_put;
1394                 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
1395                                FORCEWAKE_MT, FORCEWAKE_ACK_HSW);
1396         } else if (IS_IVYBRIDGE(i915)) {
1397                 u32 ecobus;
1398
1399                 /* IVB configs may use multi-threaded forcewake */
1400
1401                 /* A small trick here - if the bios hasn't configured
1402                  * MT forcewake, and if the device is in RC6, then
1403                  * force_wake_mt_get will not wake the device and the
1404                  * ECOBUS read will return zero. Which will be
1405                  * (correctly) interpreted by the test below as MT
1406                  * forcewake being disabled.
1407                  */
1408                 uncore->funcs.force_wake_get =
1409                         fw_domains_get_with_thread_status;
1410                 uncore->funcs.force_wake_put = fw_domains_put;
1411
1412                 /* We need to init first for ECOBUS access and then
1413                  * determine later if we want to reinit, in case of MT access is
1414                  * not working. In this stage we don't know which flavour this
1415                  * ivb is, so it is better to reset also the gen6 fw registers
1416                  * before the ecobus check.
1417                  */
1418
1419                 __raw_uncore_write32(uncore, FORCEWAKE, 0);
1420                 __raw_posting_read(uncore, ECOBUS);
1421
1422                 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
1423                                FORCEWAKE_MT, FORCEWAKE_MT_ACK);
1424
1425                 spin_lock_irq(&uncore->lock);
1426                 fw_domains_get_with_thread_status(uncore, FORCEWAKE_RENDER);
1427                 ecobus = __raw_uncore_read32(uncore, ECOBUS);
1428                 fw_domains_put(uncore, FORCEWAKE_RENDER);
1429                 spin_unlock_irq(&uncore->lock);
1430
1431                 if (!(ecobus & FORCEWAKE_MT_ENABLE)) {
1432                         DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n");
1433                         DRM_INFO("when using vblank-synced partial screen updates.\n");
1434                         fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
1435                                        FORCEWAKE, FORCEWAKE_ACK);
1436                 }
1437         } else if (IS_GEN(i915, 6)) {
1438                 uncore->funcs.force_wake_get =
1439                         fw_domains_get_with_thread_status;
1440                 uncore->funcs.force_wake_put = fw_domains_put;
1441                 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
1442                                FORCEWAKE, FORCEWAKE_ACK);
1443         }
1444
1445         /* All future platforms are expected to require complex power gating */
1446         WARN_ON(uncore->fw_domains == 0);
1447 }
1448
1449 #define ASSIGN_FW_DOMAINS_TABLE(uncore, d) \
1450 { \
1451         (uncore)->fw_domains_table = \
1452                         (struct intel_forcewake_range *)(d); \
1453         (uncore)->fw_domains_table_entries = ARRAY_SIZE((d)); \
1454 }
1455
1456 static int i915_pmic_bus_access_notifier(struct notifier_block *nb,
1457                                          unsigned long action, void *data)
1458 {
1459         struct drm_i915_private *dev_priv = container_of(nb,
1460                         struct drm_i915_private, uncore.pmic_bus_access_nb);
1461
1462         switch (action) {
1463         case MBI_PMIC_BUS_ACCESS_BEGIN:
1464                 /*
1465                  * forcewake all now to make sure that we don't need to do a
1466                  * forcewake later which on systems where this notifier gets
1467                  * called requires the punit to access to the shared pmic i2c
1468                  * bus, which will be busy after this notification, leading to:
1469                  * "render: timed out waiting for forcewake ack request."
1470                  * errors.
1471                  *
1472                  * The notifier is unregistered during intel_runtime_suspend(),
1473                  * so it's ok to access the HW here without holding a RPM
1474                  * wake reference -> disable wakeref asserts for the time of
1475                  * the access.
1476                  */
1477                 disable_rpm_wakeref_asserts(dev_priv);
1478                 intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
1479                 enable_rpm_wakeref_asserts(dev_priv);
1480                 break;
1481         case MBI_PMIC_BUS_ACCESS_END:
1482                 intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
1483                 break;
1484         }
1485
1486         return NOTIFY_OK;
1487 }
1488
1489 static int uncore_mmio_setup(struct intel_uncore *uncore)
1490 {
1491         struct drm_i915_private *i915 = uncore_to_i915(uncore);
1492         struct pci_dev *pdev = i915->drm.pdev;
1493         int mmio_bar;
1494         int mmio_size;
1495
1496         mmio_bar = IS_GEN(i915, 2) ? 1 : 0;
1497         /*
1498          * Before gen4, the registers and the GTT are behind different BARs.
1499          * However, from gen4 onwards, the registers and the GTT are shared
1500          * in the same BAR, so we want to restrict this ioremap from
1501          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
1502          * the register BAR remains the same size for all the earlier
1503          * generations up to Ironlake.
1504          */
1505         if (INTEL_GEN(i915) < 5)
1506                 mmio_size = 512 * 1024;
1507         else
1508                 mmio_size = 2 * 1024 * 1024;
1509         uncore->regs = pci_iomap(pdev, mmio_bar, mmio_size);
1510         if (uncore->regs == NULL) {
1511                 DRM_ERROR("failed to map registers\n");
1512
1513                 return -EIO;
1514         }
1515
1516         return 0;
1517 }
1518
1519 static void uncore_mmio_cleanup(struct intel_uncore *uncore)
1520 {
1521         struct drm_i915_private *i915 = uncore_to_i915(uncore);
1522         struct pci_dev *pdev = i915->drm.pdev;
1523
1524         pci_iounmap(pdev, uncore->regs);
1525 }
1526
1527 void intel_uncore_init_early(struct intel_uncore *uncore)
1528 {
1529         spin_lock_init(&uncore->lock);
1530 }
1531
1532 int intel_uncore_init_mmio(struct intel_uncore *uncore)
1533 {
1534         struct drm_i915_private *i915 = uncore_to_i915(uncore);
1535         int ret;
1536
1537         ret = uncore_mmio_setup(uncore);
1538         if (ret)
1539                 return ret;
1540
1541         i915_check_vgpu(i915);
1542
1543         if (INTEL_GEN(i915) > 5 && !intel_vgpu_active(i915))
1544                 uncore->flags |= UNCORE_HAS_FORCEWAKE;
1545
1546         intel_uncore_fw_domains_init(uncore);
1547         __intel_uncore_early_sanitize(uncore, 0);
1548
1549         uncore->unclaimed_mmio_check = 1;
1550         uncore->pmic_bus_access_nb.notifier_call =
1551                 i915_pmic_bus_access_notifier;
1552
1553         uncore->rpm = &i915->runtime_pm;
1554
1555         if (!intel_uncore_has_forcewake(uncore)) {
1556                 if (IS_GEN(i915, 5)) {
1557                         ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen5);
1558                         ASSIGN_READ_MMIO_VFUNCS(uncore, gen5);
1559                 } else {
1560                         ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen2);
1561                         ASSIGN_READ_MMIO_VFUNCS(uncore, gen2);
1562                 }
1563         } else if (IS_GEN_RANGE(i915, 6, 7)) {
1564                 ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen6);
1565
1566                 if (IS_VALLEYVIEW(i915)) {
1567                         ASSIGN_FW_DOMAINS_TABLE(uncore, __vlv_fw_ranges);
1568                         ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
1569                 } else {
1570                         ASSIGN_READ_MMIO_VFUNCS(uncore, gen6);
1571                 }
1572         } else if (IS_GEN(i915, 8)) {
1573                 if (IS_CHERRYVIEW(i915)) {
1574                         ASSIGN_FW_DOMAINS_TABLE(uncore, __chv_fw_ranges);
1575                         ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
1576                         ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
1577
1578                 } else {
1579                         ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen8);
1580                         ASSIGN_READ_MMIO_VFUNCS(uncore, gen6);
1581                 }
1582         } else if (IS_GEN_RANGE(i915, 9, 10)) {
1583                 ASSIGN_FW_DOMAINS_TABLE(uncore, __gen9_fw_ranges);
1584                 ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
1585                 ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
1586         } else {
1587                 ASSIGN_FW_DOMAINS_TABLE(uncore, __gen11_fw_ranges);
1588                 ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen11_fwtable);
1589                 ASSIGN_READ_MMIO_VFUNCS(uncore, gen11_fwtable);
1590         }
1591
1592         if (HAS_FPGA_DBG_UNCLAIMED(i915))
1593                 uncore->flags |= UNCORE_HAS_FPGA_DBG_UNCLAIMED;
1594
1595         if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
1596                 uncore->flags |= UNCORE_HAS_DBG_UNCLAIMED;
1597
1598         if (IS_GEN_RANGE(i915, 6, 7))
1599                 uncore->flags |= UNCORE_HAS_FIFO;
1600
1601         iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb);
1602
1603         return 0;
1604 }
1605
1606 /*
1607  * We might have detected that some engines are fused off after we initialized
1608  * the forcewake domains. Prune them, to make sure they only reference existing
1609  * engines.
1610  */
1611 void intel_uncore_prune_mmio_domains(struct intel_uncore *uncore)
1612 {
1613         struct drm_i915_private *i915 = uncore_to_i915(uncore);
1614
1615         if (INTEL_GEN(i915) >= 11) {
1616                 enum forcewake_domains fw_domains = uncore->fw_domains;
1617                 enum forcewake_domain_id domain_id;
1618                 int i;
1619
1620                 for (i = 0; i < I915_MAX_VCS; i++) {
1621                         domain_id = FW_DOMAIN_ID_MEDIA_VDBOX0 + i;
1622
1623                         if (HAS_ENGINE(i915, _VCS(i)))
1624                                 continue;
1625
1626                         if (fw_domains & BIT(domain_id))
1627                                 fw_domain_fini(uncore, domain_id);
1628                 }
1629
1630                 for (i = 0; i < I915_MAX_VECS; i++) {
1631                         domain_id = FW_DOMAIN_ID_MEDIA_VEBOX0 + i;
1632
1633                         if (HAS_ENGINE(i915, _VECS(i)))
1634                                 continue;
1635
1636                         if (fw_domains & BIT(domain_id))
1637                                 fw_domain_fini(uncore, domain_id);
1638                 }
1639         }
1640 }
1641
1642 void intel_uncore_fini_mmio(struct intel_uncore *uncore)
1643 {
1644         /* Paranoia: make sure we have disabled everything before we exit. */
1645         intel_uncore_sanitize(uncore_to_i915(uncore));
1646
1647         iosf_mbi_punit_acquire();
1648         iosf_mbi_unregister_pmic_bus_access_notifier_unlocked(
1649                 &uncore->pmic_bus_access_nb);
1650         intel_uncore_forcewake_reset(uncore);
1651         iosf_mbi_punit_release();
1652         uncore_mmio_cleanup(uncore);
1653 }
1654
1655 static const struct reg_whitelist {
1656         i915_reg_t offset_ldw;
1657         i915_reg_t offset_udw;
1658         u16 gen_mask;
1659         u8 size;
1660 } reg_read_whitelist[] = { {
1661         .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
1662         .offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
1663         .gen_mask = INTEL_GEN_MASK(4, 11),
1664         .size = 8
1665 } };
1666
1667 int i915_reg_read_ioctl(struct drm_device *dev,
1668                         void *data, struct drm_file *file)
1669 {
1670         struct drm_i915_private *dev_priv = to_i915(dev);
1671         struct drm_i915_reg_read *reg = data;
1672         struct reg_whitelist const *entry;
1673         intel_wakeref_t wakeref;
1674         unsigned int flags;
1675         int remain;
1676         int ret = 0;
1677
1678         entry = reg_read_whitelist;
1679         remain = ARRAY_SIZE(reg_read_whitelist);
1680         while (remain) {
1681                 u32 entry_offset = i915_mmio_reg_offset(entry->offset_ldw);
1682
1683                 GEM_BUG_ON(!is_power_of_2(entry->size));
1684                 GEM_BUG_ON(entry->size > 8);
1685                 GEM_BUG_ON(entry_offset & (entry->size - 1));
1686
1687                 if (INTEL_INFO(dev_priv)->gen_mask & entry->gen_mask &&
1688                     entry_offset == (reg->offset & -entry->size))
1689                         break;
1690                 entry++;
1691                 remain--;
1692         }
1693
1694         if (!remain)
1695                 return -EINVAL;
1696
1697         flags = reg->offset & (entry->size - 1);
1698
1699         with_intel_runtime_pm(dev_priv, wakeref) {
1700                 if (entry->size == 8 && flags == I915_REG_READ_8B_WA)
1701                         reg->val = I915_READ64_2x32(entry->offset_ldw,
1702                                                     entry->offset_udw);
1703                 else if (entry->size == 8 && flags == 0)
1704                         reg->val = I915_READ64(entry->offset_ldw);
1705                 else if (entry->size == 4 && flags == 0)
1706                         reg->val = I915_READ(entry->offset_ldw);
1707                 else if (entry->size == 2 && flags == 0)
1708                         reg->val = I915_READ16(entry->offset_ldw);
1709                 else if (entry->size == 1 && flags == 0)
1710                         reg->val = I915_READ8(entry->offset_ldw);
1711                 else
1712                         ret = -EINVAL;
1713         }
1714
1715         return ret;
1716 }
1717
1718 /**
1719  * __intel_wait_for_register_fw - wait until register matches expected state
1720  * @uncore: the struct intel_uncore
1721  * @reg: the register to read
1722  * @mask: mask to apply to register value
1723  * @value: expected value
1724  * @fast_timeout_us: fast timeout in microsecond for atomic/tight wait
1725  * @slow_timeout_ms: slow timeout in millisecond
1726  * @out_value: optional placeholder to hold registry value
1727  *
1728  * This routine waits until the target register @reg contains the expected
1729  * @value after applying the @mask, i.e. it waits until ::
1730  *
1731  *     (I915_READ_FW(reg) & mask) == value
1732  *
1733  * Otherwise, the wait will timeout after @slow_timeout_ms milliseconds.
1734  * For atomic context @slow_timeout_ms must be zero and @fast_timeout_us
1735  * must be not larger than 20,0000 microseconds.
1736  *
1737  * Note that this routine assumes the caller holds forcewake asserted, it is
1738  * not suitable for very long waits. See intel_wait_for_register() if you
1739  * wish to wait without holding forcewake for the duration (i.e. you expect
1740  * the wait to be slow).
1741  *
1742  * Returns 0 if the register matches the desired condition, or -ETIMEOUT.
1743  */
1744 int __intel_wait_for_register_fw(struct intel_uncore *uncore,
1745                                  i915_reg_t reg,
1746                                  u32 mask,
1747                                  u32 value,
1748                                  unsigned int fast_timeout_us,
1749                                  unsigned int slow_timeout_ms,
1750                                  u32 *out_value)
1751 {
1752         u32 uninitialized_var(reg_value);
1753 #define done (((reg_value = intel_uncore_read_fw(uncore, reg)) & mask) == value)
1754         int ret;
1755
1756         /* Catch any overuse of this function */
1757         might_sleep_if(slow_timeout_ms);
1758         GEM_BUG_ON(fast_timeout_us > 20000);
1759
1760         ret = -ETIMEDOUT;
1761         if (fast_timeout_us && fast_timeout_us <= 20000)
1762                 ret = _wait_for_atomic(done, fast_timeout_us, 0);
1763         if (ret && slow_timeout_ms)
1764                 ret = wait_for(done, slow_timeout_ms);
1765
1766         if (out_value)
1767                 *out_value = reg_value;
1768
1769         return ret;
1770 #undef done
1771 }
1772
1773 /**
1774  * __intel_wait_for_register - wait until register matches expected state
1775  * @uncore: the struct intel_uncore
1776  * @reg: the register to read
1777  * @mask: mask to apply to register value
1778  * @value: expected value
1779  * @fast_timeout_us: fast timeout in microsecond for atomic/tight wait
1780  * @slow_timeout_ms: slow timeout in millisecond
1781  * @out_value: optional placeholder to hold registry value
1782  *
1783  * This routine waits until the target register @reg contains the expected
1784  * @value after applying the @mask, i.e. it waits until ::
1785  *
1786  *     (I915_READ(reg) & mask) == value
1787  *
1788  * Otherwise, the wait will timeout after @timeout_ms milliseconds.
1789  *
1790  * Returns 0 if the register matches the desired condition, or -ETIMEOUT.
1791  */
1792 int __intel_wait_for_register(struct intel_uncore *uncore,
1793                               i915_reg_t reg,
1794                               u32 mask,
1795                               u32 value,
1796                               unsigned int fast_timeout_us,
1797                               unsigned int slow_timeout_ms,
1798                               u32 *out_value)
1799 {
1800         unsigned fw =
1801                 intel_uncore_forcewake_for_reg(uncore, reg, FW_REG_READ);
1802         u32 reg_value;
1803         int ret;
1804
1805         might_sleep_if(slow_timeout_ms);
1806
1807         spin_lock_irq(&uncore->lock);
1808         intel_uncore_forcewake_get__locked(uncore, fw);
1809
1810         ret = __intel_wait_for_register_fw(uncore,
1811                                            reg, mask, value,
1812                                            fast_timeout_us, 0, &reg_value);
1813
1814         intel_uncore_forcewake_put__locked(uncore, fw);
1815         spin_unlock_irq(&uncore->lock);
1816
1817         if (ret && slow_timeout_ms)
1818                 ret = __wait_for(reg_value = intel_uncore_read_notrace(uncore,
1819                                                                        reg),
1820                                  (reg_value & mask) == value,
1821                                  slow_timeout_ms * 1000, 10, 1000);
1822
1823         /* just trace the final value */
1824         trace_i915_reg_rw(false, reg, reg_value, sizeof(reg_value), true);
1825
1826         if (out_value)
1827                 *out_value = reg_value;
1828
1829         return ret;
1830 }
1831
1832 bool intel_uncore_unclaimed_mmio(struct intel_uncore *uncore)
1833 {
1834         return check_for_unclaimed_mmio(uncore);
1835 }
1836
1837 bool
1838 intel_uncore_arm_unclaimed_mmio_detection(struct intel_uncore *uncore)
1839 {
1840         bool ret = false;
1841
1842         spin_lock_irq(&uncore->lock);
1843
1844         if (unlikely(uncore->unclaimed_mmio_check <= 0))
1845                 goto out;
1846
1847         if (unlikely(intel_uncore_unclaimed_mmio(uncore))) {
1848                 if (!i915_modparams.mmio_debug) {
1849                         DRM_DEBUG("Unclaimed register detected, "
1850                                   "enabling oneshot unclaimed register reporting. "
1851                                   "Please use i915.mmio_debug=N for more information.\n");
1852                         i915_modparams.mmio_debug++;
1853                 }
1854                 uncore->unclaimed_mmio_check--;
1855                 ret = true;
1856         }
1857
1858 out:
1859         spin_unlock_irq(&uncore->lock);
1860
1861         return ret;
1862 }
1863
1864 static enum forcewake_domains
1865 intel_uncore_forcewake_for_read(struct intel_uncore *uncore,
1866                                 i915_reg_t reg)
1867 {
1868         struct drm_i915_private *i915 = uncore_to_i915(uncore);
1869         u32 offset = i915_mmio_reg_offset(reg);
1870         enum forcewake_domains fw_domains;
1871
1872         if (INTEL_GEN(i915) >= 11) {
1873                 fw_domains = __gen11_fwtable_reg_read_fw_domains(uncore, offset);
1874         } else if (HAS_FWTABLE(i915)) {
1875                 fw_domains = __fwtable_reg_read_fw_domains(uncore, offset);
1876         } else if (INTEL_GEN(i915) >= 6) {
1877                 fw_domains = __gen6_reg_read_fw_domains(uncore, offset);
1878         } else {
1879                 /* on devices with FW we expect to hit one of the above cases */
1880                 if (intel_uncore_has_forcewake(uncore))
1881                         MISSING_CASE(INTEL_GEN(i915));
1882
1883                 fw_domains = 0;
1884         }
1885
1886         WARN_ON(fw_domains & ~uncore->fw_domains);
1887
1888         return fw_domains;
1889 }
1890
1891 static enum forcewake_domains
1892 intel_uncore_forcewake_for_write(struct intel_uncore *uncore,
1893                                  i915_reg_t reg)
1894 {
1895         struct drm_i915_private *i915 = uncore_to_i915(uncore);
1896         u32 offset = i915_mmio_reg_offset(reg);
1897         enum forcewake_domains fw_domains;
1898
1899         if (INTEL_GEN(i915) >= 11) {
1900                 fw_domains = __gen11_fwtable_reg_write_fw_domains(uncore, offset);
1901         } else if (HAS_FWTABLE(i915) && !IS_VALLEYVIEW(i915)) {
1902                 fw_domains = __fwtable_reg_write_fw_domains(uncore, offset);
1903         } else if (IS_GEN(i915, 8)) {
1904                 fw_domains = __gen8_reg_write_fw_domains(uncore, offset);
1905         } else if (IS_GEN_RANGE(i915, 6, 7)) {
1906                 fw_domains = FORCEWAKE_RENDER;
1907         } else {
1908                 /* on devices with FW we expect to hit one of the above cases */
1909                 if (intel_uncore_has_forcewake(uncore))
1910                         MISSING_CASE(INTEL_GEN(i915));
1911
1912                 fw_domains = 0;
1913         }
1914
1915         WARN_ON(fw_domains & ~uncore->fw_domains);
1916
1917         return fw_domains;
1918 }
1919
1920 /**
1921  * intel_uncore_forcewake_for_reg - which forcewake domains are needed to access
1922  *                                  a register
1923  * @uncore: pointer to struct intel_uncore
1924  * @reg: register in question
1925  * @op: operation bitmask of FW_REG_READ and/or FW_REG_WRITE
1926  *
1927  * Returns a set of forcewake domains required to be taken with for example
1928  * intel_uncore_forcewake_get for the specified register to be accessible in the
1929  * specified mode (read, write or read/write) with raw mmio accessors.
1930  *
1931  * NOTE: On Gen6 and Gen7 write forcewake domain (FORCEWAKE_RENDER) requires the
1932  * callers to do FIFO management on their own or risk losing writes.
1933  */
1934 enum forcewake_domains
1935 intel_uncore_forcewake_for_reg(struct intel_uncore *uncore,
1936                                i915_reg_t reg, unsigned int op)
1937 {
1938         enum forcewake_domains fw_domains = 0;
1939
1940         WARN_ON(!op);
1941
1942         if (!intel_uncore_has_forcewake(uncore))
1943                 return 0;
1944
1945         if (op & FW_REG_READ)
1946                 fw_domains = intel_uncore_forcewake_for_read(uncore, reg);
1947
1948         if (op & FW_REG_WRITE)
1949                 fw_domains |= intel_uncore_forcewake_for_write(uncore, reg);
1950
1951         return fw_domains;
1952 }
1953
1954 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1955 #include "selftests/mock_uncore.c"
1956 #include "selftests/intel_uncore.c"
1957 #endif