2 * Copyright © 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "intel_drv.h"
27 #define FORCEWAKE_ACK_TIMEOUT_MS 2
29 #define __raw_i915_read8(dev_priv__, reg__) readb((dev_priv__)->regs + (reg__))
30 #define __raw_i915_write8(dev_priv__, reg__, val__) writeb(val__, (dev_priv__)->regs + (reg__))
32 #define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + (reg__))
33 #define __raw_i915_write16(dev_priv__, reg__, val__) writew(val__, (dev_priv__)->regs + (reg__))
35 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
36 #define __raw_i915_write32(dev_priv__, reg__, val__) writel(val__, (dev_priv__)->regs + (reg__))
38 #define __raw_i915_read64(dev_priv__, reg__) readq((dev_priv__)->regs + (reg__))
39 #define __raw_i915_write64(dev_priv__, reg__, val__) writeq(val__, (dev_priv__)->regs + (reg__))
41 #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32(dev_priv__, reg__)
44 assert_device_not_suspended(struct drm_i915_private *dev_priv)
46 WARN_ONCE(HAS_RUNTIME_PM(dev_priv->dev) && dev_priv->pm.suspended,
47 "Device suspended\n");
50 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
52 /* w/a for a sporadic read returning 0 by waiting for the GT
55 if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) &
56 GEN6_GT_THREAD_STATUS_CORE_MASK) == 0, 500))
57 DRM_ERROR("GT thread status wait timed out\n");
60 static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv)
62 __raw_i915_write32(dev_priv, FORCEWAKE, 0);
63 /* something from same cacheline, but !FORCEWAKE */
64 __raw_posting_read(dev_priv, ECOBUS);
67 static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv,
70 if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1) == 0,
71 FORCEWAKE_ACK_TIMEOUT_MS))
72 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
74 __raw_i915_write32(dev_priv, FORCEWAKE, 1);
75 /* something from same cacheline, but !FORCEWAKE */
76 __raw_posting_read(dev_priv, ECOBUS);
78 if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1),
79 FORCEWAKE_ACK_TIMEOUT_MS))
80 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
82 /* WaRsForcewakeWaitTC0:snb */
83 __gen6_gt_wait_for_thread_c0(dev_priv);
86 static void __gen7_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv)
88 __raw_i915_write32(dev_priv, FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff));
89 /* something from same cacheline, but !FORCEWAKE_MT */
90 __raw_posting_read(dev_priv, ECOBUS);
93 static void __gen7_gt_force_wake_mt_get(struct drm_i915_private *dev_priv,
98 if (IS_HASWELL(dev_priv->dev) || IS_BROADWELL(dev_priv->dev))
99 forcewake_ack = FORCEWAKE_ACK_HSW;
101 forcewake_ack = FORCEWAKE_MT_ACK;
103 if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL) == 0,
104 FORCEWAKE_ACK_TIMEOUT_MS))
105 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
107 __raw_i915_write32(dev_priv, FORCEWAKE_MT,
108 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
109 /* something from same cacheline, but !FORCEWAKE_MT */
110 __raw_posting_read(dev_priv, ECOBUS);
112 if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL),
113 FORCEWAKE_ACK_TIMEOUT_MS))
114 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
116 /* WaRsForcewakeWaitTC0:ivb,hsw */
117 __gen6_gt_wait_for_thread_c0(dev_priv);
120 static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
124 gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG);
125 if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg))
126 __raw_i915_write32(dev_priv, GTFIFODBG, gtfifodbg);
129 static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv,
132 __raw_i915_write32(dev_priv, FORCEWAKE, 0);
133 /* something from same cacheline, but !FORCEWAKE */
134 __raw_posting_read(dev_priv, ECOBUS);
135 gen6_gt_check_fifodbg(dev_priv);
138 static void __gen7_gt_force_wake_mt_put(struct drm_i915_private *dev_priv,
141 __raw_i915_write32(dev_priv, FORCEWAKE_MT,
142 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
143 /* something from same cacheline, but !FORCEWAKE_MT */
144 __raw_posting_read(dev_priv, ECOBUS);
146 if (IS_GEN7(dev_priv->dev))
147 gen6_gt_check_fifodbg(dev_priv);
150 static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
154 /* On VLV, FIFO will be shared by both SW and HW.
155 * So, we need to read the FREE_ENTRIES everytime */
156 if (IS_VALLEYVIEW(dev_priv->dev))
157 dev_priv->uncore.fifo_count =
158 __raw_i915_read32(dev_priv, GTFIFOCTL) &
159 GT_FIFO_FREE_ENTRIES_MASK;
161 if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
163 u32 fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK;
164 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
166 fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK;
168 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
170 dev_priv->uncore.fifo_count = fifo;
172 dev_priv->uncore.fifo_count--;
177 static void vlv_force_wake_reset(struct drm_i915_private *dev_priv)
179 __raw_i915_write32(dev_priv, FORCEWAKE_VLV,
180 _MASKED_BIT_DISABLE(0xffff));
181 __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV,
182 _MASKED_BIT_DISABLE(0xffff));
183 /* something from same cacheline, but !FORCEWAKE_VLV */
184 __raw_posting_read(dev_priv, FORCEWAKE_ACK_VLV);
187 static void __vlv_force_wake_get(struct drm_i915_private *dev_priv,
190 /* Check for Render Engine */
191 if (FORCEWAKE_RENDER & fw_engine) {
192 if (wait_for_atomic((__raw_i915_read32(dev_priv,
194 FORCEWAKE_KERNEL) == 0,
195 FORCEWAKE_ACK_TIMEOUT_MS))
196 DRM_ERROR("Timed out: Render forcewake old ack to clear.\n");
198 __raw_i915_write32(dev_priv, FORCEWAKE_VLV,
199 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
201 if (wait_for_atomic((__raw_i915_read32(dev_priv,
204 FORCEWAKE_ACK_TIMEOUT_MS))
205 DRM_ERROR("Timed out: waiting for Render to ack.\n");
208 /* Check for Media Engine */
209 if (FORCEWAKE_MEDIA & fw_engine) {
210 if (wait_for_atomic((__raw_i915_read32(dev_priv,
211 FORCEWAKE_ACK_MEDIA_VLV) &
212 FORCEWAKE_KERNEL) == 0,
213 FORCEWAKE_ACK_TIMEOUT_MS))
214 DRM_ERROR("Timed out: Media forcewake old ack to clear.\n");
216 __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV,
217 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
219 if (wait_for_atomic((__raw_i915_read32(dev_priv,
220 FORCEWAKE_ACK_MEDIA_VLV) &
222 FORCEWAKE_ACK_TIMEOUT_MS))
223 DRM_ERROR("Timed out: waiting for media to ack.\n");
227 static void __vlv_force_wake_put(struct drm_i915_private *dev_priv,
231 /* Check for Render Engine */
232 if (FORCEWAKE_RENDER & fw_engine)
233 __raw_i915_write32(dev_priv, FORCEWAKE_VLV,
234 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
237 /* Check for Media Engine */
238 if (FORCEWAKE_MEDIA & fw_engine)
239 __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV,
240 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
242 /* something from same cacheline, but !FORCEWAKE_VLV */
243 __raw_posting_read(dev_priv, FORCEWAKE_ACK_VLV);
244 if (!IS_CHERRYVIEW(dev_priv->dev))
245 gen6_gt_check_fifodbg(dev_priv);
248 static void vlv_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine)
250 unsigned long irqflags;
252 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
254 if (fw_engine & FORCEWAKE_RENDER &&
255 dev_priv->uncore.fw_rendercount++ != 0)
256 fw_engine &= ~FORCEWAKE_RENDER;
257 if (fw_engine & FORCEWAKE_MEDIA &&
258 dev_priv->uncore.fw_mediacount++ != 0)
259 fw_engine &= ~FORCEWAKE_MEDIA;
262 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_engine);
264 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
267 static void vlv_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine)
269 unsigned long irqflags;
271 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
273 if (fw_engine & FORCEWAKE_RENDER) {
274 WARN_ON(!dev_priv->uncore.fw_rendercount);
275 if (--dev_priv->uncore.fw_rendercount != 0)
276 fw_engine &= ~FORCEWAKE_RENDER;
279 if (fw_engine & FORCEWAKE_MEDIA) {
280 WARN_ON(!dev_priv->uncore.fw_mediacount);
281 if (--dev_priv->uncore.fw_mediacount != 0)
282 fw_engine &= ~FORCEWAKE_MEDIA;
286 dev_priv->uncore.funcs.force_wake_put(dev_priv, fw_engine);
288 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
291 static void __gen9_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv)
293 __raw_i915_write32(dev_priv, FORCEWAKE_RENDER_GEN9,
294 _MASKED_BIT_DISABLE(0xffff));
296 __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_GEN9,
297 _MASKED_BIT_DISABLE(0xffff));
299 __raw_i915_write32(dev_priv, FORCEWAKE_BLITTER_GEN9,
300 _MASKED_BIT_DISABLE(0xffff));
304 __gen9_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine)
306 /* Check for Render Engine */
307 if (FORCEWAKE_RENDER & fw_engine) {
308 if (wait_for_atomic((__raw_i915_read32(dev_priv,
309 FORCEWAKE_ACK_RENDER_GEN9) &
310 FORCEWAKE_KERNEL) == 0,
311 FORCEWAKE_ACK_TIMEOUT_MS))
312 DRM_ERROR("Timed out: Render forcewake old ack to clear.\n");
314 __raw_i915_write32(dev_priv, FORCEWAKE_RENDER_GEN9,
315 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
317 if (wait_for_atomic((__raw_i915_read32(dev_priv,
318 FORCEWAKE_ACK_RENDER_GEN9) &
320 FORCEWAKE_ACK_TIMEOUT_MS))
321 DRM_ERROR("Timed out: waiting for Render to ack.\n");
324 /* Check for Media Engine */
325 if (FORCEWAKE_MEDIA & fw_engine) {
326 if (wait_for_atomic((__raw_i915_read32(dev_priv,
327 FORCEWAKE_ACK_MEDIA_GEN9) &
328 FORCEWAKE_KERNEL) == 0,
329 FORCEWAKE_ACK_TIMEOUT_MS))
330 DRM_ERROR("Timed out: Media forcewake old ack to clear.\n");
332 __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_GEN9,
333 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
335 if (wait_for_atomic((__raw_i915_read32(dev_priv,
336 FORCEWAKE_ACK_MEDIA_GEN9) &
338 FORCEWAKE_ACK_TIMEOUT_MS))
339 DRM_ERROR("Timed out: waiting for Media to ack.\n");
342 /* Check for Blitter Engine */
343 if (FORCEWAKE_BLITTER & fw_engine) {
344 if (wait_for_atomic((__raw_i915_read32(dev_priv,
345 FORCEWAKE_ACK_BLITTER_GEN9) &
346 FORCEWAKE_KERNEL) == 0,
347 FORCEWAKE_ACK_TIMEOUT_MS))
348 DRM_ERROR("Timed out: Blitter forcewake old ack to clear.\n");
350 __raw_i915_write32(dev_priv, FORCEWAKE_BLITTER_GEN9,
351 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
353 if (wait_for_atomic((__raw_i915_read32(dev_priv,
354 FORCEWAKE_ACK_BLITTER_GEN9) &
356 FORCEWAKE_ACK_TIMEOUT_MS))
357 DRM_ERROR("Timed out: waiting for Blitter to ack.\n");
362 __gen9_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine)
364 /* Check for Render Engine */
365 if (FORCEWAKE_RENDER & fw_engine)
366 __raw_i915_write32(dev_priv, FORCEWAKE_RENDER_GEN9,
367 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
369 /* Check for Media Engine */
370 if (FORCEWAKE_MEDIA & fw_engine)
371 __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_GEN9,
372 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
374 /* Check for Blitter Engine */
375 if (FORCEWAKE_BLITTER & fw_engine)
376 __raw_i915_write32(dev_priv, FORCEWAKE_BLITTER_GEN9,
377 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
381 gen9_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine)
383 unsigned long irqflags;
385 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
387 if (FORCEWAKE_RENDER & fw_engine) {
388 if (dev_priv->uncore.fw_rendercount++ == 0)
389 dev_priv->uncore.funcs.force_wake_get(dev_priv,
393 if (FORCEWAKE_MEDIA & fw_engine) {
394 if (dev_priv->uncore.fw_mediacount++ == 0)
395 dev_priv->uncore.funcs.force_wake_get(dev_priv,
399 if (FORCEWAKE_BLITTER & fw_engine) {
400 if (dev_priv->uncore.fw_blittercount++ == 0)
401 dev_priv->uncore.funcs.force_wake_get(dev_priv,
405 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
409 gen9_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine)
411 unsigned long irqflags;
413 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
415 if (FORCEWAKE_RENDER & fw_engine) {
416 WARN_ON(dev_priv->uncore.fw_rendercount == 0);
417 if (--dev_priv->uncore.fw_rendercount == 0)
418 dev_priv->uncore.funcs.force_wake_put(dev_priv,
422 if (FORCEWAKE_MEDIA & fw_engine) {
423 WARN_ON(dev_priv->uncore.fw_mediacount == 0);
424 if (--dev_priv->uncore.fw_mediacount == 0)
425 dev_priv->uncore.funcs.force_wake_put(dev_priv,
429 if (FORCEWAKE_BLITTER & fw_engine) {
430 WARN_ON(dev_priv->uncore.fw_blittercount == 0);
431 if (--dev_priv->uncore.fw_blittercount == 0)
432 dev_priv->uncore.funcs.force_wake_put(dev_priv,
436 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
439 static void gen6_force_wake_timer(unsigned long arg)
441 struct drm_i915_private *dev_priv = (void *)arg;
442 unsigned long irqflags;
444 assert_device_not_suspended(dev_priv);
446 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
447 WARN_ON(!dev_priv->uncore.forcewake_count);
449 if (--dev_priv->uncore.forcewake_count == 0)
450 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
451 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
453 intel_runtime_pm_put(dev_priv);
456 void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore)
458 struct drm_i915_private *dev_priv = dev->dev_private;
459 unsigned long irqflags;
461 if (del_timer_sync(&dev_priv->uncore.force_wake_timer))
462 gen6_force_wake_timer((unsigned long)dev_priv);
464 /* Hold uncore.lock across reset to prevent any register access
465 * with forcewake not set correctly
467 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
469 if (IS_VALLEYVIEW(dev))
470 vlv_force_wake_reset(dev_priv);
471 else if (IS_GEN6(dev) || IS_GEN7(dev))
472 __gen6_gt_force_wake_reset(dev_priv);
474 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev))
475 __gen7_gt_force_wake_mt_reset(dev_priv);
478 __gen9_gt_force_wake_mt_reset(dev_priv);
480 if (restore) { /* If reset with a user forcewake, try to restore */
483 if (IS_VALLEYVIEW(dev)) {
484 if (dev_priv->uncore.fw_rendercount)
485 fw |= FORCEWAKE_RENDER;
487 if (dev_priv->uncore.fw_mediacount)
488 fw |= FORCEWAKE_MEDIA;
489 } else if (IS_GEN9(dev)) {
490 if (dev_priv->uncore.fw_rendercount)
491 fw |= FORCEWAKE_RENDER;
493 if (dev_priv->uncore.fw_mediacount)
494 fw |= FORCEWAKE_MEDIA;
496 if (dev_priv->uncore.fw_blittercount)
497 fw |= FORCEWAKE_BLITTER;
499 if (dev_priv->uncore.forcewake_count)
504 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw);
506 if (IS_GEN6(dev) || IS_GEN7(dev))
507 dev_priv->uncore.fifo_count =
508 __raw_i915_read32(dev_priv, GTFIFOCTL) &
509 GT_FIFO_FREE_ENTRIES_MASK;
512 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
515 static void __intel_uncore_early_sanitize(struct drm_device *dev,
516 bool restore_forcewake)
518 struct drm_i915_private *dev_priv = dev->dev_private;
520 if (HAS_FPGA_DBG_UNCLAIMED(dev))
521 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
523 if ((IS_HASWELL(dev) || IS_BROADWELL(dev)) &&
524 (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) == 1)) {
525 /* The docs do not explain exactly how the calculation can be
526 * made. It is somewhat guessable, but for now, it's always
528 * NB: We can't write IDICR yet because we do not have gt funcs
530 dev_priv->ellc_size = 128;
531 DRM_INFO("Found %zuMB of eLLC\n", dev_priv->ellc_size);
534 /* clear out old GT FIFO errors */
535 if (IS_GEN6(dev) || IS_GEN7(dev))
536 __raw_i915_write32(dev_priv, GTFIFODBG,
537 __raw_i915_read32(dev_priv, GTFIFODBG));
539 intel_uncore_forcewake_reset(dev, restore_forcewake);
542 void intel_uncore_early_sanitize(struct drm_device *dev, bool restore_forcewake)
544 __intel_uncore_early_sanitize(dev, restore_forcewake);
545 i915_check_and_clear_faults(dev);
548 void intel_uncore_sanitize(struct drm_device *dev)
550 /* BIOS often leaves RC6 enabled, but disable it for hw init */
551 intel_disable_gt_powersave(dev);
555 * Generally this is called implicitly by the register read function. However,
556 * if some sequence requires the GT to not power down then this function should
557 * be called at the beginning of the sequence followed by a call to
558 * gen6_gt_force_wake_put() at the end of the sequence.
560 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine)
562 unsigned long irqflags;
564 if (!dev_priv->uncore.funcs.force_wake_get)
567 intel_runtime_pm_get(dev_priv);
569 /* Redirect to Gen9 specific routine */
570 if (IS_GEN9(dev_priv->dev))
571 return gen9_force_wake_get(dev_priv, fw_engine);
573 /* Redirect to VLV specific routine */
574 if (IS_VALLEYVIEW(dev_priv->dev))
575 return vlv_force_wake_get(dev_priv, fw_engine);
577 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
578 if (dev_priv->uncore.forcewake_count++ == 0)
579 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
580 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
584 * see gen6_gt_force_wake_get()
586 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine)
588 unsigned long irqflags;
589 bool delayed = false;
591 if (!dev_priv->uncore.funcs.force_wake_put)
594 /* Redirect to Gen9 specific routine */
595 if (IS_GEN9(dev_priv->dev)) {
596 gen9_force_wake_put(dev_priv, fw_engine);
600 /* Redirect to VLV specific routine */
601 if (IS_VALLEYVIEW(dev_priv->dev)) {
602 vlv_force_wake_put(dev_priv, fw_engine);
607 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
608 WARN_ON(!dev_priv->uncore.forcewake_count);
610 if (--dev_priv->uncore.forcewake_count == 0) {
611 dev_priv->uncore.forcewake_count++;
613 mod_timer_pinned(&dev_priv->uncore.force_wake_timer,
616 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
620 intel_runtime_pm_put(dev_priv);
623 void assert_force_wake_inactive(struct drm_i915_private *dev_priv)
625 if (!dev_priv->uncore.funcs.force_wake_get)
628 WARN_ON(dev_priv->uncore.forcewake_count > 0);
631 /* We give fast paths for the really cool registers */
632 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
633 ((reg) < 0x40000 && (reg) != FORCEWAKE)
635 #define REG_RANGE(reg, start, end) ((reg) >= (start) && (reg) < (end))
637 #define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \
638 (REG_RANGE((reg), 0x2000, 0x4000) || \
639 REG_RANGE((reg), 0x5000, 0x8000) || \
640 REG_RANGE((reg), 0xB000, 0x12000) || \
641 REG_RANGE((reg), 0x2E000, 0x30000))
643 #define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg) \
644 (REG_RANGE((reg), 0x12000, 0x14000) || \
645 REG_RANGE((reg), 0x22000, 0x24000) || \
646 REG_RANGE((reg), 0x30000, 0x40000))
648 #define FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg) \
649 (REG_RANGE((reg), 0x2000, 0x4000) || \
650 REG_RANGE((reg), 0x5200, 0x8000) || \
651 REG_RANGE((reg), 0x8300, 0x8500) || \
652 REG_RANGE((reg), 0xB000, 0xB480) || \
653 REG_RANGE((reg), 0xE000, 0xE800))
655 #define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg) \
656 (REG_RANGE((reg), 0x8800, 0x8900) || \
657 REG_RANGE((reg), 0xD000, 0xD800) || \
658 REG_RANGE((reg), 0x12000, 0x14000) || \
659 REG_RANGE((reg), 0x1A000, 0x1C000) || \
660 REG_RANGE((reg), 0x1E800, 0x1EA00) || \
661 REG_RANGE((reg), 0x30000, 0x38000))
663 #define FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg) \
664 (REG_RANGE((reg), 0x4000, 0x5000) || \
665 REG_RANGE((reg), 0x8000, 0x8300) || \
666 REG_RANGE((reg), 0x8500, 0x8600) || \
667 REG_RANGE((reg), 0x9000, 0xB000) || \
668 REG_RANGE((reg), 0xF000, 0x10000))
670 #define FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) \
671 REG_RANGE((reg), 0xB00, 0x2000)
673 #define FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) \
674 (REG_RANGE((reg), 0x2000, 0x2700) || \
675 REG_RANGE((reg), 0x3000, 0x4000) || \
676 REG_RANGE((reg), 0x5200, 0x8000) || \
677 REG_RANGE((reg), 0x8140, 0x8160) || \
678 REG_RANGE((reg), 0x8300, 0x8500) || \
679 REG_RANGE((reg), 0x8C00, 0x8D00) || \
680 REG_RANGE((reg), 0xB000, 0xB480) || \
681 REG_RANGE((reg), 0xE000, 0xE900) || \
682 REG_RANGE((reg), 0x24400, 0x24800))
684 #define FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) \
685 (REG_RANGE((reg), 0x8130, 0x8140) || \
686 REG_RANGE((reg), 0x8800, 0x8A00) || \
687 REG_RANGE((reg), 0xD000, 0xD800) || \
688 REG_RANGE((reg), 0x12000, 0x14000) || \
689 REG_RANGE((reg), 0x1A000, 0x1EA00) || \
690 REG_RANGE((reg), 0x30000, 0x40000))
692 #define FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg) \
693 REG_RANGE((reg), 0x9400, 0x9800)
695 #define FORCEWAKE_GEN9_BLITTER_RANGE_OFFSET(reg) \
697 !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) && \
698 !FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) && \
699 !FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) && \
700 !FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg))
703 ilk_dummy_write(struct drm_i915_private *dev_priv)
705 /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
706 * the chip from rc6 before touching it for real. MI_MODE is masked,
707 * hence harmless to write 0 into. */
708 __raw_i915_write32(dev_priv, MI_MODE, 0);
712 hsw_unclaimed_reg_debug(struct drm_i915_private *dev_priv, u32 reg, bool read,
715 const char *op = read ? "reading" : "writing to";
716 const char *when = before ? "before" : "after";
718 if (!i915.mmio_debug)
721 if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {
722 WARN(1, "Unclaimed register detected %s %s register 0x%x\n",
724 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
729 hsw_unclaimed_reg_detect(struct drm_i915_private *dev_priv)
734 if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {
735 DRM_ERROR("Unclaimed register detected. Please use the i915.mmio_debug=1 to debug this problem.");
736 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
740 #define REG_READ_HEADER(x) \
741 unsigned long irqflags; \
743 assert_device_not_suspended(dev_priv); \
744 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
746 #define REG_READ_FOOTER \
747 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
748 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
751 #define __gen4_read(x) \
753 gen4_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
754 REG_READ_HEADER(x); \
755 val = __raw_i915_read##x(dev_priv, reg); \
759 #define __gen5_read(x) \
761 gen5_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
762 REG_READ_HEADER(x); \
763 ilk_dummy_write(dev_priv); \
764 val = __raw_i915_read##x(dev_priv, reg); \
768 #define __gen6_read(x) \
770 gen6_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
771 REG_READ_HEADER(x); \
772 hsw_unclaimed_reg_debug(dev_priv, reg, true, true); \
773 if (dev_priv->uncore.forcewake_count == 0 && \
774 NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
775 dev_priv->uncore.funcs.force_wake_get(dev_priv, \
777 val = __raw_i915_read##x(dev_priv, reg); \
778 dev_priv->uncore.funcs.force_wake_put(dev_priv, \
781 val = __raw_i915_read##x(dev_priv, reg); \
783 hsw_unclaimed_reg_debug(dev_priv, reg, true, false); \
787 #define __vlv_read(x) \
789 vlv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
790 unsigned fwengine = 0; \
791 REG_READ_HEADER(x); \
792 if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg)) { \
793 if (dev_priv->uncore.fw_rendercount == 0) \
794 fwengine = FORCEWAKE_RENDER; \
795 } else if (FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)) { \
796 if (dev_priv->uncore.fw_mediacount == 0) \
797 fwengine = FORCEWAKE_MEDIA; \
800 dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \
801 val = __raw_i915_read##x(dev_priv, reg); \
803 dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
807 #define __chv_read(x) \
809 chv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
810 unsigned fwengine = 0; \
811 REG_READ_HEADER(x); \
812 if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \
813 if (dev_priv->uncore.fw_rendercount == 0) \
814 fwengine = FORCEWAKE_RENDER; \
815 } else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
816 if (dev_priv->uncore.fw_mediacount == 0) \
817 fwengine = FORCEWAKE_MEDIA; \
818 } else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
819 if (dev_priv->uncore.fw_rendercount == 0) \
820 fwengine |= FORCEWAKE_RENDER; \
821 if (dev_priv->uncore.fw_mediacount == 0) \
822 fwengine |= FORCEWAKE_MEDIA; \
825 dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \
826 val = __raw_i915_read##x(dev_priv, reg); \
828 dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
832 #define SKL_NEEDS_FORCE_WAKE(dev_priv, reg) \
833 ((reg) < 0x40000 && !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg))
835 #define __gen9_read(x) \
837 gen9_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
838 REG_READ_HEADER(x); \
839 if (!SKL_NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
840 val = __raw_i915_read##x(dev_priv, reg); \
842 unsigned fwengine = 0; \
843 if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg)) { \
844 if (dev_priv->uncore.fw_rendercount == 0) \
845 fwengine = FORCEWAKE_RENDER; \
846 } else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg)) { \
847 if (dev_priv->uncore.fw_mediacount == 0) \
848 fwengine = FORCEWAKE_MEDIA; \
849 } else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg)) { \
850 if (dev_priv->uncore.fw_rendercount == 0) \
851 fwengine |= FORCEWAKE_RENDER; \
852 if (dev_priv->uncore.fw_mediacount == 0) \
853 fwengine |= FORCEWAKE_MEDIA; \
855 if (dev_priv->uncore.fw_blittercount == 0) \
856 fwengine = FORCEWAKE_BLITTER; \
859 dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \
860 val = __raw_i915_read##x(dev_priv, reg); \
862 dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
898 #undef REG_READ_FOOTER
899 #undef REG_READ_HEADER
901 #define REG_WRITE_HEADER \
902 unsigned long irqflags; \
903 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
904 assert_device_not_suspended(dev_priv); \
905 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
907 #define REG_WRITE_FOOTER \
908 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
910 #define __gen4_write(x) \
912 gen4_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
914 __raw_i915_write##x(dev_priv, reg, val); \
918 #define __gen5_write(x) \
920 gen5_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
922 ilk_dummy_write(dev_priv); \
923 __raw_i915_write##x(dev_priv, reg, val); \
927 #define __gen6_write(x) \
929 gen6_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
930 u32 __fifo_ret = 0; \
932 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
933 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
935 __raw_i915_write##x(dev_priv, reg, val); \
936 if (unlikely(__fifo_ret)) { \
937 gen6_gt_check_fifodbg(dev_priv); \
942 #define __hsw_write(x) \
944 hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
945 u32 __fifo_ret = 0; \
947 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
948 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
950 hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \
951 __raw_i915_write##x(dev_priv, reg, val); \
952 if (unlikely(__fifo_ret)) { \
953 gen6_gt_check_fifodbg(dev_priv); \
955 hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
956 hsw_unclaimed_reg_detect(dev_priv); \
960 static const u32 gen8_shadowed_regs[] = {
964 RING_TAIL(RENDER_RING_BASE),
965 RING_TAIL(GEN6_BSD_RING_BASE),
966 RING_TAIL(VEBOX_RING_BASE),
967 RING_TAIL(BLT_RING_BASE),
968 /* TODO: Other registers are not yet used */
971 static bool is_gen8_shadowed(struct drm_i915_private *dev_priv, u32 reg)
974 for (i = 0; i < ARRAY_SIZE(gen8_shadowed_regs); i++)
975 if (reg == gen8_shadowed_regs[i])
981 #define __gen8_write(x) \
983 gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
985 hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \
986 if (reg < 0x40000 && !is_gen8_shadowed(dev_priv, reg)) { \
987 if (dev_priv->uncore.forcewake_count == 0) \
988 dev_priv->uncore.funcs.force_wake_get(dev_priv, \
990 __raw_i915_write##x(dev_priv, reg, val); \
991 if (dev_priv->uncore.forcewake_count == 0) \
992 dev_priv->uncore.funcs.force_wake_put(dev_priv, \
995 __raw_i915_write##x(dev_priv, reg, val); \
997 hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
998 hsw_unclaimed_reg_detect(dev_priv); \
1002 #define __chv_write(x) \
1004 chv_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
1005 unsigned fwengine = 0; \
1006 bool shadowed = is_gen8_shadowed(dev_priv, reg); \
1009 if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \
1010 if (dev_priv->uncore.fw_rendercount == 0) \
1011 fwengine = FORCEWAKE_RENDER; \
1012 } else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
1013 if (dev_priv->uncore.fw_mediacount == 0) \
1014 fwengine = FORCEWAKE_MEDIA; \
1015 } else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
1016 if (dev_priv->uncore.fw_rendercount == 0) \
1017 fwengine |= FORCEWAKE_RENDER; \
1018 if (dev_priv->uncore.fw_mediacount == 0) \
1019 fwengine |= FORCEWAKE_MEDIA; \
1023 dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \
1024 __raw_i915_write##x(dev_priv, reg, val); \
1026 dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
1030 static const u32 gen9_shadowed_regs[] = {
1031 RING_TAIL(RENDER_RING_BASE),
1032 RING_TAIL(GEN6_BSD_RING_BASE),
1033 RING_TAIL(VEBOX_RING_BASE),
1034 RING_TAIL(BLT_RING_BASE),
1035 FORCEWAKE_BLITTER_GEN9,
1036 FORCEWAKE_RENDER_GEN9,
1037 FORCEWAKE_MEDIA_GEN9,
1040 /* TODO: Other registers are not yet used */
1043 static bool is_gen9_shadowed(struct drm_i915_private *dev_priv, u32 reg)
1046 for (i = 0; i < ARRAY_SIZE(gen9_shadowed_regs); i++)
1047 if (reg == gen9_shadowed_regs[i])
1053 #define __gen9_write(x) \
1055 gen9_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, \
1058 if (!SKL_NEEDS_FORCE_WAKE((dev_priv), (reg)) || \
1059 is_gen9_shadowed(dev_priv, reg)) { \
1060 __raw_i915_write##x(dev_priv, reg, val); \
1062 unsigned fwengine = 0; \
1063 if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg)) { \
1064 if (dev_priv->uncore.fw_rendercount == 0) \
1065 fwengine = FORCEWAKE_RENDER; \
1066 } else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg)) { \
1067 if (dev_priv->uncore.fw_mediacount == 0) \
1068 fwengine = FORCEWAKE_MEDIA; \
1069 } else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg)) { \
1070 if (dev_priv->uncore.fw_rendercount == 0) \
1071 fwengine |= FORCEWAKE_RENDER; \
1072 if (dev_priv->uncore.fw_mediacount == 0) \
1073 fwengine |= FORCEWAKE_MEDIA; \
1075 if (dev_priv->uncore.fw_blittercount == 0) \
1076 fwengine = FORCEWAKE_BLITTER; \
1079 dev_priv->uncore.funcs.force_wake_get(dev_priv, \
1081 __raw_i915_write##x(dev_priv, reg, val); \
1083 dev_priv->uncore.funcs.force_wake_put(dev_priv, \
1125 #undef REG_WRITE_FOOTER
1126 #undef REG_WRITE_HEADER
1128 #define ASSIGN_WRITE_MMIO_VFUNCS(x) \
1130 dev_priv->uncore.funcs.mmio_writeb = x##_write8; \
1131 dev_priv->uncore.funcs.mmio_writew = x##_write16; \
1132 dev_priv->uncore.funcs.mmio_writel = x##_write32; \
1133 dev_priv->uncore.funcs.mmio_writeq = x##_write64; \
1136 #define ASSIGN_READ_MMIO_VFUNCS(x) \
1138 dev_priv->uncore.funcs.mmio_readb = x##_read8; \
1139 dev_priv->uncore.funcs.mmio_readw = x##_read16; \
1140 dev_priv->uncore.funcs.mmio_readl = x##_read32; \
1141 dev_priv->uncore.funcs.mmio_readq = x##_read64; \
1144 void intel_uncore_init(struct drm_device *dev)
1146 struct drm_i915_private *dev_priv = dev->dev_private;
1148 setup_timer(&dev_priv->uncore.force_wake_timer,
1149 gen6_force_wake_timer, (unsigned long)dev_priv);
1151 __intel_uncore_early_sanitize(dev, false);
1154 dev_priv->uncore.funcs.force_wake_get = __gen9_force_wake_get;
1155 dev_priv->uncore.funcs.force_wake_put = __gen9_force_wake_put;
1156 } else if (IS_VALLEYVIEW(dev)) {
1157 dev_priv->uncore.funcs.force_wake_get = __vlv_force_wake_get;
1158 dev_priv->uncore.funcs.force_wake_put = __vlv_force_wake_put;
1159 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1160 dev_priv->uncore.funcs.force_wake_get = __gen7_gt_force_wake_mt_get;
1161 dev_priv->uncore.funcs.force_wake_put = __gen7_gt_force_wake_mt_put;
1162 } else if (IS_IVYBRIDGE(dev)) {
1165 /* IVB configs may use multi-threaded forcewake */
1167 /* A small trick here - if the bios hasn't configured
1168 * MT forcewake, and if the device is in RC6, then
1169 * force_wake_mt_get will not wake the device and the
1170 * ECOBUS read will return zero. Which will be
1171 * (correctly) interpreted by the test below as MT
1172 * forcewake being disabled.
1174 mutex_lock(&dev->struct_mutex);
1175 __gen7_gt_force_wake_mt_get(dev_priv, FORCEWAKE_ALL);
1176 ecobus = __raw_i915_read32(dev_priv, ECOBUS);
1177 __gen7_gt_force_wake_mt_put(dev_priv, FORCEWAKE_ALL);
1178 mutex_unlock(&dev->struct_mutex);
1180 if (ecobus & FORCEWAKE_MT_ENABLE) {
1181 dev_priv->uncore.funcs.force_wake_get =
1182 __gen7_gt_force_wake_mt_get;
1183 dev_priv->uncore.funcs.force_wake_put =
1184 __gen7_gt_force_wake_mt_put;
1186 DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n");
1187 DRM_INFO("when using vblank-synced partial screen updates.\n");
1188 dev_priv->uncore.funcs.force_wake_get =
1189 __gen6_gt_force_wake_get;
1190 dev_priv->uncore.funcs.force_wake_put =
1191 __gen6_gt_force_wake_put;
1193 } else if (IS_GEN6(dev)) {
1194 dev_priv->uncore.funcs.force_wake_get =
1195 __gen6_gt_force_wake_get;
1196 dev_priv->uncore.funcs.force_wake_put =
1197 __gen6_gt_force_wake_put;
1200 switch (INTEL_INFO(dev)->gen) {
1202 MISSING_CASE(INTEL_INFO(dev)->gen);
1205 ASSIGN_WRITE_MMIO_VFUNCS(gen9);
1206 ASSIGN_READ_MMIO_VFUNCS(gen9);
1209 if (IS_CHERRYVIEW(dev)) {
1210 ASSIGN_WRITE_MMIO_VFUNCS(chv);
1211 ASSIGN_READ_MMIO_VFUNCS(chv);
1214 ASSIGN_WRITE_MMIO_VFUNCS(gen8);
1215 ASSIGN_READ_MMIO_VFUNCS(gen6);
1220 if (IS_HASWELL(dev)) {
1221 ASSIGN_WRITE_MMIO_VFUNCS(hsw);
1223 ASSIGN_WRITE_MMIO_VFUNCS(gen6);
1226 if (IS_VALLEYVIEW(dev)) {
1227 ASSIGN_READ_MMIO_VFUNCS(vlv);
1229 ASSIGN_READ_MMIO_VFUNCS(gen6);
1233 ASSIGN_WRITE_MMIO_VFUNCS(gen5);
1234 ASSIGN_READ_MMIO_VFUNCS(gen5);
1239 ASSIGN_WRITE_MMIO_VFUNCS(gen4);
1240 ASSIGN_READ_MMIO_VFUNCS(gen4);
1244 i915_check_and_clear_faults(dev);
1246 #undef ASSIGN_WRITE_MMIO_VFUNCS
1247 #undef ASSIGN_READ_MMIO_VFUNCS
1249 void intel_uncore_fini(struct drm_device *dev)
1251 /* Paranoia: make sure we have disabled everything before we exit. */
1252 intel_uncore_sanitize(dev);
1253 intel_uncore_forcewake_reset(dev, false);
1256 #define GEN_RANGE(l, h) GENMASK(h, l)
1258 static const struct register_whitelist {
1261 /* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
1262 uint32_t gen_bitmask;
1264 { RING_TIMESTAMP(RENDER_RING_BASE), 8, GEN_RANGE(4, 9) },
1267 int i915_reg_read_ioctl(struct drm_device *dev,
1268 void *data, struct drm_file *file)
1270 struct drm_i915_private *dev_priv = dev->dev_private;
1271 struct drm_i915_reg_read *reg = data;
1272 struct register_whitelist const *entry = whitelist;
1275 for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
1276 if (entry->offset == reg->offset &&
1277 (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
1281 if (i == ARRAY_SIZE(whitelist))
1284 intel_runtime_pm_get(dev_priv);
1286 switch (entry->size) {
1288 reg->val = I915_READ64(reg->offset);
1291 reg->val = I915_READ(reg->offset);
1294 reg->val = I915_READ16(reg->offset);
1297 reg->val = I915_READ8(reg->offset);
1300 MISSING_CASE(entry->size);
1306 intel_runtime_pm_put(dev_priv);
1310 int i915_get_reset_stats_ioctl(struct drm_device *dev,
1311 void *data, struct drm_file *file)
1313 struct drm_i915_private *dev_priv = dev->dev_private;
1314 struct drm_i915_reset_stats *args = data;
1315 struct i915_ctx_hang_stats *hs;
1316 struct intel_context *ctx;
1319 if (args->flags || args->pad)
1322 if (args->ctx_id == DEFAULT_CONTEXT_HANDLE && !capable(CAP_SYS_ADMIN))
1325 ret = mutex_lock_interruptible(&dev->struct_mutex);
1329 ctx = i915_gem_context_get(file->driver_priv, args->ctx_id);
1331 mutex_unlock(&dev->struct_mutex);
1332 return PTR_ERR(ctx);
1334 hs = &ctx->hang_stats;
1336 if (capable(CAP_SYS_ADMIN))
1337 args->reset_count = i915_reset_count(&dev_priv->gpu_error);
1339 args->reset_count = 0;
1341 args->batch_active = hs->batch_active;
1342 args->batch_pending = hs->batch_pending;
1344 mutex_unlock(&dev->struct_mutex);
1349 static int i915_reset_complete(struct drm_device *dev)
1352 pci_read_config_byte(dev->pdev, I915_GDRST, &gdrst);
1353 return (gdrst & GRDOM_RESET_STATUS) == 0;
1356 static int i915_do_reset(struct drm_device *dev)
1358 /* assert reset for at least 20 usec */
1359 pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_RESET_ENABLE);
1361 pci_write_config_byte(dev->pdev, I915_GDRST, 0);
1363 return wait_for(i915_reset_complete(dev), 500);
1366 static int g4x_reset_complete(struct drm_device *dev)
1369 pci_read_config_byte(dev->pdev, I915_GDRST, &gdrst);
1370 return (gdrst & GRDOM_RESET_ENABLE) == 0;
1373 static int g33_do_reset(struct drm_device *dev)
1375 pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_RESET_ENABLE);
1376 return wait_for(g4x_reset_complete(dev), 500);
1379 static int g4x_do_reset(struct drm_device *dev)
1381 struct drm_i915_private *dev_priv = dev->dev_private;
1384 pci_write_config_byte(dev->pdev, I915_GDRST,
1385 GRDOM_RENDER | GRDOM_RESET_ENABLE);
1386 ret = wait_for(g4x_reset_complete(dev), 500);
1390 /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1391 I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE);
1392 POSTING_READ(VDECCLK_GATE_D);
1394 pci_write_config_byte(dev->pdev, I915_GDRST,
1395 GRDOM_MEDIA | GRDOM_RESET_ENABLE);
1396 ret = wait_for(g4x_reset_complete(dev), 500);
1400 /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1401 I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE);
1402 POSTING_READ(VDECCLK_GATE_D);
1404 pci_write_config_byte(dev->pdev, I915_GDRST, 0);
1409 static int ironlake_do_reset(struct drm_device *dev)
1411 struct drm_i915_private *dev_priv = dev->dev_private;
1414 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
1415 ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
1416 ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) &
1417 ILK_GRDOM_RESET_ENABLE) == 0, 500);
1421 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
1422 ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
1423 ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) &
1424 ILK_GRDOM_RESET_ENABLE) == 0, 500);
1428 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, 0);
1433 static int gen6_do_reset(struct drm_device *dev)
1435 struct drm_i915_private *dev_priv = dev->dev_private;
1438 /* Reset the chip */
1440 /* GEN6_GDRST is not in the gt power well, no need to check
1441 * for fifo space for the write or forcewake the chip for
1444 __raw_i915_write32(dev_priv, GEN6_GDRST, GEN6_GRDOM_FULL);
1446 /* Spin waiting for the device to ack the reset request */
1447 ret = wait_for((__raw_i915_read32(dev_priv, GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
1449 intel_uncore_forcewake_reset(dev, true);
1454 int intel_gpu_reset(struct drm_device *dev)
1456 if (INTEL_INFO(dev)->gen >= 6)
1457 return gen6_do_reset(dev);
1458 else if (IS_GEN5(dev))
1459 return ironlake_do_reset(dev);
1460 else if (IS_G4X(dev))
1461 return g4x_do_reset(dev);
1462 else if (IS_G33(dev))
1463 return g33_do_reset(dev);
1464 else if (INTEL_INFO(dev)->gen >= 3)
1465 return i915_do_reset(dev);
1470 void intel_uncore_check_errors(struct drm_device *dev)
1472 struct drm_i915_private *dev_priv = dev->dev_private;
1474 if (HAS_FPGA_DBG_UNCLAIMED(dev) &&
1475 (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
1476 DRM_ERROR("Unclaimed register before interrupt\n");
1477 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);