drivers/gpu/drm/i915/intel_uncore.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "i915_drv.h"
  25 #include "intel_drv.h"
  26 #include "i915_vgpu.h"
  27
  28 #include <linux/pm_runtime.h>
  29
  30 #define FORCEWAKE_ACK_TIMEOUT_MS 50
  31
  32 #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32((dev_priv__), (reg__))
  33
  34 static const char * const forcewake_domain_names[] = {
  35         "render",
  36         "blitter",
  37         "media",
  38 };
  39
  40 const char *
  41 intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id)
  42 {
  43         BUILD_BUG_ON(ARRAY_SIZE(forcewake_domain_names) != FW_DOMAIN_ID_COUNT);
  44
  45         if (id >= 0 && id < FW_DOMAIN_ID_COUNT)
  46                 return forcewake_domain_names[id];
  47
  48         WARN_ON(id);
  49
  50         return "unknown";
  51 }
  52
  53 static inline void
  54 fw_domain_reset(const struct intel_uncore_forcewake_domain *d)
  55 {
  56         WARN_ON(!i915_mmio_reg_valid(d->reg_set));
  57         __raw_i915_write32(d->i915, d->reg_set, d->val_reset);
  58 }
  59
  60 static inline void
  61 fw_domain_arm_timer(struct intel_uncore_forcewake_domain *d)
  62 {
  63         d->wake_count++;
  64         hrtimer_start_range_ns(&d->timer,
  65                                ktime_set(0, NSEC_PER_MSEC),
  66                                NSEC_PER_MSEC,
  67                                HRTIMER_MODE_REL);
  68 }
  69
  70 static inline void
  71 fw_domain_wait_ack_clear(const struct intel_uncore_forcewake_domain *d)
  72 {
  73         if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) &
  74                              FORCEWAKE_KERNEL) == 0,
  75                             FORCEWAKE_ACK_TIMEOUT_MS))
  76                 DRM_ERROR("%s: timed out waiting for forcewake ack to clear.\n",
  77                           intel_uncore_forcewake_domain_to_str(d->id));
  78 }
  79
  80 static inline void
  81 fw_domain_get(const struct intel_uncore_forcewake_domain *d)
  82 {
  83         __raw_i915_write32(d->i915, d->reg_set, d->val_set);
  84 }
  85
  86 static inline void
  87 fw_domain_wait_ack(const struct intel_uncore_forcewake_domain *d)
  88 {
  89         if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) &
  90                              FORCEWAKE_KERNEL),
  91                             FORCEWAKE_ACK_TIMEOUT_MS))
  92                 DRM_ERROR("%s: timed out waiting for forcewake ack request.\n",
  93                           intel_uncore_forcewake_domain_to_str(d->id));
  94 }
  95
  96 static inline void
  97 fw_domain_put(const struct intel_uncore_forcewake_domain *d)
  98 {
  99         __raw_i915_write32(d->i915, d->reg_set, d->val_clear);
 100 }
 101
 102 static inline void
 103 fw_domain_posting_read(const struct intel_uncore_forcewake_domain *d)
 104 {
 105         /* something from same cacheline, but not from the set register */
 106         if (i915_mmio_reg_valid(d->reg_post))
 107                 __raw_posting_read(d->i915, d->reg_post);
 108 }
 109
 110 static void
 111 fw_domains_get(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
 112 {
 113         struct intel_uncore_forcewake_domain *d;
 114
 115         for_each_fw_domain_masked(d, fw_domains, dev_priv) {
 116                 fw_domain_wait_ack_clear(d);
 117                 fw_domain_get(d);
 118         }
 119
 120         for_each_fw_domain_masked(d, fw_domains, dev_priv)
 121                 fw_domain_wait_ack(d);
 122 }
 123
 124 static void
 125 fw_domains_put(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
 126 {
 127         struct intel_uncore_forcewake_domain *d;
 128
 129         for_each_fw_domain_masked(d, fw_domains, dev_priv) {
 130                 fw_domain_put(d);
 131                 fw_domain_posting_read(d);
 132         }
 133 }
 134
 135 static void
 136 fw_domains_posting_read(struct drm_i915_private *dev_priv)
 137 {
 138         struct intel_uncore_forcewake_domain *d;
 139
 140         /* No need to do for all, just do for first found */
 141         for_each_fw_domain(d, dev_priv) {
 142                 fw_domain_posting_read(d);
 143                 break;
 144         }
 145 }
 146
 147 static void
 148 fw_domains_reset(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
 149 {
 150         struct intel_uncore_forcewake_domain *d;
 151
 152         if (dev_priv->uncore.fw_domains == 0)
 153                 return;
 154
 155         for_each_fw_domain_masked(d, fw_domains, dev_priv)
 156                 fw_domain_reset(d);
 157
 158         fw_domains_posting_read(dev_priv);
 159 }
 160
 161 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
 162 {
 163         /* w/a for a sporadic read returning 0 by waiting for the GT
 164          * thread to wake up.
 165          */
 166         if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) &
 167                                 GEN6_GT_THREAD_STATUS_CORE_MASK) == 0, 500))
 168                 DRM_ERROR("GT thread status wait timed out\n");
 169 }
 170
 171 static void fw_domains_get_with_thread_status(struct drm_i915_private *dev_priv,
 172                                               enum forcewake_domains fw_domains)
 173 {
 174         fw_domains_get(dev_priv, fw_domains);
 175
 176         /* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */
 177         __gen6_gt_wait_for_thread_c0(dev_priv);
 178 }
 179
 180 static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
 181 {
 182         u32 gtfifodbg;
 183
 184         gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG);
 185         if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg))
 186                 __raw_i915_write32(dev_priv, GTFIFODBG, gtfifodbg);
 187 }
 188
 189 static void fw_domains_put_with_fifo(struct drm_i915_private *dev_priv,
 190                                      enum forcewake_domains fw_domains)
 191 {
 192         fw_domains_put(dev_priv, fw_domains);
 193         gen6_gt_check_fifodbg(dev_priv);
 194 }
 195
 196 static inline u32 fifo_free_entries(struct drm_i915_private *dev_priv)
 197 {
 198         u32 count = __raw_i915_read32(dev_priv, GTFIFOCTL);
 199
 200         return count & GT_FIFO_FREE_ENTRIES_MASK;
 201 }
 202
 203 static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
 204 {
 205         int ret = 0;
 206
 207         /* On VLV, FIFO will be shared by both SW and HW.
 208          * So, we need to read the FREE_ENTRIES everytime */
 209         if (IS_VALLEYVIEW(dev_priv))
 210                 dev_priv->uncore.fifo_count = fifo_free_entries(dev_priv);
 211
 212         if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
 213                 int loop = 500;
 214                 u32 fifo = fifo_free_entries(dev_priv);
 215
 216                 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
 217                         udelay(10);
 218                         fifo = fifo_free_entries(dev_priv);
 219                 }
 220                 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
 221                         ++ret;
 222                 dev_priv->uncore.fifo_count = fifo;
 223         }
 224         dev_priv->uncore.fifo_count--;
 225
 226         return ret;
 227 }
 228
 229 static enum hrtimer_restart
 230 intel_uncore_fw_release_timer(struct hrtimer *timer)
 231 {
 232         struct intel_uncore_forcewake_domain *domain =
 233                container_of(timer, struct intel_uncore_forcewake_domain, timer);
 234         struct drm_i915_private *dev_priv = domain->i915;
 235         unsigned long irqflags;
 236
 237         assert_rpm_device_not_suspended(dev_priv);
 238
 239         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 240         if (WARN_ON(domain->wake_count == 0))
 241                 domain->wake_count++;
 242
 243         if (--domain->wake_count == 0) {
 244                 dev_priv->uncore.funcs.force_wake_put(dev_priv, domain->mask);
 245                 dev_priv->uncore.fw_domains_active &= ~domain->mask;
 246         }
 247
 248         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 249
 250         return HRTIMER_NORESTART;
 251 }
 252
 253 void intel_uncore_forcewake_reset(struct drm_i915_private *dev_priv,
 254                                   bool restore)
 255 {
 256         unsigned long irqflags;
 257         struct intel_uncore_forcewake_domain *domain;
 258         int retry_count = 100;
 259         enum forcewake_domains fw, active_domains;
 260
 261         /* Hold uncore.lock across reset to prevent any register access
 262          * with forcewake not set correctly. Wait until all pending
 263          * timers are run before holding.
 264          */
 265         while (1) {
 266                 active_domains = 0;
 267
 268                 for_each_fw_domain(domain, dev_priv) {
 269                         if (hrtimer_cancel(&domain->timer) == 0)
 270                                 continue;
 271
 272                         intel_uncore_fw_release_timer(&domain->timer);
 273                 }
 274
 275                 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 276
 277                 for_each_fw_domain(domain, dev_priv) {
 278                         if (hrtimer_active(&domain->timer))
 279                                 active_domains |= domain->mask;
 280                 }
 281
 282                 if (active_domains == 0)
 283                         break;
 284
 285                 if (--retry_count == 0) {
 286                         DRM_ERROR("Timed out waiting for forcewake timers to finish\n");
 287                         break;
 288                 }
 289
 290                 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 291                 cond_resched();
 292         }
 293
 294         WARN_ON(active_domains);
 295
 296         fw = dev_priv->uncore.fw_domains_active;
 297         if (fw)
 298                 dev_priv->uncore.funcs.force_wake_put(dev_priv, fw);
 299
 300         fw_domains_reset(dev_priv, FORCEWAKE_ALL);
 301
 302         if (restore) { /* If reset with a user forcewake, try to restore */
 303                 if (fw)
 304                         dev_priv->uncore.funcs.force_wake_get(dev_priv, fw);
 305
 306                 if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv))
 307                         dev_priv->uncore.fifo_count =
 308                                 fifo_free_entries(dev_priv);
 309         }
 310
 311         if (!restore)
 312                 assert_forcewakes_inactive(dev_priv);
 313
 314         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 315 }
 316
 317 static u64 gen9_edram_size(struct drm_i915_private *dev_priv)
 318 {
 319         const unsigned int ways[8] = { 4, 8, 12, 16, 16, 16, 16, 16 };
 320         const unsigned int sets[4] = { 1, 1, 2, 2 };
 321         const u32 cap = dev_priv->edram_cap;
 322
 323         return EDRAM_NUM_BANKS(cap) *
 324                 ways[EDRAM_WAYS_IDX(cap)] *
 325                 sets[EDRAM_SETS_IDX(cap)] *
 326                 1024 * 1024;
 327 }
 328
 329 u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv)
 330 {
 331         if (!HAS_EDRAM(dev_priv))
 332                 return 0;
 333
 334         /* The needed capability bits for size calculation
 335          * are not there with pre gen9 so return 128MB always.
 336          */
 337         if (INTEL_GEN(dev_priv) < 9)
 338                 return 128 * 1024 * 1024;
 339
 340         return gen9_edram_size(dev_priv);
 341 }
 342
 343 static void intel_uncore_edram_detect(struct drm_i915_private *dev_priv)
 344 {
 345         if (IS_HASWELL(dev_priv) ||
 346             IS_BROADWELL(dev_priv) ||
 347             INTEL_GEN(dev_priv) >= 9) {
 348                 dev_priv->edram_cap = __raw_i915_read32(dev_priv,
 349                                                         HSW_EDRAM_CAP);
 350
 351                 /* NB: We can't write IDICR yet because we do not have gt funcs
 352                  * set up */
 353         } else {
 354                 dev_priv->edram_cap = 0;
 355         }
 356
 357         if (HAS_EDRAM(dev_priv))
 358                 DRM_INFO("Found %lluMB of eDRAM\n",
 359                          intel_uncore_edram_size(dev_priv) / (1024 * 1024));
 360 }
 361
 362 static bool
 363 fpga_check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
 364 {
 365         u32 dbg;
 366
 367         dbg = __raw_i915_read32(dev_priv, FPGA_DBG);
 368         if (likely(!(dbg & FPGA_DBG_RM_NOCLAIM)))
 369                 return false;
 370
 371         __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
 372
 373         return true;
 374 }
 375
 376 static bool
 377 vlv_check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
 378 {
 379         u32 cer;
 380
 381         cer = __raw_i915_read32(dev_priv, CLAIM_ER);
 382         if (likely(!(cer & (CLAIM_ER_OVERFLOW | CLAIM_ER_CTR_MASK))))
 383                 return false;
 384
 385         __raw_i915_write32(dev_priv, CLAIM_ER, CLAIM_ER_CLR);
 386
 387         return true;
 388 }
 389
 390 static bool
 391 check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
 392 {
 393         if (HAS_FPGA_DBG_UNCLAIMED(dev_priv))
 394                 return fpga_check_for_unclaimed_mmio(dev_priv);
 395
 396         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 397                 return vlv_check_for_unclaimed_mmio(dev_priv);
 398
 399         return false;
 400 }
 401
 402 static void __intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,
 403                                           bool restore_forcewake)
 404 {
 405         struct intel_device_info *info = mkwrite_device_info(dev_priv);
 406
 407         /* clear out unclaimed reg detection bit */
 408         if (check_for_unclaimed_mmio(dev_priv))
 409                 DRM_DEBUG("unclaimed mmio detected on uncore init, clearing\n");
 410
 411         /* clear out old GT FIFO errors */
 412         if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv))
 413                 __raw_i915_write32(dev_priv, GTFIFODBG,
 414                                    __raw_i915_read32(dev_priv, GTFIFODBG));
 415
 416         /* WaDisableShadowRegForCpd:chv */
 417         if (IS_CHERRYVIEW(dev_priv)) {
 418                 __raw_i915_write32(dev_priv, GTFIFOCTL,
 419                                    __raw_i915_read32(dev_priv, GTFIFOCTL) |
 420                                    GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
 421                                    GT_FIFO_CTL_RC6_POLICY_STALL);
 422         }
 423
 424         /* Enable Decoupled MMIO only on BXT C stepping onwards */
 425         if (!IS_BXT_REVID(dev_priv, BXT_REVID_C0, REVID_FOREVER))
 426                 info->has_decoupled_mmio = false;
 427
 428         intel_uncore_forcewake_reset(dev_priv, restore_forcewake);
 429 }
 430
 431 void intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,
 432                                  bool restore_forcewake)
 433 {
 434         __intel_uncore_early_sanitize(dev_priv, restore_forcewake);
 435         i915_check_and_clear_faults(dev_priv);
 436 }
 437
 438 void intel_uncore_sanitize(struct drm_i915_private *dev_priv)
 439 {
 440         i915.enable_rc6 = sanitize_rc6_option(dev_priv, i915.enable_rc6);
 441
 442         /* BIOS often leaves RC6 enabled, but disable it for hw init */
 443         intel_sanitize_gt_powersave(dev_priv);
 444 }
 445
 446 static void __intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
 447                                          enum forcewake_domains fw_domains)
 448 {
 449         struct intel_uncore_forcewake_domain *domain;
 450
 451         fw_domains &= dev_priv->uncore.fw_domains;
 452
 453         for_each_fw_domain_masked(domain, fw_domains, dev_priv) {
 454                 if (domain->wake_count++)
 455                         fw_domains &= ~domain->mask;
 456         }
 457
 458         if (fw_domains) {
 459                 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
 460                 dev_priv->uncore.fw_domains_active |= fw_domains;
 461         }
 462 }
 463
 464 /**
 465  * intel_uncore_forcewake_get - grab forcewake domain references
 466  * @dev_priv: i915 device instance
 467  * @fw_domains: forcewake domains to get reference on
 468  *
 469  * This function can be used get GT's forcewake domain references.
 470  * Normal register access will handle the forcewake domains automatically.
 471  * However if some sequence requires the GT to not power down a particular
 472  * forcewake domains this function should be called at the beginning of the
 473  * sequence. And subsequently the reference should be dropped by symmetric
 474  * call to intel_unforce_forcewake_put(). Usually caller wants all the domains
 475  * to be kept awake so the @fw_domains would be then FORCEWAKE_ALL.
 476  */
 477 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
 478                                 enum forcewake_domains fw_domains)
 479 {
 480         unsigned long irqflags;
 481
 482         if (!dev_priv->uncore.funcs.force_wake_get)
 483                 return;
 484
 485         assert_rpm_wakelock_held(dev_priv);
 486
 487         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 488         __intel_uncore_forcewake_get(dev_priv, fw_domains);
 489         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 490 }
 491
 492 /**
 493  * intel_uncore_forcewake_get__locked - grab forcewake domain references
 494  * @dev_priv: i915 device instance
 495  * @fw_domains: forcewake domains to get reference on
 496  *
 497  * See intel_uncore_forcewake_get(). This variant places the onus
 498  * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
 499  */
 500 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
 501                                         enum forcewake_domains fw_domains)
 502 {
 503         assert_spin_locked(&dev_priv->uncore.lock);
 504
 505         if (!dev_priv->uncore.funcs.force_wake_get)
 506                 return;
 507
 508         __intel_uncore_forcewake_get(dev_priv, fw_domains);
 509 }
 510
 511 static void __intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
 512                                          enum forcewake_domains fw_domains)
 513 {
 514         struct intel_uncore_forcewake_domain *domain;
 515
 516         fw_domains &= dev_priv->uncore.fw_domains;
 517
 518         for_each_fw_domain_masked(domain, fw_domains, dev_priv) {
 519                 if (WARN_ON(domain->wake_count == 0))
 520                         continue;
 521
 522                 if (--domain->wake_count)
 523                         continue;
 524
 525                 fw_domain_arm_timer(domain);
 526         }
 527 }
 528
 529 /**
 530  * intel_uncore_forcewake_put - release a forcewake domain reference
 531  * @dev_priv: i915 device instance
 532  * @fw_domains: forcewake domains to put references
 533  *
 534  * This function drops the device-level forcewakes for specified
 535  * domains obtained by intel_uncore_forcewake_get().
 536  */
 537 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
 538                                 enum forcewake_domains fw_domains)
 539 {
 540         unsigned long irqflags;
 541
 542         if (!dev_priv->uncore.funcs.force_wake_put)
 543                 return;
 544
 545         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 546         __intel_uncore_forcewake_put(dev_priv, fw_domains);
 547         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 548 }
 549
 550 /**
 551  * intel_uncore_forcewake_put__locked - grab forcewake domain references
 552  * @dev_priv: i915 device instance
 553  * @fw_domains: forcewake domains to get reference on
 554  *
 555  * See intel_uncore_forcewake_put(). This variant places the onus
 556  * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
 557  */
 558 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
 559                                         enum forcewake_domains fw_domains)
 560 {
 561         assert_spin_locked(&dev_priv->uncore.lock);
 562
 563         if (!dev_priv->uncore.funcs.force_wake_put)
 564                 return;
 565
 566         __intel_uncore_forcewake_put(dev_priv, fw_domains);
 567 }
 568
 569 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv)
 570 {
 571         if (!dev_priv->uncore.funcs.force_wake_get)
 572                 return;
 573
 574         WARN_ON(dev_priv->uncore.fw_domains_active);
 575 }
 576
 577 /* We give fast paths for the really cool registers */
 578 #define NEEDS_FORCE_WAKE(reg) ((reg) < 0x40000)
 579
 580 #define __gen6_reg_read_fw_domains(offset) \
 581 ({ \
 582         enum forcewake_domains __fwd; \
 583         if (NEEDS_FORCE_WAKE(offset)) \
 584                 __fwd = FORCEWAKE_RENDER; \
 585         else \
 586                 __fwd = 0; \
 587         __fwd; \
 588 })
 589
 590 static int fw_range_cmp(u32 offset, const struct intel_forcewake_range *entry)
 591 {
 592         if (offset < entry->start)
 593                 return -1;
 594         else if (offset > entry->end)
 595                 return 1;
 596         else
 597                 return 0;
 598 }
 599
 600 /* Copied and "macroized" from lib/bsearch.c */
 601 #define BSEARCH(key, base, num, cmp) ({                                 \
 602         unsigned int start__ = 0, end__ = (num);                        \
 603         typeof(base) result__ = NULL;                                   \
 604         while (start__ < end__) {                                       \
 605                 unsigned int mid__ = start__ + (end__ - start__) / 2;   \
 606                 int ret__ = (cmp)((key), (base) + mid__);               \
 607                 if (ret__ < 0) {                                        \
 608                         end__ = mid__;                                  \
 609                 } else if (ret__ > 0) {                                 \
 610                         start__ = mid__ + 1;                            \
 611                 } else {                                                \
 612                         result__ = (base) + mid__;                      \
 613                         break;                                          \
 614                 }                                                       \
 615         }                                                               \
 616         result__;                                                       \
 617 })
 618
 619 static enum forcewake_domains
 620 find_fw_domain(struct drm_i915_private *dev_priv, u32 offset)
 621 {
 622         const struct intel_forcewake_range *entry;
 623
 624         entry = BSEARCH(offset,
 625                         dev_priv->uncore.fw_domains_table,
 626                         dev_priv->uncore.fw_domains_table_entries,
 627                         fw_range_cmp);
 628
 629         return entry ? entry->domains : 0;
 630 }
 631
 632 static void
 633 intel_fw_table_check(struct drm_i915_private *dev_priv)
 634 {
 635         const struct intel_forcewake_range *ranges;
 636         unsigned int num_ranges;
 637         s32 prev;
 638         unsigned int i;
 639
 640         if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG))
 641                 return;
 642
 643         ranges = dev_priv->uncore.fw_domains_table;
 644         if (!ranges)
 645                 return;
 646
 647         num_ranges = dev_priv->uncore.fw_domains_table_entries;
 648
 649         for (i = 0, prev = -1; i < num_ranges; i++, ranges++) {
 650                 WARN_ON_ONCE(prev >= (s32)ranges->start);
 651                 prev = ranges->start;
 652                 WARN_ON_ONCE(prev >= (s32)ranges->end);
 653                 prev = ranges->end;
 654         }
 655 }
 656
 657 #define GEN_FW_RANGE(s, e, d) \
 658         { .start = (s), .end = (e), .domains = (d) }
 659
 660 #define HAS_FWTABLE(dev_priv) \
 661         (IS_GEN9(dev_priv) || \
 662          IS_CHERRYVIEW(dev_priv) || \
 663          IS_VALLEYVIEW(dev_priv))
 664
 665 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
 666 static const struct intel_forcewake_range __vlv_fw_ranges[] = {
 667         GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER),
 668         GEN_FW_RANGE(0x5000, 0x7fff, FORCEWAKE_RENDER),
 669         GEN_FW_RANGE(0xb000, 0x11fff, FORCEWAKE_RENDER),
 670         GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
 671         GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_MEDIA),
 672         GEN_FW_RANGE(0x2e000, 0x2ffff, FORCEWAKE_RENDER),
 673         GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA),
 674 };
 675
 676 #define __fwtable_reg_read_fw_domains(offset) \
 677 ({ \
 678         enum forcewake_domains __fwd = 0; \
 679         if (NEEDS_FORCE_WAKE((offset))) \
 680                 __fwd = find_fw_domain(dev_priv, offset); \
 681         __fwd; \
 682 })
 683
 684 /* *Must* be sorted by offset! See intel_shadow_table_check(). */
 685 static const i915_reg_t gen8_shadowed_regs[] = {
 686         RING_TAIL(RENDER_RING_BASE),    /* 0x2000 (base) */
 687         GEN6_RPNSWREQ,                  /* 0xA008 */
 688         GEN6_RC_VIDEO_FREQ,             /* 0xA00C */
 689         RING_TAIL(GEN6_BSD_RING_BASE),  /* 0x12000 (base) */
 690         RING_TAIL(VEBOX_RING_BASE),     /* 0x1a000 (base) */
 691         RING_TAIL(BLT_RING_BASE),       /* 0x22000 (base) */
 692         /* TODO: Other registers are not yet used */
 693 };
 694
 695 static void intel_shadow_table_check(void)
 696 {
 697         const i915_reg_t *reg = gen8_shadowed_regs;
 698         s32 prev;
 699         u32 offset;
 700         unsigned int i;
 701
 702         if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG))
 703                 return;
 704
 705         for (i = 0, prev = -1; i < ARRAY_SIZE(gen8_shadowed_regs); i++, reg++) {
 706                 offset = i915_mmio_reg_offset(*reg);
 707                 WARN_ON_ONCE(prev >= (s32)offset);
 708                 prev = offset;
 709         }
 710 }
 711
 712 static int mmio_reg_cmp(u32 key, const i915_reg_t *reg)
 713 {
 714         u32 offset = i915_mmio_reg_offset(*reg);
 715
 716         if (key < offset)
 717                 return -1;
 718         else if (key > offset)
 719                 return 1;
 720         else
 721                 return 0;
 722 }
 723
 724 static bool is_gen8_shadowed(u32 offset)
 725 {
 726         const i915_reg_t *regs = gen8_shadowed_regs;
 727
 728         return BSEARCH(offset, regs, ARRAY_SIZE(gen8_shadowed_regs),
 729                        mmio_reg_cmp);
 730 }
 731
 732 #define __gen8_reg_write_fw_domains(offset) \
 733 ({ \
 734         enum forcewake_domains __fwd; \
 735         if (NEEDS_FORCE_WAKE(offset) && !is_gen8_shadowed(offset)) \
 736                 __fwd = FORCEWAKE_RENDER; \
 737         else \
 738                 __fwd = 0; \
 739         __fwd; \
 740 })
 741
 742 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
 743 static const struct intel_forcewake_range __chv_fw_ranges[] = {
 744         GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER),
 745         GEN_FW_RANGE(0x4000, 0x4fff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
 746         GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
 747         GEN_FW_RANGE(0x8000, 0x82ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
 748         GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
 749         GEN_FW_RANGE(0x8500, 0x85ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
 750         GEN_FW_RANGE(0x8800, 0x88ff, FORCEWAKE_MEDIA),
 751         GEN_FW_RANGE(0x9000, 0xafff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
 752         GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
 753         GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA),
 754         GEN_FW_RANGE(0xe000, 0xe7ff, FORCEWAKE_RENDER),
 755         GEN_FW_RANGE(0xf000, 0xffff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
 756         GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
 757         GEN_FW_RANGE(0x1a000, 0x1bfff, FORCEWAKE_MEDIA),
 758         GEN_FW_RANGE(0x1e800, 0x1e9ff, FORCEWAKE_MEDIA),
 759         GEN_FW_RANGE(0x30000, 0x37fff, FORCEWAKE_MEDIA),
 760 };
 761
 762 #define __fwtable_reg_write_fw_domains(offset) \
 763 ({ \
 764         enum forcewake_domains __fwd = 0; \
 765         if (NEEDS_FORCE_WAKE((offset)) && !is_gen8_shadowed(offset)) \
 766                 __fwd = find_fw_domain(dev_priv, offset); \
 767         __fwd; \
 768 })
 769
 770 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
 771 static const struct intel_forcewake_range __gen9_fw_ranges[] = {
 772         GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER),
 773         GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */
 774         GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
 775         GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER),
 776         GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
 777         GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_BLITTER),
 778         GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
 779         GEN_FW_RANGE(0x8000, 0x812f, FORCEWAKE_BLITTER),
 780         GEN_FW_RANGE(0x8130, 0x813f, FORCEWAKE_MEDIA),
 781         GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
 782         GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER),
 783         GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
 784         GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_BLITTER),
 785         GEN_FW_RANGE(0x8800, 0x89ff, FORCEWAKE_MEDIA),
 786         GEN_FW_RANGE(0x8a00, 0x8bff, FORCEWAKE_BLITTER),
 787         GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER),
 788         GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_BLITTER),
 789         GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
 790         GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_BLITTER),
 791         GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
 792         GEN_FW_RANGE(0xb480, 0xcfff, FORCEWAKE_BLITTER),
 793         GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA),
 794         GEN_FW_RANGE(0xd800, 0xdfff, FORCEWAKE_BLITTER),
 795         GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER),
 796         GEN_FW_RANGE(0xe900, 0x11fff, FORCEWAKE_BLITTER),
 797         GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
 798         GEN_FW_RANGE(0x14000, 0x19fff, FORCEWAKE_BLITTER),
 799         GEN_FW_RANGE(0x1a000, 0x1e9ff, FORCEWAKE_MEDIA),
 800         GEN_FW_RANGE(0x1ea00, 0x243ff, FORCEWAKE_BLITTER),
 801         GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER),
 802         GEN_FW_RANGE(0x24800, 0x2ffff, FORCEWAKE_BLITTER),
 803         GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA),
 804 };
 805
 806 static void
 807 ilk_dummy_write(struct drm_i915_private *dev_priv)
 808 {
 809         /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
 810          * the chip from rc6 before touching it for real. MI_MODE is masked,
 811          * hence harmless to write 0 into. */
 812         __raw_i915_write32(dev_priv, MI_MODE, 0);
 813 }
 814
 815 static void
 816 __unclaimed_reg_debug(struct drm_i915_private *dev_priv,
 817                       const i915_reg_t reg,
 818                       const bool read,
 819                       const bool before)
 820 {
 821         if (WARN(check_for_unclaimed_mmio(dev_priv) && !before,
 822                  "Unclaimed %s register 0x%x\n",
 823                  read ? "read from" : "write to",
 824                  i915_mmio_reg_offset(reg)))
 825                 i915.mmio_debug--; /* Only report the first N failures */
 826 }
 827
 828 static inline void
 829 unclaimed_reg_debug(struct drm_i915_private *dev_priv,
 830                     const i915_reg_t reg,
 831                     const bool read,
 832                     const bool before)
 833 {
 834         if (likely(!i915.mmio_debug))
 835                 return;
 836
 837         __unclaimed_reg_debug(dev_priv, reg, read, before);
 838 }
 839
 840 static const enum decoupled_power_domain fw2dpd_domain[] = {
 841         GEN9_DECOUPLED_PD_RENDER,
 842         GEN9_DECOUPLED_PD_BLITTER,
 843         GEN9_DECOUPLED_PD_ALL,
 844         GEN9_DECOUPLED_PD_MEDIA,
 845         GEN9_DECOUPLED_PD_ALL,
 846         GEN9_DECOUPLED_PD_ALL,
 847         GEN9_DECOUPLED_PD_ALL
 848 };
 849
 850 /*
 851  * Decoupled MMIO access for only 1 DWORD
 852  */
 853 static void __gen9_decoupled_mmio_access(struct drm_i915_private *dev_priv,
 854                                          u32 reg,
 855                                          enum forcewake_domains fw_domain,
 856                                          enum decoupled_ops operation)
 857 {
 858         enum decoupled_power_domain dp_domain;
 859         u32 ctrl_reg_data = 0;
 860
 861         dp_domain = fw2dpd_domain[fw_domain - 1];
 862
 863         ctrl_reg_data |= reg;
 864         ctrl_reg_data |= (operation << GEN9_DECOUPLED_OP_SHIFT);
 865         ctrl_reg_data |= (dp_domain << GEN9_DECOUPLED_PD_SHIFT);
 866         ctrl_reg_data |= GEN9_DECOUPLED_DW1_GO;
 867         __raw_i915_write32(dev_priv, GEN9_DECOUPLED_REG0_DW1, ctrl_reg_data);
 868
 869         if (wait_for_atomic((__raw_i915_read32(dev_priv,
 870                             GEN9_DECOUPLED_REG0_DW1) &
 871                             GEN9_DECOUPLED_DW1_GO) == 0,
 872                             FORCEWAKE_ACK_TIMEOUT_MS))
 873                 DRM_ERROR("Decoupled MMIO wait timed out\n");
 874 }
 875
 876 static inline u32
 877 __gen9_decoupled_mmio_read32(struct drm_i915_private *dev_priv,
 878                              u32 reg,
 879                              enum forcewake_domains fw_domain)
 880 {
 881         __gen9_decoupled_mmio_access(dev_priv, reg, fw_domain,
 882                                      GEN9_DECOUPLED_OP_READ);
 883
 884         return __raw_i915_read32(dev_priv, GEN9_DECOUPLED_REG0_DW0);
 885 }
 886
 887 static inline void
 888 __gen9_decoupled_mmio_write(struct drm_i915_private *dev_priv,
 889                             u32 reg, u32 data,
 890                             enum forcewake_domains fw_domain)
 891 {
 892
 893         __raw_i915_write32(dev_priv, GEN9_DECOUPLED_REG0_DW0, data);
 894
 895         __gen9_decoupled_mmio_access(dev_priv, reg, fw_domain,
 896                                      GEN9_DECOUPLED_OP_WRITE);
 897 }
 898
 899
 900 #define GEN2_READ_HEADER(x) \
 901         u##x val = 0; \
 902         assert_rpm_wakelock_held(dev_priv);
 903
 904 #define GEN2_READ_FOOTER \
 905         trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
 906         return val
 907
 908 #define __gen2_read(x) \
 909 static u##x \
 910 gen2_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
 911         GEN2_READ_HEADER(x); \
 912         val = __raw_i915_read##x(dev_priv, reg); \
 913         GEN2_READ_FOOTER; \
 914 }
 915
 916 #define __gen5_read(x) \
 917 static u##x \
 918 gen5_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
 919         GEN2_READ_HEADER(x); \
 920         ilk_dummy_write(dev_priv); \
 921         val = __raw_i915_read##x(dev_priv, reg); \
 922         GEN2_READ_FOOTER; \
 923 }
 924
 925 __gen5_read(8)
 926 __gen5_read(16)
 927 __gen5_read(32)
 928 __gen5_read(64)
 929 __gen2_read(8)
 930 __gen2_read(16)
 931 __gen2_read(32)
 932 __gen2_read(64)
 933
 934 #undef __gen5_read
 935 #undef __gen2_read
 936
 937 #undef GEN2_READ_FOOTER
 938 #undef GEN2_READ_HEADER
 939
 940 #define GEN6_READ_HEADER(x) \
 941         u32 offset = i915_mmio_reg_offset(reg); \
 942         unsigned long irqflags; \
 943         u##x val = 0; \
 944         assert_rpm_wakelock_held(dev_priv); \
 945         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \
 946         unclaimed_reg_debug(dev_priv, reg, true, true)
 947
 948 #define GEN6_READ_FOOTER \
 949         unclaimed_reg_debug(dev_priv, reg, true, false); \
 950         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
 951         trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
 952         return val
 953
 954 static noinline void ___force_wake_auto(struct drm_i915_private *dev_priv,
 955                                         enum forcewake_domains fw_domains)
 956 {
 957         struct intel_uncore_forcewake_domain *domain;
 958
 959         for_each_fw_domain_masked(domain, fw_domains, dev_priv)
 960                 fw_domain_arm_timer(domain);
 961
 962         dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
 963         dev_priv->uncore.fw_domains_active |= fw_domains;
 964 }
 965
 966 static inline void __force_wake_auto(struct drm_i915_private *dev_priv,
 967                                      enum forcewake_domains fw_domains)
 968 {
 969         if (WARN_ON(!fw_domains))
 970                 return;
 971
 972         /* Turn on all requested but inactive supported forcewake domains. */
 973         fw_domains &= dev_priv->uncore.fw_domains;
 974         fw_domains &= ~dev_priv->uncore.fw_domains_active;
 975
 976         if (fw_domains)
 977                 ___force_wake_auto(dev_priv, fw_domains);
 978 }
 979
 980 #define __gen6_read(x) \
 981 static u##x \
 982 gen6_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
 983         enum forcewake_domains fw_engine; \
 984         GEN6_READ_HEADER(x); \
 985         fw_engine = __gen6_reg_read_fw_domains(offset); \
 986         if (fw_engine) \
 987                 __force_wake_auto(dev_priv, fw_engine); \
 988         val = __raw_i915_read##x(dev_priv, reg); \
 989         GEN6_READ_FOOTER; \
 990 }
 991
 992 #define __fwtable_read(x) \
 993 static u##x \
 994 fwtable_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
 995         enum forcewake_domains fw_engine; \
 996         GEN6_READ_HEADER(x); \
 997         fw_engine = __fwtable_reg_read_fw_domains(offset); \
 998         if (fw_engine) \
 999                 __force_wake_auto(dev_priv, fw_engine); \
1000         val = __raw_i915_read##x(dev_priv, reg); \
1001         GEN6_READ_FOOTER; \
1002 }
1003
1004 #define __gen9_decoupled_read(x) \
1005 static u##x \
1006 gen9_decoupled_read##x(struct drm_i915_private *dev_priv, \
1007                        i915_reg_t reg, bool trace) { \
1008         enum forcewake_domains fw_engine; \
1009         GEN6_READ_HEADER(x); \
1010         fw_engine = __fwtable_reg_read_fw_domains(offset); \
1011         if (fw_engine & ~dev_priv->uncore.fw_domains_active) { \
1012                 unsigned i; \
1013                 u32 *ptr_data = (u32 *) &val; \
1014                 for (i = 0; i < x/32; i++, offset += sizeof(u32), ptr_data++) \
1015                         *ptr_data = __gen9_decoupled_mmio_read32(dev_priv, \
1016                                                                  offset, \
1017                                                                  fw_engine); \
1018         } else { \
1019                 val = __raw_i915_read##x(dev_priv, reg); \
1020         } \
1021         GEN6_READ_FOOTER; \
1022 }
1023
1024 __gen9_decoupled_read(32)
1025 __gen9_decoupled_read(64)
1026 __fwtable_read(8)
1027 __fwtable_read(16)
1028 __fwtable_read(32)
1029 __fwtable_read(64)
1030 __gen6_read(8)
1031 __gen6_read(16)
1032 __gen6_read(32)
1033 __gen6_read(64)
1034
1035 #undef __fwtable_read
1036 #undef __gen6_read
1037 #undef GEN6_READ_FOOTER
1038 #undef GEN6_READ_HEADER
1039
1040 #define VGPU_READ_HEADER(x) \
1041         unsigned long irqflags; \
1042         u##x val = 0; \
1043         assert_rpm_device_not_suspended(dev_priv); \
1044         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
1045
1046 #define VGPU_READ_FOOTER \
1047         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
1048         trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
1049         return val
1050
1051 #define __vgpu_read(x) \
1052 static u##x \
1053 vgpu_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
1054         VGPU_READ_HEADER(x); \
1055         val = __raw_i915_read##x(dev_priv, reg); \
1056         VGPU_READ_FOOTER; \
1057 }
1058
1059 __vgpu_read(8)
1060 __vgpu_read(16)
1061 __vgpu_read(32)
1062 __vgpu_read(64)
1063
1064 #undef __vgpu_read
1065 #undef VGPU_READ_FOOTER
1066 #undef VGPU_READ_HEADER
1067
1068 #define GEN2_WRITE_HEADER \
1069         trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
1070         assert_rpm_wakelock_held(dev_priv); \
1071
1072 #define GEN2_WRITE_FOOTER
1073
1074 #define __gen2_write(x) \
1075 static void \
1076 gen2_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1077         GEN2_WRITE_HEADER; \
1078         __raw_i915_write##x(dev_priv, reg, val); \
1079         GEN2_WRITE_FOOTER; \
1080 }
1081
1082 #define __gen5_write(x) \
1083 static void \
1084 gen5_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1085         GEN2_WRITE_HEADER; \
1086         ilk_dummy_write(dev_priv); \
1087         __raw_i915_write##x(dev_priv, reg, val); \
1088         GEN2_WRITE_FOOTER; \
1089 }
1090
1091 __gen5_write(8)
1092 __gen5_write(16)
1093 __gen5_write(32)
1094 __gen2_write(8)
1095 __gen2_write(16)
1096 __gen2_write(32)
1097
1098 #undef __gen5_write
1099 #undef __gen2_write
1100
1101 #undef GEN2_WRITE_FOOTER
1102 #undef GEN2_WRITE_HEADER
1103
1104 #define GEN6_WRITE_HEADER \
1105         u32 offset = i915_mmio_reg_offset(reg); \
1106         unsigned long irqflags; \
1107         trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
1108         assert_rpm_wakelock_held(dev_priv); \
1109         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \
1110         unclaimed_reg_debug(dev_priv, reg, false, true)
1111
1112 #define GEN6_WRITE_FOOTER \
1113         unclaimed_reg_debug(dev_priv, reg, false, false); \
1114         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
1115
1116 #define __gen6_write(x) \
1117 static void \
1118 gen6_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1119         u32 __fifo_ret = 0; \
1120         GEN6_WRITE_HEADER; \
1121         if (NEEDS_FORCE_WAKE(offset)) { \
1122                 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
1123         } \
1124         __raw_i915_write##x(dev_priv, reg, val); \
1125         if (unlikely(__fifo_ret)) { \
1126                 gen6_gt_check_fifodbg(dev_priv); \
1127         } \
1128         GEN6_WRITE_FOOTER; \
1129 }
1130
1131 #define __gen8_write(x) \
1132 static void \
1133 gen8_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1134         enum forcewake_domains fw_engine; \
1135         GEN6_WRITE_HEADER; \
1136         fw_engine = __gen8_reg_write_fw_domains(offset); \
1137         if (fw_engine) \
1138                 __force_wake_auto(dev_priv, fw_engine); \
1139         __raw_i915_write##x(dev_priv, reg, val); \
1140         GEN6_WRITE_FOOTER; \
1141 }
1142
1143 #define __fwtable_write(x) \
1144 static void \
1145 fwtable_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1146         enum forcewake_domains fw_engine; \
1147         GEN6_WRITE_HEADER; \
1148         fw_engine = __fwtable_reg_write_fw_domains(offset); \
1149         if (fw_engine) \
1150                 __force_wake_auto(dev_priv, fw_engine); \
1151         __raw_i915_write##x(dev_priv, reg, val); \
1152         GEN6_WRITE_FOOTER; \
1153 }
1154
1155 #define __gen9_decoupled_write(x) \
1156 static void \
1157 gen9_decoupled_write##x(struct drm_i915_private *dev_priv, \
1158                         i915_reg_t reg, u##x val, \
1159                 bool trace) { \
1160         enum forcewake_domains fw_engine; \
1161         GEN6_WRITE_HEADER; \
1162         fw_engine = __fwtable_reg_write_fw_domains(offset); \
1163         if (fw_engine & ~dev_priv->uncore.fw_domains_active) \
1164                 __gen9_decoupled_mmio_write(dev_priv, \
1165                                             offset, \
1166                                             val, \
1167                                             fw_engine); \
1168         else \
1169                 __raw_i915_write##x(dev_priv, reg, val); \
1170         GEN6_WRITE_FOOTER; \
1171 }
1172
1173 __gen9_decoupled_write(32)
1174 __fwtable_write(8)
1175 __fwtable_write(16)
1176 __fwtable_write(32)
1177 __gen8_write(8)
1178 __gen8_write(16)
1179 __gen8_write(32)
1180 __gen6_write(8)
1181 __gen6_write(16)
1182 __gen6_write(32)
1183
1184 #undef __fwtable_write
1185 #undef __gen8_write
1186 #undef __gen6_write
1187 #undef GEN6_WRITE_FOOTER
1188 #undef GEN6_WRITE_HEADER
1189
1190 #define VGPU_WRITE_HEADER \
1191         unsigned long irqflags; \
1192         trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
1193         assert_rpm_device_not_suspended(dev_priv); \
1194         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
1195
1196 #define VGPU_WRITE_FOOTER \
1197         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
1198
1199 #define __vgpu_write(x) \
1200 static void vgpu_write##x(struct drm_i915_private *dev_priv, \
1201                           i915_reg_t reg, u##x val, bool trace) { \
1202         VGPU_WRITE_HEADER; \
1203         __raw_i915_write##x(dev_priv, reg, val); \
1204         VGPU_WRITE_FOOTER; \
1205 }
1206
1207 __vgpu_write(8)
1208 __vgpu_write(16)
1209 __vgpu_write(32)
1210
1211 #undef __vgpu_write
1212 #undef VGPU_WRITE_FOOTER
1213 #undef VGPU_WRITE_HEADER
1214
1215 #define ASSIGN_WRITE_MMIO_VFUNCS(x) \
1216 do { \
1217         dev_priv->uncore.funcs.mmio_writeb = x##_write8; \
1218         dev_priv->uncore.funcs.mmio_writew = x##_write16; \
1219         dev_priv->uncore.funcs.mmio_writel = x##_write32; \
1220 } while (0)
1221
1222 #define ASSIGN_READ_MMIO_VFUNCS(x) \
1223 do { \
1224         dev_priv->uncore.funcs.mmio_readb = x##_read8; \
1225         dev_priv->uncore.funcs.mmio_readw = x##_read16; \
1226         dev_priv->uncore.funcs.mmio_readl = x##_read32; \
1227         dev_priv->uncore.funcs.mmio_readq = x##_read64; \
1228 } while (0)
1229
1230
1231 static void fw_domain_init(struct drm_i915_private *dev_priv,
1232                            enum forcewake_domain_id domain_id,
1233                            i915_reg_t reg_set,
1234                            i915_reg_t reg_ack)
1235 {
1236         struct intel_uncore_forcewake_domain *d;
1237
1238         if (WARN_ON(domain_id >= FW_DOMAIN_ID_COUNT))
1239                 return;
1240
1241         d = &dev_priv->uncore.fw_domain[domain_id];
1242
1243         WARN_ON(d->wake_count);
1244
1245         d->wake_count = 0;
1246         d->reg_set = reg_set;
1247         d->reg_ack = reg_ack;
1248
1249         if (IS_GEN6(dev_priv)) {
1250                 d->val_reset = 0;
1251                 d->val_set = FORCEWAKE_KERNEL;
1252                 d->val_clear = 0;
1253         } else {
1254                 /* WaRsClearFWBitsAtReset:bdw,skl */
1255                 d->val_reset = _MASKED_BIT_DISABLE(0xffff);
1256                 d->val_set = _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL);
1257                 d->val_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL);
1258         }
1259
1260         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1261                 d->reg_post = FORCEWAKE_ACK_VLV;
1262         else if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv) || IS_GEN8(dev_priv))
1263                 d->reg_post = ECOBUS;
1264
1265         d->i915 = dev_priv;
1266         d->id = domain_id;
1267
1268         BUILD_BUG_ON(FORCEWAKE_RENDER != (1 << FW_DOMAIN_ID_RENDER));
1269         BUILD_BUG_ON(FORCEWAKE_BLITTER != (1 << FW_DOMAIN_ID_BLITTER));
1270         BUILD_BUG_ON(FORCEWAKE_MEDIA != (1 << FW_DOMAIN_ID_MEDIA));
1271
1272         d->mask = 1 << domain_id;
1273
1274         hrtimer_init(&d->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1275         d->timer.function = intel_uncore_fw_release_timer;
1276
1277         dev_priv->uncore.fw_domains |= (1 << domain_id);
1278
1279         fw_domain_reset(d);
1280 }
1281
1282 static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv)
1283 {
1284         if (INTEL_INFO(dev_priv)->gen <= 5)
1285                 return;
1286
1287         if (IS_GEN9(dev_priv)) {
1288                 dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
1289                 dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1290                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1291                                FORCEWAKE_RENDER_GEN9,
1292                                FORCEWAKE_ACK_RENDER_GEN9);
1293                 fw_domain_init(dev_priv, FW_DOMAIN_ID_BLITTER,
1294                                FORCEWAKE_BLITTER_GEN9,
1295                                FORCEWAKE_ACK_BLITTER_GEN9);
1296                 fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
1297                                FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9);
1298         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1299                 dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
1300                 if (!IS_CHERRYVIEW(dev_priv))
1301                         dev_priv->uncore.funcs.force_wake_put =
1302                                 fw_domains_put_with_fifo;
1303                 else
1304                         dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1305                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1306                                FORCEWAKE_VLV, FORCEWAKE_ACK_VLV);
1307                 fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
1308                                FORCEWAKE_MEDIA_VLV, FORCEWAKE_ACK_MEDIA_VLV);
1309         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1310                 dev_priv->uncore.funcs.force_wake_get =
1311                         fw_domains_get_with_thread_status;
1312                 if (IS_HASWELL(dev_priv))
1313                         dev_priv->uncore.funcs.force_wake_put =
1314                                 fw_domains_put_with_fifo;
1315                 else
1316                         dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1317                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1318                                FORCEWAKE_MT, FORCEWAKE_ACK_HSW);
1319         } else if (IS_IVYBRIDGE(dev_priv)) {
1320                 u32 ecobus;
1321
1322                 /* IVB configs may use multi-threaded forcewake */
1323
1324                 /* A small trick here - if the bios hasn't configured
1325                  * MT forcewake, and if the device is in RC6, then
1326                  * force_wake_mt_get will not wake the device and the
1327                  * ECOBUS read will return zero. Which will be
1328                  * (correctly) interpreted by the test below as MT
1329                  * forcewake being disabled.
1330                  */
1331                 dev_priv->uncore.funcs.force_wake_get =
1332                         fw_domains_get_with_thread_status;
1333                 dev_priv->uncore.funcs.force_wake_put =
1334                         fw_domains_put_with_fifo;
1335
1336                 /* We need to init first for ECOBUS access and then
1337                  * determine later if we want to reinit, in case of MT access is
1338                  * not working. In this stage we don't know which flavour this
1339                  * ivb is, so it is better to reset also the gen6 fw registers
1340                  * before the ecobus check.
1341                  */
1342
1343                 __raw_i915_write32(dev_priv, FORCEWAKE, 0);
1344                 __raw_posting_read(dev_priv, ECOBUS);
1345
1346                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1347                                FORCEWAKE_MT, FORCEWAKE_MT_ACK);
1348
1349                 spin_lock_irq(&dev_priv->uncore.lock);
1350                 fw_domains_get_with_thread_status(dev_priv, FORCEWAKE_ALL);
1351                 ecobus = __raw_i915_read32(dev_priv, ECOBUS);
1352                 fw_domains_put_with_fifo(dev_priv, FORCEWAKE_ALL);
1353                 spin_unlock_irq(&dev_priv->uncore.lock);
1354
1355                 if (!(ecobus & FORCEWAKE_MT_ENABLE)) {
1356                         DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n");
1357                         DRM_INFO("when using vblank-synced partial screen updates.\n");
1358                         fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1359                                        FORCEWAKE, FORCEWAKE_ACK);
1360                 }
1361         } else if (IS_GEN6(dev_priv)) {
1362                 dev_priv->uncore.funcs.force_wake_get =
1363                         fw_domains_get_with_thread_status;
1364                 dev_priv->uncore.funcs.force_wake_put =
1365                         fw_domains_put_with_fifo;
1366                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1367                                FORCEWAKE, FORCEWAKE_ACK);
1368         }
1369
1370         /* All future platforms are expected to require complex power gating */
1371         WARN_ON(dev_priv->uncore.fw_domains == 0);
1372 }
1373
1374 #define ASSIGN_FW_DOMAINS_TABLE(d) \
1375 { \
1376         dev_priv->uncore.fw_domains_table = \
1377                         (struct intel_forcewake_range *)(d); \
1378         dev_priv->uncore.fw_domains_table_entries = ARRAY_SIZE((d)); \
1379 }
1380
1381 void intel_uncore_init(struct drm_i915_private *dev_priv)
1382 {
1383         i915_check_vgpu(dev_priv);
1384
1385         intel_uncore_edram_detect(dev_priv);
1386         intel_uncore_fw_domains_init(dev_priv);
1387         __intel_uncore_early_sanitize(dev_priv, false);
1388
1389         dev_priv->uncore.unclaimed_mmio_check = 1;
1390
1391         switch (INTEL_INFO(dev_priv)->gen) {
1392         default:
1393         case 9:
1394                 ASSIGN_FW_DOMAINS_TABLE(__gen9_fw_ranges);
1395                 ASSIGN_WRITE_MMIO_VFUNCS(fwtable);
1396                 ASSIGN_READ_MMIO_VFUNCS(fwtable);
1397                 if (HAS_DECOUPLED_MMIO(dev_priv)) {
1398                         dev_priv->uncore.funcs.mmio_readl =
1399                                                 gen9_decoupled_read32;
1400                         dev_priv->uncore.funcs.mmio_readq =
1401                                                 gen9_decoupled_read64;
1402                         dev_priv->uncore.funcs.mmio_writel =
1403                                                 gen9_decoupled_write32;
1404                 }
1405                 break;
1406         case 8:
1407                 if (IS_CHERRYVIEW(dev_priv)) {
1408                         ASSIGN_FW_DOMAINS_TABLE(__chv_fw_ranges);
1409                         ASSIGN_WRITE_MMIO_VFUNCS(fwtable);
1410                         ASSIGN_READ_MMIO_VFUNCS(fwtable);
1411
1412                 } else {
1413                         ASSIGN_WRITE_MMIO_VFUNCS(gen8);
1414                         ASSIGN_READ_MMIO_VFUNCS(gen6);
1415                 }
1416                 break;
1417         case 7:
1418         case 6:
1419                 ASSIGN_WRITE_MMIO_VFUNCS(gen6);
1420
1421                 if (IS_VALLEYVIEW(dev_priv)) {
1422                         ASSIGN_FW_DOMAINS_TABLE(__vlv_fw_ranges);
1423                         ASSIGN_READ_MMIO_VFUNCS(fwtable);
1424                 } else {
1425                         ASSIGN_READ_MMIO_VFUNCS(gen6);
1426                 }
1427                 break;
1428         case 5:
1429                 ASSIGN_WRITE_MMIO_VFUNCS(gen5);
1430                 ASSIGN_READ_MMIO_VFUNCS(gen5);
1431                 break;
1432         case 4:
1433         case 3:
1434         case 2:
1435                 ASSIGN_WRITE_MMIO_VFUNCS(gen2);
1436                 ASSIGN_READ_MMIO_VFUNCS(gen2);
1437                 break;
1438         }
1439
1440         intel_fw_table_check(dev_priv);
1441         if (INTEL_GEN(dev_priv) >= 8)
1442                 intel_shadow_table_check();
1443
1444         if (intel_vgpu_active(dev_priv)) {
1445                 ASSIGN_WRITE_MMIO_VFUNCS(vgpu);
1446                 ASSIGN_READ_MMIO_VFUNCS(vgpu);
1447         }
1448
1449         i915_check_and_clear_faults(dev_priv);
1450 }
1451 #undef ASSIGN_WRITE_MMIO_VFUNCS
1452 #undef ASSIGN_READ_MMIO_VFUNCS
1453
1454 void intel_uncore_fini(struct drm_i915_private *dev_priv)
1455 {
1456         /* Paranoia: make sure we have disabled everything before we exit. */
1457         intel_uncore_sanitize(dev_priv);
1458         intel_uncore_forcewake_reset(dev_priv, false);
1459 }
1460
1461 #define GEN_RANGE(l, h) GENMASK((h) - 1, (l) - 1)
1462
1463 static const struct register_whitelist {
1464         i915_reg_t offset_ldw, offset_udw;
1465         uint32_t size;
1466         /* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
1467         uint32_t gen_bitmask;
1468 } whitelist[] = {
1469         { .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
1470           .offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
1471           .size = 8, .gen_bitmask = GEN_RANGE(4, 9) },
1472 };
1473
1474 int i915_reg_read_ioctl(struct drm_device *dev,
1475                         void *data, struct drm_file *file)
1476 {
1477         struct drm_i915_private *dev_priv = to_i915(dev);
1478         struct drm_i915_reg_read *reg = data;
1479         struct register_whitelist const *entry = whitelist;
1480         unsigned size;
1481         i915_reg_t offset_ldw, offset_udw;
1482         int i, ret = 0;
1483
1484         for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
1485                 if (i915_mmio_reg_offset(entry->offset_ldw) == (reg->offset & -entry->size) &&
1486                     (INTEL_INFO(dev_priv)->gen_mask & entry->gen_bitmask))
1487                         break;
1488         }
1489
1490         if (i == ARRAY_SIZE(whitelist))
1491                 return -EINVAL;
1492
1493         /* We use the low bits to encode extra flags as the register should
1494          * be naturally aligned (and those that are not so aligned merely
1495          * limit the available flags for that register).
1496          */
1497         offset_ldw = entry->offset_ldw;
1498         offset_udw = entry->offset_udw;
1499         size = entry->size;
1500         size |= reg->offset ^ i915_mmio_reg_offset(offset_ldw);
1501
1502         intel_runtime_pm_get(dev_priv);
1503
1504         switch (size) {
1505         case 8 | 1:
1506                 reg->val = I915_READ64_2x32(offset_ldw, offset_udw);
1507                 break;
1508         case 8:
1509                 reg->val = I915_READ64(offset_ldw);
1510                 break;
1511         case 4:
1512                 reg->val = I915_READ(offset_ldw);
1513                 break;
1514         case 2:
1515                 reg->val = I915_READ16(offset_ldw);
1516                 break;
1517         case 1:
1518                 reg->val = I915_READ8(offset_ldw);
1519                 break;
1520         default:
1521                 ret = -EINVAL;
1522                 goto out;
1523         }
1524
1525 out:
1526         intel_runtime_pm_put(dev_priv);
1527         return ret;
1528 }
1529
1530 static int i915_reset_complete(struct pci_dev *pdev)
1531 {
1532         u8 gdrst;
1533         pci_read_config_byte(pdev, I915_GDRST, &gdrst);
1534         return (gdrst & GRDOM_RESET_STATUS) == 0;
1535 }
1536
1537 static int i915_do_reset(struct drm_i915_private *dev_priv, unsigned engine_mask)
1538 {
1539         struct pci_dev *pdev = dev_priv->drm.pdev;
1540
1541         /* assert reset for at least 20 usec */
1542         pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE);
1543         udelay(20);
1544         pci_write_config_byte(pdev, I915_GDRST, 0);
1545
1546         return wait_for(i915_reset_complete(pdev), 500);
1547 }
1548
1549 static int g4x_reset_complete(struct pci_dev *pdev)
1550 {
1551         u8 gdrst;
1552         pci_read_config_byte(pdev, I915_GDRST, &gdrst);
1553         return (gdrst & GRDOM_RESET_ENABLE) == 0;
1554 }
1555
1556 static int g33_do_reset(struct drm_i915_private *dev_priv, unsigned engine_mask)
1557 {
1558         struct pci_dev *pdev = dev_priv->drm.pdev;
1559         pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE);
1560         return wait_for(g4x_reset_complete(pdev), 500);
1561 }
1562
1563 static int g4x_do_reset(struct drm_i915_private *dev_priv, unsigned engine_mask)
1564 {
1565         struct pci_dev *pdev = dev_priv->drm.pdev;
1566         int ret;
1567
1568         pci_write_config_byte(pdev, I915_GDRST,
1569                               GRDOM_RENDER | GRDOM_RESET_ENABLE);
1570         ret =  wait_for(g4x_reset_complete(pdev), 500);
1571         if (ret)
1572                 return ret;
1573
1574         /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1575         I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE);
1576         POSTING_READ(VDECCLK_GATE_D);
1577
1578         pci_write_config_byte(pdev, I915_GDRST,
1579                               GRDOM_MEDIA | GRDOM_RESET_ENABLE);
1580         ret =  wait_for(g4x_reset_complete(pdev), 500);
1581         if (ret)
1582                 return ret;
1583
1584         /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1585         I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE);
1586         POSTING_READ(VDECCLK_GATE_D);
1587
1588         pci_write_config_byte(pdev, I915_GDRST, 0);
1589
1590         return 0;
1591 }
1592
1593 static int ironlake_do_reset(struct drm_i915_private *dev_priv,
1594                              unsigned engine_mask)
1595 {
1596         int ret;
1597
1598         I915_WRITE(ILK_GDSR,
1599                    ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
1600         ret = intel_wait_for_register(dev_priv,
1601                                       ILK_GDSR, ILK_GRDOM_RESET_ENABLE, 0,
1602                                       500);
1603         if (ret)
1604                 return ret;
1605
1606         I915_WRITE(ILK_GDSR,
1607                    ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
1608         ret = intel_wait_for_register(dev_priv,
1609                                       ILK_GDSR, ILK_GRDOM_RESET_ENABLE, 0,
1610                                       500);
1611         if (ret)
1612                 return ret;
1613
1614         I915_WRITE(ILK_GDSR, 0);
1615
1616         return 0;
1617 }
1618
1619 /* Reset the hardware domains (GENX_GRDOM_*) specified by mask */
1620 static int gen6_hw_domain_reset(struct drm_i915_private *dev_priv,
1621                                 u32 hw_domain_mask)
1622 {
1623         /* GEN6_GDRST is not in the gt power well, no need to check
1624          * for fifo space for the write or forcewake the chip for
1625          * the read
1626          */
1627         __raw_i915_write32(dev_priv, GEN6_GDRST, hw_domain_mask);
1628
1629         /* Spin waiting for the device to ack the reset requests */
1630         return intel_wait_for_register_fw(dev_priv,
1631                                           GEN6_GDRST, hw_domain_mask, 0,
1632                                           500);
1633 }
1634
1635 /**
1636  * gen6_reset_engines - reset individual engines
1637  * @dev_priv: i915 device
1638  * @engine_mask: mask of intel_ring_flag() engines or ALL_ENGINES for full reset
1639  *
1640  * This function will reset the individual engines that are set in engine_mask.
1641  * If you provide ALL_ENGINES as mask, full global domain reset will be issued.
1642  *
1643  * Note: It is responsibility of the caller to handle the difference between
1644  * asking full domain reset versus reset for all available individual engines.
1645  *
1646  * Returns 0 on success, nonzero on error.
1647  */
1648 static int gen6_reset_engines(struct drm_i915_private *dev_priv,
1649                               unsigned engine_mask)
1650 {
1651         struct intel_engine_cs *engine;
1652         const u32 hw_engine_mask[I915_NUM_ENGINES] = {
1653                 [RCS] = GEN6_GRDOM_RENDER,
1654                 [BCS] = GEN6_GRDOM_BLT,
1655                 [VCS] = GEN6_GRDOM_MEDIA,
1656                 [VCS2] = GEN8_GRDOM_MEDIA2,
1657                 [VECS] = GEN6_GRDOM_VECS,
1658         };
1659         u32 hw_mask;
1660         int ret;
1661
1662         if (engine_mask == ALL_ENGINES) {
1663                 hw_mask = GEN6_GRDOM_FULL;
1664         } else {
1665                 unsigned int tmp;
1666
1667                 hw_mask = 0;
1668                 for_each_engine_masked(engine, dev_priv, engine_mask, tmp)
1669                         hw_mask |= hw_engine_mask[engine->id];
1670         }
1671
1672         ret = gen6_hw_domain_reset(dev_priv, hw_mask);
1673
1674         intel_uncore_forcewake_reset(dev_priv, true);
1675
1676         return ret;
1677 }
1678
1679 /**
1680  * intel_wait_for_register_fw - wait until register matches expected state
1681  * @dev_priv: the i915 device
1682  * @reg: the register to read
1683  * @mask: mask to apply to register value
1684  * @value: expected value
1685  * @timeout_ms: timeout in millisecond
1686  *
1687  * This routine waits until the target register @reg contains the expected
1688  * @value after applying the @mask, i.e. it waits until ::
1689  *
1690  *     (I915_READ_FW(reg) & mask) == value
1691  *
1692  * Otherwise, the wait will timeout after @timeout_ms milliseconds.
1693  *
1694  * Note that this routine assumes the caller holds forcewake asserted, it is
1695  * not suitable for very long waits. See intel_wait_for_register() if you
1696  * wish to wait without holding forcewake for the duration (i.e. you expect
1697  * the wait to be slow).
1698  *
1699  * Returns 0 if the register matches the desired condition, or -ETIMEOUT.
1700  */
1701 int intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
1702                                i915_reg_t reg,
1703                                const u32 mask,
1704                                const u32 value,
1705                                const unsigned long timeout_ms)
1706 {
1707 #define done ((I915_READ_FW(reg) & mask) == value)
1708         int ret = wait_for_us(done, 2);
1709         if (ret)
1710                 ret = wait_for(done, timeout_ms);
1711         return ret;
1712 #undef done
1713 }
1714
1715 /**
1716  * intel_wait_for_register - wait until register matches expected state
1717  * @dev_priv: the i915 device
1718  * @reg: the register to read
1719  * @mask: mask to apply to register value
1720  * @value: expected value
1721  * @timeout_ms: timeout in millisecond
1722  *
1723  * This routine waits until the target register @reg contains the expected
1724  * @value after applying the @mask, i.e. it waits until ::
1725  *
1726  *     (I915_READ(reg) & mask) == value
1727  *
1728  * Otherwise, the wait will timeout after @timeout_ms milliseconds.
1729  *
1730  * Returns 0 if the register matches the desired condition, or -ETIMEOUT.
1731  */
1732 int intel_wait_for_register(struct drm_i915_private *dev_priv,
1733                             i915_reg_t reg,
1734                             const u32 mask,
1735                             const u32 value,
1736                             const unsigned long timeout_ms)
1737 {
1738
1739         unsigned fw =
1740                 intel_uncore_forcewake_for_reg(dev_priv, reg, FW_REG_READ);
1741         int ret;
1742
1743         intel_uncore_forcewake_get(dev_priv, fw);
1744         ret = wait_for_us((I915_READ_FW(reg) & mask) == value, 2);
1745         intel_uncore_forcewake_put(dev_priv, fw);
1746         if (ret)
1747                 ret = wait_for((I915_READ_NOTRACE(reg) & mask) == value,
1748                                timeout_ms);
1749
1750         return ret;
1751 }
1752
1753 static int gen8_request_engine_reset(struct intel_engine_cs *engine)
1754 {
1755         struct drm_i915_private *dev_priv = engine->i915;
1756         int ret;
1757
1758         I915_WRITE_FW(RING_RESET_CTL(engine->mmio_base),
1759                       _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET));
1760
1761         ret = intel_wait_for_register_fw(dev_priv,
1762                                          RING_RESET_CTL(engine->mmio_base),
1763                                          RESET_CTL_READY_TO_RESET,
1764                                          RESET_CTL_READY_TO_RESET,
1765                                          700);
1766         if (ret)
1767                 DRM_ERROR("%s: reset request timeout\n", engine->name);
1768
1769         return ret;
1770 }
1771
1772 static void gen8_unrequest_engine_reset(struct intel_engine_cs *engine)
1773 {
1774         struct drm_i915_private *dev_priv = engine->i915;
1775
1776         I915_WRITE_FW(RING_RESET_CTL(engine->mmio_base),
1777                       _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET));
1778 }
1779
1780 static int gen8_reset_engines(struct drm_i915_private *dev_priv,
1781                               unsigned engine_mask)
1782 {
1783         struct intel_engine_cs *engine;
1784         unsigned int tmp;
1785
1786         for_each_engine_masked(engine, dev_priv, engine_mask, tmp)
1787                 if (gen8_request_engine_reset(engine))
1788                         goto not_ready;
1789
1790         return gen6_reset_engines(dev_priv, engine_mask);
1791
1792 not_ready:
1793         for_each_engine_masked(engine, dev_priv, engine_mask, tmp)
1794                 gen8_unrequest_engine_reset(engine);
1795
1796         return -EIO;
1797 }
1798
1799 typedef int (*reset_func)(struct drm_i915_private *, unsigned engine_mask);
1800
1801 static reset_func intel_get_gpu_reset(struct drm_i915_private *dev_priv)
1802 {
1803         if (!i915.reset)
1804                 return NULL;
1805
1806         if (INTEL_INFO(dev_priv)->gen >= 8)
1807                 return gen8_reset_engines;
1808         else if (INTEL_INFO(dev_priv)->gen >= 6)
1809                 return gen6_reset_engines;
1810         else if (IS_GEN5(dev_priv))
1811                 return ironlake_do_reset;
1812         else if (IS_G4X(dev_priv))
1813                 return g4x_do_reset;
1814         else if (IS_G33(dev_priv))
1815                 return g33_do_reset;
1816         else if (INTEL_INFO(dev_priv)->gen >= 3)
1817                 return i915_do_reset;
1818         else
1819                 return NULL;
1820 }
1821
1822 int intel_gpu_reset(struct drm_i915_private *dev_priv, unsigned engine_mask)
1823 {
1824         reset_func reset;
1825         int ret;
1826
1827         reset = intel_get_gpu_reset(dev_priv);
1828         if (reset == NULL)
1829                 return -ENODEV;
1830
1831         /* If the power well sleeps during the reset, the reset
1832          * request may be dropped and never completes (causing -EIO).
1833          */
1834         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1835         ret = reset(dev_priv, engine_mask);
1836         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1837
1838         return ret;
1839 }
1840
1841 bool intel_has_gpu_reset(struct drm_i915_private *dev_priv)
1842 {
1843         return intel_get_gpu_reset(dev_priv) != NULL;
1844 }
1845
1846 int intel_guc_reset(struct drm_i915_private *dev_priv)
1847 {
1848         int ret;
1849         unsigned long irqflags;
1850
1851         if (!HAS_GUC(dev_priv))
1852                 return -EINVAL;
1853
1854         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1855         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
1856
1857         ret = gen6_hw_domain_reset(dev_priv, GEN9_GRDOM_GUC);
1858
1859         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1860         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1861
1862         return ret;
1863 }
1864
1865 bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv)
1866 {
1867         return check_for_unclaimed_mmio(dev_priv);
1868 }
1869
1870 bool
1871 intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv)
1872 {
1873         if (unlikely(i915.mmio_debug ||
1874                      dev_priv->uncore.unclaimed_mmio_check <= 0))
1875                 return false;
1876
1877         if (unlikely(intel_uncore_unclaimed_mmio(dev_priv))) {
1878                 DRM_DEBUG("Unclaimed register detected, "
1879                           "enabling oneshot unclaimed register reporting. "
1880                           "Please use i915.mmio_debug=N for more information.\n");
1881                 i915.mmio_debug++;
1882                 dev_priv->uncore.unclaimed_mmio_check--;
1883                 return true;
1884         }
1885
1886         return false;
1887 }
1888
1889 static enum forcewake_domains
1890 intel_uncore_forcewake_for_read(struct drm_i915_private *dev_priv,
1891                                 i915_reg_t reg)
1892 {
1893         u32 offset = i915_mmio_reg_offset(reg);
1894         enum forcewake_domains fw_domains;
1895
1896         if (HAS_FWTABLE(dev_priv)) {
1897                 fw_domains = __fwtable_reg_read_fw_domains(offset);
1898         } else if (INTEL_GEN(dev_priv) >= 6) {
1899                 fw_domains = __gen6_reg_read_fw_domains(offset);
1900         } else {
1901                 WARN_ON(!IS_GEN(dev_priv, 2, 5));
1902                 fw_domains = 0;
1903         }
1904
1905         WARN_ON(fw_domains & ~dev_priv->uncore.fw_domains);
1906
1907         return fw_domains;
1908 }
1909
1910 static enum forcewake_domains
1911 intel_uncore_forcewake_for_write(struct drm_i915_private *dev_priv,
1912                                  i915_reg_t reg)
1913 {
1914         u32 offset = i915_mmio_reg_offset(reg);
1915         enum forcewake_domains fw_domains;
1916
1917         if (HAS_FWTABLE(dev_priv) && !IS_VALLEYVIEW(dev_priv)) {
1918                 fw_domains = __fwtable_reg_write_fw_domains(offset);
1919         } else if (IS_GEN8(dev_priv)) {
1920                 fw_domains = __gen8_reg_write_fw_domains(offset);
1921         } else if (IS_GEN(dev_priv, 6, 7)) {
1922                 fw_domains = FORCEWAKE_RENDER;
1923         } else {
1924                 WARN_ON(!IS_GEN(dev_priv, 2, 5));
1925                 fw_domains = 0;
1926         }
1927
1928         WARN_ON(fw_domains & ~dev_priv->uncore.fw_domains);
1929
1930         return fw_domains;
1931 }
1932
1933 /**
1934  * intel_uncore_forcewake_for_reg - which forcewake domains are needed to access
1935  *                                  a register
1936  * @dev_priv: pointer to struct drm_i915_private
1937  * @reg: register in question
1938  * @op: operation bitmask of FW_REG_READ and/or FW_REG_WRITE
1939  *
1940  * Returns a set of forcewake domains required to be taken with for example
1941  * intel_uncore_forcewake_get for the specified register to be accessible in the
1942  * specified mode (read, write or read/write) with raw mmio accessors.
1943  *
1944  * NOTE: On Gen6 and Gen7 write forcewake domain (FORCEWAKE_RENDER) requires the
1945  * callers to do FIFO management on their own or risk losing writes.
1946  */
1947 enum forcewake_domains
1948 intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
1949                                i915_reg_t reg, unsigned int op)
1950 {
1951         enum forcewake_domains fw_domains = 0;
1952
1953         WARN_ON(!op);
1954
1955         if (intel_vgpu_active(dev_priv))
1956                 return 0;
1957
1958         if (op & FW_REG_READ)
1959                 fw_domains = intel_uncore_forcewake_for_read(dev_priv, reg);
1960
1961         if (op & FW_REG_WRITE)
1962                 fw_domains |= intel_uncore_forcewake_for_write(dev_priv, reg);
1963
1964         return fw_domains;
1965 }