drivers/gpu/drm/i915/intel_uc.c

   1 /*
   2  * Copyright © 2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include "i915_drv.h"
  26 #include "intel_uc.h"
  27
  28 void intel_uc_init_early(struct drm_i915_private *dev_priv)
  29 {
  30         mutex_init(&dev_priv->guc.send_mutex);
  31 }
  32
  33 /*
  34  * Read GuC command/status register (SOFT_SCRATCH_0)
  35  * Return true if it contains a response rather than a command
  36  */
  37 static bool intel_guc_recv(struct intel_guc *guc, u32 *status)
  38 {
  39         struct drm_i915_private *dev_priv = guc_to_i915(guc);
  40
  41         u32 val = I915_READ(SOFT_SCRATCH(0));
  42         *status = val;
  43         return INTEL_GUC_RECV_IS_RESPONSE(val);
  44 }
  45
  46 int intel_guc_send(struct intel_guc *guc, const u32 *action, u32 len)
  47 {
  48         struct drm_i915_private *dev_priv = guc_to_i915(guc);
  49         u32 status;
  50         int i;
  51         int ret;
  52
  53         if (WARN_ON(len < 1 || len > 15))
  54                 return -EINVAL;
  55
  56         mutex_lock(&guc->send_mutex);
  57         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
  58
  59         dev_priv->guc.action_count += 1;
  60         dev_priv->guc.action_cmd = action[0];
  61
  62         for (i = 0; i < len; i++)
  63                 I915_WRITE(SOFT_SCRATCH(i), action[i]);
  64
  65         POSTING_READ(SOFT_SCRATCH(i - 1));
  66
  67         I915_WRITE(GUC_SEND_INTERRUPT, GUC_SEND_TRIGGER);
  68
  69         /*
  70          * Fast commands should complete in less than 10us, so sample quickly
  71          * up to that length of time, then switch to a slower sleep-wait loop.
  72          * No inte_guc_send command should ever take longer than 10ms.
  73          */
  74         ret = wait_for_us(intel_guc_recv(guc, &status), 10);
  75         if (ret)
  76                 ret = wait_for(intel_guc_recv(guc, &status), 10);
  77         if (status != INTEL_GUC_STATUS_SUCCESS) {
  78                 /*
  79                  * Either the GuC explicitly returned an error (which
  80                  * we convert to -EIO here) or no response at all was
  81                  * received within the timeout limit (-ETIMEDOUT)
  82                  */
  83                 if (ret != -ETIMEDOUT)
  84                         ret = -EIO;
  85
  86                 DRM_WARN("INTEL_GUC_SEND: Action 0x%X failed;"
  87                          " ret=%d status=0x%08X response=0x%08X\n",
  88                          action[0], ret, status, I915_READ(SOFT_SCRATCH(15)));
  89
  90                 dev_priv->guc.action_fail += 1;
  91                 dev_priv->guc.action_err = ret;
  92         }
  93         dev_priv->guc.action_status = status;
  94
  95         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
  96         mutex_unlock(&guc->send_mutex);
  97
  98         return ret;
  99 }
 100
 101 int intel_guc_sample_forcewake(struct intel_guc *guc)
 102 {
 103         struct drm_i915_private *dev_priv = guc_to_i915(guc);
 104         u32 action[2];
 105
 106         action[0] = INTEL_GUC_ACTION_SAMPLE_FORCEWAKE;
 107         /* WaRsDisableCoarsePowerGating:skl,bxt */
 108         if (!intel_enable_rc6() || NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
 109                 action[1] = 0;
 110         else
 111                 /* bit 0 and 1 are for Render and Media domain separately */
 112                 action[1] = GUC_FORCEWAKE_RENDER | GUC_FORCEWAKE_MEDIA;
 113
 114         return intel_guc_send(guc, action, ARRAY_SIZE(action));
 115 }
 116
 117 int intel_guc_log_flush_complete(struct intel_guc *guc)
 118 {
 119         u32 action[] = { INTEL_GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE };
 120
 121         return intel_guc_send(guc, action, ARRAY_SIZE(action));
 122 }
 123
 124 int intel_guc_log_flush(struct intel_guc *guc)
 125 {
 126         u32 action[] = {
 127                 INTEL_GUC_ACTION_FORCE_LOG_BUFFER_FLUSH,
 128                 0
 129         };
 130
 131         return intel_guc_send(guc, action, ARRAY_SIZE(action));
 132 }
 133
 134 int intel_guc_log_control(struct intel_guc *guc, u32 control_val)
 135 {
 136         u32 action[] = {
 137                 INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING,
 138                 control_val
 139         };
 140
 141         return intel_guc_send(guc, action, ARRAY_SIZE(action));
 142 }