2 * Copyright © 2006-2008 Intel Corporation
3 * Jesse Barnes <jesse.barnes@intel.com>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Eric Anholt <eric@anholt.net>
30 * Integrated TV-out support for the 915GM and 945GM.
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_edid.h>
37 #include "intel_drv.h"
38 #include <drm/i915_drm.h>
42 TV_MARGIN_LEFT, TV_MARGIN_TOP,
43 TV_MARGIN_RIGHT, TV_MARGIN_BOTTOM
47 struct intel_encoder base;
57 struct color_conversion {
63 static const u32 filter_table[] = {
64 0xB1403000, 0x2E203500, 0x35002E20, 0x3000B140,
65 0x35A0B160, 0x2DC02E80, 0xB1403480, 0xB1603000,
66 0x2EA03640, 0x34002D80, 0x3000B120, 0x36E0B160,
67 0x2D202EF0, 0xB1203380, 0xB1603000, 0x2F303780,
68 0x33002CC0, 0x3000B100, 0x3820B160, 0x2C802F50,
69 0xB10032A0, 0xB1603000, 0x2F9038C0, 0x32202C20,
70 0x3000B0E0, 0x3980B160, 0x2BC02FC0, 0xB0E031C0,
71 0xB1603000, 0x2FF03A20, 0x31602B60, 0xB020B0C0,
72 0x3AE0B160, 0x2B001810, 0xB0C03120, 0xB140B020,
73 0x18283BA0, 0x30C02A80, 0xB020B0A0, 0x3C60B140,
74 0x2A201838, 0xB0A03080, 0xB120B020, 0x18383D20,
75 0x304029C0, 0xB040B080, 0x3DE0B100, 0x29601848,
76 0xB0803000, 0xB100B040, 0x18483EC0, 0xB0402900,
77 0xB040B060, 0x3F80B0C0, 0x28801858, 0xB060B080,
78 0xB0A0B060, 0x18602820, 0xB0A02820, 0x0000B060,
79 0xB1403000, 0x2E203500, 0x35002E20, 0x3000B140,
80 0x35A0B160, 0x2DC02E80, 0xB1403480, 0xB1603000,
81 0x2EA03640, 0x34002D80, 0x3000B120, 0x36E0B160,
82 0x2D202EF0, 0xB1203380, 0xB1603000, 0x2F303780,
83 0x33002CC0, 0x3000B100, 0x3820B160, 0x2C802F50,
84 0xB10032A0, 0xB1603000, 0x2F9038C0, 0x32202C20,
85 0x3000B0E0, 0x3980B160, 0x2BC02FC0, 0xB0E031C0,
86 0xB1603000, 0x2FF03A20, 0x31602B60, 0xB020B0C0,
87 0x3AE0B160, 0x2B001810, 0xB0C03120, 0xB140B020,
88 0x18283BA0, 0x30C02A80, 0xB020B0A0, 0x3C60B140,
89 0x2A201838, 0xB0A03080, 0xB120B020, 0x18383D20,
90 0x304029C0, 0xB040B080, 0x3DE0B100, 0x29601848,
91 0xB0803000, 0xB100B040, 0x18483EC0, 0xB0402900,
92 0xB040B060, 0x3F80B0C0, 0x28801858, 0xB060B080,
93 0xB0A0B060, 0x18602820, 0xB0A02820, 0x0000B060,
94 0x36403000, 0x2D002CC0, 0x30003640, 0x2D0036C0,
95 0x35C02CC0, 0x37403000, 0x2C802D40, 0x30003540,
96 0x2D8037C0, 0x34C02C40, 0x38403000, 0x2BC02E00,
97 0x30003440, 0x2E2038C0, 0x34002B80, 0x39803000,
98 0x2B402E40, 0x30003380, 0x2E603A00, 0x33402B00,
99 0x3A803040, 0x2A802EA0, 0x30403300, 0x2EC03B40,
100 0x32802A40, 0x3C003040, 0x2A002EC0, 0x30803240,
101 0x2EC03C80, 0x320029C0, 0x3D403080, 0x29402F00,
102 0x308031C0, 0x2F203DC0, 0x31802900, 0x3E8030C0,
103 0x28802F40, 0x30C03140, 0x2F203F40, 0x31402840,
104 0x28003100, 0x28002F00, 0x00003100, 0x36403000,
105 0x2D002CC0, 0x30003640, 0x2D0036C0,
106 0x35C02CC0, 0x37403000, 0x2C802D40, 0x30003540,
107 0x2D8037C0, 0x34C02C40, 0x38403000, 0x2BC02E00,
108 0x30003440, 0x2E2038C0, 0x34002B80, 0x39803000,
109 0x2B402E40, 0x30003380, 0x2E603A00, 0x33402B00,
110 0x3A803040, 0x2A802EA0, 0x30403300, 0x2EC03B40,
111 0x32802A40, 0x3C003040, 0x2A002EC0, 0x30803240,
112 0x2EC03C80, 0x320029C0, 0x3D403080, 0x29402F00,
113 0x308031C0, 0x2F203DC0, 0x31802900, 0x3E8030C0,
114 0x28802F40, 0x30C03140, 0x2F203F40, 0x31402840,
115 0x28003100, 0x28002F00, 0x00003100,
119 * Color conversion values have 3 separate fixed point formats:
121 * 10 bit fields (ay, au)
122 * 1.9 fixed point (b.bbbbbbbbb)
123 * 11 bit fields (ry, by, ru, gu, gv)
124 * exp.mantissa (ee.mmmmmmmmm)
125 * ee = 00 = 10^-1 (0.mmmmmmmmm)
126 * ee = 01 = 10^-2 (0.0mmmmmmmmm)
127 * ee = 10 = 10^-3 (0.00mmmmmmmmm)
128 * ee = 11 = 10^-4 (0.000mmmmmmmmm)
129 * 12 bit fields (gy, rv, bu)
130 * exp.mantissa (eee.mmmmmmmmm)
131 * eee = 000 = 10^-1 (0.mmmmmmmmm)
132 * eee = 001 = 10^-2 (0.0mmmmmmmmm)
133 * eee = 010 = 10^-3 (0.00mmmmmmmmm)
134 * eee = 011 = 10^-4 (0.000mmmmmmmmm)
135 * eee = 100 = reserved
136 * eee = 101 = reserved
137 * eee = 110 = reserved
138 * eee = 111 = 10^0 (m.mmmmmmmm) (only usable for 1.0 representation)
140 * Saturation and contrast are 8 bits, with their own representation:
141 * 8 bit field (saturation, contrast)
142 * exp.mantissa (ee.mmmmmm)
143 * ee = 00 = 10^-1 (0.mmmmmm)
144 * ee = 01 = 10^0 (m.mmmmm)
145 * ee = 10 = 10^1 (mm.mmmm)
146 * ee = 11 = 10^2 (mmm.mmm)
148 * Simple conversion function:
151 * float_to_csc_11(float f)
164 * for (exp = 0; exp < 3 && f < 0.5; exp++)
166 * mant = (f * (1 << 9) + 0.5);
167 * if (mant >= (1 << 9))
168 * mant = (1 << 9) - 1;
170 * ret = (exp << 9) | mant;
176 * Behold, magic numbers! If we plant them they might grow a big
177 * s-video cable to the sky... or something.
179 * Pre-converted to appropriate hex value.
183 * PAL & NTSC values for composite & s-video connections
185 static const struct color_conversion ntsc_m_csc_composite = {
186 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0104,
187 .ru = 0x0733, .gu = 0x052d, .bu = 0x05c7, .au = 0x0200,
188 .rv = 0x0340, .gv = 0x030c, .bv = 0x06d0, .av = 0x0200,
191 static const struct video_levels ntsc_m_levels_composite = {
192 .blank = 225, .black = 267, .burst = 113,
195 static const struct color_conversion ntsc_m_csc_svideo = {
196 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0133,
197 .ru = 0x076a, .gu = 0x0564, .bu = 0x030d, .au = 0x0200,
198 .rv = 0x037a, .gv = 0x033d, .bv = 0x06f6, .av = 0x0200,
201 static const struct video_levels ntsc_m_levels_svideo = {
202 .blank = 266, .black = 316, .burst = 133,
205 static const struct color_conversion ntsc_j_csc_composite = {
206 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0119,
207 .ru = 0x074c, .gu = 0x0546, .bu = 0x05ec, .au = 0x0200,
208 .rv = 0x035a, .gv = 0x0322, .bv = 0x06e1, .av = 0x0200,
211 static const struct video_levels ntsc_j_levels_composite = {
212 .blank = 225, .black = 225, .burst = 113,
215 static const struct color_conversion ntsc_j_csc_svideo = {
216 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x014c,
217 .ru = 0x0788, .gu = 0x0581, .bu = 0x0322, .au = 0x0200,
218 .rv = 0x0399, .gv = 0x0356, .bv = 0x070a, .av = 0x0200,
221 static const struct video_levels ntsc_j_levels_svideo = {
222 .blank = 266, .black = 266, .burst = 133,
225 static const struct color_conversion pal_csc_composite = {
226 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0113,
227 .ru = 0x0745, .gu = 0x053f, .bu = 0x05e1, .au = 0x0200,
228 .rv = 0x0353, .gv = 0x031c, .bv = 0x06dc, .av = 0x0200,
231 static const struct video_levels pal_levels_composite = {
232 .blank = 237, .black = 237, .burst = 118,
235 static const struct color_conversion pal_csc_svideo = {
236 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0145,
237 .ru = 0x0780, .gu = 0x0579, .bu = 0x031c, .au = 0x0200,
238 .rv = 0x0390, .gv = 0x034f, .bv = 0x0705, .av = 0x0200,
241 static const struct video_levels pal_levels_svideo = {
242 .blank = 280, .black = 280, .burst = 139,
245 static const struct color_conversion pal_m_csc_composite = {
246 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0104,
247 .ru = 0x0733, .gu = 0x052d, .bu = 0x05c7, .au = 0x0200,
248 .rv = 0x0340, .gv = 0x030c, .bv = 0x06d0, .av = 0x0200,
251 static const struct video_levels pal_m_levels_composite = {
252 .blank = 225, .black = 267, .burst = 113,
255 static const struct color_conversion pal_m_csc_svideo = {
256 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0133,
257 .ru = 0x076a, .gu = 0x0564, .bu = 0x030d, .au = 0x0200,
258 .rv = 0x037a, .gv = 0x033d, .bv = 0x06f6, .av = 0x0200,
261 static const struct video_levels pal_m_levels_svideo = {
262 .blank = 266, .black = 316, .burst = 133,
265 static const struct color_conversion pal_n_csc_composite = {
266 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0104,
267 .ru = 0x0733, .gu = 0x052d, .bu = 0x05c7, .au = 0x0200,
268 .rv = 0x0340, .gv = 0x030c, .bv = 0x06d0, .av = 0x0200,
271 static const struct video_levels pal_n_levels_composite = {
272 .blank = 225, .black = 267, .burst = 118,
275 static const struct color_conversion pal_n_csc_svideo = {
276 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0133,
277 .ru = 0x076a, .gu = 0x0564, .bu = 0x030d, .au = 0x0200,
278 .rv = 0x037a, .gv = 0x033d, .bv = 0x06f6, .av = 0x0200,
281 static const struct video_levels pal_n_levels_svideo = {
282 .blank = 266, .black = 316, .burst = 139,
286 * Component connections
288 static const struct color_conversion sdtv_csc_yprpb = {
289 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0145,
290 .ru = 0x0559, .gu = 0x0353, .bu = 0x0100, .au = 0x0200,
291 .rv = 0x0100, .gv = 0x03ad, .bv = 0x074d, .av = 0x0200,
294 static const struct color_conversion hdtv_csc_yprpb = {
295 .ry = 0x05b3, .gy = 0x016e, .by = 0x0728, .ay = 0x0145,
296 .ru = 0x07d5, .gu = 0x038b, .bu = 0x0100, .au = 0x0200,
297 .rv = 0x0100, .gv = 0x03d1, .bv = 0x06bc, .av = 0x0200,
300 static const struct video_levels component_levels = {
301 .blank = 279, .black = 279, .burst = 0,
309 u16 refresh; /* in millihertz (for precision) */
312 u16 hblank_start, hblank_end, htotal;
313 bool progressive : 1, trilevel_sync : 1, component_only : 1;
314 u8 vsync_start_f1, vsync_start_f2, vsync_len;
316 u8 veq_start_f1, veq_start_f2, veq_len;
317 u8 vi_end_f1, vi_end_f2;
320 u8 hburst_start, hburst_len;
330 * subcarrier programming
332 u16 dda2_size, dda3_size;
334 u16 dda2_inc, dda3_inc;
340 const struct video_levels *composite_levels, *svideo_levels;
341 const struct color_conversion *composite_color, *svideo_color;
342 const u32 *filter_table;
350 * I think this works as follows:
352 * subcarrier freq = pixel_clock * (dda1_inc + dda2_inc / dda2_size) / 4096
354 * Presumably, when dda3 is added in, it gets to adjust the dda2_inc value
357 * dda1_ideal = subcarrier/pixel * 4096
358 * dda1_inc = floor (dda1_ideal)
359 * dda2 = dda1_ideal - dda1_inc
361 * then pick a ratio for dda2 that gives the closest approximation. If
362 * you can't get close enough, you can play with dda3 as well. This
363 * seems likely to happen when dda2 is small as the jumps would be larger
367 * pixel_clock = subcarrier * 4096 / (dda1_inc + dda2_inc / dda2_size)
369 * The constants below were all computed using a 107.520MHz clock
373 * Register programming values for TV modes.
375 * These values account for -1s required.
377 static const struct tv_mode tv_modes[] = {
382 .oversample = TV_OVERSAMPLE_8X,
384 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 3.580MHz */
386 .hsync_end = 64, .hblank_end = 124,
387 .hblank_start = 836, .htotal = 857,
389 .progressive = false, .trilevel_sync = false,
391 .vsync_start_f1 = 6, .vsync_start_f2 = 7,
394 .veq_ena = true, .veq_start_f1 = 0,
395 .veq_start_f2 = 1, .veq_len = 18,
397 .vi_end_f1 = 20, .vi_end_f2 = 21,
401 .hburst_start = 72, .hburst_len = 34,
402 .vburst_start_f1 = 9, .vburst_end_f1 = 240,
403 .vburst_start_f2 = 10, .vburst_end_f2 = 240,
404 .vburst_start_f3 = 9, .vburst_end_f3 = 240,
405 .vburst_start_f4 = 10, .vburst_end_f4 = 240,
407 /* desired 3.5800000 actual 3.5800000 clock 107.52 */
409 .dda2_inc = 20800, .dda2_size = 27456,
410 .dda3_inc = 0, .dda3_size = 0,
411 .sc_reset = TV_SC_RESET_EVERY_4,
414 .composite_levels = &ntsc_m_levels_composite,
415 .composite_color = &ntsc_m_csc_composite,
416 .svideo_levels = &ntsc_m_levels_svideo,
417 .svideo_color = &ntsc_m_csc_svideo,
419 .filter_table = filter_table,
425 .oversample = TV_OVERSAMPLE_8X,
427 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 4.43MHz */
428 .hsync_end = 64, .hblank_end = 124,
429 .hblank_start = 836, .htotal = 857,
431 .progressive = false, .trilevel_sync = false,
433 .vsync_start_f1 = 6, .vsync_start_f2 = 7,
436 .veq_ena = true, .veq_start_f1 = 0,
437 .veq_start_f2 = 1, .veq_len = 18,
439 .vi_end_f1 = 20, .vi_end_f2 = 21,
443 .hburst_start = 72, .hburst_len = 34,
444 .vburst_start_f1 = 9, .vburst_end_f1 = 240,
445 .vburst_start_f2 = 10, .vburst_end_f2 = 240,
446 .vburst_start_f3 = 9, .vburst_end_f3 = 240,
447 .vburst_start_f4 = 10, .vburst_end_f4 = 240,
449 /* desired 4.4336180 actual 4.4336180 clock 107.52 */
451 .dda2_inc = 4093, .dda2_size = 27456,
452 .dda3_inc = 310, .dda3_size = 525,
453 .sc_reset = TV_SC_RESET_NEVER,
456 .composite_levels = &ntsc_m_levels_composite,
457 .composite_color = &ntsc_m_csc_composite,
458 .svideo_levels = &ntsc_m_levels_svideo,
459 .svideo_color = &ntsc_m_csc_svideo,
461 .filter_table = filter_table,
467 .oversample = TV_OVERSAMPLE_8X,
470 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 3.580MHz */
471 .hsync_end = 64, .hblank_end = 124,
472 .hblank_start = 836, .htotal = 857,
474 .progressive = false, .trilevel_sync = false,
476 .vsync_start_f1 = 6, .vsync_start_f2 = 7,
479 .veq_ena = true, .veq_start_f1 = 0,
480 .veq_start_f2 = 1, .veq_len = 18,
482 .vi_end_f1 = 20, .vi_end_f2 = 21,
486 .hburst_start = 72, .hburst_len = 34,
487 .vburst_start_f1 = 9, .vburst_end_f1 = 240,
488 .vburst_start_f2 = 10, .vburst_end_f2 = 240,
489 .vburst_start_f3 = 9, .vburst_end_f3 = 240,
490 .vburst_start_f4 = 10, .vburst_end_f4 = 240,
492 /* desired 3.5800000 actual 3.5800000 clock 107.52 */
494 .dda2_inc = 20800, .dda2_size = 27456,
495 .dda3_inc = 0, .dda3_size = 0,
496 .sc_reset = TV_SC_RESET_EVERY_4,
499 .composite_levels = &ntsc_j_levels_composite,
500 .composite_color = &ntsc_j_csc_composite,
501 .svideo_levels = &ntsc_j_levels_svideo,
502 .svideo_color = &ntsc_j_csc_svideo,
504 .filter_table = filter_table,
510 .oversample = TV_OVERSAMPLE_8X,
513 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 3.580MHz */
514 .hsync_end = 64, .hblank_end = 124,
515 .hblank_start = 836, .htotal = 857,
517 .progressive = false, .trilevel_sync = false,
519 .vsync_start_f1 = 6, .vsync_start_f2 = 7,
522 .veq_ena = true, .veq_start_f1 = 0,
523 .veq_start_f2 = 1, .veq_len = 18,
525 .vi_end_f1 = 20, .vi_end_f2 = 21,
529 .hburst_start = 72, .hburst_len = 34,
530 .vburst_start_f1 = 9, .vburst_end_f1 = 240,
531 .vburst_start_f2 = 10, .vburst_end_f2 = 240,
532 .vburst_start_f3 = 9, .vburst_end_f3 = 240,
533 .vburst_start_f4 = 10, .vburst_end_f4 = 240,
535 /* desired 3.5800000 actual 3.5800000 clock 107.52 */
537 .dda2_inc = 16704, .dda2_size = 27456,
538 .dda3_inc = 0, .dda3_size = 0,
539 .sc_reset = TV_SC_RESET_EVERY_8,
542 .composite_levels = &pal_m_levels_composite,
543 .composite_color = &pal_m_csc_composite,
544 .svideo_levels = &pal_m_levels_svideo,
545 .svideo_color = &pal_m_csc_svideo,
547 .filter_table = filter_table,
550 /* 625 Lines, 50 Fields, 15.625KHz line, Sub-Carrier 4.434MHz */
554 .oversample = TV_OVERSAMPLE_8X,
557 .hsync_end = 64, .hblank_end = 128,
558 .hblank_start = 844, .htotal = 863,
560 .progressive = false, .trilevel_sync = false,
563 .vsync_start_f1 = 6, .vsync_start_f2 = 7,
566 .veq_ena = true, .veq_start_f1 = 0,
567 .veq_start_f2 = 1, .veq_len = 18,
569 .vi_end_f1 = 24, .vi_end_f2 = 25,
573 .hburst_start = 73, .hburst_len = 34,
574 .vburst_start_f1 = 8, .vburst_end_f1 = 285,
575 .vburst_start_f2 = 8, .vburst_end_f2 = 286,
576 .vburst_start_f3 = 9, .vburst_end_f3 = 286,
577 .vburst_start_f4 = 9, .vburst_end_f4 = 285,
580 /* desired 4.4336180 actual 4.4336180 clock 107.52 */
582 .dda2_inc = 23578, .dda2_size = 27648,
583 .dda3_inc = 134, .dda3_size = 625,
584 .sc_reset = TV_SC_RESET_EVERY_8,
587 .composite_levels = &pal_n_levels_composite,
588 .composite_color = &pal_n_csc_composite,
589 .svideo_levels = &pal_n_levels_svideo,
590 .svideo_color = &pal_n_csc_svideo,
592 .filter_table = filter_table,
595 /* 625 Lines, 50 Fields, 15.625KHz line, Sub-Carrier 4.434MHz */
599 .oversample = TV_OVERSAMPLE_8X,
602 .hsync_end = 64, .hblank_end = 142,
603 .hblank_start = 844, .htotal = 863,
605 .progressive = false, .trilevel_sync = false,
607 .vsync_start_f1 = 5, .vsync_start_f2 = 6,
610 .veq_ena = true, .veq_start_f1 = 0,
611 .veq_start_f2 = 1, .veq_len = 15,
613 .vi_end_f1 = 24, .vi_end_f2 = 25,
617 .hburst_start = 73, .hburst_len = 32,
618 .vburst_start_f1 = 8, .vburst_end_f1 = 285,
619 .vburst_start_f2 = 8, .vburst_end_f2 = 286,
620 .vburst_start_f3 = 9, .vburst_end_f3 = 286,
621 .vburst_start_f4 = 9, .vburst_end_f4 = 285,
623 /* desired 4.4336180 actual 4.4336180 clock 107.52 */
625 .dda2_inc = 4122, .dda2_size = 27648,
626 .dda3_inc = 67, .dda3_size = 625,
627 .sc_reset = TV_SC_RESET_EVERY_8,
630 .composite_levels = &pal_levels_composite,
631 .composite_color = &pal_csc_composite,
632 .svideo_levels = &pal_levels_svideo,
633 .svideo_color = &pal_csc_svideo,
635 .filter_table = filter_table,
641 .oversample = TV_OVERSAMPLE_4X,
644 .hsync_end = 64, .hblank_end = 122,
645 .hblank_start = 842, .htotal = 857,
647 .progressive = true, .trilevel_sync = false,
649 .vsync_start_f1 = 12, .vsync_start_f2 = 12,
654 .vi_end_f1 = 44, .vi_end_f2 = 44,
659 .filter_table = filter_table,
665 .oversample = TV_OVERSAMPLE_4X,
668 .hsync_end = 64, .hblank_end = 139,
669 .hblank_start = 859, .htotal = 863,
671 .progressive = true, .trilevel_sync = false,
673 .vsync_start_f1 = 10, .vsync_start_f2 = 10,
678 .vi_end_f1 = 48, .vi_end_f2 = 48,
683 .filter_table = filter_table,
689 .oversample = TV_OVERSAMPLE_2X,
692 .hsync_end = 80, .hblank_end = 300,
693 .hblank_start = 1580, .htotal = 1649,
695 .progressive = true, .trilevel_sync = true,
697 .vsync_start_f1 = 10, .vsync_start_f2 = 10,
702 .vi_end_f1 = 29, .vi_end_f2 = 29,
707 .filter_table = filter_table,
713 .oversample = TV_OVERSAMPLE_2X,
716 .hsync_end = 80, .hblank_end = 300,
717 .hblank_start = 1580, .htotal = 1979,
719 .progressive = true, .trilevel_sync = true,
721 .vsync_start_f1 = 10, .vsync_start_f2 = 10,
726 .vi_end_f1 = 29, .vi_end_f2 = 29,
731 .filter_table = filter_table,
735 .name = "1080i@50Hz",
738 .oversample = TV_OVERSAMPLE_2X,
741 .hsync_end = 88, .hblank_end = 235,
742 .hblank_start = 2155, .htotal = 2639,
744 .progressive = false, .trilevel_sync = true,
746 .vsync_start_f1 = 4, .vsync_start_f2 = 5,
749 .veq_ena = true, .veq_start_f1 = 4,
750 .veq_start_f2 = 4, .veq_len = 10,
753 .vi_end_f1 = 21, .vi_end_f2 = 22,
758 .filter_table = filter_table,
761 .name = "1080i@60Hz",
764 .oversample = TV_OVERSAMPLE_2X,
767 .hsync_end = 88, .hblank_end = 235,
768 .hblank_start = 2155, .htotal = 2199,
770 .progressive = false, .trilevel_sync = true,
772 .vsync_start_f1 = 4, .vsync_start_f2 = 5,
775 .veq_ena = true, .veq_start_f1 = 4,
776 .veq_start_f2 = 4, .veq_len = 10,
779 .vi_end_f1 = 21, .vi_end_f2 = 22,
784 .filter_table = filter_table,
788 static struct intel_tv *enc_to_tv(struct intel_encoder *encoder)
790 return container_of(encoder, struct intel_tv, base);
793 static struct intel_tv *intel_attached_tv(struct drm_connector *connector)
795 return enc_to_tv(intel_attached_encoder(connector));
799 intel_tv_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe)
801 struct drm_device *dev = encoder->base.dev;
802 struct drm_i915_private *dev_priv = to_i915(dev);
803 u32 tmp = I915_READ(TV_CTL);
805 if (!(tmp & TV_ENC_ENABLE))
808 *pipe = PORT_TO_PIPE(tmp);
814 intel_enable_tv(struct intel_encoder *encoder,
815 const struct intel_crtc_state *pipe_config,
816 const struct drm_connector_state *conn_state)
818 struct drm_device *dev = encoder->base.dev;
819 struct drm_i915_private *dev_priv = to_i915(dev);
821 /* Prevents vblank waits from timing out in intel_tv_detect_type() */
822 intel_wait_for_vblank(dev_priv,
823 to_intel_crtc(pipe_config->base.crtc)->pipe);
825 I915_WRITE(TV_CTL, I915_READ(TV_CTL) | TV_ENC_ENABLE);
829 intel_disable_tv(struct intel_encoder *encoder,
830 const struct intel_crtc_state *old_crtc_state,
831 const struct drm_connector_state *old_conn_state)
833 struct drm_device *dev = encoder->base.dev;
834 struct drm_i915_private *dev_priv = to_i915(dev);
836 I915_WRITE(TV_CTL, I915_READ(TV_CTL) & ~TV_ENC_ENABLE);
839 static const struct tv_mode *intel_tv_mode_find(const struct drm_connector_state *conn_state)
841 int format = conn_state->tv.mode;
843 return &tv_modes[format];
846 static enum drm_mode_status
847 intel_tv_mode_valid(struct drm_connector *connector,
848 struct drm_display_mode *mode)
850 const struct tv_mode *tv_mode = intel_tv_mode_find(connector->state);
851 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
853 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
854 return MODE_NO_DBLESCAN;
856 if (mode->clock > max_dotclk)
857 return MODE_CLOCK_HIGH;
859 /* Ensure TV refresh is close to desired refresh */
860 if (tv_mode && abs(tv_mode->refresh - drm_mode_vrefresh(mode) * 1000)
864 return MODE_CLOCK_RANGE;
869 intel_tv_get_config(struct intel_encoder *encoder,
870 struct intel_crtc_state *pipe_config)
872 pipe_config->output_types |= BIT(INTEL_OUTPUT_TVOUT);
874 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
878 intel_tv_compute_config(struct intel_encoder *encoder,
879 struct intel_crtc_state *pipe_config,
880 struct drm_connector_state *conn_state)
882 const struct tv_mode *tv_mode = intel_tv_mode_find(conn_state);
883 struct drm_display_mode *adjusted_mode =
884 &pipe_config->base.adjusted_mode;
889 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
892 adjusted_mode->crtc_clock = tv_mode->clock;
893 DRM_DEBUG_KMS("forcing bpc to 8 for TV\n");
894 pipe_config->pipe_bpp = 8*3;
896 /* TV has it's own notion of sync and other mode flags, so clear them. */
897 adjusted_mode->flags = 0;
900 * FIXME: We don't check whether the input mode is actually what we want
901 * or whether userspace is doing something stupid.
908 set_tv_mode_timings(struct drm_i915_private *dev_priv,
909 const struct tv_mode *tv_mode,
912 u32 hctl1, hctl2, hctl3;
913 u32 vctl1, vctl2, vctl3, vctl4, vctl5, vctl6, vctl7;
915 hctl1 = (tv_mode->hsync_end << TV_HSYNC_END_SHIFT) |
916 (tv_mode->htotal << TV_HTOTAL_SHIFT);
918 hctl2 = (tv_mode->hburst_start << 16) |
919 (tv_mode->hburst_len << TV_HBURST_LEN_SHIFT);
922 hctl2 |= TV_BURST_ENA;
924 hctl3 = (tv_mode->hblank_start << TV_HBLANK_START_SHIFT) |
925 (tv_mode->hblank_end << TV_HBLANK_END_SHIFT);
927 vctl1 = (tv_mode->nbr_end << TV_NBR_END_SHIFT) |
928 (tv_mode->vi_end_f1 << TV_VI_END_F1_SHIFT) |
929 (tv_mode->vi_end_f2 << TV_VI_END_F2_SHIFT);
931 vctl2 = (tv_mode->vsync_len << TV_VSYNC_LEN_SHIFT) |
932 (tv_mode->vsync_start_f1 << TV_VSYNC_START_F1_SHIFT) |
933 (tv_mode->vsync_start_f2 << TV_VSYNC_START_F2_SHIFT);
935 vctl3 = (tv_mode->veq_len << TV_VEQ_LEN_SHIFT) |
936 (tv_mode->veq_start_f1 << TV_VEQ_START_F1_SHIFT) |
937 (tv_mode->veq_start_f2 << TV_VEQ_START_F2_SHIFT);
939 if (tv_mode->veq_ena)
940 vctl3 |= TV_EQUAL_ENA;
942 vctl4 = (tv_mode->vburst_start_f1 << TV_VBURST_START_F1_SHIFT) |
943 (tv_mode->vburst_end_f1 << TV_VBURST_END_F1_SHIFT);
945 vctl5 = (tv_mode->vburst_start_f2 << TV_VBURST_START_F2_SHIFT) |
946 (tv_mode->vburst_end_f2 << TV_VBURST_END_F2_SHIFT);
948 vctl6 = (tv_mode->vburst_start_f3 << TV_VBURST_START_F3_SHIFT) |
949 (tv_mode->vburst_end_f3 << TV_VBURST_END_F3_SHIFT);
951 vctl7 = (tv_mode->vburst_start_f4 << TV_VBURST_START_F4_SHIFT) |
952 (tv_mode->vburst_end_f4 << TV_VBURST_END_F4_SHIFT);
954 I915_WRITE(TV_H_CTL_1, hctl1);
955 I915_WRITE(TV_H_CTL_2, hctl2);
956 I915_WRITE(TV_H_CTL_3, hctl3);
957 I915_WRITE(TV_V_CTL_1, vctl1);
958 I915_WRITE(TV_V_CTL_2, vctl2);
959 I915_WRITE(TV_V_CTL_3, vctl3);
960 I915_WRITE(TV_V_CTL_4, vctl4);
961 I915_WRITE(TV_V_CTL_5, vctl5);
962 I915_WRITE(TV_V_CTL_6, vctl6);
963 I915_WRITE(TV_V_CTL_7, vctl7);
966 static void set_color_conversion(struct drm_i915_private *dev_priv,
967 const struct color_conversion *color_conversion)
969 if (!color_conversion)
972 I915_WRITE(TV_CSC_Y, (color_conversion->ry << 16) |
973 color_conversion->gy);
974 I915_WRITE(TV_CSC_Y2, (color_conversion->by << 16) |
975 color_conversion->ay);
976 I915_WRITE(TV_CSC_U, (color_conversion->ru << 16) |
977 color_conversion->gu);
978 I915_WRITE(TV_CSC_U2, (color_conversion->bu << 16) |
979 color_conversion->au);
980 I915_WRITE(TV_CSC_V, (color_conversion->rv << 16) |
981 color_conversion->gv);
982 I915_WRITE(TV_CSC_V2, (color_conversion->bv << 16) |
983 color_conversion->av);
986 static void intel_tv_pre_enable(struct intel_encoder *encoder,
987 const struct intel_crtc_state *pipe_config,
988 const struct drm_connector_state *conn_state)
990 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
991 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
992 struct intel_tv *intel_tv = enc_to_tv(encoder);
993 const struct tv_mode *tv_mode = intel_tv_mode_find(conn_state);
995 u32 scctl1, scctl2, scctl3;
997 const struct video_levels *video_levels;
998 const struct color_conversion *color_conversion;
1000 int xpos = 0x0, ypos = 0x0;
1001 unsigned int xsize, ysize;
1004 return; /* can't happen (mode_prepare prevents this) */
1006 tv_ctl = I915_READ(TV_CTL);
1007 tv_ctl &= TV_CTL_SAVE;
1009 switch (intel_tv->type) {
1011 case DRM_MODE_CONNECTOR_Unknown:
1012 case DRM_MODE_CONNECTOR_Composite:
1013 tv_ctl |= TV_ENC_OUTPUT_COMPOSITE;
1014 video_levels = tv_mode->composite_levels;
1015 color_conversion = tv_mode->composite_color;
1016 burst_ena = tv_mode->burst_ena;
1018 case DRM_MODE_CONNECTOR_Component:
1019 tv_ctl |= TV_ENC_OUTPUT_COMPONENT;
1020 video_levels = &component_levels;
1021 if (tv_mode->burst_ena)
1022 color_conversion = &sdtv_csc_yprpb;
1024 color_conversion = &hdtv_csc_yprpb;
1027 case DRM_MODE_CONNECTOR_SVIDEO:
1028 tv_ctl |= TV_ENC_OUTPUT_SVIDEO;
1029 video_levels = tv_mode->svideo_levels;
1030 color_conversion = tv_mode->svideo_color;
1031 burst_ena = tv_mode->burst_ena;
1035 if (intel_crtc->pipe == 1)
1036 tv_ctl |= TV_ENC_PIPEB_SELECT;
1037 tv_ctl |= tv_mode->oversample;
1039 if (tv_mode->progressive)
1040 tv_ctl |= TV_PROGRESSIVE;
1041 if (tv_mode->trilevel_sync)
1042 tv_ctl |= TV_TRILEVEL_SYNC;
1043 if (tv_mode->pal_burst)
1044 tv_ctl |= TV_PAL_BURST;
1047 if (tv_mode->dda1_inc)
1048 scctl1 |= TV_SC_DDA1_EN;
1049 if (tv_mode->dda2_inc)
1050 scctl1 |= TV_SC_DDA2_EN;
1051 if (tv_mode->dda3_inc)
1052 scctl1 |= TV_SC_DDA3_EN;
1053 scctl1 |= tv_mode->sc_reset;
1055 scctl1 |= video_levels->burst << TV_BURST_LEVEL_SHIFT;
1056 scctl1 |= tv_mode->dda1_inc << TV_SCDDA1_INC_SHIFT;
1058 scctl2 = tv_mode->dda2_size << TV_SCDDA2_SIZE_SHIFT |
1059 tv_mode->dda2_inc << TV_SCDDA2_INC_SHIFT;
1061 scctl3 = tv_mode->dda3_size << TV_SCDDA3_SIZE_SHIFT |
1062 tv_mode->dda3_inc << TV_SCDDA3_INC_SHIFT;
1064 /* Enable two fixes for the chips that need them. */
1065 if (IS_I915GM(dev_priv))
1066 tv_ctl |= TV_ENC_C0_FIX | TV_ENC_SDP_FIX;
1068 set_tv_mode_timings(dev_priv, tv_mode, burst_ena);
1070 I915_WRITE(TV_SC_CTL_1, scctl1);
1071 I915_WRITE(TV_SC_CTL_2, scctl2);
1072 I915_WRITE(TV_SC_CTL_3, scctl3);
1074 set_color_conversion(dev_priv, color_conversion);
1076 if (INTEL_GEN(dev_priv) >= 4)
1077 I915_WRITE(TV_CLR_KNOBS, 0x00404000);
1079 I915_WRITE(TV_CLR_KNOBS, 0x00606000);
1082 I915_WRITE(TV_CLR_LEVEL,
1083 ((video_levels->black << TV_BLACK_LEVEL_SHIFT) |
1084 (video_levels->blank << TV_BLANK_LEVEL_SHIFT)));
1086 assert_pipe_disabled(dev_priv, intel_crtc->pipe);
1088 /* Filter ctl must be set before TV_WIN_SIZE */
1089 I915_WRITE(TV_FILTER_CTL_1, TV_AUTO_SCALE);
1090 xsize = tv_mode->hblank_start - tv_mode->hblank_end;
1091 if (tv_mode->progressive)
1092 ysize = tv_mode->nbr_end + 1;
1094 ysize = 2*tv_mode->nbr_end + 1;
1096 xpos += conn_state->tv.margins.left;
1097 ypos += conn_state->tv.margins.top;
1098 xsize -= (conn_state->tv.margins.left +
1099 conn_state->tv.margins.right);
1100 ysize -= (conn_state->tv.margins.top +
1101 conn_state->tv.margins.bottom);
1102 I915_WRITE(TV_WIN_POS, (xpos<<16)|ypos);
1103 I915_WRITE(TV_WIN_SIZE, (xsize<<16)|ysize);
1106 for (i = 0; i < 60; i++)
1107 I915_WRITE(TV_H_LUMA(i), tv_mode->filter_table[j++]);
1108 for (i = 0; i < 60; i++)
1109 I915_WRITE(TV_H_CHROMA(i), tv_mode->filter_table[j++]);
1110 for (i = 0; i < 43; i++)
1111 I915_WRITE(TV_V_LUMA(i), tv_mode->filter_table[j++]);
1112 for (i = 0; i < 43; i++)
1113 I915_WRITE(TV_V_CHROMA(i), tv_mode->filter_table[j++]);
1114 I915_WRITE(TV_DAC, I915_READ(TV_DAC) & TV_DAC_SAVE);
1115 I915_WRITE(TV_CTL, tv_ctl);
1118 static const struct drm_display_mode reported_modes[] = {
1120 .name = "NTSC 480i",
1123 .hsync_start = 1368,
1128 .vsync_start = 1027,
1131 .type = DRM_MODE_TYPE_DRIVER,
1136 intel_tv_detect_type(struct intel_tv *intel_tv,
1137 struct drm_connector *connector)
1139 struct drm_crtc *crtc = connector->state->crtc;
1140 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1141 struct drm_device *dev = connector->dev;
1142 struct drm_i915_private *dev_priv = to_i915(dev);
1143 u32 tv_ctl, save_tv_ctl;
1144 u32 tv_dac, save_tv_dac;
1147 /* Disable TV interrupts around load detect or we'll recurse */
1148 if (connector->polled & DRM_CONNECTOR_POLL_HPD) {
1149 spin_lock_irq(&dev_priv->irq_lock);
1150 i915_disable_pipestat(dev_priv, 0,
1151 PIPE_HOTPLUG_INTERRUPT_STATUS |
1152 PIPE_HOTPLUG_TV_INTERRUPT_STATUS);
1153 spin_unlock_irq(&dev_priv->irq_lock);
1156 save_tv_dac = tv_dac = I915_READ(TV_DAC);
1157 save_tv_ctl = tv_ctl = I915_READ(TV_CTL);
1159 /* Poll for TV detection */
1160 tv_ctl &= ~(TV_ENC_ENABLE | TV_TEST_MODE_MASK);
1161 tv_ctl |= TV_TEST_MODE_MONITOR_DETECT;
1162 if (intel_crtc->pipe == 1)
1163 tv_ctl |= TV_ENC_PIPEB_SELECT;
1165 tv_ctl &= ~TV_ENC_PIPEB_SELECT;
1167 tv_dac &= ~(TVDAC_SENSE_MASK | DAC_A_MASK | DAC_B_MASK | DAC_C_MASK);
1168 tv_dac |= (TVDAC_STATE_CHG_EN |
1179 * The TV sense state should be cleared to zero on cantiga platform. Otherwise
1180 * the TV is misdetected. This is hardware requirement.
1182 if (IS_GM45(dev_priv))
1183 tv_dac &= ~(TVDAC_STATE_CHG_EN | TVDAC_A_SENSE_CTL |
1184 TVDAC_B_SENSE_CTL | TVDAC_C_SENSE_CTL);
1186 I915_WRITE(TV_CTL, tv_ctl);
1187 I915_WRITE(TV_DAC, tv_dac);
1188 POSTING_READ(TV_DAC);
1190 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
1193 tv_dac = I915_READ(TV_DAC);
1194 DRM_DEBUG_KMS("TV detected: %x, %x\n", tv_ctl, tv_dac);
1201 if ((tv_dac & TVDAC_SENSE_MASK) == (TVDAC_B_SENSE | TVDAC_C_SENSE)) {
1202 DRM_DEBUG_KMS("Detected Composite TV connection\n");
1203 type = DRM_MODE_CONNECTOR_Composite;
1204 } else if ((tv_dac & (TVDAC_A_SENSE|TVDAC_B_SENSE)) == TVDAC_A_SENSE) {
1205 DRM_DEBUG_KMS("Detected S-Video TV connection\n");
1206 type = DRM_MODE_CONNECTOR_SVIDEO;
1207 } else if ((tv_dac & TVDAC_SENSE_MASK) == 0) {
1208 DRM_DEBUG_KMS("Detected Component TV connection\n");
1209 type = DRM_MODE_CONNECTOR_Component;
1211 DRM_DEBUG_KMS("Unrecognised TV connection\n");
1215 I915_WRITE(TV_DAC, save_tv_dac & ~TVDAC_STATE_CHG_EN);
1216 I915_WRITE(TV_CTL, save_tv_ctl);
1217 POSTING_READ(TV_CTL);
1219 /* For unknown reasons the hw barfs if we don't do this vblank wait. */
1220 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
1222 /* Restore interrupt config */
1223 if (connector->polled & DRM_CONNECTOR_POLL_HPD) {
1224 spin_lock_irq(&dev_priv->irq_lock);
1225 i915_enable_pipestat(dev_priv, 0,
1226 PIPE_HOTPLUG_INTERRUPT_STATUS |
1227 PIPE_HOTPLUG_TV_INTERRUPT_STATUS);
1228 spin_unlock_irq(&dev_priv->irq_lock);
1235 * Here we set accurate tv format according to connector type
1236 * i.e Component TV should not be assigned by NTSC or PAL
1238 static void intel_tv_find_better_format(struct drm_connector *connector)
1240 struct intel_tv *intel_tv = intel_attached_tv(connector);
1241 const struct tv_mode *tv_mode = intel_tv_mode_find(connector->state);
1244 if ((intel_tv->type == DRM_MODE_CONNECTOR_Component) ==
1245 tv_mode->component_only)
1249 for (i = 0; i < ARRAY_SIZE(tv_modes); i++) {
1250 tv_mode = tv_modes + i;
1252 if ((intel_tv->type == DRM_MODE_CONNECTOR_Component) ==
1253 tv_mode->component_only)
1257 connector->state->tv.mode = i;
1261 intel_tv_detect(struct drm_connector *connector,
1262 struct drm_modeset_acquire_ctx *ctx,
1265 struct drm_display_mode mode;
1266 struct intel_tv *intel_tv = intel_attached_tv(connector);
1267 enum drm_connector_status status;
1270 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n",
1271 connector->base.id, connector->name,
1274 mode = reported_modes[0];
1277 struct intel_load_detect_pipe tmp;
1280 ret = intel_get_load_detect_pipe(connector, &mode, &tmp, ctx);
1285 type = intel_tv_detect_type(intel_tv, connector);
1286 intel_release_load_detect_pipe(connector, &tmp, ctx);
1288 connector_status_disconnected :
1289 connector_status_connected;
1291 status = connector_status_unknown;
1293 if (status == connector_status_connected) {
1294 intel_tv->type = type;
1295 intel_tv_find_better_format(connector);
1300 return connector->status;
1303 static const struct input_res {
1306 } input_res_table[] = {
1307 {"640x480", 640, 480},
1308 {"800x600", 800, 600},
1309 {"1024x768", 1024, 768},
1310 {"1280x1024", 1280, 1024},
1311 {"848x480", 848, 480},
1312 {"1280x720", 1280, 720},
1313 {"1920x1080", 1920, 1080},
1317 * Chose preferred mode according to line number of TV format
1320 intel_tv_choose_preferred_modes(const struct tv_mode *tv_mode,
1321 struct drm_display_mode *mode_ptr)
1323 if (tv_mode->nbr_end < 480 && mode_ptr->vdisplay == 480)
1324 mode_ptr->type |= DRM_MODE_TYPE_PREFERRED;
1325 else if (tv_mode->nbr_end > 480) {
1326 if (tv_mode->progressive == true && tv_mode->nbr_end < 720) {
1327 if (mode_ptr->vdisplay == 720)
1328 mode_ptr->type |= DRM_MODE_TYPE_PREFERRED;
1329 } else if (mode_ptr->vdisplay == 1080)
1330 mode_ptr->type |= DRM_MODE_TYPE_PREFERRED;
1335 intel_tv_get_modes(struct drm_connector *connector)
1337 struct drm_display_mode *mode_ptr;
1338 const struct tv_mode *tv_mode = intel_tv_mode_find(connector->state);
1342 for (j = 0; j < ARRAY_SIZE(input_res_table);
1344 const struct input_res *input = &input_res_table[j];
1345 unsigned int hactive_s = input->w;
1346 unsigned int vactive_s = input->h;
1348 if (tv_mode->max_srcw && input->w > tv_mode->max_srcw)
1351 if (input->w > 1024 && (!tv_mode->progressive
1352 && !tv_mode->component_only))
1355 mode_ptr = drm_mode_create(connector->dev);
1358 strncpy(mode_ptr->name, input->name, DRM_DISPLAY_MODE_LEN);
1359 mode_ptr->name[DRM_DISPLAY_MODE_LEN - 1] = '\0';
1361 mode_ptr->hdisplay = hactive_s;
1362 mode_ptr->hsync_start = hactive_s + 1;
1363 mode_ptr->hsync_end = hactive_s + 64;
1364 if (mode_ptr->hsync_end <= mode_ptr->hsync_start)
1365 mode_ptr->hsync_end = mode_ptr->hsync_start + 1;
1366 mode_ptr->htotal = hactive_s + 96;
1368 mode_ptr->vdisplay = vactive_s;
1369 mode_ptr->vsync_start = vactive_s + 1;
1370 mode_ptr->vsync_end = vactive_s + 32;
1371 if (mode_ptr->vsync_end <= mode_ptr->vsync_start)
1372 mode_ptr->vsync_end = mode_ptr->vsync_start + 1;
1373 mode_ptr->vtotal = vactive_s + 33;
1375 tmp = mul_u32_u32(tv_mode->refresh, mode_ptr->vtotal);
1376 tmp *= mode_ptr->htotal;
1377 tmp = div_u64(tmp, 1000000);
1378 mode_ptr->clock = (int) tmp;
1380 mode_ptr->type = DRM_MODE_TYPE_DRIVER;
1381 intel_tv_choose_preferred_modes(tv_mode, mode_ptr);
1382 drm_mode_probed_add(connector, mode_ptr);
1390 intel_tv_destroy(struct drm_connector *connector)
1392 drm_connector_cleanup(connector);
1396 static const struct drm_connector_funcs intel_tv_connector_funcs = {
1397 .late_register = intel_connector_register,
1398 .early_unregister = intel_connector_unregister,
1399 .destroy = intel_tv_destroy,
1400 .fill_modes = drm_helper_probe_single_connector_modes,
1401 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1402 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1405 static int intel_tv_atomic_check(struct drm_connector *connector,
1406 struct drm_connector_state *new_state)
1408 struct drm_crtc_state *new_crtc_state;
1409 struct drm_connector_state *old_state;
1411 if (!new_state->crtc)
1414 old_state = drm_atomic_get_old_connector_state(new_state->state, connector);
1415 new_crtc_state = drm_atomic_get_new_crtc_state(new_state->state, new_state->crtc);
1417 if (old_state->tv.mode != new_state->tv.mode ||
1418 old_state->tv.margins.left != new_state->tv.margins.left ||
1419 old_state->tv.margins.right != new_state->tv.margins.right ||
1420 old_state->tv.margins.top != new_state->tv.margins.top ||
1421 old_state->tv.margins.bottom != new_state->tv.margins.bottom) {
1422 /* Force a modeset. */
1424 new_crtc_state->connectors_changed = true;
1430 static const struct drm_connector_helper_funcs intel_tv_connector_helper_funcs = {
1431 .detect_ctx = intel_tv_detect,
1432 .mode_valid = intel_tv_mode_valid,
1433 .get_modes = intel_tv_get_modes,
1434 .atomic_check = intel_tv_atomic_check,
1437 static const struct drm_encoder_funcs intel_tv_enc_funcs = {
1438 .destroy = intel_encoder_destroy,
1442 intel_tv_init(struct drm_i915_private *dev_priv)
1444 struct drm_device *dev = &dev_priv->drm;
1445 struct drm_connector *connector;
1446 struct intel_tv *intel_tv;
1447 struct intel_encoder *intel_encoder;
1448 struct intel_connector *intel_connector;
1449 u32 tv_dac_on, tv_dac_off, save_tv_dac;
1450 const char *tv_format_names[ARRAY_SIZE(tv_modes)];
1451 int i, initial_mode = 0;
1452 struct drm_connector_state *state;
1454 if ((I915_READ(TV_CTL) & TV_FUSE_STATE_MASK) == TV_FUSE_STATE_DISABLED)
1457 if (!intel_bios_is_tv_present(dev_priv)) {
1458 DRM_DEBUG_KMS("Integrated TV is not present.\n");
1463 * Sanity check the TV output by checking to see if the
1464 * DAC register holds a value
1466 save_tv_dac = I915_READ(TV_DAC);
1468 I915_WRITE(TV_DAC, save_tv_dac | TVDAC_STATE_CHG_EN);
1469 tv_dac_on = I915_READ(TV_DAC);
1471 I915_WRITE(TV_DAC, save_tv_dac & ~TVDAC_STATE_CHG_EN);
1472 tv_dac_off = I915_READ(TV_DAC);
1474 I915_WRITE(TV_DAC, save_tv_dac);
1477 * If the register does not hold the state change enable
1478 * bit, (either as a 0 or a 1), assume it doesn't really
1481 if ((tv_dac_on & TVDAC_STATE_CHG_EN) == 0 ||
1482 (tv_dac_off & TVDAC_STATE_CHG_EN) != 0)
1485 intel_tv = kzalloc(sizeof(*intel_tv), GFP_KERNEL);
1490 intel_connector = intel_connector_alloc();
1491 if (!intel_connector) {
1496 intel_encoder = &intel_tv->base;
1497 connector = &intel_connector->base;
1498 state = connector->state;
1501 * The documentation, for the older chipsets at least, recommend
1502 * using a polling method rather than hotplug detection for TVs.
1503 * This is because in order to perform the hotplug detection, the PLLs
1504 * for the TV must be kept alive increasing power drain and starving
1505 * bandwidth from other encoders. Notably for instance, it causes
1506 * pipe underruns on Crestline when this encoder is supposedly idle.
1508 * More recent chipsets favour HDMI rather than integrated S-Video.
1510 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
1512 drm_connector_init(dev, connector, &intel_tv_connector_funcs,
1513 DRM_MODE_CONNECTOR_SVIDEO);
1515 drm_encoder_init(dev, &intel_encoder->base, &intel_tv_enc_funcs,
1516 DRM_MODE_ENCODER_TVDAC, "TV");
1518 intel_encoder->compute_config = intel_tv_compute_config;
1519 intel_encoder->get_config = intel_tv_get_config;
1520 intel_encoder->pre_enable = intel_tv_pre_enable;
1521 intel_encoder->enable = intel_enable_tv;
1522 intel_encoder->disable = intel_disable_tv;
1523 intel_encoder->get_hw_state = intel_tv_get_hw_state;
1524 intel_connector->get_hw_state = intel_connector_get_hw_state;
1526 intel_connector_attach_encoder(intel_connector, intel_encoder);
1528 intel_encoder->type = INTEL_OUTPUT_TVOUT;
1529 intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER;
1530 intel_encoder->port = PORT_NONE;
1531 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1532 intel_encoder->cloneable = 0;
1533 intel_encoder->base.possible_crtcs = ((1 << 0) | (1 << 1));
1534 intel_tv->type = DRM_MODE_CONNECTOR_Unknown;
1536 /* BIOS margin values */
1537 state->tv.margins.left = 54;
1538 state->tv.margins.top = 36;
1539 state->tv.margins.right = 46;
1540 state->tv.margins.bottom = 37;
1542 state->tv.mode = initial_mode;
1544 drm_connector_helper_add(connector, &intel_tv_connector_helper_funcs);
1545 connector->interlace_allowed = false;
1546 connector->doublescan_allowed = false;
1548 /* Create TV properties then attach current values */
1549 for (i = 0; i < ARRAY_SIZE(tv_modes); i++)
1550 tv_format_names[i] = tv_modes[i].name;
1551 drm_mode_create_tv_properties(dev,
1552 ARRAY_SIZE(tv_modes),
1555 drm_object_attach_property(&connector->base, dev->mode_config.tv_mode_property,
1557 drm_object_attach_property(&connector->base,
1558 dev->mode_config.tv_left_margin_property,
1559 state->tv.margins.left);
1560 drm_object_attach_property(&connector->base,
1561 dev->mode_config.tv_top_margin_property,
1562 state->tv.margins.top);
1563 drm_object_attach_property(&connector->base,
1564 dev->mode_config.tv_right_margin_property,
1565 state->tv.margins.right);
1566 drm_object_attach_property(&connector->base,
1567 dev->mode_config.tv_bottom_margin_property,
1568 state->tv.margins.bottom);