drivers/gpu/drm/i915/intel_sprite.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *   Jesse Barnes <jbarnes@virtuousgeek.org>
  25  *
  26  * New plane/sprite handling.
  27  *
  28  * The older chips had a separate interface for programming plane related
  29  * registers; newer ones are much simpler and we can use the new DRM plane
  30  * support.
  31  */
  32 #include <drm/drmP.h>
  33 #include <drm/drm_crtc.h>
  34 #include <drm/drm_fourcc.h>
  35 #include <drm/drm_rect.h>
  36 #include <drm/drm_atomic.h>
  37 #include <drm/drm_plane_helper.h>
  38 #include "intel_drv.h"
  39 #include "intel_frontbuffer.h"
  40 #include <drm/i915_drm.h>
  41 #include "i915_drv.h"
  42
  43 static bool
  44 format_is_yuv(uint32_t format)
  45 {
  46         switch (format) {
  47         case DRM_FORMAT_YUYV:
  48         case DRM_FORMAT_UYVY:
  49         case DRM_FORMAT_VYUY:
  50         case DRM_FORMAT_YVYU:
  51                 return true;
  52         default:
  53                 return false;
  54         }
  55 }
  56
  57 static int usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
  58                               int usecs)
  59 {
  60         /* paranoia */
  61         if (!adjusted_mode->crtc_htotal)
  62                 return 1;
  63
  64         return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock,
  65                             1000 * adjusted_mode->crtc_htotal);
  66 }
  67
  68 /**
  69  * intel_pipe_update_start() - start update of a set of display registers
  70  * @crtc: the crtc of which the registers are going to be updated
  71  * @start_vbl_count: vblank counter return pointer used for error checking
  72  *
  73  * Mark the start of an update to pipe registers that should be updated
  74  * atomically regarding vblank. If the next vblank will happens within
  75  * the next 100 us, this function waits until the vblank passes.
  76  *
  77  * After a successful call to this function, interrupts will be disabled
  78  * until a subsequent call to intel_pipe_update_end(). That is done to
  79  * avoid random delays. The value written to @start_vbl_count should be
  80  * supplied to intel_pipe_update_end() for error checking.
  81  */
  82 void intel_pipe_update_start(struct intel_crtc *crtc)
  83 {
  84         const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
  85         long timeout = msecs_to_jiffies_timeout(1);
  86         int scanline, min, max, vblank_start;
  87         wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
  88         DEFINE_WAIT(wait);
  89
  90         vblank_start = adjusted_mode->crtc_vblank_start;
  91         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
  92                 vblank_start = DIV_ROUND_UP(vblank_start, 2);
  93
  94         /* FIXME needs to be calibrated sensibly */
  95         min = vblank_start - usecs_to_scanlines(adjusted_mode, 100);
  96         max = vblank_start - 1;
  97
  98         local_irq_disable();
  99
 100         if (min <= 0 || max <= 0)
 101                 return;
 102
 103         if (WARN_ON(drm_crtc_vblank_get(&crtc->base)))
 104                 return;
 105
 106         crtc->debug.min_vbl = min;
 107         crtc->debug.max_vbl = max;
 108         trace_i915_pipe_update_start(crtc);
 109
 110         for (;;) {
 111                 /*
 112                  * prepare_to_wait() has a memory barrier, which guarantees
 113                  * other CPUs can see the task state update by the time we
 114                  * read the scanline.
 115                  */
 116                 prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
 117
 118                 scanline = intel_get_crtc_scanline(crtc);
 119                 if (scanline < min || scanline > max)
 120                         break;
 121
 122                 if (timeout <= 0) {
 123                         DRM_ERROR("Potential atomic update failure on pipe %c\n",
 124                                   pipe_name(crtc->pipe));
 125                         break;
 126                 }
 127
 128                 local_irq_enable();
 129
 130                 timeout = schedule_timeout(timeout);
 131
 132                 local_irq_disable();
 133         }
 134
 135         finish_wait(wq, &wait);
 136
 137         drm_crtc_vblank_put(&crtc->base);
 138
 139         crtc->debug.scanline_start = scanline;
 140         crtc->debug.start_vbl_time = ktime_get();
 141         crtc->debug.start_vbl_count = intel_crtc_get_vblank_counter(crtc);
 142
 143         trace_i915_pipe_update_vblank_evaded(crtc);
 144 }
 145
 146 /**
 147  * intel_pipe_update_end() - end update of a set of display registers
 148  * @crtc: the crtc of which the registers were updated
 149  * @start_vbl_count: start vblank counter (used for error checking)
 150  *
 151  * Mark the end of an update started with intel_pipe_update_start(). This
 152  * re-enables interrupts and verifies the update was actually completed
 153  * before a vblank using the value of @start_vbl_count.
 154  */
 155 void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work)
 156 {
 157         enum pipe pipe = crtc->pipe;
 158         int scanline_end = intel_get_crtc_scanline(crtc);
 159         u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc);
 160         ktime_t end_vbl_time = ktime_get();
 161
 162         if (work) {
 163                 work->flip_queued_vblank = end_vbl_count;
 164                 smp_mb__before_atomic();
 165                 atomic_set(&work->pending, 1);
 166         }
 167
 168         trace_i915_pipe_update_end(crtc, end_vbl_count, scanline_end);
 169
 170         /* We're still in the vblank-evade critical section, this can't race.
 171          * Would be slightly nice to just grab the vblank count and arm the
 172          * event outside of the critical section - the spinlock might spin for a
 173          * while ... */
 174         if (crtc->base.state->event) {
 175                 WARN_ON(drm_crtc_vblank_get(&crtc->base) != 0);
 176
 177                 spin_lock(&crtc->base.dev->event_lock);
 178                 drm_crtc_arm_vblank_event(&crtc->base, crtc->base.state->event);
 179                 spin_unlock(&crtc->base.dev->event_lock);
 180
 181                 crtc->base.state->event = NULL;
 182         }
 183
 184         local_irq_enable();
 185
 186         if (crtc->debug.start_vbl_count &&
 187             crtc->debug.start_vbl_count != end_vbl_count) {
 188                 DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n",
 189                           pipe_name(pipe), crtc->debug.start_vbl_count,
 190                           end_vbl_count,
 191                           ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
 192                           crtc->debug.min_vbl, crtc->debug.max_vbl,
 193                           crtc->debug.scanline_start, scanline_end);
 194         }
 195 }
 196
 197 static void
 198 skl_update_plane(struct drm_plane *drm_plane,
 199                  const struct intel_crtc_state *crtc_state,
 200                  const struct intel_plane_state *plane_state)
 201 {
 202         struct drm_device *dev = drm_plane->dev;
 203         struct drm_i915_private *dev_priv = to_i915(dev);
 204         struct intel_plane *intel_plane = to_intel_plane(drm_plane);
 205         struct drm_framebuffer *fb = plane_state->base.fb;
 206         const int pipe = intel_plane->pipe;
 207         const int plane = intel_plane->plane + 1;
 208         u32 plane_ctl;
 209         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 210         u32 surf_addr;
 211         unsigned int rotation = plane_state->base.rotation;
 212         u32 stride = skl_plane_stride(fb, 0, rotation);
 213         int crtc_x = plane_state->dst.x1;
 214         int crtc_y = plane_state->dst.y1;
 215         uint32_t crtc_w = drm_rect_width(&plane_state->dst);
 216         uint32_t crtc_h = drm_rect_height(&plane_state->dst);
 217         uint32_t x = plane_state->src.x1 >> 16;
 218         uint32_t y = plane_state->src.y1 >> 16;
 219         uint32_t src_w = drm_rect_width(&plane_state->src) >> 16;
 220         uint32_t src_h = drm_rect_height(&plane_state->src) >> 16;
 221
 222         plane_ctl = PLANE_CTL_ENABLE |
 223                 PLANE_CTL_PIPE_GAMMA_ENABLE |
 224                 PLANE_CTL_PIPE_CSC_ENABLE;
 225
 226         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
 227         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
 228
 229         plane_ctl |= skl_plane_ctl_rotation(rotation);
 230
 231         if (key->flags) {
 232                 I915_WRITE(PLANE_KEYVAL(pipe, plane), key->min_value);
 233                 I915_WRITE(PLANE_KEYMAX(pipe, plane), key->max_value);
 234                 I915_WRITE(PLANE_KEYMSK(pipe, plane), key->channel_mask);
 235         }
 236
 237         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 238                 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
 239         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 240                 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
 241
 242         if (intel_rotation_90_or_270(rotation)) {
 243                 struct drm_rect r = {
 244                         .x1 = x,
 245                         .x2 = x + src_w,
 246                         .y1 = y,
 247                         .y2 = y + src_h,
 248                 };
 249
 250                 /* Rotate src coordinates to match rotated GTT view */
 251                 drm_rect_rotate(&r, fb->width, fb->height, BIT(DRM_ROTATE_270));
 252
 253                 x = r.x1;
 254                 y = r.y1;
 255                 src_w = drm_rect_width(&r);
 256                 src_h = drm_rect_height(&r);
 257         }
 258
 259         intel_add_fb_offsets(&x, &y, plane_state, 0);
 260         surf_addr = intel_compute_tile_offset(&x, &y, plane_state, 0);
 261
 262         /* Sizes are 0 based */
 263         src_w--;
 264         src_h--;
 265         crtc_w--;
 266         crtc_h--;
 267
 268         I915_WRITE(PLANE_OFFSET(pipe, plane), (y << 16) | x);
 269         I915_WRITE(PLANE_STRIDE(pipe, plane), stride);
 270         I915_WRITE(PLANE_SIZE(pipe, plane), (src_h << 16) | src_w);
 271
 272         /* program plane scaler */
 273         if (plane_state->scaler_id >= 0) {
 274                 int scaler_id = plane_state->scaler_id;
 275                 const struct intel_scaler *scaler;
 276
 277                 DRM_DEBUG_KMS("plane = %d PS_PLANE_SEL(plane) = 0x%x\n", plane,
 278                         PS_PLANE_SEL(plane));
 279
 280                 scaler = &crtc_state->scaler_state.scalers[scaler_id];
 281
 282                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id),
 283                            PS_SCALER_EN | PS_PLANE_SEL(plane) | scaler->mode);
 284                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
 285                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y);
 286                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id),
 287                         ((crtc_w + 1) << 16)|(crtc_h + 1));
 288
 289                 I915_WRITE(PLANE_POS(pipe, plane), 0);
 290         } else {
 291                 I915_WRITE(PLANE_POS(pipe, plane), (crtc_y << 16) | crtc_x);
 292         }
 293
 294         I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl);
 295         I915_WRITE(PLANE_SURF(pipe, plane),
 296                    intel_fb_gtt_offset(fb, rotation) + surf_addr);
 297         POSTING_READ(PLANE_SURF(pipe, plane));
 298 }
 299
 300 static void
 301 skl_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
 302 {
 303         struct drm_device *dev = dplane->dev;
 304         struct drm_i915_private *dev_priv = to_i915(dev);
 305         struct intel_plane *intel_plane = to_intel_plane(dplane);
 306         const int pipe = intel_plane->pipe;
 307         const int plane = intel_plane->plane + 1;
 308
 309         I915_WRITE(PLANE_CTL(pipe, plane), 0);
 310
 311         I915_WRITE(PLANE_SURF(pipe, plane), 0);
 312         POSTING_READ(PLANE_SURF(pipe, plane));
 313 }
 314
 315 static void
 316 chv_update_csc(struct intel_plane *intel_plane, uint32_t format)
 317 {
 318         struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
 319         int plane = intel_plane->plane;
 320
 321         /* Seems RGB data bypasses the CSC always */
 322         if (!format_is_yuv(format))
 323                 return;
 324
 325         /*
 326          * BT.601 limited range YCbCr -> full range RGB
 327          *
 328          * |r|   | 6537 4769     0|   |cr  |
 329          * |g| = |-3330 4769 -1605| x |y-64|
 330          * |b|   |    0 4769  8263|   |cb  |
 331          *
 332          * Cb and Cr apparently come in as signed already, so no
 333          * need for any offset. For Y we need to remove the offset.
 334          */
 335         I915_WRITE(SPCSCYGOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(-64));
 336         I915_WRITE(SPCSCCBOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0));
 337         I915_WRITE(SPCSCCROFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0));
 338
 339         I915_WRITE(SPCSCC01(plane), SPCSC_C1(4769) | SPCSC_C0(6537));
 340         I915_WRITE(SPCSCC23(plane), SPCSC_C1(-3330) | SPCSC_C0(0));
 341         I915_WRITE(SPCSCC45(plane), SPCSC_C1(-1605) | SPCSC_C0(4769));
 342         I915_WRITE(SPCSCC67(plane), SPCSC_C1(4769) | SPCSC_C0(0));
 343         I915_WRITE(SPCSCC8(plane), SPCSC_C0(8263));
 344
 345         I915_WRITE(SPCSCYGICLAMP(plane), SPCSC_IMAX(940) | SPCSC_IMIN(64));
 346         I915_WRITE(SPCSCCBICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
 347         I915_WRITE(SPCSCCRICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
 348
 349         I915_WRITE(SPCSCYGOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 350         I915_WRITE(SPCSCCBOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 351         I915_WRITE(SPCSCCROCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 352 }
 353
 354 static void
 355 vlv_update_plane(struct drm_plane *dplane,
 356                  const struct intel_crtc_state *crtc_state,
 357                  const struct intel_plane_state *plane_state)
 358 {
 359         struct drm_device *dev = dplane->dev;
 360         struct drm_i915_private *dev_priv = to_i915(dev);
 361         struct intel_plane *intel_plane = to_intel_plane(dplane);
 362         struct drm_framebuffer *fb = plane_state->base.fb;
 363         int pipe = intel_plane->pipe;
 364         int plane = intel_plane->plane;
 365         u32 sprctl;
 366         u32 sprsurf_offset, linear_offset;
 367         unsigned int rotation = dplane->state->rotation;
 368         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 369         int crtc_x = plane_state->dst.x1;
 370         int crtc_y = plane_state->dst.y1;
 371         uint32_t crtc_w = drm_rect_width(&plane_state->dst);
 372         uint32_t crtc_h = drm_rect_height(&plane_state->dst);
 373         uint32_t x = plane_state->src.x1 >> 16;
 374         uint32_t y = plane_state->src.y1 >> 16;
 375         uint32_t src_w = drm_rect_width(&plane_state->src) >> 16;
 376         uint32_t src_h = drm_rect_height(&plane_state->src) >> 16;
 377
 378         sprctl = SP_ENABLE;
 379
 380         switch (fb->pixel_format) {
 381         case DRM_FORMAT_YUYV:
 382                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV;
 383                 break;
 384         case DRM_FORMAT_YVYU:
 385                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU;
 386                 break;
 387         case DRM_FORMAT_UYVY:
 388                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY;
 389                 break;
 390         case DRM_FORMAT_VYUY:
 391                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
 392                 break;
 393         case DRM_FORMAT_RGB565:
 394                 sprctl |= SP_FORMAT_BGR565;
 395                 break;
 396         case DRM_FORMAT_XRGB8888:
 397                 sprctl |= SP_FORMAT_BGRX8888;
 398                 break;
 399         case DRM_FORMAT_ARGB8888:
 400                 sprctl |= SP_FORMAT_BGRA8888;
 401                 break;
 402         case DRM_FORMAT_XBGR2101010:
 403                 sprctl |= SP_FORMAT_RGBX1010102;
 404                 break;
 405         case DRM_FORMAT_ABGR2101010:
 406                 sprctl |= SP_FORMAT_RGBA1010102;
 407                 break;
 408         case DRM_FORMAT_XBGR8888:
 409                 sprctl |= SP_FORMAT_RGBX8888;
 410                 break;
 411         case DRM_FORMAT_ABGR8888:
 412                 sprctl |= SP_FORMAT_RGBA8888;
 413                 break;
 414         default:
 415                 /*
 416                  * If we get here one of the upper layers failed to filter
 417                  * out the unsupported plane formats
 418                  */
 419                 BUG();
 420                 break;
 421         }
 422
 423         /*
 424          * Enable gamma to match primary/cursor plane behaviour.
 425          * FIXME should be user controllable via propertiesa.
 426          */
 427         sprctl |= SP_GAMMA_ENABLE;
 428
 429         if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
 430                 sprctl |= SP_TILED;
 431
 432         /* Sizes are 0 based */
 433         src_w--;
 434         src_h--;
 435         crtc_w--;
 436         crtc_h--;
 437
 438         intel_add_fb_offsets(&x, &y, plane_state, 0);
 439         sprsurf_offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
 440
 441         if (rotation == BIT(DRM_ROTATE_180)) {
 442                 sprctl |= SP_ROTATE_180;
 443
 444                 x += src_w;
 445                 y += src_h;
 446         }
 447
 448         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 449
 450         if (key->flags) {
 451                 I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value);
 452                 I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value);
 453                 I915_WRITE(SPKEYMSK(pipe, plane), key->channel_mask);
 454         }
 455
 456         if (key->flags & I915_SET_COLORKEY_SOURCE)
 457                 sprctl |= SP_SOURCE_KEY;
 458
 459         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B)
 460                 chv_update_csc(intel_plane, fb->pixel_format);
 461
 462         I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]);
 463         I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x);
 464
 465         if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
 466                 I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x);
 467         else
 468                 I915_WRITE(SPLINOFF(pipe, plane), linear_offset);
 469
 470         I915_WRITE(SPCONSTALPHA(pipe, plane), 0);
 471
 472         I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w);
 473         I915_WRITE(SPCNTR(pipe, plane), sprctl);
 474         I915_WRITE(SPSURF(pipe, plane),
 475                    intel_fb_gtt_offset(fb, rotation) + sprsurf_offset);
 476         POSTING_READ(SPSURF(pipe, plane));
 477 }
 478
 479 static void
 480 vlv_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
 481 {
 482         struct drm_device *dev = dplane->dev;
 483         struct drm_i915_private *dev_priv = to_i915(dev);
 484         struct intel_plane *intel_plane = to_intel_plane(dplane);
 485         int pipe = intel_plane->pipe;
 486         int plane = intel_plane->plane;
 487
 488         I915_WRITE(SPCNTR(pipe, plane), 0);
 489
 490         I915_WRITE(SPSURF(pipe, plane), 0);
 491         POSTING_READ(SPSURF(pipe, plane));
 492 }
 493
 494 static void
 495 ivb_update_plane(struct drm_plane *plane,
 496                  const struct intel_crtc_state *crtc_state,
 497                  const struct intel_plane_state *plane_state)
 498 {
 499         struct drm_device *dev = plane->dev;
 500         struct drm_i915_private *dev_priv = to_i915(dev);
 501         struct intel_plane *intel_plane = to_intel_plane(plane);
 502         struct drm_framebuffer *fb = plane_state->base.fb;
 503         enum pipe pipe = intel_plane->pipe;
 504         u32 sprctl, sprscale = 0;
 505         u32 sprsurf_offset, linear_offset;
 506         unsigned int rotation = plane_state->base.rotation;
 507         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 508         int crtc_x = plane_state->dst.x1;
 509         int crtc_y = plane_state->dst.y1;
 510         uint32_t crtc_w = drm_rect_width(&plane_state->dst);
 511         uint32_t crtc_h = drm_rect_height(&plane_state->dst);
 512         uint32_t x = plane_state->src.x1 >> 16;
 513         uint32_t y = plane_state->src.y1 >> 16;
 514         uint32_t src_w = drm_rect_width(&plane_state->src) >> 16;
 515         uint32_t src_h = drm_rect_height(&plane_state->src) >> 16;
 516
 517         sprctl = SPRITE_ENABLE;
 518
 519         switch (fb->pixel_format) {
 520         case DRM_FORMAT_XBGR8888:
 521                 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
 522                 break;
 523         case DRM_FORMAT_XRGB8888:
 524                 sprctl |= SPRITE_FORMAT_RGBX888;
 525                 break;
 526         case DRM_FORMAT_YUYV:
 527                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
 528                 break;
 529         case DRM_FORMAT_YVYU:
 530                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
 531                 break;
 532         case DRM_FORMAT_UYVY:
 533                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
 534                 break;
 535         case DRM_FORMAT_VYUY:
 536                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
 537                 break;
 538         default:
 539                 BUG();
 540         }
 541
 542         /*
 543          * Enable gamma to match primary/cursor plane behaviour.
 544          * FIXME should be user controllable via propertiesa.
 545          */
 546         sprctl |= SPRITE_GAMMA_ENABLE;
 547
 548         if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
 549                 sprctl |= SPRITE_TILED;
 550
 551         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 552                 sprctl &= ~SPRITE_TRICKLE_FEED_DISABLE;
 553         else
 554                 sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
 555
 556         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 557                 sprctl |= SPRITE_PIPE_CSC_ENABLE;
 558
 559         /* Sizes are 0 based */
 560         src_w--;
 561         src_h--;
 562         crtc_w--;
 563         crtc_h--;
 564
 565         if (crtc_w != src_w || crtc_h != src_h)
 566                 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
 567
 568         intel_add_fb_offsets(&x, &y, plane_state, 0);
 569         sprsurf_offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
 570
 571         if (rotation == BIT(DRM_ROTATE_180)) {
 572                 sprctl |= SPRITE_ROTATE_180;
 573
 574                 /* HSW and BDW does this automagically in hardware */
 575                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
 576                         x += src_w;
 577                         y += src_h;
 578                 }
 579         }
 580
 581         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 582
 583         if (key->flags) {
 584                 I915_WRITE(SPRKEYVAL(pipe), key->min_value);
 585                 I915_WRITE(SPRKEYMAX(pipe), key->max_value);
 586                 I915_WRITE(SPRKEYMSK(pipe), key->channel_mask);
 587         }
 588
 589         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 590                 sprctl |= SPRITE_DEST_KEY;
 591         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 592                 sprctl |= SPRITE_SOURCE_KEY;
 593
 594         I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]);
 595         I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
 596
 597         /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
 598          * register */
 599         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 600                 I915_WRITE(SPROFFSET(pipe), (y << 16) | x);
 601         else if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
 602                 I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x);
 603         else
 604                 I915_WRITE(SPRLINOFF(pipe), linear_offset);
 605
 606         I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
 607         if (intel_plane->can_scale)
 608                 I915_WRITE(SPRSCALE(pipe), sprscale);
 609         I915_WRITE(SPRCTL(pipe), sprctl);
 610         I915_WRITE(SPRSURF(pipe),
 611                    intel_fb_gtt_offset(fb, rotation) + sprsurf_offset);
 612         POSTING_READ(SPRSURF(pipe));
 613 }
 614
 615 static void
 616 ivb_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
 617 {
 618         struct drm_device *dev = plane->dev;
 619         struct drm_i915_private *dev_priv = to_i915(dev);
 620         struct intel_plane *intel_plane = to_intel_plane(plane);
 621         int pipe = intel_plane->pipe;
 622
 623         I915_WRITE(SPRCTL(pipe), 0);
 624         /* Can't leave the scaler enabled... */
 625         if (intel_plane->can_scale)
 626                 I915_WRITE(SPRSCALE(pipe), 0);
 627
 628         I915_WRITE(SPRSURF(pipe), 0);
 629         POSTING_READ(SPRSURF(pipe));
 630 }
 631
 632 static void
 633 ilk_update_plane(struct drm_plane *plane,
 634                  const struct intel_crtc_state *crtc_state,
 635                  const struct intel_plane_state *plane_state)
 636 {
 637         struct drm_device *dev = plane->dev;
 638         struct drm_i915_private *dev_priv = to_i915(dev);
 639         struct intel_plane *intel_plane = to_intel_plane(plane);
 640         struct drm_framebuffer *fb = plane_state->base.fb;
 641         int pipe = intel_plane->pipe;
 642         u32 dvscntr, dvsscale;
 643         u32 dvssurf_offset, linear_offset;
 644         unsigned int rotation = plane_state->base.rotation;
 645         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 646         int crtc_x = plane_state->dst.x1;
 647         int crtc_y = plane_state->dst.y1;
 648         uint32_t crtc_w = drm_rect_width(&plane_state->dst);
 649         uint32_t crtc_h = drm_rect_height(&plane_state->dst);
 650         uint32_t x = plane_state->src.x1 >> 16;
 651         uint32_t y = plane_state->src.y1 >> 16;
 652         uint32_t src_w = drm_rect_width(&plane_state->src) >> 16;
 653         uint32_t src_h = drm_rect_height(&plane_state->src) >> 16;
 654
 655         dvscntr = DVS_ENABLE;
 656
 657         switch (fb->pixel_format) {
 658         case DRM_FORMAT_XBGR8888:
 659                 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
 660                 break;
 661         case DRM_FORMAT_XRGB8888:
 662                 dvscntr |= DVS_FORMAT_RGBX888;
 663                 break;
 664         case DRM_FORMAT_YUYV:
 665                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
 666                 break;
 667         case DRM_FORMAT_YVYU:
 668                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
 669                 break;
 670         case DRM_FORMAT_UYVY:
 671                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
 672                 break;
 673         case DRM_FORMAT_VYUY:
 674                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
 675                 break;
 676         default:
 677                 BUG();
 678         }
 679
 680         /*
 681          * Enable gamma to match primary/cursor plane behaviour.
 682          * FIXME should be user controllable via propertiesa.
 683          */
 684         dvscntr |= DVS_GAMMA_ENABLE;
 685
 686         if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
 687                 dvscntr |= DVS_TILED;
 688
 689         if (IS_GEN6(dev))
 690                 dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */
 691
 692         /* Sizes are 0 based */
 693         src_w--;
 694         src_h--;
 695         crtc_w--;
 696         crtc_h--;
 697
 698         dvsscale = 0;
 699         if (crtc_w != src_w || crtc_h != src_h)
 700                 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
 701
 702         intel_add_fb_offsets(&x, &y, plane_state, 0);
 703         dvssurf_offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
 704
 705         if (rotation == BIT(DRM_ROTATE_180)) {
 706                 dvscntr |= DVS_ROTATE_180;
 707
 708                 x += src_w;
 709                 y += src_h;
 710         }
 711
 712         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 713
 714         if (key->flags) {
 715                 I915_WRITE(DVSKEYVAL(pipe), key->min_value);
 716                 I915_WRITE(DVSKEYMAX(pipe), key->max_value);
 717                 I915_WRITE(DVSKEYMSK(pipe), key->channel_mask);
 718         }
 719
 720         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 721                 dvscntr |= DVS_DEST_KEY;
 722         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 723                 dvscntr |= DVS_SOURCE_KEY;
 724
 725         I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]);
 726         I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
 727
 728         if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
 729                 I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x);
 730         else
 731                 I915_WRITE(DVSLINOFF(pipe), linear_offset);
 732
 733         I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
 734         I915_WRITE(DVSSCALE(pipe), dvsscale);
 735         I915_WRITE(DVSCNTR(pipe), dvscntr);
 736         I915_WRITE(DVSSURF(pipe),
 737                    intel_fb_gtt_offset(fb, rotation) + dvssurf_offset);
 738         POSTING_READ(DVSSURF(pipe));
 739 }
 740
 741 static void
 742 ilk_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
 743 {
 744         struct drm_device *dev = plane->dev;
 745         struct drm_i915_private *dev_priv = to_i915(dev);
 746         struct intel_plane *intel_plane = to_intel_plane(plane);
 747         int pipe = intel_plane->pipe;
 748
 749         I915_WRITE(DVSCNTR(pipe), 0);
 750         /* Disable the scaler */
 751         I915_WRITE(DVSSCALE(pipe), 0);
 752
 753         I915_WRITE(DVSSURF(pipe), 0);
 754         POSTING_READ(DVSSURF(pipe));
 755 }
 756
 757 static int
 758 intel_check_sprite_plane(struct drm_plane *plane,
 759                          struct intel_crtc_state *crtc_state,
 760                          struct intel_plane_state *state)
 761 {
 762         struct drm_device *dev = plane->dev;
 763         struct drm_crtc *crtc = state->base.crtc;
 764         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 765         struct intel_plane *intel_plane = to_intel_plane(plane);
 766         struct drm_framebuffer *fb = state->base.fb;
 767         int crtc_x, crtc_y;
 768         unsigned int crtc_w, crtc_h;
 769         uint32_t src_x, src_y, src_w, src_h;
 770         struct drm_rect *src = &state->src;
 771         struct drm_rect *dst = &state->dst;
 772         const struct drm_rect *clip = &state->clip;
 773         int hscale, vscale;
 774         int max_scale, min_scale;
 775         bool can_scale;
 776
 777         if (!fb) {
 778                 state->visible = false;
 779                 return 0;
 780         }
 781
 782         /* Don't modify another pipe's plane */
 783         if (intel_plane->pipe != intel_crtc->pipe) {
 784                 DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n");
 785                 return -EINVAL;
 786         }
 787
 788         /* FIXME check all gen limits */
 789         if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > 16384) {
 790                 DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n");
 791                 return -EINVAL;
 792         }
 793
 794         /* setup can_scale, min_scale, max_scale */
 795         if (INTEL_INFO(dev)->gen >= 9) {
 796                 /* use scaler when colorkey is not required */
 797                 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
 798                         can_scale = 1;
 799                         min_scale = 1;
 800                         max_scale = skl_max_scale(intel_crtc, crtc_state);
 801                 } else {
 802                         can_scale = 0;
 803                         min_scale = DRM_PLANE_HELPER_NO_SCALING;
 804                         max_scale = DRM_PLANE_HELPER_NO_SCALING;
 805                 }
 806         } else {
 807                 can_scale = intel_plane->can_scale;
 808                 max_scale = intel_plane->max_downscale << 16;
 809                 min_scale = intel_plane->can_scale ? 1 : (1 << 16);
 810         }
 811
 812         /*
 813          * FIXME the following code does a bunch of fuzzy adjustments to the
 814          * coordinates and sizes. We probably need some way to decide whether
 815          * more strict checking should be done instead.
 816          */
 817         drm_rect_rotate(src, fb->width << 16, fb->height << 16,
 818                         state->base.rotation);
 819
 820         hscale = drm_rect_calc_hscale_relaxed(src, dst, min_scale, max_scale);
 821         BUG_ON(hscale < 0);
 822
 823         vscale = drm_rect_calc_vscale_relaxed(src, dst, min_scale, max_scale);
 824         BUG_ON(vscale < 0);
 825
 826         state->visible = drm_rect_clip_scaled(src, dst, clip, hscale, vscale);
 827
 828         crtc_x = dst->x1;
 829         crtc_y = dst->y1;
 830         crtc_w = drm_rect_width(dst);
 831         crtc_h = drm_rect_height(dst);
 832
 833         if (state->visible) {
 834                 /* check again in case clipping clamped the results */
 835                 hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale);
 836                 if (hscale < 0) {
 837                         DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n");
 838                         drm_rect_debug_print("src: ", src, true);
 839                         drm_rect_debug_print("dst: ", dst, false);
 840
 841                         return hscale;
 842                 }
 843
 844                 vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale);
 845                 if (vscale < 0) {
 846                         DRM_DEBUG_KMS("Vertical scaling factor out of limits\n");
 847                         drm_rect_debug_print("src: ", src, true);
 848                         drm_rect_debug_print("dst: ", dst, false);
 849
 850                         return vscale;
 851                 }
 852
 853                 /* Make the source viewport size an exact multiple of the scaling factors. */
 854                 drm_rect_adjust_size(src,
 855                                      drm_rect_width(dst) * hscale - drm_rect_width(src),
 856                                      drm_rect_height(dst) * vscale - drm_rect_height(src));
 857
 858                 drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16,
 859                                     state->base.rotation);
 860
 861                 /* sanity check to make sure the src viewport wasn't enlarged */
 862                 WARN_ON(src->x1 < (int) state->base.src_x ||
 863                         src->y1 < (int) state->base.src_y ||
 864                         src->x2 > (int) state->base.src_x + state->base.src_w ||
 865                         src->y2 > (int) state->base.src_y + state->base.src_h);
 866
 867                 /*
 868                  * Hardware doesn't handle subpixel coordinates.
 869                  * Adjust to (macro)pixel boundary, but be careful not to
 870                  * increase the source viewport size, because that could
 871                  * push the downscaling factor out of bounds.
 872                  */
 873                 src_x = src->x1 >> 16;
 874                 src_w = drm_rect_width(src) >> 16;
 875                 src_y = src->y1 >> 16;
 876                 src_h = drm_rect_height(src) >> 16;
 877
 878                 if (format_is_yuv(fb->pixel_format)) {
 879                         src_x &= ~1;
 880                         src_w &= ~1;
 881
 882                         /*
 883                          * Must keep src and dst the
 884                          * same if we can't scale.
 885                          */
 886                         if (!can_scale)
 887                                 crtc_w &= ~1;
 888
 889                         if (crtc_w == 0)
 890                                 state->visible = false;
 891                 }
 892         }
 893
 894         /* Check size restrictions when scaling */
 895         if (state->visible && (src_w != crtc_w || src_h != crtc_h)) {
 896                 unsigned int width_bytes;
 897                 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
 898
 899                 WARN_ON(!can_scale);
 900
 901                 /* FIXME interlacing min height is 6 */
 902
 903                 if (crtc_w < 3 || crtc_h < 3)
 904                         state->visible = false;
 905
 906                 if (src_w < 3 || src_h < 3)
 907                         state->visible = false;
 908
 909                 width_bytes = ((src_x * cpp) & 63) + src_w * cpp;
 910
 911                 if (INTEL_INFO(dev)->gen < 9 && (src_w > 2048 || src_h > 2048 ||
 912                     width_bytes > 4096 || fb->pitches[0] > 4096)) {
 913                         DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
 914                         return -EINVAL;
 915                 }
 916         }
 917
 918         if (state->visible) {
 919                 src->x1 = src_x << 16;
 920                 src->x2 = (src_x + src_w) << 16;
 921                 src->y1 = src_y << 16;
 922                 src->y2 = (src_y + src_h) << 16;
 923         }
 924
 925         dst->x1 = crtc_x;
 926         dst->x2 = crtc_x + crtc_w;
 927         dst->y1 = crtc_y;
 928         dst->y2 = crtc_y + crtc_h;
 929
 930         return 0;
 931 }
 932
 933 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
 934                               struct drm_file *file_priv)
 935 {
 936         struct drm_intel_sprite_colorkey *set = data;
 937         struct drm_plane *plane;
 938         struct drm_plane_state *plane_state;
 939         struct drm_atomic_state *state;
 940         struct drm_modeset_acquire_ctx ctx;
 941         int ret = 0;
 942
 943         /* Make sure we don't try to enable both src & dest simultaneously */
 944         if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
 945                 return -EINVAL;
 946
 947         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
 948             set->flags & I915_SET_COLORKEY_DESTINATION)
 949                 return -EINVAL;
 950
 951         plane = drm_plane_find(dev, set->plane_id);
 952         if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY)
 953                 return -ENOENT;
 954
 955         drm_modeset_acquire_init(&ctx, 0);
 956
 957         state = drm_atomic_state_alloc(plane->dev);
 958         if (!state) {
 959                 ret = -ENOMEM;
 960                 goto out;
 961         }
 962         state->acquire_ctx = &ctx;
 963
 964         while (1) {
 965                 plane_state = drm_atomic_get_plane_state(state, plane);
 966                 ret = PTR_ERR_OR_ZERO(plane_state);
 967                 if (!ret) {
 968                         to_intel_plane_state(plane_state)->ckey = *set;
 969                         ret = drm_atomic_commit(state);
 970                 }
 971
 972                 if (ret != -EDEADLK)
 973                         break;
 974
 975                 drm_atomic_state_clear(state);
 976                 drm_modeset_backoff(&ctx);
 977         }
 978
 979         if (ret)
 980                 drm_atomic_state_free(state);
 981
 982 out:
 983         drm_modeset_drop_locks(&ctx);
 984         drm_modeset_acquire_fini(&ctx);
 985         return ret;
 986 }
 987
 988 static const uint32_t ilk_plane_formats[] = {
 989         DRM_FORMAT_XRGB8888,
 990         DRM_FORMAT_YUYV,
 991         DRM_FORMAT_YVYU,
 992         DRM_FORMAT_UYVY,
 993         DRM_FORMAT_VYUY,
 994 };
 995
 996 static const uint32_t snb_plane_formats[] = {
 997         DRM_FORMAT_XBGR8888,
 998         DRM_FORMAT_XRGB8888,
 999         DRM_FORMAT_YUYV,
1000         DRM_FORMAT_YVYU,
1001         DRM_FORMAT_UYVY,
1002         DRM_FORMAT_VYUY,
1003 };
1004
1005 static const uint32_t vlv_plane_formats[] = {
1006         DRM_FORMAT_RGB565,
1007         DRM_FORMAT_ABGR8888,
1008         DRM_FORMAT_ARGB8888,
1009         DRM_FORMAT_XBGR8888,
1010         DRM_FORMAT_XRGB8888,
1011         DRM_FORMAT_XBGR2101010,
1012         DRM_FORMAT_ABGR2101010,
1013         DRM_FORMAT_YUYV,
1014         DRM_FORMAT_YVYU,
1015         DRM_FORMAT_UYVY,
1016         DRM_FORMAT_VYUY,
1017 };
1018
1019 static uint32_t skl_plane_formats[] = {
1020         DRM_FORMAT_RGB565,
1021         DRM_FORMAT_ABGR8888,
1022         DRM_FORMAT_ARGB8888,
1023         DRM_FORMAT_XBGR8888,
1024         DRM_FORMAT_XRGB8888,
1025         DRM_FORMAT_YUYV,
1026         DRM_FORMAT_YVYU,
1027         DRM_FORMAT_UYVY,
1028         DRM_FORMAT_VYUY,
1029 };
1030
1031 int
1032 intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
1033 {
1034         struct intel_plane *intel_plane = NULL;
1035         struct intel_plane_state *state = NULL;
1036         unsigned long possible_crtcs;
1037         const uint32_t *plane_formats;
1038         int num_plane_formats;
1039         int ret;
1040
1041         if (INTEL_INFO(dev)->gen < 5)
1042                 return -ENODEV;
1043
1044         intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL);
1045         if (!intel_plane) {
1046                 ret = -ENOMEM;
1047                 goto fail;
1048         }
1049
1050         state = intel_create_plane_state(&intel_plane->base);
1051         if (!state) {
1052                 ret = -ENOMEM;
1053                 goto fail;
1054         }
1055         intel_plane->base.state = &state->base;
1056
1057         switch (INTEL_INFO(dev)->gen) {
1058         case 5:
1059         case 6:
1060                 intel_plane->can_scale = true;
1061                 intel_plane->max_downscale = 16;
1062                 intel_plane->update_plane = ilk_update_plane;
1063                 intel_plane->disable_plane = ilk_disable_plane;
1064
1065                 if (IS_GEN6(dev)) {
1066                         plane_formats = snb_plane_formats;
1067                         num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1068                 } else {
1069                         plane_formats = ilk_plane_formats;
1070                         num_plane_formats = ARRAY_SIZE(ilk_plane_formats);
1071                 }
1072                 break;
1073
1074         case 7:
1075         case 8:
1076                 if (IS_IVYBRIDGE(dev)) {
1077                         intel_plane->can_scale = true;
1078                         intel_plane->max_downscale = 2;
1079                 } else {
1080                         intel_plane->can_scale = false;
1081                         intel_plane->max_downscale = 1;
1082                 }
1083
1084                 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1085                         intel_plane->update_plane = vlv_update_plane;
1086                         intel_plane->disable_plane = vlv_disable_plane;
1087
1088                         plane_formats = vlv_plane_formats;
1089                         num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
1090                 } else {
1091                         intel_plane->update_plane = ivb_update_plane;
1092                         intel_plane->disable_plane = ivb_disable_plane;
1093
1094                         plane_formats = snb_plane_formats;
1095                         num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1096                 }
1097                 break;
1098         case 9:
1099                 intel_plane->can_scale = true;
1100                 intel_plane->update_plane = skl_update_plane;
1101                 intel_plane->disable_plane = skl_disable_plane;
1102                 state->scaler_id = -1;
1103
1104                 plane_formats = skl_plane_formats;
1105                 num_plane_formats = ARRAY_SIZE(skl_plane_formats);
1106                 break;
1107         default:
1108                 MISSING_CASE(INTEL_INFO(dev)->gen);
1109                 ret = -ENODEV;
1110                 goto fail;
1111         }
1112
1113         intel_plane->pipe = pipe;
1114         intel_plane->plane = plane;
1115         intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER_SPRITE(pipe, plane);
1116         intel_plane->check_plane = intel_check_sprite_plane;
1117
1118         possible_crtcs = (1 << pipe);
1119
1120         if (INTEL_INFO(dev)->gen >= 9)
1121                 ret = drm_universal_plane_init(dev, &intel_plane->base, possible_crtcs,
1122                                                &intel_plane_funcs,
1123                                                plane_formats, num_plane_formats,
1124                                                DRM_PLANE_TYPE_OVERLAY,
1125                                                "plane %d%c", plane + 2, pipe_name(pipe));
1126         else
1127                 ret = drm_universal_plane_init(dev, &intel_plane->base, possible_crtcs,
1128                                                &intel_plane_funcs,
1129                                                plane_formats, num_plane_formats,
1130                                                DRM_PLANE_TYPE_OVERLAY,
1131                                                "sprite %c", sprite_name(pipe, plane));
1132         if (ret)
1133                 goto fail;
1134
1135         intel_create_rotation_property(dev, intel_plane);
1136
1137         drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs);
1138
1139         return 0;
1140
1141 fail:
1142         kfree(state);
1143         kfree(intel_plane);
1144
1145         return ret;
1146 }