drivers/gpu/drm/i915/intel_sprite.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *   Jesse Barnes <jbarnes@virtuousgeek.org>
  25  *
  26  * New plane/sprite handling.
  27  *
  28  * The older chips had a separate interface for programming plane related
  29  * registers; newer ones are much simpler and we can use the new DRM plane
  30  * support.
  31  */
  32 #include <drm/drmP.h>
  33 #include <drm/drm_crtc.h>
  34 #include <drm/drm_fourcc.h>
  35 #include <drm/drm_rect.h>
  36 #include <drm/drm_atomic.h>
  37 #include <drm/drm_plane_helper.h>
  38 #include "intel_drv.h"
  39 #include "intel_frontbuffer.h"
  40 #include <drm/i915_drm.h>
  41 #include "i915_drv.h"
  42
  43 static bool
  44 format_is_yuv(uint32_t format)
  45 {
  46         switch (format) {
  47         case DRM_FORMAT_YUYV:
  48         case DRM_FORMAT_UYVY:
  49         case DRM_FORMAT_VYUY:
  50         case DRM_FORMAT_YVYU:
  51                 return true;
  52         default:
  53                 return false;
  54         }
  55 }
  56
  57 static int usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
  58                               int usecs)
  59 {
  60         /* paranoia */
  61         if (!adjusted_mode->crtc_htotal)
  62                 return 1;
  63
  64         return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock,
  65                             1000 * adjusted_mode->crtc_htotal);
  66 }
  67
  68 /**
  69  * intel_pipe_update_start() - start update of a set of display registers
  70  * @crtc: the crtc of which the registers are going to be updated
  71  * @start_vbl_count: vblank counter return pointer used for error checking
  72  *
  73  * Mark the start of an update to pipe registers that should be updated
  74  * atomically regarding vblank. If the next vblank will happens within
  75  * the next 100 us, this function waits until the vblank passes.
  76  *
  77  * After a successful call to this function, interrupts will be disabled
  78  * until a subsequent call to intel_pipe_update_end(). That is done to
  79  * avoid random delays. The value written to @start_vbl_count should be
  80  * supplied to intel_pipe_update_end() for error checking.
  81  */
  82 void intel_pipe_update_start(struct intel_crtc *crtc)
  83 {
  84         const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
  85         long timeout = msecs_to_jiffies_timeout(1);
  86         int scanline, min, max, vblank_start;
  87         wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
  88         DEFINE_WAIT(wait);
  89
  90         vblank_start = adjusted_mode->crtc_vblank_start;
  91         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
  92                 vblank_start = DIV_ROUND_UP(vblank_start, 2);
  93
  94         /* FIXME needs to be calibrated sensibly */
  95         min = vblank_start - usecs_to_scanlines(adjusted_mode, 100);
  96         max = vblank_start - 1;
  97
  98         local_irq_disable();
  99
 100         if (min <= 0 || max <= 0)
 101                 return;
 102
 103         if (WARN_ON(drm_crtc_vblank_get(&crtc->base)))
 104                 return;
 105
 106         crtc->debug.min_vbl = min;
 107         crtc->debug.max_vbl = max;
 108         trace_i915_pipe_update_start(crtc);
 109
 110         for (;;) {
 111                 /*
 112                  * prepare_to_wait() has a memory barrier, which guarantees
 113                  * other CPUs can see the task state update by the time we
 114                  * read the scanline.
 115                  */
 116                 prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
 117
 118                 scanline = intel_get_crtc_scanline(crtc);
 119                 if (scanline < min || scanline > max)
 120                         break;
 121
 122                 if (timeout <= 0) {
 123                         DRM_ERROR("Potential atomic update failure on pipe %c\n",
 124                                   pipe_name(crtc->pipe));
 125                         break;
 126                 }
 127
 128                 local_irq_enable();
 129
 130                 timeout = schedule_timeout(timeout);
 131
 132                 local_irq_disable();
 133         }
 134
 135         finish_wait(wq, &wait);
 136
 137         drm_crtc_vblank_put(&crtc->base);
 138
 139         crtc->debug.scanline_start = scanline;
 140         crtc->debug.start_vbl_time = ktime_get();
 141         crtc->debug.start_vbl_count = intel_crtc_get_vblank_counter(crtc);
 142
 143         trace_i915_pipe_update_vblank_evaded(crtc);
 144 }
 145
 146 /**
 147  * intel_pipe_update_end() - end update of a set of display registers
 148  * @crtc: the crtc of which the registers were updated
 149  * @start_vbl_count: start vblank counter (used for error checking)
 150  *
 151  * Mark the end of an update started with intel_pipe_update_start(). This
 152  * re-enables interrupts and verifies the update was actually completed
 153  * before a vblank using the value of @start_vbl_count.
 154  */
 155 void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work)
 156 {
 157         enum pipe pipe = crtc->pipe;
 158         int scanline_end = intel_get_crtc_scanline(crtc);
 159         u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc);
 160         ktime_t end_vbl_time = ktime_get();
 161
 162         if (work) {
 163                 work->flip_queued_vblank = end_vbl_count;
 164                 smp_mb__before_atomic();
 165                 atomic_set(&work->pending, 1);
 166         }
 167
 168         trace_i915_pipe_update_end(crtc, end_vbl_count, scanline_end);
 169
 170         /* We're still in the vblank-evade critical section, this can't race.
 171          * Would be slightly nice to just grab the vblank count and arm the
 172          * event outside of the critical section - the spinlock might spin for a
 173          * while ... */
 174         if (crtc->base.state->event) {
 175                 WARN_ON(drm_crtc_vblank_get(&crtc->base) != 0);
 176
 177                 spin_lock(&crtc->base.dev->event_lock);
 178                 drm_crtc_arm_vblank_event(&crtc->base, crtc->base.state->event);
 179                 spin_unlock(&crtc->base.dev->event_lock);
 180
 181                 crtc->base.state->event = NULL;
 182         }
 183
 184         local_irq_enable();
 185
 186         if (crtc->debug.start_vbl_count &&
 187             crtc->debug.start_vbl_count != end_vbl_count) {
 188                 DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n",
 189                           pipe_name(pipe), crtc->debug.start_vbl_count,
 190                           end_vbl_count,
 191                           ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
 192                           crtc->debug.min_vbl, crtc->debug.max_vbl,
 193                           crtc->debug.scanline_start, scanline_end);
 194         }
 195 }
 196
 197 static void
 198 skl_update_plane(struct drm_plane *drm_plane,
 199                  const struct intel_crtc_state *crtc_state,
 200                  const struct intel_plane_state *plane_state)
 201 {
 202         struct drm_device *dev = drm_plane->dev;
 203         struct drm_i915_private *dev_priv = to_i915(dev);
 204         struct intel_plane *intel_plane = to_intel_plane(drm_plane);
 205         struct drm_framebuffer *fb = plane_state->base.fb;
 206         const int pipe = intel_plane->pipe;
 207         const int plane = intel_plane->plane + 1;
 208         u32 plane_ctl;
 209         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 210         u32 surf_addr;
 211         unsigned int rotation = plane_state->base.rotation;
 212         u32 stride = skl_plane_stride(fb, 0, rotation);
 213         int crtc_x = plane_state->dst.x1;
 214         int crtc_y = plane_state->dst.y1;
 215         uint32_t crtc_w = drm_rect_width(&plane_state->dst);
 216         uint32_t crtc_h = drm_rect_height(&plane_state->dst);
 217         uint32_t x = plane_state->src.x1 >> 16;
 218         uint32_t y = plane_state->src.y1 >> 16;
 219         uint32_t src_w = drm_rect_width(&plane_state->src) >> 16;
 220         uint32_t src_h = drm_rect_height(&plane_state->src) >> 16;
 221
 222         plane_ctl = PLANE_CTL_ENABLE |
 223                 PLANE_CTL_PIPE_GAMMA_ENABLE |
 224                 PLANE_CTL_PIPE_CSC_ENABLE;
 225
 226         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
 227         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
 228
 229         plane_ctl |= skl_plane_ctl_rotation(rotation);
 230
 231         if (key->flags) {
 232                 I915_WRITE(PLANE_KEYVAL(pipe, plane), key->min_value);
 233                 I915_WRITE(PLANE_KEYMAX(pipe, plane), key->max_value);
 234                 I915_WRITE(PLANE_KEYMSK(pipe, plane), key->channel_mask);
 235         }
 236
 237         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 238                 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
 239         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 240                 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
 241
 242         if (intel_rotation_90_or_270(rotation)) {
 243                 struct drm_rect r = {
 244                         .x1 = x,
 245                         .x2 = x + src_w,
 246                         .y1 = y,
 247                         .y2 = y + src_h,
 248                 };
 249
 250                 /* Rotate src coordinates to match rotated GTT view */
 251                 drm_rect_rotate(&r, fb->width, fb->height, BIT(DRM_ROTATE_270));
 252
 253                 x = r.x1;
 254                 y = r.y1;
 255                 src_w = drm_rect_width(&r);
 256                 src_h = drm_rect_height(&r);
 257         }
 258
 259         intel_add_fb_offsets(&x, &y, plane_state, 0);
 260         surf_addr = intel_compute_tile_offset(&x, &y, plane_state, 0);
 261
 262         /* Sizes are 0 based */
 263         src_w--;
 264         src_h--;
 265         crtc_w--;
 266         crtc_h--;
 267
 268         I915_WRITE(PLANE_OFFSET(pipe, plane), (y << 16) | x);
 269         I915_WRITE(PLANE_STRIDE(pipe, plane), stride);
 270         I915_WRITE(PLANE_SIZE(pipe, plane), (src_h << 16) | src_w);
 271
 272         /* program plane scaler */
 273         if (plane_state->scaler_id >= 0) {
 274                 int scaler_id = plane_state->scaler_id;
 275                 const struct intel_scaler *scaler;
 276
 277                 DRM_DEBUG_KMS("plane = %d PS_PLANE_SEL(plane) = 0x%x\n", plane,
 278                         PS_PLANE_SEL(plane));
 279
 280                 scaler = &crtc_state->scaler_state.scalers[scaler_id];
 281
 282                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id),
 283                            PS_SCALER_EN | PS_PLANE_SEL(plane) | scaler->mode);
 284                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
 285                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y);
 286                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id),
 287                         ((crtc_w + 1) << 16)|(crtc_h + 1));
 288
 289                 I915_WRITE(PLANE_POS(pipe, plane), 0);
 290         } else {
 291                 I915_WRITE(PLANE_POS(pipe, plane), (crtc_y << 16) | crtc_x);
 292         }
 293
 294         I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl);
 295         I915_WRITE(PLANE_SURF(pipe, plane),
 296                    intel_fb_gtt_offset(fb, rotation) + surf_addr);
 297         POSTING_READ(PLANE_SURF(pipe, plane));
 298 }
 299
 300 static void
 301 skl_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
 302 {
 303         struct drm_device *dev = dplane->dev;
 304         struct drm_i915_private *dev_priv = to_i915(dev);
 305         struct intel_plane *intel_plane = to_intel_plane(dplane);
 306         const int pipe = intel_plane->pipe;
 307         const int plane = intel_plane->plane + 1;
 308
 309         I915_WRITE(PLANE_CTL(pipe, plane), 0);
 310
 311         I915_WRITE(PLANE_SURF(pipe, plane), 0);
 312         POSTING_READ(PLANE_SURF(pipe, plane));
 313 }
 314
 315 static void
 316 chv_update_csc(struct intel_plane *intel_plane, uint32_t format)
 317 {
 318         struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
 319         int plane = intel_plane->plane;
 320
 321         /* Seems RGB data bypasses the CSC always */
 322         if (!format_is_yuv(format))
 323                 return;
 324
 325         /*
 326          * BT.601 limited range YCbCr -> full range RGB
 327          *
 328          * |r|   | 6537 4769     0|   |cr  |
 329          * |g| = |-3330 4769 -1605| x |y-64|
 330          * |b|   |    0 4769  8263|   |cb  |
 331          *
 332          * Cb and Cr apparently come in as signed already, so no
 333          * need for any offset. For Y we need to remove the offset.
 334          */
 335         I915_WRITE(SPCSCYGOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(-64));
 336         I915_WRITE(SPCSCCBOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0));
 337         I915_WRITE(SPCSCCROFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0));
 338
 339         I915_WRITE(SPCSCC01(plane), SPCSC_C1(4769) | SPCSC_C0(6537));
 340         I915_WRITE(SPCSCC23(plane), SPCSC_C1(-3330) | SPCSC_C0(0));
 341         I915_WRITE(SPCSCC45(plane), SPCSC_C1(-1605) | SPCSC_C0(4769));
 342         I915_WRITE(SPCSCC67(plane), SPCSC_C1(4769) | SPCSC_C0(0));
 343         I915_WRITE(SPCSCC8(plane), SPCSC_C0(8263));
 344
 345         I915_WRITE(SPCSCYGICLAMP(plane), SPCSC_IMAX(940) | SPCSC_IMIN(64));
 346         I915_WRITE(SPCSCCBICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
 347         I915_WRITE(SPCSCCRICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
 348
 349         I915_WRITE(SPCSCYGOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 350         I915_WRITE(SPCSCCBOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 351         I915_WRITE(SPCSCCROCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 352 }
 353
 354 static void
 355 vlv_update_plane(struct drm_plane *dplane,
 356                  const struct intel_crtc_state *crtc_state,
 357                  const struct intel_plane_state *plane_state)
 358 {
 359         struct drm_device *dev = dplane->dev;
 360         struct drm_i915_private *dev_priv = to_i915(dev);
 361         struct intel_plane *intel_plane = to_intel_plane(dplane);
 362         struct drm_framebuffer *fb = plane_state->base.fb;
 363         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
 364         int pipe = intel_plane->pipe;
 365         int plane = intel_plane->plane;
 366         u32 sprctl;
 367         u32 sprsurf_offset, linear_offset;
 368         unsigned int rotation = dplane->state->rotation;
 369         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 370         int crtc_x = plane_state->dst.x1;
 371         int crtc_y = plane_state->dst.y1;
 372         uint32_t crtc_w = drm_rect_width(&plane_state->dst);
 373         uint32_t crtc_h = drm_rect_height(&plane_state->dst);
 374         uint32_t x = plane_state->src.x1 >> 16;
 375         uint32_t y = plane_state->src.y1 >> 16;
 376         uint32_t src_w = drm_rect_width(&plane_state->src) >> 16;
 377         uint32_t src_h = drm_rect_height(&plane_state->src) >> 16;
 378
 379         sprctl = SP_ENABLE;
 380
 381         switch (fb->pixel_format) {
 382         case DRM_FORMAT_YUYV:
 383                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV;
 384                 break;
 385         case DRM_FORMAT_YVYU:
 386                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU;
 387                 break;
 388         case DRM_FORMAT_UYVY:
 389                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY;
 390                 break;
 391         case DRM_FORMAT_VYUY:
 392                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
 393                 break;
 394         case DRM_FORMAT_RGB565:
 395                 sprctl |= SP_FORMAT_BGR565;
 396                 break;
 397         case DRM_FORMAT_XRGB8888:
 398                 sprctl |= SP_FORMAT_BGRX8888;
 399                 break;
 400         case DRM_FORMAT_ARGB8888:
 401                 sprctl |= SP_FORMAT_BGRA8888;
 402                 break;
 403         case DRM_FORMAT_XBGR2101010:
 404                 sprctl |= SP_FORMAT_RGBX1010102;
 405                 break;
 406         case DRM_FORMAT_ABGR2101010:
 407                 sprctl |= SP_FORMAT_RGBA1010102;
 408                 break;
 409         case DRM_FORMAT_XBGR8888:
 410                 sprctl |= SP_FORMAT_RGBX8888;
 411                 break;
 412         case DRM_FORMAT_ABGR8888:
 413                 sprctl |= SP_FORMAT_RGBA8888;
 414                 break;
 415         default:
 416                 /*
 417                  * If we get here one of the upper layers failed to filter
 418                  * out the unsupported plane formats
 419                  */
 420                 BUG();
 421                 break;
 422         }
 423
 424         /*
 425          * Enable gamma to match primary/cursor plane behaviour.
 426          * FIXME should be user controllable via propertiesa.
 427          */
 428         sprctl |= SP_GAMMA_ENABLE;
 429
 430         if (i915_gem_object_is_tiled(obj))
 431                 sprctl |= SP_TILED;
 432
 433         /* Sizes are 0 based */
 434         src_w--;
 435         src_h--;
 436         crtc_w--;
 437         crtc_h--;
 438
 439         intel_add_fb_offsets(&x, &y, plane_state, 0);
 440         sprsurf_offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
 441
 442         if (rotation == BIT(DRM_ROTATE_180)) {
 443                 sprctl |= SP_ROTATE_180;
 444
 445                 x += src_w;
 446                 y += src_h;
 447         }
 448
 449         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 450
 451         if (key->flags) {
 452                 I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value);
 453                 I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value);
 454                 I915_WRITE(SPKEYMSK(pipe, plane), key->channel_mask);
 455         }
 456
 457         if (key->flags & I915_SET_COLORKEY_SOURCE)
 458                 sprctl |= SP_SOURCE_KEY;
 459
 460         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B)
 461                 chv_update_csc(intel_plane, fb->pixel_format);
 462
 463         I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]);
 464         I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x);
 465
 466         if (i915_gem_object_is_tiled(obj))
 467                 I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x);
 468         else
 469                 I915_WRITE(SPLINOFF(pipe, plane), linear_offset);
 470
 471         I915_WRITE(SPCONSTALPHA(pipe, plane), 0);
 472
 473         I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w);
 474         I915_WRITE(SPCNTR(pipe, plane), sprctl);
 475         I915_WRITE(SPSURF(pipe, plane),
 476                    intel_fb_gtt_offset(fb, rotation) + sprsurf_offset);
 477         POSTING_READ(SPSURF(pipe, plane));
 478 }
 479
 480 static void
 481 vlv_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
 482 {
 483         struct drm_device *dev = dplane->dev;
 484         struct drm_i915_private *dev_priv = to_i915(dev);
 485         struct intel_plane *intel_plane = to_intel_plane(dplane);
 486         int pipe = intel_plane->pipe;
 487         int plane = intel_plane->plane;
 488
 489         I915_WRITE(SPCNTR(pipe, plane), 0);
 490
 491         I915_WRITE(SPSURF(pipe, plane), 0);
 492         POSTING_READ(SPSURF(pipe, plane));
 493 }
 494
 495 static void
 496 ivb_update_plane(struct drm_plane *plane,
 497                  const struct intel_crtc_state *crtc_state,
 498                  const struct intel_plane_state *plane_state)
 499 {
 500         struct drm_device *dev = plane->dev;
 501         struct drm_i915_private *dev_priv = to_i915(dev);
 502         struct intel_plane *intel_plane = to_intel_plane(plane);
 503         struct drm_framebuffer *fb = plane_state->base.fb;
 504         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
 505         enum pipe pipe = intel_plane->pipe;
 506         u32 sprctl, sprscale = 0;
 507         u32 sprsurf_offset, linear_offset;
 508         unsigned int rotation = plane_state->base.rotation;
 509         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 510         int crtc_x = plane_state->dst.x1;
 511         int crtc_y = plane_state->dst.y1;
 512         uint32_t crtc_w = drm_rect_width(&plane_state->dst);
 513         uint32_t crtc_h = drm_rect_height(&plane_state->dst);
 514         uint32_t x = plane_state->src.x1 >> 16;
 515         uint32_t y = plane_state->src.y1 >> 16;
 516         uint32_t src_w = drm_rect_width(&plane_state->src) >> 16;
 517         uint32_t src_h = drm_rect_height(&plane_state->src) >> 16;
 518
 519         sprctl = SPRITE_ENABLE;
 520
 521         switch (fb->pixel_format) {
 522         case DRM_FORMAT_XBGR8888:
 523                 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
 524                 break;
 525         case DRM_FORMAT_XRGB8888:
 526                 sprctl |= SPRITE_FORMAT_RGBX888;
 527                 break;
 528         case DRM_FORMAT_YUYV:
 529                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
 530                 break;
 531         case DRM_FORMAT_YVYU:
 532                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
 533                 break;
 534         case DRM_FORMAT_UYVY:
 535                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
 536                 break;
 537         case DRM_FORMAT_VYUY:
 538                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
 539                 break;
 540         default:
 541                 BUG();
 542         }
 543
 544         /*
 545          * Enable gamma to match primary/cursor plane behaviour.
 546          * FIXME should be user controllable via propertiesa.
 547          */
 548         sprctl |= SPRITE_GAMMA_ENABLE;
 549
 550         if (i915_gem_object_is_tiled(obj))
 551                 sprctl |= SPRITE_TILED;
 552
 553         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 554                 sprctl &= ~SPRITE_TRICKLE_FEED_DISABLE;
 555         else
 556                 sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
 557
 558         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 559                 sprctl |= SPRITE_PIPE_CSC_ENABLE;
 560
 561         /* Sizes are 0 based */
 562         src_w--;
 563         src_h--;
 564         crtc_w--;
 565         crtc_h--;
 566
 567         if (crtc_w != src_w || crtc_h != src_h)
 568                 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
 569
 570         intel_add_fb_offsets(&x, &y, plane_state, 0);
 571         sprsurf_offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
 572
 573         if (rotation == BIT(DRM_ROTATE_180)) {
 574                 sprctl |= SPRITE_ROTATE_180;
 575
 576                 /* HSW and BDW does this automagically in hardware */
 577                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
 578                         x += src_w;
 579                         y += src_h;
 580                 }
 581         }
 582
 583         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 584
 585         if (key->flags) {
 586                 I915_WRITE(SPRKEYVAL(pipe), key->min_value);
 587                 I915_WRITE(SPRKEYMAX(pipe), key->max_value);
 588                 I915_WRITE(SPRKEYMSK(pipe), key->channel_mask);
 589         }
 590
 591         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 592                 sprctl |= SPRITE_DEST_KEY;
 593         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 594                 sprctl |= SPRITE_SOURCE_KEY;
 595
 596         I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]);
 597         I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
 598
 599         /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
 600          * register */
 601         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 602                 I915_WRITE(SPROFFSET(pipe), (y << 16) | x);
 603         else if (i915_gem_object_is_tiled(obj))
 604                 I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x);
 605         else
 606                 I915_WRITE(SPRLINOFF(pipe), linear_offset);
 607
 608         I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
 609         if (intel_plane->can_scale)
 610                 I915_WRITE(SPRSCALE(pipe), sprscale);
 611         I915_WRITE(SPRCTL(pipe), sprctl);
 612         I915_WRITE(SPRSURF(pipe),
 613                    intel_fb_gtt_offset(fb, rotation) + sprsurf_offset);
 614         POSTING_READ(SPRSURF(pipe));
 615 }
 616
 617 static void
 618 ivb_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
 619 {
 620         struct drm_device *dev = plane->dev;
 621         struct drm_i915_private *dev_priv = to_i915(dev);
 622         struct intel_plane *intel_plane = to_intel_plane(plane);
 623         int pipe = intel_plane->pipe;
 624
 625         I915_WRITE(SPRCTL(pipe), 0);
 626         /* Can't leave the scaler enabled... */
 627         if (intel_plane->can_scale)
 628                 I915_WRITE(SPRSCALE(pipe), 0);
 629
 630         I915_WRITE(SPRSURF(pipe), 0);
 631         POSTING_READ(SPRSURF(pipe));
 632 }
 633
 634 static void
 635 ilk_update_plane(struct drm_plane *plane,
 636                  const struct intel_crtc_state *crtc_state,
 637                  const struct intel_plane_state *plane_state)
 638 {
 639         struct drm_device *dev = plane->dev;
 640         struct drm_i915_private *dev_priv = to_i915(dev);
 641         struct intel_plane *intel_plane = to_intel_plane(plane);
 642         struct drm_framebuffer *fb = plane_state->base.fb;
 643         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
 644         int pipe = intel_plane->pipe;
 645         u32 dvscntr, dvsscale;
 646         u32 dvssurf_offset, linear_offset;
 647         unsigned int rotation = plane_state->base.rotation;
 648         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 649         int crtc_x = plane_state->dst.x1;
 650         int crtc_y = plane_state->dst.y1;
 651         uint32_t crtc_w = drm_rect_width(&plane_state->dst);
 652         uint32_t crtc_h = drm_rect_height(&plane_state->dst);
 653         uint32_t x = plane_state->src.x1 >> 16;
 654         uint32_t y = plane_state->src.y1 >> 16;
 655         uint32_t src_w = drm_rect_width(&plane_state->src) >> 16;
 656         uint32_t src_h = drm_rect_height(&plane_state->src) >> 16;
 657
 658         dvscntr = DVS_ENABLE;
 659
 660         switch (fb->pixel_format) {
 661         case DRM_FORMAT_XBGR8888:
 662                 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
 663                 break;
 664         case DRM_FORMAT_XRGB8888:
 665                 dvscntr |= DVS_FORMAT_RGBX888;
 666                 break;
 667         case DRM_FORMAT_YUYV:
 668                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
 669                 break;
 670         case DRM_FORMAT_YVYU:
 671                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
 672                 break;
 673         case DRM_FORMAT_UYVY:
 674                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
 675                 break;
 676         case DRM_FORMAT_VYUY:
 677                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
 678                 break;
 679         default:
 680                 BUG();
 681         }
 682
 683         /*
 684          * Enable gamma to match primary/cursor plane behaviour.
 685          * FIXME should be user controllable via propertiesa.
 686          */
 687         dvscntr |= DVS_GAMMA_ENABLE;
 688
 689         if (i915_gem_object_is_tiled(obj))
 690                 dvscntr |= DVS_TILED;
 691
 692         if (IS_GEN6(dev))
 693                 dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */
 694
 695         /* Sizes are 0 based */
 696         src_w--;
 697         src_h--;
 698         crtc_w--;
 699         crtc_h--;
 700
 701         dvsscale = 0;
 702         if (crtc_w != src_w || crtc_h != src_h)
 703                 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
 704
 705         intel_add_fb_offsets(&x, &y, plane_state, 0);
 706         dvssurf_offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
 707
 708         if (rotation == BIT(DRM_ROTATE_180)) {
 709                 dvscntr |= DVS_ROTATE_180;
 710
 711                 x += src_w;
 712                 y += src_h;
 713         }
 714
 715         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 716
 717         if (key->flags) {
 718                 I915_WRITE(DVSKEYVAL(pipe), key->min_value);
 719                 I915_WRITE(DVSKEYMAX(pipe), key->max_value);
 720                 I915_WRITE(DVSKEYMSK(pipe), key->channel_mask);
 721         }
 722
 723         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 724                 dvscntr |= DVS_DEST_KEY;
 725         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 726                 dvscntr |= DVS_SOURCE_KEY;
 727
 728         I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]);
 729         I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
 730
 731         if (i915_gem_object_is_tiled(obj))
 732                 I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x);
 733         else
 734                 I915_WRITE(DVSLINOFF(pipe), linear_offset);
 735
 736         I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
 737         I915_WRITE(DVSSCALE(pipe), dvsscale);
 738         I915_WRITE(DVSCNTR(pipe), dvscntr);
 739         I915_WRITE(DVSSURF(pipe),
 740                    intel_fb_gtt_offset(fb, rotation) + dvssurf_offset);
 741         POSTING_READ(DVSSURF(pipe));
 742 }
 743
 744 static void
 745 ilk_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
 746 {
 747         struct drm_device *dev = plane->dev;
 748         struct drm_i915_private *dev_priv = to_i915(dev);
 749         struct intel_plane *intel_plane = to_intel_plane(plane);
 750         int pipe = intel_plane->pipe;
 751
 752         I915_WRITE(DVSCNTR(pipe), 0);
 753         /* Disable the scaler */
 754         I915_WRITE(DVSSCALE(pipe), 0);
 755
 756         I915_WRITE(DVSSURF(pipe), 0);
 757         POSTING_READ(DVSSURF(pipe));
 758 }
 759
 760 static int
 761 intel_check_sprite_plane(struct drm_plane *plane,
 762                          struct intel_crtc_state *crtc_state,
 763                          struct intel_plane_state *state)
 764 {
 765         struct drm_device *dev = plane->dev;
 766         struct drm_crtc *crtc = state->base.crtc;
 767         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 768         struct intel_plane *intel_plane = to_intel_plane(plane);
 769         struct drm_framebuffer *fb = state->base.fb;
 770         int crtc_x, crtc_y;
 771         unsigned int crtc_w, crtc_h;
 772         uint32_t src_x, src_y, src_w, src_h;
 773         struct drm_rect *src = &state->src;
 774         struct drm_rect *dst = &state->dst;
 775         const struct drm_rect *clip = &state->clip;
 776         int hscale, vscale;
 777         int max_scale, min_scale;
 778         bool can_scale;
 779
 780         if (!fb) {
 781                 state->visible = false;
 782                 return 0;
 783         }
 784
 785         /* Don't modify another pipe's plane */
 786         if (intel_plane->pipe != intel_crtc->pipe) {
 787                 DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n");
 788                 return -EINVAL;
 789         }
 790
 791         /* FIXME check all gen limits */
 792         if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > 16384) {
 793                 DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n");
 794                 return -EINVAL;
 795         }
 796
 797         /* setup can_scale, min_scale, max_scale */
 798         if (INTEL_INFO(dev)->gen >= 9) {
 799                 /* use scaler when colorkey is not required */
 800                 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
 801                         can_scale = 1;
 802                         min_scale = 1;
 803                         max_scale = skl_max_scale(intel_crtc, crtc_state);
 804                 } else {
 805                         can_scale = 0;
 806                         min_scale = DRM_PLANE_HELPER_NO_SCALING;
 807                         max_scale = DRM_PLANE_HELPER_NO_SCALING;
 808                 }
 809         } else {
 810                 can_scale = intel_plane->can_scale;
 811                 max_scale = intel_plane->max_downscale << 16;
 812                 min_scale = intel_plane->can_scale ? 1 : (1 << 16);
 813         }
 814
 815         /*
 816          * FIXME the following code does a bunch of fuzzy adjustments to the
 817          * coordinates and sizes. We probably need some way to decide whether
 818          * more strict checking should be done instead.
 819          */
 820         drm_rect_rotate(src, fb->width << 16, fb->height << 16,
 821                         state->base.rotation);
 822
 823         hscale = drm_rect_calc_hscale_relaxed(src, dst, min_scale, max_scale);
 824         BUG_ON(hscale < 0);
 825
 826         vscale = drm_rect_calc_vscale_relaxed(src, dst, min_scale, max_scale);
 827         BUG_ON(vscale < 0);
 828
 829         state->visible = drm_rect_clip_scaled(src, dst, clip, hscale, vscale);
 830
 831         crtc_x = dst->x1;
 832         crtc_y = dst->y1;
 833         crtc_w = drm_rect_width(dst);
 834         crtc_h = drm_rect_height(dst);
 835
 836         if (state->visible) {
 837                 /* check again in case clipping clamped the results */
 838                 hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale);
 839                 if (hscale < 0) {
 840                         DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n");
 841                         drm_rect_debug_print("src: ", src, true);
 842                         drm_rect_debug_print("dst: ", dst, false);
 843
 844                         return hscale;
 845                 }
 846
 847                 vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale);
 848                 if (vscale < 0) {
 849                         DRM_DEBUG_KMS("Vertical scaling factor out of limits\n");
 850                         drm_rect_debug_print("src: ", src, true);
 851                         drm_rect_debug_print("dst: ", dst, false);
 852
 853                         return vscale;
 854                 }
 855
 856                 /* Make the source viewport size an exact multiple of the scaling factors. */
 857                 drm_rect_adjust_size(src,
 858                                      drm_rect_width(dst) * hscale - drm_rect_width(src),
 859                                      drm_rect_height(dst) * vscale - drm_rect_height(src));
 860
 861                 drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16,
 862                                     state->base.rotation);
 863
 864                 /* sanity check to make sure the src viewport wasn't enlarged */
 865                 WARN_ON(src->x1 < (int) state->base.src_x ||
 866                         src->y1 < (int) state->base.src_y ||
 867                         src->x2 > (int) state->base.src_x + state->base.src_w ||
 868                         src->y2 > (int) state->base.src_y + state->base.src_h);
 869
 870                 /*
 871                  * Hardware doesn't handle subpixel coordinates.
 872                  * Adjust to (macro)pixel boundary, but be careful not to
 873                  * increase the source viewport size, because that could
 874                  * push the downscaling factor out of bounds.
 875                  */
 876                 src_x = src->x1 >> 16;
 877                 src_w = drm_rect_width(src) >> 16;
 878                 src_y = src->y1 >> 16;
 879                 src_h = drm_rect_height(src) >> 16;
 880
 881                 if (format_is_yuv(fb->pixel_format)) {
 882                         src_x &= ~1;
 883                         src_w &= ~1;
 884
 885                         /*
 886                          * Must keep src and dst the
 887                          * same if we can't scale.
 888                          */
 889                         if (!can_scale)
 890                                 crtc_w &= ~1;
 891
 892                         if (crtc_w == 0)
 893                                 state->visible = false;
 894                 }
 895         }
 896
 897         /* Check size restrictions when scaling */
 898         if (state->visible && (src_w != crtc_w || src_h != crtc_h)) {
 899                 unsigned int width_bytes;
 900                 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
 901
 902                 WARN_ON(!can_scale);
 903
 904                 /* FIXME interlacing min height is 6 */
 905
 906                 if (crtc_w < 3 || crtc_h < 3)
 907                         state->visible = false;
 908
 909                 if (src_w < 3 || src_h < 3)
 910                         state->visible = false;
 911
 912                 width_bytes = ((src_x * cpp) & 63) + src_w * cpp;
 913
 914                 if (INTEL_INFO(dev)->gen < 9 && (src_w > 2048 || src_h > 2048 ||
 915                     width_bytes > 4096 || fb->pitches[0] > 4096)) {
 916                         DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
 917                         return -EINVAL;
 918                 }
 919         }
 920
 921         if (state->visible) {
 922                 src->x1 = src_x << 16;
 923                 src->x2 = (src_x + src_w) << 16;
 924                 src->y1 = src_y << 16;
 925                 src->y2 = (src_y + src_h) << 16;
 926         }
 927
 928         dst->x1 = crtc_x;
 929         dst->x2 = crtc_x + crtc_w;
 930         dst->y1 = crtc_y;
 931         dst->y2 = crtc_y + crtc_h;
 932
 933         return 0;
 934 }
 935
 936 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
 937                               struct drm_file *file_priv)
 938 {
 939         struct drm_intel_sprite_colorkey *set = data;
 940         struct drm_plane *plane;
 941         struct drm_plane_state *plane_state;
 942         struct drm_atomic_state *state;
 943         struct drm_modeset_acquire_ctx ctx;
 944         int ret = 0;
 945
 946         /* Make sure we don't try to enable both src & dest simultaneously */
 947         if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
 948                 return -EINVAL;
 949
 950         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
 951             set->flags & I915_SET_COLORKEY_DESTINATION)
 952                 return -EINVAL;
 953
 954         plane = drm_plane_find(dev, set->plane_id);
 955         if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY)
 956                 return -ENOENT;
 957
 958         drm_modeset_acquire_init(&ctx, 0);
 959
 960         state = drm_atomic_state_alloc(plane->dev);
 961         if (!state) {
 962                 ret = -ENOMEM;
 963                 goto out;
 964         }
 965         state->acquire_ctx = &ctx;
 966
 967         while (1) {
 968                 plane_state = drm_atomic_get_plane_state(state, plane);
 969                 ret = PTR_ERR_OR_ZERO(plane_state);
 970                 if (!ret) {
 971                         to_intel_plane_state(plane_state)->ckey = *set;
 972                         ret = drm_atomic_commit(state);
 973                 }
 974
 975                 if (ret != -EDEADLK)
 976                         break;
 977
 978                 drm_atomic_state_clear(state);
 979                 drm_modeset_backoff(&ctx);
 980         }
 981
 982         if (ret)
 983                 drm_atomic_state_free(state);
 984
 985 out:
 986         drm_modeset_drop_locks(&ctx);
 987         drm_modeset_acquire_fini(&ctx);
 988         return ret;
 989 }
 990
 991 static const uint32_t ilk_plane_formats[] = {
 992         DRM_FORMAT_XRGB8888,
 993         DRM_FORMAT_YUYV,
 994         DRM_FORMAT_YVYU,
 995         DRM_FORMAT_UYVY,
 996         DRM_FORMAT_VYUY,
 997 };
 998
 999 static const uint32_t snb_plane_formats[] = {
1000         DRM_FORMAT_XBGR8888,
1001         DRM_FORMAT_XRGB8888,
1002         DRM_FORMAT_YUYV,
1003         DRM_FORMAT_YVYU,
1004         DRM_FORMAT_UYVY,
1005         DRM_FORMAT_VYUY,
1006 };
1007
1008 static const uint32_t vlv_plane_formats[] = {
1009         DRM_FORMAT_RGB565,
1010         DRM_FORMAT_ABGR8888,
1011         DRM_FORMAT_ARGB8888,
1012         DRM_FORMAT_XBGR8888,
1013         DRM_FORMAT_XRGB8888,
1014         DRM_FORMAT_XBGR2101010,
1015         DRM_FORMAT_ABGR2101010,
1016         DRM_FORMAT_YUYV,
1017         DRM_FORMAT_YVYU,
1018         DRM_FORMAT_UYVY,
1019         DRM_FORMAT_VYUY,
1020 };
1021
1022 static uint32_t skl_plane_formats[] = {
1023         DRM_FORMAT_RGB565,
1024         DRM_FORMAT_ABGR8888,
1025         DRM_FORMAT_ARGB8888,
1026         DRM_FORMAT_XBGR8888,
1027         DRM_FORMAT_XRGB8888,
1028         DRM_FORMAT_YUYV,
1029         DRM_FORMAT_YVYU,
1030         DRM_FORMAT_UYVY,
1031         DRM_FORMAT_VYUY,
1032 };
1033
1034 int
1035 intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
1036 {
1037         struct intel_plane *intel_plane = NULL;
1038         struct intel_plane_state *state = NULL;
1039         unsigned long possible_crtcs;
1040         const uint32_t *plane_formats;
1041         int num_plane_formats;
1042         int ret;
1043
1044         if (INTEL_INFO(dev)->gen < 5)
1045                 return -ENODEV;
1046
1047         intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL);
1048         if (!intel_plane) {
1049                 ret = -ENOMEM;
1050                 goto fail;
1051         }
1052
1053         state = intel_create_plane_state(&intel_plane->base);
1054         if (!state) {
1055                 ret = -ENOMEM;
1056                 goto fail;
1057         }
1058         intel_plane->base.state = &state->base;
1059
1060         switch (INTEL_INFO(dev)->gen) {
1061         case 5:
1062         case 6:
1063                 intel_plane->can_scale = true;
1064                 intel_plane->max_downscale = 16;
1065                 intel_plane->update_plane = ilk_update_plane;
1066                 intel_plane->disable_plane = ilk_disable_plane;
1067
1068                 if (IS_GEN6(dev)) {
1069                         plane_formats = snb_plane_formats;
1070                         num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1071                 } else {
1072                         plane_formats = ilk_plane_formats;
1073                         num_plane_formats = ARRAY_SIZE(ilk_plane_formats);
1074                 }
1075                 break;
1076
1077         case 7:
1078         case 8:
1079                 if (IS_IVYBRIDGE(dev)) {
1080                         intel_plane->can_scale = true;
1081                         intel_plane->max_downscale = 2;
1082                 } else {
1083                         intel_plane->can_scale = false;
1084                         intel_plane->max_downscale = 1;
1085                 }
1086
1087                 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1088                         intel_plane->update_plane = vlv_update_plane;
1089                         intel_plane->disable_plane = vlv_disable_plane;
1090
1091                         plane_formats = vlv_plane_formats;
1092                         num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
1093                 } else {
1094                         intel_plane->update_plane = ivb_update_plane;
1095                         intel_plane->disable_plane = ivb_disable_plane;
1096
1097                         plane_formats = snb_plane_formats;
1098                         num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1099                 }
1100                 break;
1101         case 9:
1102                 intel_plane->can_scale = true;
1103                 intel_plane->update_plane = skl_update_plane;
1104                 intel_plane->disable_plane = skl_disable_plane;
1105                 state->scaler_id = -1;
1106
1107                 plane_formats = skl_plane_formats;
1108                 num_plane_formats = ARRAY_SIZE(skl_plane_formats);
1109                 break;
1110         default:
1111                 MISSING_CASE(INTEL_INFO(dev)->gen);
1112                 ret = -ENODEV;
1113                 goto fail;
1114         }
1115
1116         intel_plane->pipe = pipe;
1117         intel_plane->plane = plane;
1118         intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER_SPRITE(pipe, plane);
1119         intel_plane->check_plane = intel_check_sprite_plane;
1120
1121         possible_crtcs = (1 << pipe);
1122
1123         if (INTEL_INFO(dev)->gen >= 9)
1124                 ret = drm_universal_plane_init(dev, &intel_plane->base, possible_crtcs,
1125                                                &intel_plane_funcs,
1126                                                plane_formats, num_plane_formats,
1127                                                DRM_PLANE_TYPE_OVERLAY,
1128                                                "plane %d%c", plane + 2, pipe_name(pipe));
1129         else
1130                 ret = drm_universal_plane_init(dev, &intel_plane->base, possible_crtcs,
1131                                                &intel_plane_funcs,
1132                                                plane_formats, num_plane_formats,
1133                                                DRM_PLANE_TYPE_OVERLAY,
1134                                                "sprite %c", sprite_name(pipe, plane));
1135         if (ret)
1136                 goto fail;
1137
1138         intel_create_rotation_property(dev, intel_plane);
1139
1140         drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs);
1141
1142         return 0;
1143
1144 fail:
1145         kfree(state);
1146         kfree(intel_plane);
1147
1148         return ret;
1149 }