2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Jesse Barnes <jbarnes@virtuousgeek.org>
26 * New plane/sprite handling.
28 * The older chips had a separate interface for programming plane related
29 * registers; newer ones are much simpler and we can use the new DRM plane
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_fourcc.h>
35 #include <drm/drm_rect.h>
36 #include <drm/drm_atomic.h>
37 #include <drm/drm_plane_helper.h>
38 #include "intel_drv.h"
39 #include "intel_frontbuffer.h"
40 #include <drm/i915_drm.h>
44 format_is_yuv(uint32_t format)
57 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
61 if (!adjusted_mode->crtc_htotal)
64 return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock,
65 1000 * adjusted_mode->crtc_htotal);
68 #define VBLANK_EVASION_TIME_US 100
71 * intel_pipe_update_start() - start update of a set of display registers
72 * @crtc: the crtc of which the registers are going to be updated
73 * @start_vbl_count: vblank counter return pointer used for error checking
75 * Mark the start of an update to pipe registers that should be updated
76 * atomically regarding vblank. If the next vblank will happens within
77 * the next 100 us, this function waits until the vblank passes.
79 * After a successful call to this function, interrupts will be disabled
80 * until a subsequent call to intel_pipe_update_end(). That is done to
81 * avoid random delays. The value written to @start_vbl_count should be
82 * supplied to intel_pipe_update_end() for error checking.
84 void intel_pipe_update_start(struct intel_crtc *crtc)
86 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
87 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
88 long timeout = msecs_to_jiffies_timeout(1);
89 int scanline, min, max, vblank_start;
90 wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
91 bool need_vlv_dsi_wa = (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
92 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI);
95 vblank_start = adjusted_mode->crtc_vblank_start;
96 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
97 vblank_start = DIV_ROUND_UP(vblank_start, 2);
99 /* FIXME needs to be calibrated sensibly */
100 min = vblank_start - intel_usecs_to_scanlines(adjusted_mode,
101 VBLANK_EVASION_TIME_US);
102 max = vblank_start - 1;
106 if (min <= 0 || max <= 0)
109 if (WARN_ON(drm_crtc_vblank_get(&crtc->base)))
112 crtc->debug.min_vbl = min;
113 crtc->debug.max_vbl = max;
114 trace_i915_pipe_update_start(crtc);
118 * prepare_to_wait() has a memory barrier, which guarantees
119 * other CPUs can see the task state update by the time we
122 prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
124 scanline = intel_get_crtc_scanline(crtc);
125 if (scanline < min || scanline > max)
129 DRM_ERROR("Potential atomic update failure on pipe %c\n",
130 pipe_name(crtc->pipe));
136 timeout = schedule_timeout(timeout);
141 finish_wait(wq, &wait);
143 drm_crtc_vblank_put(&crtc->base);
146 * On VLV/CHV DSI the scanline counter would appear to
147 * increment approx. 1/3 of a scanline before start of vblank.
148 * The registers still get latched at start of vblank however.
149 * This means we must not write any registers on the first
150 * line of vblank (since not the whole line is actually in
151 * vblank). And unfortunately we can't use the interrupt to
152 * wait here since it will fire too soon. We could use the
153 * frame start interrupt instead since it will fire after the
154 * critical scanline, but that would require more changes
155 * in the interrupt code. So for now we'll just do the nasty
156 * thing and poll for the bad scanline to pass us by.
158 * FIXME figure out if BXT+ DSI suffers from this as well
160 while (need_vlv_dsi_wa && scanline == vblank_start)
161 scanline = intel_get_crtc_scanline(crtc);
163 crtc->debug.scanline_start = scanline;
164 crtc->debug.start_vbl_time = ktime_get();
165 crtc->debug.start_vbl_count = intel_crtc_get_vblank_counter(crtc);
167 trace_i915_pipe_update_vblank_evaded(crtc);
171 * intel_pipe_update_end() - end update of a set of display registers
172 * @crtc: the crtc of which the registers were updated
173 * @start_vbl_count: start vblank counter (used for error checking)
175 * Mark the end of an update started with intel_pipe_update_start(). This
176 * re-enables interrupts and verifies the update was actually completed
177 * before a vblank using the value of @start_vbl_count.
179 void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work)
181 enum pipe pipe = crtc->pipe;
182 int scanline_end = intel_get_crtc_scanline(crtc);
183 u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc);
184 ktime_t end_vbl_time = ktime_get();
185 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
188 work->flip_queued_vblank = end_vbl_count;
189 smp_mb__before_atomic();
190 atomic_set(&work->pending, 1);
193 trace_i915_pipe_update_end(crtc, end_vbl_count, scanline_end);
195 /* We're still in the vblank-evade critical section, this can't race.
196 * Would be slightly nice to just grab the vblank count and arm the
197 * event outside of the critical section - the spinlock might spin for a
199 if (crtc->base.state->event) {
200 WARN_ON(drm_crtc_vblank_get(&crtc->base) != 0);
202 spin_lock(&crtc->base.dev->event_lock);
203 drm_crtc_arm_vblank_event(&crtc->base, crtc->base.state->event);
204 spin_unlock(&crtc->base.dev->event_lock);
206 crtc->base.state->event = NULL;
211 if (intel_vgpu_active(dev_priv))
214 if (crtc->debug.start_vbl_count &&
215 crtc->debug.start_vbl_count != end_vbl_count) {
216 DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n",
217 pipe_name(pipe), crtc->debug.start_vbl_count,
219 ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
220 crtc->debug.min_vbl, crtc->debug.max_vbl,
221 crtc->debug.scanline_start, scanline_end);
223 #ifdef CONFIG_DRM_I915_DEBUG_VBLANK_EVADE
224 else if (ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time) >
225 VBLANK_EVASION_TIME_US)
226 DRM_WARN("Atomic update on pipe (%c) took %lld us, max time under evasion is %u us\n",
228 ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
229 VBLANK_EVASION_TIME_US);
234 skl_update_plane(struct intel_plane *plane,
235 const struct intel_crtc_state *crtc_state,
236 const struct intel_plane_state *plane_state)
238 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
239 const struct drm_framebuffer *fb = plane_state->base.fb;
240 enum plane_id plane_id = plane->id;
241 enum pipe pipe = plane->pipe;
242 u32 plane_ctl = plane_state->ctl;
243 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
244 u32 surf_addr = plane_state->main.offset;
245 unsigned int rotation = plane_state->base.rotation;
246 u32 stride = skl_plane_stride(fb, 0, rotation);
247 int crtc_x = plane_state->base.dst.x1;
248 int crtc_y = plane_state->base.dst.y1;
249 uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
250 uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
251 uint32_t x = plane_state->main.x;
252 uint32_t y = plane_state->main.y;
253 uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
254 uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
255 unsigned long irqflags;
257 /* Sizes are 0 based */
263 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
265 if (IS_GEMINILAKE(dev_priv)) {
266 I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
267 PLANE_COLOR_PIPE_GAMMA_ENABLE |
268 PLANE_COLOR_PIPE_CSC_ENABLE |
269 PLANE_COLOR_PLANE_GAMMA_DISABLE);
273 I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value);
274 I915_WRITE_FW(PLANE_KEYMAX(pipe, plane_id), key->max_value);
275 I915_WRITE_FW(PLANE_KEYMSK(pipe, plane_id), key->channel_mask);
278 I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (y << 16) | x);
279 I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
280 I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
282 /* program plane scaler */
283 if (plane_state->scaler_id >= 0) {
284 int scaler_id = plane_state->scaler_id;
285 const struct intel_scaler *scaler;
287 scaler = &crtc_state->scaler_state.scalers[scaler_id];
289 I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id),
290 PS_SCALER_EN | PS_PLANE_SEL(plane_id) | scaler->mode);
291 I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
292 I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y);
293 I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id),
294 ((crtc_w + 1) << 16)|(crtc_h + 1));
296 I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0);
298 I915_WRITE_FW(PLANE_POS(pipe, plane_id), (crtc_y << 16) | crtc_x);
301 I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl);
302 I915_WRITE_FW(PLANE_SURF(pipe, plane_id),
303 intel_plane_ggtt_offset(plane_state) + surf_addr);
304 POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
306 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
310 skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
312 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
313 enum plane_id plane_id = plane->id;
314 enum pipe pipe = plane->pipe;
315 unsigned long irqflags;
317 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
319 I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0);
321 I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0);
322 POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
324 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
328 chv_update_csc(struct intel_plane *plane, uint32_t format)
330 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
331 enum plane_id plane_id = plane->id;
333 /* Seems RGB data bypasses the CSC always */
334 if (!format_is_yuv(format))
338 * BT.601 limited range YCbCr -> full range RGB
340 * |r| | 6537 4769 0| |cr |
341 * |g| = |-3330 4769 -1605| x |y-64|
342 * |b| | 0 4769 8263| |cb |
344 * Cb and Cr apparently come in as signed already, so no
345 * need for any offset. For Y we need to remove the offset.
347 I915_WRITE_FW(SPCSCYGOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(-64));
348 I915_WRITE_FW(SPCSCCBOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
349 I915_WRITE_FW(SPCSCCROFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
351 I915_WRITE_FW(SPCSCC01(plane_id), SPCSC_C1(4769) | SPCSC_C0(6537));
352 I915_WRITE_FW(SPCSCC23(plane_id), SPCSC_C1(-3330) | SPCSC_C0(0));
353 I915_WRITE_FW(SPCSCC45(plane_id), SPCSC_C1(-1605) | SPCSC_C0(4769));
354 I915_WRITE_FW(SPCSCC67(plane_id), SPCSC_C1(4769) | SPCSC_C0(0));
355 I915_WRITE_FW(SPCSCC8(plane_id), SPCSC_C0(8263));
357 I915_WRITE_FW(SPCSCYGICLAMP(plane_id), SPCSC_IMAX(940) | SPCSC_IMIN(64));
358 I915_WRITE_FW(SPCSCCBICLAMP(plane_id), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
359 I915_WRITE_FW(SPCSCCRICLAMP(plane_id), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
361 I915_WRITE_FW(SPCSCYGOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
362 I915_WRITE_FW(SPCSCCBOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
363 I915_WRITE_FW(SPCSCCROCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
366 static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state,
367 const struct intel_plane_state *plane_state)
369 const struct drm_framebuffer *fb = plane_state->base.fb;
370 unsigned int rotation = plane_state->base.rotation;
371 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
374 sprctl = SP_ENABLE | SP_GAMMA_ENABLE;
376 switch (fb->format->format) {
377 case DRM_FORMAT_YUYV:
378 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV;
380 case DRM_FORMAT_YVYU:
381 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU;
383 case DRM_FORMAT_UYVY:
384 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY;
386 case DRM_FORMAT_VYUY:
387 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
389 case DRM_FORMAT_RGB565:
390 sprctl |= SP_FORMAT_BGR565;
392 case DRM_FORMAT_XRGB8888:
393 sprctl |= SP_FORMAT_BGRX8888;
395 case DRM_FORMAT_ARGB8888:
396 sprctl |= SP_FORMAT_BGRA8888;
398 case DRM_FORMAT_XBGR2101010:
399 sprctl |= SP_FORMAT_RGBX1010102;
401 case DRM_FORMAT_ABGR2101010:
402 sprctl |= SP_FORMAT_RGBA1010102;
404 case DRM_FORMAT_XBGR8888:
405 sprctl |= SP_FORMAT_RGBX8888;
407 case DRM_FORMAT_ABGR8888:
408 sprctl |= SP_FORMAT_RGBA8888;
411 MISSING_CASE(fb->format->format);
415 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
418 if (rotation & DRM_MODE_ROTATE_180)
419 sprctl |= SP_ROTATE_180;
421 if (rotation & DRM_MODE_REFLECT_X)
424 if (key->flags & I915_SET_COLORKEY_SOURCE)
425 sprctl |= SP_SOURCE_KEY;
431 vlv_update_plane(struct intel_plane *plane,
432 const struct intel_crtc_state *crtc_state,
433 const struct intel_plane_state *plane_state)
435 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
436 const struct drm_framebuffer *fb = plane_state->base.fb;
437 enum pipe pipe = plane->pipe;
438 enum plane_id plane_id = plane->id;
439 u32 sprctl = plane_state->ctl;
440 u32 sprsurf_offset = plane_state->main.offset;
442 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
443 int crtc_x = plane_state->base.dst.x1;
444 int crtc_y = plane_state->base.dst.y1;
445 uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
446 uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
447 uint32_t x = plane_state->main.x;
448 uint32_t y = plane_state->main.y;
449 unsigned long irqflags;
451 /* Sizes are 0 based */
455 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
457 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
459 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B)
460 chv_update_csc(plane, fb->format->format);
463 I915_WRITE_FW(SPKEYMINVAL(pipe, plane_id), key->min_value);
464 I915_WRITE_FW(SPKEYMAXVAL(pipe, plane_id), key->max_value);
465 I915_WRITE_FW(SPKEYMSK(pipe, plane_id), key->channel_mask);
467 I915_WRITE_FW(SPSTRIDE(pipe, plane_id), fb->pitches[0]);
468 I915_WRITE_FW(SPPOS(pipe, plane_id), (crtc_y << 16) | crtc_x);
470 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
471 I915_WRITE_FW(SPTILEOFF(pipe, plane_id), (y << 16) | x);
473 I915_WRITE_FW(SPLINOFF(pipe, plane_id), linear_offset);
475 I915_WRITE_FW(SPCONSTALPHA(pipe, plane_id), 0);
477 I915_WRITE_FW(SPSIZE(pipe, plane_id), (crtc_h << 16) | crtc_w);
478 I915_WRITE_FW(SPCNTR(pipe, plane_id), sprctl);
479 I915_WRITE_FW(SPSURF(pipe, plane_id),
480 intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
481 POSTING_READ_FW(SPSURF(pipe, plane_id));
483 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
487 vlv_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
489 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
490 enum pipe pipe = plane->pipe;
491 enum plane_id plane_id = plane->id;
492 unsigned long irqflags;
494 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
496 I915_WRITE_FW(SPCNTR(pipe, plane_id), 0);
498 I915_WRITE_FW(SPSURF(pipe, plane_id), 0);
499 POSTING_READ_FW(SPSURF(pipe, plane_id));
501 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
504 static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state,
505 const struct intel_plane_state *plane_state)
507 struct drm_i915_private *dev_priv =
508 to_i915(plane_state->base.plane->dev);
509 const struct drm_framebuffer *fb = plane_state->base.fb;
510 unsigned int rotation = plane_state->base.rotation;
511 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
514 sprctl = SPRITE_ENABLE | SPRITE_GAMMA_ENABLE;
516 if (IS_IVYBRIDGE(dev_priv))
517 sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
519 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
520 sprctl |= SPRITE_PIPE_CSC_ENABLE;
522 switch (fb->format->format) {
523 case DRM_FORMAT_XBGR8888:
524 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
526 case DRM_FORMAT_XRGB8888:
527 sprctl |= SPRITE_FORMAT_RGBX888;
529 case DRM_FORMAT_YUYV:
530 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
532 case DRM_FORMAT_YVYU:
533 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
535 case DRM_FORMAT_UYVY:
536 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
538 case DRM_FORMAT_VYUY:
539 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
542 MISSING_CASE(fb->format->format);
546 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
547 sprctl |= SPRITE_TILED;
549 if (rotation & DRM_MODE_ROTATE_180)
550 sprctl |= SPRITE_ROTATE_180;
552 if (key->flags & I915_SET_COLORKEY_DESTINATION)
553 sprctl |= SPRITE_DEST_KEY;
554 else if (key->flags & I915_SET_COLORKEY_SOURCE)
555 sprctl |= SPRITE_SOURCE_KEY;
561 ivb_update_plane(struct intel_plane *plane,
562 const struct intel_crtc_state *crtc_state,
563 const struct intel_plane_state *plane_state)
565 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
566 const struct drm_framebuffer *fb = plane_state->base.fb;
567 enum pipe pipe = plane->pipe;
568 u32 sprctl = plane_state->ctl, sprscale = 0;
569 u32 sprsurf_offset = plane_state->main.offset;
571 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
572 int crtc_x = plane_state->base.dst.x1;
573 int crtc_y = plane_state->base.dst.y1;
574 uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
575 uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
576 uint32_t x = plane_state->main.x;
577 uint32_t y = plane_state->main.y;
578 uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
579 uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
580 unsigned long irqflags;
582 /* Sizes are 0 based */
588 if (crtc_w != src_w || crtc_h != src_h)
589 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
591 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
593 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
596 I915_WRITE_FW(SPRKEYVAL(pipe), key->min_value);
597 I915_WRITE_FW(SPRKEYMAX(pipe), key->max_value);
598 I915_WRITE_FW(SPRKEYMSK(pipe), key->channel_mask);
601 I915_WRITE_FW(SPRSTRIDE(pipe), fb->pitches[0]);
602 I915_WRITE_FW(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
604 /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
606 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
607 I915_WRITE_FW(SPROFFSET(pipe), (y << 16) | x);
608 else if (fb->modifier == I915_FORMAT_MOD_X_TILED)
609 I915_WRITE_FW(SPRTILEOFF(pipe), (y << 16) | x);
611 I915_WRITE_FW(SPRLINOFF(pipe), linear_offset);
613 I915_WRITE_FW(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
614 if (plane->can_scale)
615 I915_WRITE_FW(SPRSCALE(pipe), sprscale);
616 I915_WRITE_FW(SPRCTL(pipe), sprctl);
617 I915_WRITE_FW(SPRSURF(pipe),
618 intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
619 POSTING_READ_FW(SPRSURF(pipe));
621 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
625 ivb_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
627 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
628 enum pipe pipe = plane->pipe;
629 unsigned long irqflags;
631 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
633 I915_WRITE_FW(SPRCTL(pipe), 0);
634 /* Can't leave the scaler enabled... */
635 if (plane->can_scale)
636 I915_WRITE_FW(SPRSCALE(pipe), 0);
638 I915_WRITE_FW(SPRSURF(pipe), 0);
639 POSTING_READ_FW(SPRSURF(pipe));
641 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
644 static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
645 const struct intel_plane_state *plane_state)
647 struct drm_i915_private *dev_priv =
648 to_i915(plane_state->base.plane->dev);
649 const struct drm_framebuffer *fb = plane_state->base.fb;
650 unsigned int rotation = plane_state->base.rotation;
651 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
654 dvscntr = DVS_ENABLE | DVS_GAMMA_ENABLE;
656 if (IS_GEN6(dev_priv))
657 dvscntr |= DVS_TRICKLE_FEED_DISABLE;
659 switch (fb->format->format) {
660 case DRM_FORMAT_XBGR8888:
661 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
663 case DRM_FORMAT_XRGB8888:
664 dvscntr |= DVS_FORMAT_RGBX888;
666 case DRM_FORMAT_YUYV:
667 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
669 case DRM_FORMAT_YVYU:
670 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
672 case DRM_FORMAT_UYVY:
673 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
675 case DRM_FORMAT_VYUY:
676 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
679 MISSING_CASE(fb->format->format);
683 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
684 dvscntr |= DVS_TILED;
686 if (rotation & DRM_MODE_ROTATE_180)
687 dvscntr |= DVS_ROTATE_180;
689 if (key->flags & I915_SET_COLORKEY_DESTINATION)
690 dvscntr |= DVS_DEST_KEY;
691 else if (key->flags & I915_SET_COLORKEY_SOURCE)
692 dvscntr |= DVS_SOURCE_KEY;
698 g4x_update_plane(struct intel_plane *plane,
699 const struct intel_crtc_state *crtc_state,
700 const struct intel_plane_state *plane_state)
702 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
703 const struct drm_framebuffer *fb = plane_state->base.fb;
704 enum pipe pipe = plane->pipe;
705 u32 dvscntr = plane_state->ctl, dvsscale = 0;
706 u32 dvssurf_offset = plane_state->main.offset;
708 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
709 int crtc_x = plane_state->base.dst.x1;
710 int crtc_y = plane_state->base.dst.y1;
711 uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
712 uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
713 uint32_t x = plane_state->main.x;
714 uint32_t y = plane_state->main.y;
715 uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
716 uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
717 unsigned long irqflags;
719 /* Sizes are 0 based */
725 if (crtc_w != src_w || crtc_h != src_h)
726 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
728 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
730 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
733 I915_WRITE_FW(DVSKEYVAL(pipe), key->min_value);
734 I915_WRITE_FW(DVSKEYMAX(pipe), key->max_value);
735 I915_WRITE_FW(DVSKEYMSK(pipe), key->channel_mask);
738 I915_WRITE_FW(DVSSTRIDE(pipe), fb->pitches[0]);
739 I915_WRITE_FW(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
741 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
742 I915_WRITE_FW(DVSTILEOFF(pipe), (y << 16) | x);
744 I915_WRITE_FW(DVSLINOFF(pipe), linear_offset);
746 I915_WRITE_FW(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
747 I915_WRITE_FW(DVSSCALE(pipe), dvsscale);
748 I915_WRITE_FW(DVSCNTR(pipe), dvscntr);
749 I915_WRITE_FW(DVSSURF(pipe),
750 intel_plane_ggtt_offset(plane_state) + dvssurf_offset);
751 POSTING_READ_FW(DVSSURF(pipe));
753 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
757 g4x_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
759 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
760 enum pipe pipe = plane->pipe;
761 unsigned long irqflags;
763 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
765 I915_WRITE_FW(DVSCNTR(pipe), 0);
766 /* Disable the scaler */
767 I915_WRITE_FW(DVSSCALE(pipe), 0);
769 I915_WRITE_FW(DVSSURF(pipe), 0);
770 POSTING_READ_FW(DVSSURF(pipe));
772 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
776 intel_check_sprite_plane(struct intel_plane *plane,
777 struct intel_crtc_state *crtc_state,
778 struct intel_plane_state *state)
780 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
781 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
782 struct drm_framebuffer *fb = state->base.fb;
784 unsigned int crtc_w, crtc_h;
785 uint32_t src_x, src_y, src_w, src_h;
786 struct drm_rect *src = &state->base.src;
787 struct drm_rect *dst = &state->base.dst;
788 const struct drm_rect *clip = &state->clip;
790 int max_scale, min_scale;
794 *src = drm_plane_state_src(&state->base);
795 *dst = drm_plane_state_dest(&state->base);
798 state->base.visible = false;
802 /* Don't modify another pipe's plane */
803 if (plane->pipe != crtc->pipe) {
804 DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n");
808 /* FIXME check all gen limits */
809 if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > 16384) {
810 DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n");
814 /* setup can_scale, min_scale, max_scale */
815 if (INTEL_GEN(dev_priv) >= 9) {
816 /* use scaler when colorkey is not required */
817 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
820 max_scale = skl_max_scale(crtc, crtc_state);
823 min_scale = DRM_PLANE_HELPER_NO_SCALING;
824 max_scale = DRM_PLANE_HELPER_NO_SCALING;
827 can_scale = plane->can_scale;
828 max_scale = plane->max_downscale << 16;
829 min_scale = plane->can_scale ? 1 : (1 << 16);
833 * FIXME the following code does a bunch of fuzzy adjustments to the
834 * coordinates and sizes. We probably need some way to decide whether
835 * more strict checking should be done instead.
837 drm_rect_rotate(src, fb->width << 16, fb->height << 16,
838 state->base.rotation);
840 hscale = drm_rect_calc_hscale_relaxed(src, dst, min_scale, max_scale);
843 vscale = drm_rect_calc_vscale_relaxed(src, dst, min_scale, max_scale);
846 state->base.visible = drm_rect_clip_scaled(src, dst, clip, hscale, vscale);
850 crtc_w = drm_rect_width(dst);
851 crtc_h = drm_rect_height(dst);
853 if (state->base.visible) {
854 /* check again in case clipping clamped the results */
855 hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale);
857 DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n");
858 drm_rect_debug_print("src: ", src, true);
859 drm_rect_debug_print("dst: ", dst, false);
864 vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale);
866 DRM_DEBUG_KMS("Vertical scaling factor out of limits\n");
867 drm_rect_debug_print("src: ", src, true);
868 drm_rect_debug_print("dst: ", dst, false);
873 /* Make the source viewport size an exact multiple of the scaling factors. */
874 drm_rect_adjust_size(src,
875 drm_rect_width(dst) * hscale - drm_rect_width(src),
876 drm_rect_height(dst) * vscale - drm_rect_height(src));
878 drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16,
879 state->base.rotation);
881 /* sanity check to make sure the src viewport wasn't enlarged */
882 WARN_ON(src->x1 < (int) state->base.src_x ||
883 src->y1 < (int) state->base.src_y ||
884 src->x2 > (int) state->base.src_x + state->base.src_w ||
885 src->y2 > (int) state->base.src_y + state->base.src_h);
888 * Hardware doesn't handle subpixel coordinates.
889 * Adjust to (macro)pixel boundary, but be careful not to
890 * increase the source viewport size, because that could
891 * push the downscaling factor out of bounds.
893 src_x = src->x1 >> 16;
894 src_w = drm_rect_width(src) >> 16;
895 src_y = src->y1 >> 16;
896 src_h = drm_rect_height(src) >> 16;
898 if (format_is_yuv(fb->format->format)) {
903 * Must keep src and dst the
904 * same if we can't scale.
910 state->base.visible = false;
914 /* Check size restrictions when scaling */
915 if (state->base.visible && (src_w != crtc_w || src_h != crtc_h)) {
916 unsigned int width_bytes;
917 int cpp = fb->format->cpp[0];
921 /* FIXME interlacing min height is 6 */
923 if (crtc_w < 3 || crtc_h < 3)
924 state->base.visible = false;
926 if (src_w < 3 || src_h < 3)
927 state->base.visible = false;
929 width_bytes = ((src_x * cpp) & 63) + src_w * cpp;
931 if (INTEL_GEN(dev_priv) < 9 && (src_w > 2048 || src_h > 2048 ||
932 width_bytes > 4096 || fb->pitches[0] > 4096)) {
933 DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
938 if (state->base.visible) {
939 src->x1 = src_x << 16;
940 src->x2 = (src_x + src_w) << 16;
941 src->y1 = src_y << 16;
942 src->y2 = (src_y + src_h) << 16;
946 dst->x2 = crtc_x + crtc_w;
948 dst->y2 = crtc_y + crtc_h;
950 if (INTEL_GEN(dev_priv) >= 9) {
951 ret = skl_check_plane_surface(state);
955 state->ctl = skl_plane_ctl(crtc_state, state);
956 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
957 ret = i9xx_check_plane_surface(state);
961 state->ctl = vlv_sprite_ctl(crtc_state, state);
962 } else if (INTEL_GEN(dev_priv) >= 7) {
963 ret = i9xx_check_plane_surface(state);
967 state->ctl = ivb_sprite_ctl(crtc_state, state);
969 ret = i9xx_check_plane_surface(state);
973 state->ctl = g4x_sprite_ctl(crtc_state, state);
979 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
980 struct drm_file *file_priv)
982 struct drm_i915_private *dev_priv = to_i915(dev);
983 struct drm_intel_sprite_colorkey *set = data;
984 struct drm_plane *plane;
985 struct drm_plane_state *plane_state;
986 struct drm_atomic_state *state;
987 struct drm_modeset_acquire_ctx ctx;
990 /* Make sure we don't try to enable both src & dest simultaneously */
991 if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
994 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
995 set->flags & I915_SET_COLORKEY_DESTINATION)
998 plane = drm_plane_find(dev, set->plane_id);
999 if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY)
1002 drm_modeset_acquire_init(&ctx, 0);
1004 state = drm_atomic_state_alloc(plane->dev);
1009 state->acquire_ctx = &ctx;
1012 plane_state = drm_atomic_get_plane_state(state, plane);
1013 ret = PTR_ERR_OR_ZERO(plane_state);
1015 to_intel_plane_state(plane_state)->ckey = *set;
1016 ret = drm_atomic_commit(state);
1019 if (ret != -EDEADLK)
1022 drm_atomic_state_clear(state);
1023 drm_modeset_backoff(&ctx);
1026 drm_atomic_state_put(state);
1028 drm_modeset_drop_locks(&ctx);
1029 drm_modeset_acquire_fini(&ctx);
1033 static const uint32_t g4x_plane_formats[] = {
1034 DRM_FORMAT_XRGB8888,
1041 static const uint32_t snb_plane_formats[] = {
1042 DRM_FORMAT_XBGR8888,
1043 DRM_FORMAT_XRGB8888,
1050 static const uint32_t vlv_plane_formats[] = {
1052 DRM_FORMAT_ABGR8888,
1053 DRM_FORMAT_ARGB8888,
1054 DRM_FORMAT_XBGR8888,
1055 DRM_FORMAT_XRGB8888,
1056 DRM_FORMAT_XBGR2101010,
1057 DRM_FORMAT_ABGR2101010,
1064 static uint32_t skl_plane_formats[] = {
1066 DRM_FORMAT_ABGR8888,
1067 DRM_FORMAT_ARGB8888,
1068 DRM_FORMAT_XBGR8888,
1069 DRM_FORMAT_XRGB8888,
1076 struct intel_plane *
1077 intel_sprite_plane_create(struct drm_i915_private *dev_priv,
1078 enum pipe pipe, int plane)
1080 struct intel_plane *intel_plane = NULL;
1081 struct intel_plane_state *state = NULL;
1082 unsigned long possible_crtcs;
1083 const uint32_t *plane_formats;
1084 unsigned int supported_rotations;
1085 int num_plane_formats;
1088 intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL);
1094 state = intel_create_plane_state(&intel_plane->base);
1099 intel_plane->base.state = &state->base;
1101 if (INTEL_GEN(dev_priv) >= 9) {
1102 intel_plane->can_scale = true;
1103 state->scaler_id = -1;
1105 intel_plane->update_plane = skl_update_plane;
1106 intel_plane->disable_plane = skl_disable_plane;
1108 plane_formats = skl_plane_formats;
1109 num_plane_formats = ARRAY_SIZE(skl_plane_formats);
1110 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1111 intel_plane->can_scale = false;
1112 intel_plane->max_downscale = 1;
1114 intel_plane->update_plane = vlv_update_plane;
1115 intel_plane->disable_plane = vlv_disable_plane;
1117 plane_formats = vlv_plane_formats;
1118 num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
1119 } else if (INTEL_GEN(dev_priv) >= 7) {
1120 if (IS_IVYBRIDGE(dev_priv)) {
1121 intel_plane->can_scale = true;
1122 intel_plane->max_downscale = 2;
1124 intel_plane->can_scale = false;
1125 intel_plane->max_downscale = 1;
1128 intel_plane->update_plane = ivb_update_plane;
1129 intel_plane->disable_plane = ivb_disable_plane;
1131 plane_formats = snb_plane_formats;
1132 num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1134 intel_plane->can_scale = true;
1135 intel_plane->max_downscale = 16;
1137 intel_plane->update_plane = g4x_update_plane;
1138 intel_plane->disable_plane = g4x_disable_plane;
1140 if (IS_GEN6(dev_priv)) {
1141 plane_formats = snb_plane_formats;
1142 num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1144 plane_formats = g4x_plane_formats;
1145 num_plane_formats = ARRAY_SIZE(g4x_plane_formats);
1149 if (INTEL_GEN(dev_priv) >= 9) {
1150 supported_rotations =
1151 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
1152 DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
1153 } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
1154 supported_rotations =
1155 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
1158 supported_rotations =
1159 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
1162 intel_plane->pipe = pipe;
1163 intel_plane->plane = plane;
1164 intel_plane->id = PLANE_SPRITE0 + plane;
1165 intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER_SPRITE(pipe, plane);
1166 intel_plane->check_plane = intel_check_sprite_plane;
1168 possible_crtcs = (1 << pipe);
1170 if (INTEL_GEN(dev_priv) >= 9)
1171 ret = drm_universal_plane_init(&dev_priv->drm, &intel_plane->base,
1172 possible_crtcs, &intel_plane_funcs,
1173 plane_formats, num_plane_formats,
1174 DRM_PLANE_TYPE_OVERLAY,
1175 "plane %d%c", plane + 2, pipe_name(pipe));
1177 ret = drm_universal_plane_init(&dev_priv->drm, &intel_plane->base,
1178 possible_crtcs, &intel_plane_funcs,
1179 plane_formats, num_plane_formats,
1180 DRM_PLANE_TYPE_OVERLAY,
1181 "sprite %c", sprite_name(pipe, plane));
1185 drm_plane_create_rotation_property(&intel_plane->base,
1187 supported_rotations);
1189 drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs);
1197 return ERR_PTR(ret);