2 * Copyright © 2013 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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25 #include <asm/iosf_mbi.h>
28 #include "intel_sideband.h"
31 * IOSF sideband, see VLV2_SidebandMsg_HAS.docx and
32 * VLV_VLV2_PUNIT_HAS_0.8.docx
35 /* Standard MMIO read, non-posted */
36 #define SB_MRD_NP 0x00
37 /* Standard MMIO write, non-posted */
38 #define SB_MWR_NP 0x01
39 /* Private register read, double-word addressing, non-posted */
40 #define SB_CRRDDA_NP 0x06
41 /* Private register write, double-word addressing, non-posted */
42 #define SB_CRWRDA_NP 0x07
44 static void ping(void *info)
48 static void __vlv_punit_get(struct drm_i915_private *i915)
50 iosf_mbi_punit_acquire();
53 * Prevent the cpu from sleeping while we use this sideband, otherwise
54 * the punit may cause a machine hang. The issue appears to be isolated
55 * with changing the power state of the CPU package while changing
56 * the power state via the punit, and we have only observed it
57 * reliably on 4-core Baytail systems suggesting the issue is in the
58 * power delivery mechanism and likely to be be board/function
59 * specific. Hence we presume the workaround needs only be applied
60 * to the Valleyview P-unit and not all sideband communications.
62 if (IS_VALLEYVIEW(i915)) {
63 cpu_latency_qos_update_request(&i915->sb_qos, 0);
64 on_each_cpu(ping, NULL, 1);
68 static void __vlv_punit_put(struct drm_i915_private *i915)
70 if (IS_VALLEYVIEW(i915))
71 cpu_latency_qos_update_request(&i915->sb_qos,
72 PM_QOS_DEFAULT_VALUE);
74 iosf_mbi_punit_release();
77 void vlv_iosf_sb_get(struct drm_i915_private *i915, unsigned long ports)
79 if (ports & BIT(VLV_IOSF_SB_PUNIT))
80 __vlv_punit_get(i915);
82 mutex_lock(&i915->sb_lock);
85 void vlv_iosf_sb_put(struct drm_i915_private *i915, unsigned long ports)
87 mutex_unlock(&i915->sb_lock);
89 if (ports & BIT(VLV_IOSF_SB_PUNIT))
90 __vlv_punit_put(i915);
93 static int vlv_sideband_rw(struct drm_i915_private *i915,
94 u32 devfn, u32 port, u32 opcode,
97 struct intel_uncore *uncore = &i915->uncore;
98 const bool is_read = (opcode == SB_MRD_NP || opcode == SB_CRRDDA_NP);
101 lockdep_assert_held(&i915->sb_lock);
102 if (port == IOSF_PORT_PUNIT)
103 iosf_mbi_assert_punit_acquired();
105 /* Flush the previous comms, just in case it failed last time. */
106 if (intel_wait_for_register(uncore,
107 VLV_IOSF_DOORBELL_REQ, IOSF_SB_BUSY, 0,
109 drm_dbg(&i915->drm, "IOSF sideband idle wait (%s) timed out\n",
110 is_read ? "read" : "write");
116 intel_uncore_write_fw(uncore, VLV_IOSF_ADDR, addr);
117 intel_uncore_write_fw(uncore, VLV_IOSF_DATA, is_read ? 0 : *val);
118 intel_uncore_write_fw(uncore, VLV_IOSF_DOORBELL_REQ,
119 (devfn << IOSF_DEVFN_SHIFT) |
120 (opcode << IOSF_OPCODE_SHIFT) |
121 (port << IOSF_PORT_SHIFT) |
122 (0xf << IOSF_BYTE_ENABLES_SHIFT) |
123 (0 << IOSF_BAR_SHIFT) |
126 if (__intel_wait_for_register_fw(uncore,
127 VLV_IOSF_DOORBELL_REQ, IOSF_SB_BUSY, 0,
128 10000, 0, NULL) == 0) {
130 *val = intel_uncore_read_fw(uncore, VLV_IOSF_DATA);
133 drm_dbg(&i915->drm, "IOSF sideband finish wait (%s) timed out\n",
134 is_read ? "read" : "write");
143 u32 vlv_punit_read(struct drm_i915_private *i915, u32 addr)
147 vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_PUNIT,
148 SB_CRRDDA_NP, addr, &val);
153 int vlv_punit_write(struct drm_i915_private *i915, u32 addr, u32 val)
155 return vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_PUNIT,
156 SB_CRWRDA_NP, addr, &val);
159 u32 vlv_bunit_read(struct drm_i915_private *i915, u32 reg)
163 vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_BUNIT,
164 SB_CRRDDA_NP, reg, &val);
169 void vlv_bunit_write(struct drm_i915_private *i915, u32 reg, u32 val)
171 vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_BUNIT,
172 SB_CRWRDA_NP, reg, &val);
175 u32 vlv_nc_read(struct drm_i915_private *i915, u8 addr)
179 vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_NC,
180 SB_CRRDDA_NP, addr, &val);
185 u32 vlv_iosf_sb_read(struct drm_i915_private *i915, u8 port, u32 reg)
189 vlv_sideband_rw(i915, PCI_DEVFN(0, 0), port,
190 SB_CRRDDA_NP, reg, &val);
195 void vlv_iosf_sb_write(struct drm_i915_private *i915,
196 u8 port, u32 reg, u32 val)
198 vlv_sideband_rw(i915, PCI_DEVFN(0, 0), port,
199 SB_CRWRDA_NP, reg, &val);
202 u32 vlv_cck_read(struct drm_i915_private *i915, u32 reg)
206 vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_CCK,
207 SB_CRRDDA_NP, reg, &val);
212 void vlv_cck_write(struct drm_i915_private *i915, u32 reg, u32 val)
214 vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_CCK,
215 SB_CRWRDA_NP, reg, &val);
218 u32 vlv_ccu_read(struct drm_i915_private *i915, u32 reg)
222 vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_CCU,
223 SB_CRRDDA_NP, reg, &val);
228 void vlv_ccu_write(struct drm_i915_private *i915, u32 reg, u32 val)
230 vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_CCU,
231 SB_CRWRDA_NP, reg, &val);
234 u32 vlv_dpio_read(struct drm_i915_private *i915, enum pipe pipe, int reg)
236 int port = i915->dpio_phy_iosf_port[DPIO_PHY(pipe)];
239 vlv_sideband_rw(i915, DPIO_DEVFN, port, SB_MRD_NP, reg, &val);
242 * FIXME: There might be some registers where all 1's is a valid value,
243 * so ideally we should check the register offset instead...
245 WARN(val == 0xffffffff, "DPIO read pipe %c reg 0x%x == 0x%x\n",
246 pipe_name(pipe), reg, val);
251 void vlv_dpio_write(struct drm_i915_private *i915,
252 enum pipe pipe, int reg, u32 val)
254 int port = i915->dpio_phy_iosf_port[DPIO_PHY(pipe)];
256 vlv_sideband_rw(i915, DPIO_DEVFN, port, SB_MWR_NP, reg, &val);
259 u32 vlv_flisdsi_read(struct drm_i915_private *i915, u32 reg)
263 vlv_sideband_rw(i915, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRRDDA_NP,
268 void vlv_flisdsi_write(struct drm_i915_private *i915, u32 reg, u32 val)
270 vlv_sideband_rw(i915, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRWRDA_NP,
275 static int intel_sbi_rw(struct drm_i915_private *i915, u16 reg,
276 enum intel_sbi_destination destination,
277 u32 *val, bool is_read)
279 struct intel_uncore *uncore = &i915->uncore;
282 lockdep_assert_held(&i915->sb_lock);
284 if (intel_wait_for_register_fw(uncore,
285 SBI_CTL_STAT, SBI_BUSY, 0,
288 "timeout waiting for SBI to become ready\n");
292 intel_uncore_write_fw(uncore, SBI_ADDR, (u32)reg << 16);
293 intel_uncore_write_fw(uncore, SBI_DATA, is_read ? 0 : *val);
295 if (destination == SBI_ICLK)
296 cmd = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
298 cmd = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
301 intel_uncore_write_fw(uncore, SBI_CTL_STAT, cmd | SBI_BUSY);
303 if (__intel_wait_for_register_fw(uncore,
304 SBI_CTL_STAT, SBI_BUSY, 0,
307 "timeout waiting for SBI to complete read\n");
311 if (cmd & SBI_RESPONSE_FAIL) {
312 drm_err(&i915->drm, "error during SBI read of reg %x\n", reg);
317 *val = intel_uncore_read_fw(uncore, SBI_DATA);
322 u32 intel_sbi_read(struct drm_i915_private *i915, u16 reg,
323 enum intel_sbi_destination destination)
327 intel_sbi_rw(i915, reg, destination, &result, true);
332 void intel_sbi_write(struct drm_i915_private *i915, u16 reg, u32 value,
333 enum intel_sbi_destination destination)
335 intel_sbi_rw(i915, reg, destination, &value, false);
338 static inline int gen6_check_mailbox_status(u32 mbox)
340 switch (mbox & GEN6_PCODE_ERROR_MASK) {
341 case GEN6_PCODE_SUCCESS:
343 case GEN6_PCODE_UNIMPLEMENTED_CMD:
345 case GEN6_PCODE_ILLEGAL_CMD:
347 case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
348 case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
350 case GEN6_PCODE_TIMEOUT:
353 MISSING_CASE(mbox & GEN6_PCODE_ERROR_MASK);
358 static inline int gen7_check_mailbox_status(u32 mbox)
360 switch (mbox & GEN6_PCODE_ERROR_MASK) {
361 case GEN6_PCODE_SUCCESS:
363 case GEN6_PCODE_ILLEGAL_CMD:
365 case GEN7_PCODE_TIMEOUT:
367 case GEN7_PCODE_ILLEGAL_DATA:
369 case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
372 MISSING_CASE(mbox & GEN6_PCODE_ERROR_MASK);
377 static int __sandybridge_pcode_rw(struct drm_i915_private *i915,
378 u32 mbox, u32 *val, u32 *val1,
383 struct intel_uncore *uncore = &i915->uncore;
385 lockdep_assert_held(&i915->sb_lock);
388 * GEN6_PCODE_* are outside of the forcewake domain, we can
389 * use te fw I915_READ variants to reduce the amount of work
390 * required when reading/writing.
393 if (intel_uncore_read_fw(uncore, GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY)
396 intel_uncore_write_fw(uncore, GEN6_PCODE_DATA, *val);
397 intel_uncore_write_fw(uncore, GEN6_PCODE_DATA1, val1 ? *val1 : 0);
398 intel_uncore_write_fw(uncore,
399 GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
401 if (__intel_wait_for_register_fw(uncore,
410 *val = intel_uncore_read_fw(uncore, GEN6_PCODE_DATA);
412 *val1 = intel_uncore_read_fw(uncore, GEN6_PCODE_DATA1);
414 if (INTEL_GEN(i915) > 6)
415 return gen7_check_mailbox_status(mbox);
417 return gen6_check_mailbox_status(mbox);
420 int sandybridge_pcode_read(struct drm_i915_private *i915, u32 mbox,
425 mutex_lock(&i915->sb_lock);
426 err = __sandybridge_pcode_rw(i915, mbox, val, val1,
429 mutex_unlock(&i915->sb_lock);
433 "warning: pcode (read from mbox %x) mailbox access failed for %ps: %d\n",
434 mbox, __builtin_return_address(0), err);
440 int sandybridge_pcode_write_timeout(struct drm_i915_private *i915,
447 mutex_lock(&i915->sb_lock);
448 err = __sandybridge_pcode_rw(i915, mbox, &val, NULL,
449 fast_timeout_us, slow_timeout_ms,
451 mutex_unlock(&i915->sb_lock);
455 "warning: pcode (write of 0x%08x to mbox %x) mailbox access failed for %ps: %d\n",
456 val, mbox, __builtin_return_address(0), err);
462 static bool skl_pcode_try_request(struct drm_i915_private *i915, u32 mbox,
463 u32 request, u32 reply_mask, u32 reply,
466 *status = __sandybridge_pcode_rw(i915, mbox, &request, NULL,
470 return *status || ((request & reply_mask) == reply);
474 * skl_pcode_request - send PCODE request until acknowledgment
475 * @i915: device private
476 * @mbox: PCODE mailbox ID the request is targeted for
477 * @request: request ID
478 * @reply_mask: mask used to check for request acknowledgment
479 * @reply: value used to check for request acknowledgment
480 * @timeout_base_ms: timeout for polling with preemption enabled
482 * Keep resending the @request to @mbox until PCODE acknowledges it, PCODE
483 * reports an error or an overall timeout of @timeout_base_ms+50 ms expires.
484 * The request is acknowledged once the PCODE reply dword equals @reply after
485 * applying @reply_mask. Polling is first attempted with preemption enabled
486 * for @timeout_base_ms and if this times out for another 50 ms with
487 * preemption disabled.
489 * Returns 0 on success, %-ETIMEDOUT in case of a timeout, <0 in case of some
490 * other error as reported by PCODE.
492 int skl_pcode_request(struct drm_i915_private *i915, u32 mbox, u32 request,
493 u32 reply_mask, u32 reply, int timeout_base_ms)
498 mutex_lock(&i915->sb_lock);
501 skl_pcode_try_request(i915, mbox, request, reply_mask, reply, &status)
504 * Prime the PCODE by doing a request first. Normally it guarantees
505 * that a subsequent request, at most @timeout_base_ms later, succeeds.
506 * _wait_for() doesn't guarantee when its passed condition is evaluated
507 * first, so send the first request explicitly.
513 ret = _wait_for(COND, timeout_base_ms * 1000, 10, 10);
518 * The above can time out if the number of requests was low (2 in the
519 * worst case) _and_ PCODE was busy for some reason even after a
520 * (queued) request and @timeout_base_ms delay. As a workaround retry
521 * the poll with preemption disabled to maximize the number of
522 * requests. Increase the timeout from @timeout_base_ms to 50ms to
523 * account for interrupts that could reduce the number of these
524 * requests, and for any quirks of the PCODE firmware that delays
525 * the request completion.
527 drm_dbg_kms(&i915->drm,
528 "PCODE timeout, retrying with preemption disabled\n");
529 WARN_ON_ONCE(timeout_base_ms > 3);
531 ret = wait_for_atomic(COND, 50);
535 mutex_unlock(&i915->sb_lock);
536 return ret ? ret : status;