1 // SPDX-License-Identifier: MIT
3 * Copyright © 2013-2021 Intel Corporation
5 * LPT/WPT IOSF sideband.
13 static int intel_sbi_rw(struct drm_i915_private *i915, u16 reg,
14 enum intel_sbi_destination destination,
15 u32 *val, bool is_read)
17 struct intel_uncore *uncore = &i915->uncore;
20 lockdep_assert_held(&i915->sb_lock);
22 if (intel_wait_for_register_fw(uncore,
23 SBI_CTL_STAT, SBI_BUSY, 0,
26 "timeout waiting for SBI to become ready\n");
30 intel_uncore_write_fw(uncore, SBI_ADDR, (u32)reg << 16);
31 intel_uncore_write_fw(uncore, SBI_DATA, is_read ? 0 : *val);
33 if (destination == SBI_ICLK)
34 cmd = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
36 cmd = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
39 intel_uncore_write_fw(uncore, SBI_CTL_STAT, cmd | SBI_BUSY);
41 if (__intel_wait_for_register_fw(uncore,
42 SBI_CTL_STAT, SBI_BUSY, 0,
45 "timeout waiting for SBI to complete read\n");
49 if (cmd & SBI_RESPONSE_FAIL) {
50 drm_err(&i915->drm, "error during SBI read of reg %x\n", reg);
55 *val = intel_uncore_read_fw(uncore, SBI_DATA);
60 u32 intel_sbi_read(struct drm_i915_private *i915, u16 reg,
61 enum intel_sbi_destination destination)
65 intel_sbi_rw(i915, reg, destination, &result, true);
70 void intel_sbi_write(struct drm_i915_private *i915, u16 reg, u32 value,
71 enum intel_sbi_destination destination)
73 intel_sbi_rw(i915, reg, destination, &value, false);