2 * Copyright © 2008-2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
32 #include <drm/i915_drm.h>
33 #include "i915_trace.h"
34 #include "intel_drv.h"
36 static inline int ring_space(struct intel_ring_buffer *ring)
38 int space = (ring->head & HEAD_ADDR) - (ring->tail + I915_RING_FREE_SPACE);
44 void __intel_ring_advance(struct intel_ring_buffer *ring)
46 struct drm_i915_private *dev_priv = ring->dev->dev_private;
48 ring->tail &= ring->size - 1;
49 if (dev_priv->gpu_error.stop_rings & intel_ring_flag(ring))
51 ring->write_tail(ring, ring->tail);
55 gen2_render_ring_flush(struct intel_ring_buffer *ring,
56 u32 invalidate_domains,
63 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
64 cmd |= MI_NO_WRITE_FLUSH;
66 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
69 ret = intel_ring_begin(ring, 2);
73 intel_ring_emit(ring, cmd);
74 intel_ring_emit(ring, MI_NOOP);
75 intel_ring_advance(ring);
81 gen4_render_ring_flush(struct intel_ring_buffer *ring,
82 u32 invalidate_domains,
85 struct drm_device *dev = ring->dev;
92 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
93 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
94 * also flushed at 2d versus 3d pipeline switches.
98 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
99 * MI_READ_FLUSH is set, and is always flushed on 965.
101 * I915_GEM_DOMAIN_COMMAND may not exist?
103 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
104 * invalidated when MI_EXE_FLUSH is set.
106 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
107 * invalidated with every MI_FLUSH.
111 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
112 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
113 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
114 * are flushed at any MI_FLUSH.
117 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
118 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
119 cmd &= ~MI_NO_WRITE_FLUSH;
120 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
123 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
124 (IS_G4X(dev) || IS_GEN5(dev)))
125 cmd |= MI_INVALIDATE_ISP;
127 ret = intel_ring_begin(ring, 2);
131 intel_ring_emit(ring, cmd);
132 intel_ring_emit(ring, MI_NOOP);
133 intel_ring_advance(ring);
139 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
140 * implementing two workarounds on gen6. From section 1.4.7.1
141 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
143 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
144 * produced by non-pipelined state commands), software needs to first
145 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
148 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
149 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
151 * And the workaround for these two requires this workaround first:
153 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
154 * BEFORE the pipe-control with a post-sync op and no write-cache
157 * And this last workaround is tricky because of the requirements on
158 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
161 * "1 of the following must also be set:
162 * - Render Target Cache Flush Enable ([12] of DW1)
163 * - Depth Cache Flush Enable ([0] of DW1)
164 * - Stall at Pixel Scoreboard ([1] of DW1)
165 * - Depth Stall ([13] of DW1)
166 * - Post-Sync Operation ([13] of DW1)
167 * - Notify Enable ([8] of DW1)"
169 * The cache flushes require the workaround flush that triggered this
170 * one, so we can't use it. Depth stall would trigger the same.
171 * Post-sync nonzero is what triggered this second workaround, so we
172 * can't use that one either. Notify enable is IRQs, which aren't
173 * really our business. That leaves only stall at scoreboard.
176 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)
178 u32 scratch_addr = ring->scratch.gtt_offset + 128;
182 ret = intel_ring_begin(ring, 6);
186 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
187 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
188 PIPE_CONTROL_STALL_AT_SCOREBOARD);
189 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
190 intel_ring_emit(ring, 0); /* low dword */
191 intel_ring_emit(ring, 0); /* high dword */
192 intel_ring_emit(ring, MI_NOOP);
193 intel_ring_advance(ring);
195 ret = intel_ring_begin(ring, 6);
199 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
200 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
201 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
202 intel_ring_emit(ring, 0);
203 intel_ring_emit(ring, 0);
204 intel_ring_emit(ring, MI_NOOP);
205 intel_ring_advance(ring);
211 gen6_render_ring_flush(struct intel_ring_buffer *ring,
212 u32 invalidate_domains, u32 flush_domains)
215 u32 scratch_addr = ring->scratch.gtt_offset + 128;
218 /* Force SNB workarounds for PIPE_CONTROL flushes */
219 ret = intel_emit_post_sync_nonzero_flush(ring);
223 /* Just flush everything. Experiments have shown that reducing the
224 * number of bits based on the write domains has little performance
228 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
229 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
231 * Ensure that any following seqno writes only happen
232 * when the render cache is indeed flushed.
234 flags |= PIPE_CONTROL_CS_STALL;
236 if (invalidate_domains) {
237 flags |= PIPE_CONTROL_TLB_INVALIDATE;
238 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
239 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
240 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
241 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
242 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
244 * TLB invalidate requires a post-sync write.
246 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
249 ret = intel_ring_begin(ring, 4);
253 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
254 intel_ring_emit(ring, flags);
255 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
256 intel_ring_emit(ring, 0);
257 intel_ring_advance(ring);
263 gen7_render_ring_cs_stall_wa(struct intel_ring_buffer *ring)
267 ret = intel_ring_begin(ring, 4);
271 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
272 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
273 PIPE_CONTROL_STALL_AT_SCOREBOARD);
274 intel_ring_emit(ring, 0);
275 intel_ring_emit(ring, 0);
276 intel_ring_advance(ring);
281 static int gen7_ring_fbc_flush(struct intel_ring_buffer *ring, u32 value)
285 if (!ring->fbc_dirty)
288 ret = intel_ring_begin(ring, 6);
291 /* WaFbcNukeOn3DBlt:ivb/hsw */
292 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
293 intel_ring_emit(ring, MSG_FBC_REND_STATE);
294 intel_ring_emit(ring, value);
295 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT);
296 intel_ring_emit(ring, MSG_FBC_REND_STATE);
297 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
298 intel_ring_advance(ring);
300 ring->fbc_dirty = false;
305 gen7_render_ring_flush(struct intel_ring_buffer *ring,
306 u32 invalidate_domains, u32 flush_domains)
309 u32 scratch_addr = ring->scratch.gtt_offset + 128;
313 * Ensure that any following seqno writes only happen when the render
314 * cache is indeed flushed.
316 * Workaround: 4th PIPE_CONTROL command (except the ones with only
317 * read-cache invalidate bits set) must have the CS_STALL bit set. We
318 * don't try to be clever and just set it unconditionally.
320 flags |= PIPE_CONTROL_CS_STALL;
322 /* Just flush everything. Experiments have shown that reducing the
323 * number of bits based on the write domains has little performance
327 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
328 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
330 if (invalidate_domains) {
331 flags |= PIPE_CONTROL_TLB_INVALIDATE;
332 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
333 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
334 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
335 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
336 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
338 * TLB invalidate requires a post-sync write.
340 flags |= PIPE_CONTROL_QW_WRITE;
341 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
343 /* Workaround: we must issue a pipe_control with CS-stall bit
344 * set before a pipe_control command that has the state cache
345 * invalidate bit set. */
346 gen7_render_ring_cs_stall_wa(ring);
349 ret = intel_ring_begin(ring, 4);
353 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
354 intel_ring_emit(ring, flags);
355 intel_ring_emit(ring, scratch_addr);
356 intel_ring_emit(ring, 0);
357 intel_ring_advance(ring);
359 if (!invalidate_domains && flush_domains)
360 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
366 gen8_render_ring_flush(struct intel_ring_buffer *ring,
367 u32 invalidate_domains, u32 flush_domains)
370 u32 scratch_addr = ring->scratch.gtt_offset + 128;
373 flags |= PIPE_CONTROL_CS_STALL;
376 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
377 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
379 if (invalidate_domains) {
380 flags |= PIPE_CONTROL_TLB_INVALIDATE;
381 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
382 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
383 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
384 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
385 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
386 flags |= PIPE_CONTROL_QW_WRITE;
387 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
390 ret = intel_ring_begin(ring, 6);
394 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
395 intel_ring_emit(ring, flags);
396 intel_ring_emit(ring, scratch_addr);
397 intel_ring_emit(ring, 0);
398 intel_ring_emit(ring, 0);
399 intel_ring_emit(ring, 0);
400 intel_ring_advance(ring);
406 static void ring_write_tail(struct intel_ring_buffer *ring,
409 drm_i915_private_t *dev_priv = ring->dev->dev_private;
410 I915_WRITE_TAIL(ring, value);
413 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
415 drm_i915_private_t *dev_priv = ring->dev->dev_private;
416 u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
417 RING_ACTHD(ring->mmio_base) : ACTHD;
419 return I915_READ(acthd_reg);
422 static void ring_setup_phys_status_page(struct intel_ring_buffer *ring)
424 struct drm_i915_private *dev_priv = ring->dev->dev_private;
427 addr = dev_priv->status_page_dmah->busaddr;
428 if (INTEL_INFO(ring->dev)->gen >= 4)
429 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
430 I915_WRITE(HWS_PGA, addr);
433 static int init_ring_common(struct intel_ring_buffer *ring)
435 struct drm_device *dev = ring->dev;
436 drm_i915_private_t *dev_priv = dev->dev_private;
437 struct drm_i915_gem_object *obj = ring->obj;
441 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
443 /* Stop the ring if it's running. */
444 I915_WRITE_CTL(ring, 0);
445 I915_WRITE_HEAD(ring, 0);
446 ring->write_tail(ring, 0);
447 if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000))
448 DRM_ERROR("%s :timed out trying to stop ring\n", ring->name);
450 if (I915_NEED_GFX_HWS(dev))
451 intel_ring_setup_status_page(ring);
453 ring_setup_phys_status_page(ring);
455 head = I915_READ_HEAD(ring) & HEAD_ADDR;
457 /* G45 ring initialization fails to reset head to zero */
459 DRM_DEBUG_KMS("%s head not reset to zero "
460 "ctl %08x head %08x tail %08x start %08x\n",
463 I915_READ_HEAD(ring),
464 I915_READ_TAIL(ring),
465 I915_READ_START(ring));
467 I915_WRITE_HEAD(ring, 0);
469 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
470 DRM_ERROR("failed to set %s head to zero "
471 "ctl %08x head %08x tail %08x start %08x\n",
474 I915_READ_HEAD(ring),
475 I915_READ_TAIL(ring),
476 I915_READ_START(ring));
480 /* Initialize the ring. This must happen _after_ we've cleared the ring
481 * registers with the above sequence (the readback of the HEAD registers
482 * also enforces ordering), otherwise the hw might lose the new ring
483 * register values. */
484 I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
486 ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
489 /* If the head is still not zero, the ring is dead */
490 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
491 I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
492 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
493 DRM_ERROR("%s initialization failed "
494 "ctl %08x head %08x tail %08x start %08x\n",
497 I915_READ_HEAD(ring),
498 I915_READ_TAIL(ring),
499 I915_READ_START(ring));
504 if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
505 i915_kernel_lost_context(ring->dev);
507 ring->head = I915_READ_HEAD(ring);
508 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
509 ring->space = ring_space(ring);
510 ring->last_retired_head = -1;
513 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
516 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
522 init_pipe_control(struct intel_ring_buffer *ring)
526 if (ring->scratch.obj)
529 ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
530 if (ring->scratch.obj == NULL) {
531 DRM_ERROR("Failed to allocate seqno page\n");
536 ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
540 ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
544 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
545 ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
546 if (ring->scratch.cpu_page == NULL) {
551 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
552 ring->name, ring->scratch.gtt_offset);
556 i915_gem_object_ggtt_unpin(ring->scratch.obj);
558 drm_gem_object_unreference(&ring->scratch.obj->base);
563 static int init_render_ring(struct intel_ring_buffer *ring)
565 struct drm_device *dev = ring->dev;
566 struct drm_i915_private *dev_priv = dev->dev_private;
567 int ret = init_ring_common(ring);
569 if (INTEL_INFO(dev)->gen > 3)
570 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
572 /* We need to disable the AsyncFlip performance optimisations in order
573 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
574 * programmed to '1' on all products.
576 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw
578 if (INTEL_INFO(dev)->gen >= 6)
579 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
581 /* Required for the hardware to program scanline values for waiting */
582 if (INTEL_INFO(dev)->gen == 6)
584 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_ALWAYS));
587 I915_WRITE(GFX_MODE_GEN7,
588 _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
589 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
591 if (INTEL_INFO(dev)->gen >= 5) {
592 ret = init_pipe_control(ring);
598 /* From the Sandybridge PRM, volume 1 part 3, page 24:
599 * "If this bit is set, STCunit will have LRA as replacement
600 * policy. [...] This bit must be reset. LRA replacement
601 * policy is not supported."
603 I915_WRITE(CACHE_MODE_0,
604 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
606 /* This is not explicitly set for GEN6, so read the register.
607 * see intel_ring_mi_set_context() for why we care.
608 * TODO: consider explicitly setting the bit for GEN5
610 ring->itlb_before_ctx_switch =
611 !!(I915_READ(GFX_MODE) & GFX_TLB_INVALIDATE_ALWAYS);
614 if (INTEL_INFO(dev)->gen >= 6)
615 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
618 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
623 static void render_ring_cleanup(struct intel_ring_buffer *ring)
625 struct drm_device *dev = ring->dev;
627 if (ring->scratch.obj == NULL)
630 if (INTEL_INFO(dev)->gen >= 5) {
631 kunmap(sg_page(ring->scratch.obj->pages->sgl));
632 i915_gem_object_ggtt_unpin(ring->scratch.obj);
635 drm_gem_object_unreference(&ring->scratch.obj->base);
636 ring->scratch.obj = NULL;
640 update_mboxes(struct intel_ring_buffer *ring,
643 /* NB: In order to be able to do semaphore MBOX updates for varying number
644 * of rings, it's easiest if we round up each individual update to a
645 * multiple of 2 (since ring updates must always be a multiple of 2)
646 * even though the actual update only requires 3 dwords.
648 #define MBOX_UPDATE_DWORDS 4
649 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
650 intel_ring_emit(ring, mmio_offset);
651 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
652 intel_ring_emit(ring, MI_NOOP);
656 * gen6_add_request - Update the semaphore mailbox registers
658 * @ring - ring that is adding a request
659 * @seqno - return seqno stuck into the ring
661 * Update the mailbox registers in the *other* rings with the current seqno.
662 * This acts like a signal in the canonical semaphore.
665 gen6_add_request(struct intel_ring_buffer *ring)
667 struct drm_device *dev = ring->dev;
668 struct drm_i915_private *dev_priv = dev->dev_private;
669 struct intel_ring_buffer *useless;
670 int i, ret, num_dwords = 4;
672 if (i915_semaphore_is_enabled(dev))
673 num_dwords += ((I915_NUM_RINGS-1) * MBOX_UPDATE_DWORDS);
674 #undef MBOX_UPDATE_DWORDS
676 ret = intel_ring_begin(ring, num_dwords);
680 if (i915_semaphore_is_enabled(dev)) {
681 for_each_ring(useless, dev_priv, i) {
682 u32 mbox_reg = ring->signal_mbox[i];
683 if (mbox_reg != GEN6_NOSYNC)
684 update_mboxes(ring, mbox_reg);
688 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
689 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
690 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
691 intel_ring_emit(ring, MI_USER_INTERRUPT);
692 __intel_ring_advance(ring);
697 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
700 struct drm_i915_private *dev_priv = dev->dev_private;
701 return dev_priv->last_seqno < seqno;
705 * intel_ring_sync - sync the waiter to the signaller on seqno
707 * @waiter - ring that is waiting
708 * @signaller - ring which has, or will signal
709 * @seqno - seqno which the waiter will block on
712 gen6_ring_sync(struct intel_ring_buffer *waiter,
713 struct intel_ring_buffer *signaller,
717 u32 dw1 = MI_SEMAPHORE_MBOX |
718 MI_SEMAPHORE_COMPARE |
719 MI_SEMAPHORE_REGISTER;
721 /* Throughout all of the GEM code, seqno passed implies our current
722 * seqno is >= the last seqno executed. However for hardware the
723 * comparison is strictly greater than.
727 WARN_ON(signaller->semaphore_register[waiter->id] ==
728 MI_SEMAPHORE_SYNC_INVALID);
730 ret = intel_ring_begin(waiter, 4);
734 /* If seqno wrap happened, omit the wait with no-ops */
735 if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
736 intel_ring_emit(waiter,
738 signaller->semaphore_register[waiter->id]);
739 intel_ring_emit(waiter, seqno);
740 intel_ring_emit(waiter, 0);
741 intel_ring_emit(waiter, MI_NOOP);
743 intel_ring_emit(waiter, MI_NOOP);
744 intel_ring_emit(waiter, MI_NOOP);
745 intel_ring_emit(waiter, MI_NOOP);
746 intel_ring_emit(waiter, MI_NOOP);
748 intel_ring_advance(waiter);
753 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
755 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
756 PIPE_CONTROL_DEPTH_STALL); \
757 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
758 intel_ring_emit(ring__, 0); \
759 intel_ring_emit(ring__, 0); \
763 pc_render_add_request(struct intel_ring_buffer *ring)
765 u32 scratch_addr = ring->scratch.gtt_offset + 128;
768 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
769 * incoherent with writes to memory, i.e. completely fubar,
770 * so we need to use PIPE_NOTIFY instead.
772 * However, we also need to workaround the qword write
773 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
774 * memory before requesting an interrupt.
776 ret = intel_ring_begin(ring, 32);
780 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
781 PIPE_CONTROL_WRITE_FLUSH |
782 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
783 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
784 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
785 intel_ring_emit(ring, 0);
786 PIPE_CONTROL_FLUSH(ring, scratch_addr);
787 scratch_addr += 128; /* write to separate cachelines */
788 PIPE_CONTROL_FLUSH(ring, scratch_addr);
790 PIPE_CONTROL_FLUSH(ring, scratch_addr);
792 PIPE_CONTROL_FLUSH(ring, scratch_addr);
794 PIPE_CONTROL_FLUSH(ring, scratch_addr);
796 PIPE_CONTROL_FLUSH(ring, scratch_addr);
798 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
799 PIPE_CONTROL_WRITE_FLUSH |
800 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
801 PIPE_CONTROL_NOTIFY);
802 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
803 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
804 intel_ring_emit(ring, 0);
805 __intel_ring_advance(ring);
811 gen6_ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
813 /* Workaround to force correct ordering between irq and seqno writes on
814 * ivb (and maybe also on snb) by reading from a CS register (like
815 * ACTHD) before reading the status page. */
817 intel_ring_get_active_head(ring);
818 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
822 ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
824 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
828 ring_set_seqno(struct intel_ring_buffer *ring, u32 seqno)
830 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
834 pc_render_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
836 return ring->scratch.cpu_page[0];
840 pc_render_set_seqno(struct intel_ring_buffer *ring, u32 seqno)
842 ring->scratch.cpu_page[0] = seqno;
846 gen5_ring_get_irq(struct intel_ring_buffer *ring)
848 struct drm_device *dev = ring->dev;
849 drm_i915_private_t *dev_priv = dev->dev_private;
852 if (!dev->irq_enabled)
855 spin_lock_irqsave(&dev_priv->irq_lock, flags);
856 if (ring->irq_refcount++ == 0)
857 ilk_enable_gt_irq(dev_priv, ring->irq_enable_mask);
858 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
864 gen5_ring_put_irq(struct intel_ring_buffer *ring)
866 struct drm_device *dev = ring->dev;
867 drm_i915_private_t *dev_priv = dev->dev_private;
870 spin_lock_irqsave(&dev_priv->irq_lock, flags);
871 if (--ring->irq_refcount == 0)
872 ilk_disable_gt_irq(dev_priv, ring->irq_enable_mask);
873 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
877 i9xx_ring_get_irq(struct intel_ring_buffer *ring)
879 struct drm_device *dev = ring->dev;
880 drm_i915_private_t *dev_priv = dev->dev_private;
883 if (!dev->irq_enabled)
886 spin_lock_irqsave(&dev_priv->irq_lock, flags);
887 if (ring->irq_refcount++ == 0) {
888 dev_priv->irq_mask &= ~ring->irq_enable_mask;
889 I915_WRITE(IMR, dev_priv->irq_mask);
892 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
898 i9xx_ring_put_irq(struct intel_ring_buffer *ring)
900 struct drm_device *dev = ring->dev;
901 drm_i915_private_t *dev_priv = dev->dev_private;
904 spin_lock_irqsave(&dev_priv->irq_lock, flags);
905 if (--ring->irq_refcount == 0) {
906 dev_priv->irq_mask |= ring->irq_enable_mask;
907 I915_WRITE(IMR, dev_priv->irq_mask);
910 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
914 i8xx_ring_get_irq(struct intel_ring_buffer *ring)
916 struct drm_device *dev = ring->dev;
917 drm_i915_private_t *dev_priv = dev->dev_private;
920 if (!dev->irq_enabled)
923 spin_lock_irqsave(&dev_priv->irq_lock, flags);
924 if (ring->irq_refcount++ == 0) {
925 dev_priv->irq_mask &= ~ring->irq_enable_mask;
926 I915_WRITE16(IMR, dev_priv->irq_mask);
929 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
935 i8xx_ring_put_irq(struct intel_ring_buffer *ring)
937 struct drm_device *dev = ring->dev;
938 drm_i915_private_t *dev_priv = dev->dev_private;
941 spin_lock_irqsave(&dev_priv->irq_lock, flags);
942 if (--ring->irq_refcount == 0) {
943 dev_priv->irq_mask |= ring->irq_enable_mask;
944 I915_WRITE16(IMR, dev_priv->irq_mask);
947 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
950 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
952 struct drm_device *dev = ring->dev;
953 drm_i915_private_t *dev_priv = ring->dev->dev_private;
956 /* The ring status page addresses are no longer next to the rest of
957 * the ring registers as of gen7.
962 mmio = RENDER_HWS_PGA_GEN7;
965 mmio = BLT_HWS_PGA_GEN7;
968 mmio = BSD_HWS_PGA_GEN7;
971 mmio = VEBOX_HWS_PGA_GEN7;
974 } else if (IS_GEN6(ring->dev)) {
975 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
977 /* XXX: gen8 returns to sanity */
978 mmio = RING_HWS_PGA(ring->mmio_base);
981 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
985 * Flush the TLB for this page
987 * FIXME: These two bits have disappeared on gen8, so a question
988 * arises: do we still need this and if so how should we go about
989 * invalidating the TLB?
991 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
992 u32 reg = RING_INSTPM(ring->mmio_base);
994 /* ring should be idle before issuing a sync flush*/
995 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
998 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
1000 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
1002 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
1008 bsd_ring_flush(struct intel_ring_buffer *ring,
1009 u32 invalidate_domains,
1014 ret = intel_ring_begin(ring, 2);
1018 intel_ring_emit(ring, MI_FLUSH);
1019 intel_ring_emit(ring, MI_NOOP);
1020 intel_ring_advance(ring);
1025 i9xx_add_request(struct intel_ring_buffer *ring)
1029 ret = intel_ring_begin(ring, 4);
1033 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1034 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1035 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
1036 intel_ring_emit(ring, MI_USER_INTERRUPT);
1037 __intel_ring_advance(ring);
1043 gen6_ring_get_irq(struct intel_ring_buffer *ring)
1045 struct drm_device *dev = ring->dev;
1046 drm_i915_private_t *dev_priv = dev->dev_private;
1047 unsigned long flags;
1049 if (!dev->irq_enabled)
1052 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1053 if (ring->irq_refcount++ == 0) {
1054 if (HAS_L3_DPF(dev) && ring->id == RCS)
1055 I915_WRITE_IMR(ring,
1056 ~(ring->irq_enable_mask |
1057 GT_PARITY_ERROR(dev)));
1059 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1060 ilk_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1062 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1068 gen6_ring_put_irq(struct intel_ring_buffer *ring)
1070 struct drm_device *dev = ring->dev;
1071 drm_i915_private_t *dev_priv = dev->dev_private;
1072 unsigned long flags;
1074 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1075 if (--ring->irq_refcount == 0) {
1076 if (HAS_L3_DPF(dev) && ring->id == RCS)
1077 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1079 I915_WRITE_IMR(ring, ~0);
1080 ilk_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1082 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1086 hsw_vebox_get_irq(struct intel_ring_buffer *ring)
1088 struct drm_device *dev = ring->dev;
1089 struct drm_i915_private *dev_priv = dev->dev_private;
1090 unsigned long flags;
1092 if (!dev->irq_enabled)
1095 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1096 if (ring->irq_refcount++ == 0) {
1097 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1098 snb_enable_pm_irq(dev_priv, ring->irq_enable_mask);
1100 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1106 hsw_vebox_put_irq(struct intel_ring_buffer *ring)
1108 struct drm_device *dev = ring->dev;
1109 struct drm_i915_private *dev_priv = dev->dev_private;
1110 unsigned long flags;
1112 if (!dev->irq_enabled)
1115 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1116 if (--ring->irq_refcount == 0) {
1117 I915_WRITE_IMR(ring, ~0);
1118 snb_disable_pm_irq(dev_priv, ring->irq_enable_mask);
1120 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1124 gen8_ring_get_irq(struct intel_ring_buffer *ring)
1126 struct drm_device *dev = ring->dev;
1127 struct drm_i915_private *dev_priv = dev->dev_private;
1128 unsigned long flags;
1130 if (!dev->irq_enabled)
1133 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1134 if (ring->irq_refcount++ == 0) {
1135 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1136 I915_WRITE_IMR(ring,
1137 ~(ring->irq_enable_mask |
1138 GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1140 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1142 POSTING_READ(RING_IMR(ring->mmio_base));
1144 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1150 gen8_ring_put_irq(struct intel_ring_buffer *ring)
1152 struct drm_device *dev = ring->dev;
1153 struct drm_i915_private *dev_priv = dev->dev_private;
1154 unsigned long flags;
1156 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1157 if (--ring->irq_refcount == 0) {
1158 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1159 I915_WRITE_IMR(ring,
1160 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1162 I915_WRITE_IMR(ring, ~0);
1164 POSTING_READ(RING_IMR(ring->mmio_base));
1166 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1170 i965_dispatch_execbuffer(struct intel_ring_buffer *ring,
1171 u32 offset, u32 length,
1176 ret = intel_ring_begin(ring, 2);
1180 intel_ring_emit(ring,
1181 MI_BATCH_BUFFER_START |
1183 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1184 intel_ring_emit(ring, offset);
1185 intel_ring_advance(ring);
1190 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1191 #define I830_BATCH_LIMIT (256*1024)
1193 i830_dispatch_execbuffer(struct intel_ring_buffer *ring,
1194 u32 offset, u32 len,
1199 if (flags & I915_DISPATCH_PINNED) {
1200 ret = intel_ring_begin(ring, 4);
1204 intel_ring_emit(ring, MI_BATCH_BUFFER);
1205 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1206 intel_ring_emit(ring, offset + len - 8);
1207 intel_ring_emit(ring, MI_NOOP);
1208 intel_ring_advance(ring);
1210 u32 cs_offset = ring->scratch.gtt_offset;
1212 if (len > I830_BATCH_LIMIT)
1215 ret = intel_ring_begin(ring, 9+3);
1218 /* Blit the batch (which has now all relocs applied) to the stable batch
1219 * scratch bo area (so that the CS never stumbles over its tlb
1220 * invalidation bug) ... */
1221 intel_ring_emit(ring, XY_SRC_COPY_BLT_CMD |
1222 XY_SRC_COPY_BLT_WRITE_ALPHA |
1223 XY_SRC_COPY_BLT_WRITE_RGB);
1224 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_GXCOPY | 4096);
1225 intel_ring_emit(ring, 0);
1226 intel_ring_emit(ring, (DIV_ROUND_UP(len, 4096) << 16) | 1024);
1227 intel_ring_emit(ring, cs_offset);
1228 intel_ring_emit(ring, 0);
1229 intel_ring_emit(ring, 4096);
1230 intel_ring_emit(ring, offset);
1231 intel_ring_emit(ring, MI_FLUSH);
1233 /* ... and execute it. */
1234 intel_ring_emit(ring, MI_BATCH_BUFFER);
1235 intel_ring_emit(ring, cs_offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1236 intel_ring_emit(ring, cs_offset + len - 8);
1237 intel_ring_advance(ring);
1244 i915_dispatch_execbuffer(struct intel_ring_buffer *ring,
1245 u32 offset, u32 len,
1250 ret = intel_ring_begin(ring, 2);
1254 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1255 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1256 intel_ring_advance(ring);
1261 static void cleanup_status_page(struct intel_ring_buffer *ring)
1263 struct drm_i915_gem_object *obj;
1265 obj = ring->status_page.obj;
1269 kunmap(sg_page(obj->pages->sgl));
1270 i915_gem_object_ggtt_unpin(obj);
1271 drm_gem_object_unreference(&obj->base);
1272 ring->status_page.obj = NULL;
1275 static int init_status_page(struct intel_ring_buffer *ring)
1277 struct drm_device *dev = ring->dev;
1278 struct drm_i915_gem_object *obj;
1281 obj = i915_gem_alloc_object(dev, 4096);
1283 DRM_ERROR("Failed to allocate status page\n");
1288 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1292 ret = i915_gem_obj_ggtt_pin(obj, 4096, 0);
1296 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
1297 ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1298 if (ring->status_page.page_addr == NULL) {
1302 ring->status_page.obj = obj;
1303 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1305 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1306 ring->name, ring->status_page.gfx_addr);
1311 i915_gem_object_ggtt_unpin(obj);
1313 drm_gem_object_unreference(&obj->base);
1318 static int init_phys_status_page(struct intel_ring_buffer *ring)
1320 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1322 if (!dev_priv->status_page_dmah) {
1323 dev_priv->status_page_dmah =
1324 drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1325 if (!dev_priv->status_page_dmah)
1329 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1330 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1335 static int intel_init_ring_buffer(struct drm_device *dev,
1336 struct intel_ring_buffer *ring)
1338 struct drm_i915_gem_object *obj;
1339 struct drm_i915_private *dev_priv = dev->dev_private;
1343 INIT_LIST_HEAD(&ring->active_list);
1344 INIT_LIST_HEAD(&ring->request_list);
1345 ring->size = 32 * PAGE_SIZE;
1346 memset(ring->sync_seqno, 0, sizeof(ring->sync_seqno));
1348 init_waitqueue_head(&ring->irq_queue);
1350 if (I915_NEED_GFX_HWS(dev)) {
1351 ret = init_status_page(ring);
1355 BUG_ON(ring->id != RCS);
1356 ret = init_phys_status_page(ring);
1363 obj = i915_gem_object_create_stolen(dev, ring->size);
1365 obj = i915_gem_alloc_object(dev, ring->size);
1367 DRM_ERROR("Failed to allocate ringbuffer\n");
1374 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
1378 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1382 ring->virtual_start =
1383 ioremap_wc(dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj),
1385 if (ring->virtual_start == NULL) {
1386 DRM_ERROR("Failed to map ringbuffer.\n");
1391 ret = ring->init(ring);
1395 /* Workaround an erratum on the i830 which causes a hang if
1396 * the TAIL pointer points to within the last 2 cachelines
1399 ring->effective_size = ring->size;
1400 if (IS_I830(ring->dev) || IS_845G(ring->dev))
1401 ring->effective_size -= 128;
1403 i915_cmd_parser_init_ring(ring);
1408 iounmap(ring->virtual_start);
1410 i915_gem_object_ggtt_unpin(obj);
1412 drm_gem_object_unreference(&obj->base);
1415 cleanup_status_page(ring);
1419 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
1421 struct drm_i915_private *dev_priv;
1424 if (ring->obj == NULL)
1427 /* Disable the ring buffer. The ring must be idle at this point */
1428 dev_priv = ring->dev->dev_private;
1429 ret = intel_ring_idle(ring);
1430 if (ret && !i915_reset_in_progress(&dev_priv->gpu_error))
1431 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1434 I915_WRITE_CTL(ring, 0);
1436 iounmap(ring->virtual_start);
1438 i915_gem_object_ggtt_unpin(ring->obj);
1439 drm_gem_object_unreference(&ring->obj->base);
1441 ring->preallocated_lazy_request = NULL;
1442 ring->outstanding_lazy_seqno = 0;
1445 ring->cleanup(ring);
1447 cleanup_status_page(ring);
1450 static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n)
1452 struct drm_i915_gem_request *request;
1453 u32 seqno = 0, tail;
1456 if (ring->last_retired_head != -1) {
1457 ring->head = ring->last_retired_head;
1458 ring->last_retired_head = -1;
1460 ring->space = ring_space(ring);
1461 if (ring->space >= n)
1465 list_for_each_entry(request, &ring->request_list, list) {
1468 if (request->tail == -1)
1471 space = request->tail - (ring->tail + I915_RING_FREE_SPACE);
1473 space += ring->size;
1475 seqno = request->seqno;
1476 tail = request->tail;
1480 /* Consume this request in case we need more space than
1481 * is available and so need to prevent a race between
1482 * updating last_retired_head and direct reads of
1483 * I915_RING_HEAD. It also provides a nice sanity check.
1491 ret = i915_wait_seqno(ring, seqno);
1496 ring->space = ring_space(ring);
1497 if (WARN_ON(ring->space < n))
1503 static int ring_wait_for_space(struct intel_ring_buffer *ring, int n)
1505 struct drm_device *dev = ring->dev;
1506 struct drm_i915_private *dev_priv = dev->dev_private;
1510 ret = intel_ring_wait_request(ring, n);
1514 /* force the tail write in case we have been skipping them */
1515 __intel_ring_advance(ring);
1517 trace_i915_ring_wait_begin(ring);
1518 /* With GEM the hangcheck timer should kick us out of the loop,
1519 * leaving it early runs the risk of corrupting GEM state (due
1520 * to running on almost untested codepaths). But on resume
1521 * timers don't work yet, so prevent a complete hang in that
1522 * case by choosing an insanely large timeout. */
1523 end = jiffies + 60 * HZ;
1526 ring->head = I915_READ_HEAD(ring);
1527 ring->space = ring_space(ring);
1528 if (ring->space >= n) {
1529 trace_i915_ring_wait_end(ring);
1533 if (!drm_core_check_feature(dev, DRIVER_MODESET) &&
1534 dev->primary->master) {
1535 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1536 if (master_priv->sarea_priv)
1537 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1542 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1543 dev_priv->mm.interruptible);
1546 } while (!time_after(jiffies, end));
1547 trace_i915_ring_wait_end(ring);
1551 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
1553 uint32_t __iomem *virt;
1554 int rem = ring->size - ring->tail;
1556 if (ring->space < rem) {
1557 int ret = ring_wait_for_space(ring, rem);
1562 virt = ring->virtual_start + ring->tail;
1565 iowrite32(MI_NOOP, virt++);
1568 ring->space = ring_space(ring);
1573 int intel_ring_idle(struct intel_ring_buffer *ring)
1578 /* We need to add any requests required to flush the objects and ring */
1579 if (ring->outstanding_lazy_seqno) {
1580 ret = i915_add_request(ring, NULL);
1585 /* Wait upon the last request to be completed */
1586 if (list_empty(&ring->request_list))
1589 seqno = list_entry(ring->request_list.prev,
1590 struct drm_i915_gem_request,
1593 return i915_wait_seqno(ring, seqno);
1597 intel_ring_alloc_seqno(struct intel_ring_buffer *ring)
1599 if (ring->outstanding_lazy_seqno)
1602 if (ring->preallocated_lazy_request == NULL) {
1603 struct drm_i915_gem_request *request;
1605 request = kmalloc(sizeof(*request), GFP_KERNEL);
1606 if (request == NULL)
1609 ring->preallocated_lazy_request = request;
1612 return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_seqno);
1615 static int __intel_ring_prepare(struct intel_ring_buffer *ring,
1620 if (unlikely(ring->tail + bytes > ring->effective_size)) {
1621 ret = intel_wrap_ring_buffer(ring);
1626 if (unlikely(ring->space < bytes)) {
1627 ret = ring_wait_for_space(ring, bytes);
1635 int intel_ring_begin(struct intel_ring_buffer *ring,
1638 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1641 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1642 dev_priv->mm.interruptible);
1646 ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
1650 /* Preallocate the olr before touching the ring */
1651 ret = intel_ring_alloc_seqno(ring);
1655 ring->space -= num_dwords * sizeof(uint32_t);
1659 /* Align the ring tail to a cacheline boundary */
1660 int intel_ring_cacheline_align(struct intel_ring_buffer *ring)
1662 int num_dwords = (64 - (ring->tail & 63)) / sizeof(uint32_t);
1665 if (num_dwords == 0)
1668 ret = intel_ring_begin(ring, num_dwords);
1672 while (num_dwords--)
1673 intel_ring_emit(ring, MI_NOOP);
1675 intel_ring_advance(ring);
1680 void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno)
1682 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1684 BUG_ON(ring->outstanding_lazy_seqno);
1686 if (INTEL_INFO(ring->dev)->gen >= 6) {
1687 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
1688 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
1689 if (HAS_VEBOX(ring->dev))
1690 I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
1693 ring->set_seqno(ring, seqno);
1694 ring->hangcheck.seqno = seqno;
1697 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1700 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1702 /* Every tail move must follow the sequence below */
1704 /* Disable notification that the ring is IDLE. The GT
1705 * will then assume that it is busy and bring it out of rc6.
1707 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1708 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1710 /* Clear the context id. Here be magic! */
1711 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
1713 /* Wait for the ring not to be idle, i.e. for it to wake up. */
1714 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1715 GEN6_BSD_SLEEP_INDICATOR) == 0,
1717 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
1719 /* Now that the ring is fully powered up, update the tail */
1720 I915_WRITE_TAIL(ring, value);
1721 POSTING_READ(RING_TAIL(ring->mmio_base));
1723 /* Let the ring send IDLE messages to the GT again,
1724 * and so let it sleep to conserve power when idle.
1726 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1727 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1730 static int gen6_bsd_ring_flush(struct intel_ring_buffer *ring,
1731 u32 invalidate, u32 flush)
1736 ret = intel_ring_begin(ring, 4);
1741 if (INTEL_INFO(ring->dev)->gen >= 8)
1744 * Bspec vol 1c.5 - video engine command streamer:
1745 * "If ENABLED, all TLBs will be invalidated once the flush
1746 * operation is complete. This bit is only valid when the
1747 * Post-Sync Operation field is a value of 1h or 3h."
1749 if (invalidate & I915_GEM_GPU_DOMAINS)
1750 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
1751 MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1752 intel_ring_emit(ring, cmd);
1753 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1754 if (INTEL_INFO(ring->dev)->gen >= 8) {
1755 intel_ring_emit(ring, 0); /* upper addr */
1756 intel_ring_emit(ring, 0); /* value */
1758 intel_ring_emit(ring, 0);
1759 intel_ring_emit(ring, MI_NOOP);
1761 intel_ring_advance(ring);
1766 gen8_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1767 u32 offset, u32 len,
1770 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1771 bool ppgtt = dev_priv->mm.aliasing_ppgtt != NULL &&
1772 !(flags & I915_DISPATCH_SECURE);
1775 ret = intel_ring_begin(ring, 4);
1779 /* FIXME(BDW): Address space and security selectors. */
1780 intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
1781 intel_ring_emit(ring, offset);
1782 intel_ring_emit(ring, 0);
1783 intel_ring_emit(ring, MI_NOOP);
1784 intel_ring_advance(ring);
1790 hsw_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1791 u32 offset, u32 len,
1796 ret = intel_ring_begin(ring, 2);
1800 intel_ring_emit(ring,
1801 MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW |
1802 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_HSW));
1803 /* bit0-7 is the length on GEN6+ */
1804 intel_ring_emit(ring, offset);
1805 intel_ring_advance(ring);
1811 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1812 u32 offset, u32 len,
1817 ret = intel_ring_begin(ring, 2);
1821 intel_ring_emit(ring,
1822 MI_BATCH_BUFFER_START |
1823 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1824 /* bit0-7 is the length on GEN6+ */
1825 intel_ring_emit(ring, offset);
1826 intel_ring_advance(ring);
1831 /* Blitter support (SandyBridge+) */
1833 static int gen6_ring_flush(struct intel_ring_buffer *ring,
1834 u32 invalidate, u32 flush)
1836 struct drm_device *dev = ring->dev;
1840 ret = intel_ring_begin(ring, 4);
1845 if (INTEL_INFO(ring->dev)->gen >= 8)
1848 * Bspec vol 1c.3 - blitter engine command streamer:
1849 * "If ENABLED, all TLBs will be invalidated once the flush
1850 * operation is complete. This bit is only valid when the
1851 * Post-Sync Operation field is a value of 1h or 3h."
1853 if (invalidate & I915_GEM_DOMAIN_RENDER)
1854 cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
1855 MI_FLUSH_DW_OP_STOREDW;
1856 intel_ring_emit(ring, cmd);
1857 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1858 if (INTEL_INFO(ring->dev)->gen >= 8) {
1859 intel_ring_emit(ring, 0); /* upper addr */
1860 intel_ring_emit(ring, 0); /* value */
1862 intel_ring_emit(ring, 0);
1863 intel_ring_emit(ring, MI_NOOP);
1865 intel_ring_advance(ring);
1867 if (IS_GEN7(dev) && !invalidate && flush)
1868 return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN);
1873 int intel_init_render_ring_buffer(struct drm_device *dev)
1875 drm_i915_private_t *dev_priv = dev->dev_private;
1876 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1878 ring->name = "render ring";
1880 ring->mmio_base = RENDER_RING_BASE;
1882 if (INTEL_INFO(dev)->gen >= 6) {
1883 ring->add_request = gen6_add_request;
1884 ring->flush = gen7_render_ring_flush;
1885 if (INTEL_INFO(dev)->gen == 6)
1886 ring->flush = gen6_render_ring_flush;
1887 if (INTEL_INFO(dev)->gen >= 8) {
1888 ring->flush = gen8_render_ring_flush;
1889 ring->irq_get = gen8_ring_get_irq;
1890 ring->irq_put = gen8_ring_put_irq;
1892 ring->irq_get = gen6_ring_get_irq;
1893 ring->irq_put = gen6_ring_put_irq;
1895 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
1896 ring->get_seqno = gen6_ring_get_seqno;
1897 ring->set_seqno = ring_set_seqno;
1898 ring->sync_to = gen6_ring_sync;
1899 ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_INVALID;
1900 ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_RV;
1901 ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_RB;
1902 ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_RVE;
1903 ring->signal_mbox[RCS] = GEN6_NOSYNC;
1904 ring->signal_mbox[VCS] = GEN6_VRSYNC;
1905 ring->signal_mbox[BCS] = GEN6_BRSYNC;
1906 ring->signal_mbox[VECS] = GEN6_VERSYNC;
1907 } else if (IS_GEN5(dev)) {
1908 ring->add_request = pc_render_add_request;
1909 ring->flush = gen4_render_ring_flush;
1910 ring->get_seqno = pc_render_get_seqno;
1911 ring->set_seqno = pc_render_set_seqno;
1912 ring->irq_get = gen5_ring_get_irq;
1913 ring->irq_put = gen5_ring_put_irq;
1914 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
1915 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
1917 ring->add_request = i9xx_add_request;
1918 if (INTEL_INFO(dev)->gen < 4)
1919 ring->flush = gen2_render_ring_flush;
1921 ring->flush = gen4_render_ring_flush;
1922 ring->get_seqno = ring_get_seqno;
1923 ring->set_seqno = ring_set_seqno;
1925 ring->irq_get = i8xx_ring_get_irq;
1926 ring->irq_put = i8xx_ring_put_irq;
1928 ring->irq_get = i9xx_ring_get_irq;
1929 ring->irq_put = i9xx_ring_put_irq;
1931 ring->irq_enable_mask = I915_USER_INTERRUPT;
1933 ring->write_tail = ring_write_tail;
1934 if (IS_HASWELL(dev))
1935 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
1936 else if (IS_GEN8(dev))
1937 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
1938 else if (INTEL_INFO(dev)->gen >= 6)
1939 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1940 else if (INTEL_INFO(dev)->gen >= 4)
1941 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1942 else if (IS_I830(dev) || IS_845G(dev))
1943 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1945 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1946 ring->init = init_render_ring;
1947 ring->cleanup = render_ring_cleanup;
1949 /* Workaround batchbuffer to combat CS tlb bug. */
1950 if (HAS_BROKEN_CS_TLB(dev)) {
1951 struct drm_i915_gem_object *obj;
1954 obj = i915_gem_alloc_object(dev, I830_BATCH_LIMIT);
1956 DRM_ERROR("Failed to allocate batch bo\n");
1960 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
1962 drm_gem_object_unreference(&obj->base);
1963 DRM_ERROR("Failed to ping batch bo\n");
1967 ring->scratch.obj = obj;
1968 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
1971 return intel_init_ring_buffer(dev, ring);
1974 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
1976 drm_i915_private_t *dev_priv = dev->dev_private;
1977 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1980 ring->name = "render ring";
1982 ring->mmio_base = RENDER_RING_BASE;
1984 if (INTEL_INFO(dev)->gen >= 6) {
1985 /* non-kms not supported on gen6+ */
1989 /* Note: gem is not supported on gen5/ilk without kms (the corresponding
1990 * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
1991 * the special gen5 functions. */
1992 ring->add_request = i9xx_add_request;
1993 if (INTEL_INFO(dev)->gen < 4)
1994 ring->flush = gen2_render_ring_flush;
1996 ring->flush = gen4_render_ring_flush;
1997 ring->get_seqno = ring_get_seqno;
1998 ring->set_seqno = ring_set_seqno;
2000 ring->irq_get = i8xx_ring_get_irq;
2001 ring->irq_put = i8xx_ring_put_irq;
2003 ring->irq_get = i9xx_ring_get_irq;
2004 ring->irq_put = i9xx_ring_put_irq;
2006 ring->irq_enable_mask = I915_USER_INTERRUPT;
2007 ring->write_tail = ring_write_tail;
2008 if (INTEL_INFO(dev)->gen >= 4)
2009 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2010 else if (IS_I830(dev) || IS_845G(dev))
2011 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2013 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
2014 ring->init = init_render_ring;
2015 ring->cleanup = render_ring_cleanup;
2018 INIT_LIST_HEAD(&ring->active_list);
2019 INIT_LIST_HEAD(&ring->request_list);
2022 ring->effective_size = ring->size;
2023 if (IS_I830(ring->dev) || IS_845G(ring->dev))
2024 ring->effective_size -= 128;
2026 ring->virtual_start = ioremap_wc(start, size);
2027 if (ring->virtual_start == NULL) {
2028 DRM_ERROR("can not ioremap virtual address for"
2033 if (!I915_NEED_GFX_HWS(dev)) {
2034 ret = init_phys_status_page(ring);
2042 int intel_init_bsd_ring_buffer(struct drm_device *dev)
2044 drm_i915_private_t *dev_priv = dev->dev_private;
2045 struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
2047 ring->name = "bsd ring";
2050 ring->write_tail = ring_write_tail;
2051 if (INTEL_INFO(dev)->gen >= 6) {
2052 ring->mmio_base = GEN6_BSD_RING_BASE;
2053 /* gen6 bsd needs a special wa for tail updates */
2055 ring->write_tail = gen6_bsd_ring_write_tail;
2056 ring->flush = gen6_bsd_ring_flush;
2057 ring->add_request = gen6_add_request;
2058 ring->get_seqno = gen6_ring_get_seqno;
2059 ring->set_seqno = ring_set_seqno;
2060 if (INTEL_INFO(dev)->gen >= 8) {
2061 ring->irq_enable_mask =
2062 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2063 ring->irq_get = gen8_ring_get_irq;
2064 ring->irq_put = gen8_ring_put_irq;
2065 ring->dispatch_execbuffer =
2066 gen8_ring_dispatch_execbuffer;
2068 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2069 ring->irq_get = gen6_ring_get_irq;
2070 ring->irq_put = gen6_ring_put_irq;
2071 ring->dispatch_execbuffer =
2072 gen6_ring_dispatch_execbuffer;
2074 ring->sync_to = gen6_ring_sync;
2075 ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VR;
2076 ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2077 ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VB;
2078 ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_VVE;
2079 ring->signal_mbox[RCS] = GEN6_RVSYNC;
2080 ring->signal_mbox[VCS] = GEN6_NOSYNC;
2081 ring->signal_mbox[BCS] = GEN6_BVSYNC;
2082 ring->signal_mbox[VECS] = GEN6_VEVSYNC;
2084 ring->mmio_base = BSD_RING_BASE;
2085 ring->flush = bsd_ring_flush;
2086 ring->add_request = i9xx_add_request;
2087 ring->get_seqno = ring_get_seqno;
2088 ring->set_seqno = ring_set_seqno;
2090 ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2091 ring->irq_get = gen5_ring_get_irq;
2092 ring->irq_put = gen5_ring_put_irq;
2094 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2095 ring->irq_get = i9xx_ring_get_irq;
2096 ring->irq_put = i9xx_ring_put_irq;
2098 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2100 ring->init = init_ring_common;
2102 return intel_init_ring_buffer(dev, ring);
2105 int intel_init_blt_ring_buffer(struct drm_device *dev)
2107 drm_i915_private_t *dev_priv = dev->dev_private;
2108 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
2110 ring->name = "blitter ring";
2113 ring->mmio_base = BLT_RING_BASE;
2114 ring->write_tail = ring_write_tail;
2115 ring->flush = gen6_ring_flush;
2116 ring->add_request = gen6_add_request;
2117 ring->get_seqno = gen6_ring_get_seqno;
2118 ring->set_seqno = ring_set_seqno;
2119 if (INTEL_INFO(dev)->gen >= 8) {
2120 ring->irq_enable_mask =
2121 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2122 ring->irq_get = gen8_ring_get_irq;
2123 ring->irq_put = gen8_ring_put_irq;
2124 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2126 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2127 ring->irq_get = gen6_ring_get_irq;
2128 ring->irq_put = gen6_ring_put_irq;
2129 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2131 ring->sync_to = gen6_ring_sync;
2132 ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_BR;
2133 ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_BV;
2134 ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2135 ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_BVE;
2136 ring->signal_mbox[RCS] = GEN6_RBSYNC;
2137 ring->signal_mbox[VCS] = GEN6_VBSYNC;
2138 ring->signal_mbox[BCS] = GEN6_NOSYNC;
2139 ring->signal_mbox[VECS] = GEN6_VEBSYNC;
2140 ring->init = init_ring_common;
2142 return intel_init_ring_buffer(dev, ring);
2145 int intel_init_vebox_ring_buffer(struct drm_device *dev)
2147 drm_i915_private_t *dev_priv = dev->dev_private;
2148 struct intel_ring_buffer *ring = &dev_priv->ring[VECS];
2150 ring->name = "video enhancement ring";
2153 ring->mmio_base = VEBOX_RING_BASE;
2154 ring->write_tail = ring_write_tail;
2155 ring->flush = gen6_ring_flush;
2156 ring->add_request = gen6_add_request;
2157 ring->get_seqno = gen6_ring_get_seqno;
2158 ring->set_seqno = ring_set_seqno;
2160 if (INTEL_INFO(dev)->gen >= 8) {
2161 ring->irq_enable_mask =
2162 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
2163 ring->irq_get = gen8_ring_get_irq;
2164 ring->irq_put = gen8_ring_put_irq;
2165 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2167 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2168 ring->irq_get = hsw_vebox_get_irq;
2169 ring->irq_put = hsw_vebox_put_irq;
2170 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2172 ring->sync_to = gen6_ring_sync;
2173 ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VER;
2174 ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_VEV;
2175 ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VEB;
2176 ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2177 ring->signal_mbox[RCS] = GEN6_RVESYNC;
2178 ring->signal_mbox[VCS] = GEN6_VVESYNC;
2179 ring->signal_mbox[BCS] = GEN6_BVESYNC;
2180 ring->signal_mbox[VECS] = GEN6_NOSYNC;
2181 ring->init = init_ring_common;
2183 return intel_init_ring_buffer(dev, ring);
2187 intel_ring_flush_all_caches(struct intel_ring_buffer *ring)
2191 if (!ring->gpu_caches_dirty)
2194 ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
2198 trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
2200 ring->gpu_caches_dirty = false;
2205 intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring)
2207 uint32_t flush_domains;
2211 if (ring->gpu_caches_dirty)
2212 flush_domains = I915_GEM_GPU_DOMAINS;
2214 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2218 trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2220 ring->gpu_caches_dirty = false;