drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Zou Nan hai <nanhai.zou@intel.com>
  26  *    Xiang Hai hao<haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 #include <drm/drmP.h>
  31 #include "i915_drv.h"
  32 #include <drm/i915_drm.h>
  33 #include "i915_trace.h"
  34 #include "intel_drv.h"
  35
  36 static inline int ring_space(struct intel_ring_buffer *ring)
  37 {
  38         int space = (ring->head & HEAD_ADDR) - (ring->tail + I915_RING_FREE_SPACE);
  39         if (space < 0)
  40                 space += ring->size;
  41         return space;
  42 }
  43
  44 void __intel_ring_advance(struct intel_ring_buffer *ring)
  45 {
  46         struct drm_i915_private *dev_priv = ring->dev->dev_private;
  47
  48         ring->tail &= ring->size - 1;
  49         if (dev_priv->gpu_error.stop_rings & intel_ring_flag(ring))
  50                 return;
  51         ring->write_tail(ring, ring->tail);
  52 }
  53
  54 static int
  55 gen2_render_ring_flush(struct intel_ring_buffer *ring,
  56                        u32      invalidate_domains,
  57                        u32      flush_domains)
  58 {
  59         u32 cmd;
  60         int ret;
  61
  62         cmd = MI_FLUSH;
  63         if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
  64                 cmd |= MI_NO_WRITE_FLUSH;
  65
  66         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
  67                 cmd |= MI_READ_FLUSH;
  68
  69         ret = intel_ring_begin(ring, 2);
  70         if (ret)
  71                 return ret;
  72
  73         intel_ring_emit(ring, cmd);
  74         intel_ring_emit(ring, MI_NOOP);
  75         intel_ring_advance(ring);
  76
  77         return 0;
  78 }
  79
  80 static int
  81 gen4_render_ring_flush(struct intel_ring_buffer *ring,
  82                        u32      invalidate_domains,
  83                        u32      flush_domains)
  84 {
  85         struct drm_device *dev = ring->dev;
  86         u32 cmd;
  87         int ret;
  88
  89         /*
  90          * read/write caches:
  91          *
  92          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
  93          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
  94          * also flushed at 2d versus 3d pipeline switches.
  95          *
  96          * read-only caches:
  97          *
  98          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
  99          * MI_READ_FLUSH is set, and is always flushed on 965.
 100          *
 101          * I915_GEM_DOMAIN_COMMAND may not exist?
 102          *
 103          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
 104          * invalidated when MI_EXE_FLUSH is set.
 105          *
 106          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
 107          * invalidated with every MI_FLUSH.
 108          *
 109          * TLBs:
 110          *
 111          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 112          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 113          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 114          * are flushed at any MI_FLUSH.
 115          */
 116
 117         cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
 118         if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
 119                 cmd &= ~MI_NO_WRITE_FLUSH;
 120         if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 121                 cmd |= MI_EXE_FLUSH;
 122
 123         if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
 124             (IS_G4X(dev) || IS_GEN5(dev)))
 125                 cmd |= MI_INVALIDATE_ISP;
 126
 127         ret = intel_ring_begin(ring, 2);
 128         if (ret)
 129                 return ret;
 130
 131         intel_ring_emit(ring, cmd);
 132         intel_ring_emit(ring, MI_NOOP);
 133         intel_ring_advance(ring);
 134
 135         return 0;
 136 }
 137
 138 /**
 139  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 140  * implementing two workarounds on gen6.  From section 1.4.7.1
 141  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 142  *
 143  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 144  * produced by non-pipelined state commands), software needs to first
 145  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 146  * 0.
 147  *
 148  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 149  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 150  *
 151  * And the workaround for these two requires this workaround first:
 152  *
 153  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 154  * BEFORE the pipe-control with a post-sync op and no write-cache
 155  * flushes.
 156  *
 157  * And this last workaround is tricky because of the requirements on
 158  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 159  * volume 2 part 1:
 160  *
 161  *     "1 of the following must also be set:
 162  *      - Render Target Cache Flush Enable ([12] of DW1)
 163  *      - Depth Cache Flush Enable ([0] of DW1)
 164  *      - Stall at Pixel Scoreboard ([1] of DW1)
 165  *      - Depth Stall ([13] of DW1)
 166  *      - Post-Sync Operation ([13] of DW1)
 167  *      - Notify Enable ([8] of DW1)"
 168  *
 169  * The cache flushes require the workaround flush that triggered this
 170  * one, so we can't use it.  Depth stall would trigger the same.
 171  * Post-sync nonzero is what triggered this second workaround, so we
 172  * can't use that one either.  Notify enable is IRQs, which aren't
 173  * really our business.  That leaves only stall at scoreboard.
 174  */
 175 static int
 176 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)
 177 {
 178         u32 scratch_addr = ring->scratch.gtt_offset + 128;
 179         int ret;
 180
 181
 182         ret = intel_ring_begin(ring, 6);
 183         if (ret)
 184                 return ret;
 185
 186         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 187         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 188                         PIPE_CONTROL_STALL_AT_SCOREBOARD);
 189         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 190         intel_ring_emit(ring, 0); /* low dword */
 191         intel_ring_emit(ring, 0); /* high dword */
 192         intel_ring_emit(ring, MI_NOOP);
 193         intel_ring_advance(ring);
 194
 195         ret = intel_ring_begin(ring, 6);
 196         if (ret)
 197                 return ret;
 198
 199         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 200         intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
 201         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 202         intel_ring_emit(ring, 0);
 203         intel_ring_emit(ring, 0);
 204         intel_ring_emit(ring, MI_NOOP);
 205         intel_ring_advance(ring);
 206
 207         return 0;
 208 }
 209
 210 static int
 211 gen6_render_ring_flush(struct intel_ring_buffer *ring,
 212                          u32 invalidate_domains, u32 flush_domains)
 213 {
 214         u32 flags = 0;
 215         u32 scratch_addr = ring->scratch.gtt_offset + 128;
 216         int ret;
 217
 218         /* Force SNB workarounds for PIPE_CONTROL flushes */
 219         ret = intel_emit_post_sync_nonzero_flush(ring);
 220         if (ret)
 221                 return ret;
 222
 223         /* Just flush everything.  Experiments have shown that reducing the
 224          * number of bits based on the write domains has little performance
 225          * impact.
 226          */
 227         if (flush_domains) {
 228                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 229                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 230                 /*
 231                  * Ensure that any following seqno writes only happen
 232                  * when the render cache is indeed flushed.
 233                  */
 234                 flags |= PIPE_CONTROL_CS_STALL;
 235         }
 236         if (invalidate_domains) {
 237                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 238                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 239                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 240                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 241                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 242                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 243                 /*
 244                  * TLB invalidate requires a post-sync write.
 245                  */
 246                 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
 247         }
 248
 249         ret = intel_ring_begin(ring, 4);
 250         if (ret)
 251                 return ret;
 252
 253         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 254         intel_ring_emit(ring, flags);
 255         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
 256         intel_ring_emit(ring, 0);
 257         intel_ring_advance(ring);
 258
 259         return 0;
 260 }
 261
 262 static int
 263 gen7_render_ring_cs_stall_wa(struct intel_ring_buffer *ring)
 264 {
 265         int ret;
 266
 267         ret = intel_ring_begin(ring, 4);
 268         if (ret)
 269                 return ret;
 270
 271         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 272         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 273                               PIPE_CONTROL_STALL_AT_SCOREBOARD);
 274         intel_ring_emit(ring, 0);
 275         intel_ring_emit(ring, 0);
 276         intel_ring_advance(ring);
 277
 278         return 0;
 279 }
 280
 281 static int gen7_ring_fbc_flush(struct intel_ring_buffer *ring, u32 value)
 282 {
 283         int ret;
 284
 285         if (!ring->fbc_dirty)
 286                 return 0;
 287
 288         ret = intel_ring_begin(ring, 6);
 289         if (ret)
 290                 return ret;
 291         /* WaFbcNukeOn3DBlt:ivb/hsw */
 292         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 293         intel_ring_emit(ring, MSG_FBC_REND_STATE);
 294         intel_ring_emit(ring, value);
 295         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT);
 296         intel_ring_emit(ring, MSG_FBC_REND_STATE);
 297         intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
 298         intel_ring_advance(ring);
 299
 300         ring->fbc_dirty = false;
 301         return 0;
 302 }
 303
 304 static int
 305 gen7_render_ring_flush(struct intel_ring_buffer *ring,
 306                        u32 invalidate_domains, u32 flush_domains)
 307 {
 308         u32 flags = 0;
 309         u32 scratch_addr = ring->scratch.gtt_offset + 128;
 310         int ret;
 311
 312         /*
 313          * Ensure that any following seqno writes only happen when the render
 314          * cache is indeed flushed.
 315          *
 316          * Workaround: 4th PIPE_CONTROL command (except the ones with only
 317          * read-cache invalidate bits set) must have the CS_STALL bit set. We
 318          * don't try to be clever and just set it unconditionally.
 319          */
 320         flags |= PIPE_CONTROL_CS_STALL;
 321
 322         /* Just flush everything.  Experiments have shown that reducing the
 323          * number of bits based on the write domains has little performance
 324          * impact.
 325          */
 326         if (flush_domains) {
 327                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 328                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 329         }
 330         if (invalidate_domains) {
 331                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 332                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 333                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 334                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 335                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 336                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 337                 /*
 338                  * TLB invalidate requires a post-sync write.
 339                  */
 340                 flags |= PIPE_CONTROL_QW_WRITE;
 341                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 342
 343                 /* Workaround: we must issue a pipe_control with CS-stall bit
 344                  * set before a pipe_control command that has the state cache
 345                  * invalidate bit set. */
 346                 gen7_render_ring_cs_stall_wa(ring);
 347         }
 348
 349         ret = intel_ring_begin(ring, 4);
 350         if (ret)
 351                 return ret;
 352
 353         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 354         intel_ring_emit(ring, flags);
 355         intel_ring_emit(ring, scratch_addr);
 356         intel_ring_emit(ring, 0);
 357         intel_ring_advance(ring);
 358
 359         if (!invalidate_domains && flush_domains)
 360                 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
 361
 362         return 0;
 363 }
 364
 365 static int
 366 gen8_render_ring_flush(struct intel_ring_buffer *ring,
 367                        u32 invalidate_domains, u32 flush_domains)
 368 {
 369         u32 flags = 0;
 370         u32 scratch_addr = ring->scratch.gtt_offset + 128;
 371         int ret;
 372
 373         flags |= PIPE_CONTROL_CS_STALL;
 374
 375         if (flush_domains) {
 376                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 377                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 378         }
 379         if (invalidate_domains) {
 380                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 381                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 382                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 383                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 384                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 385                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 386                 flags |= PIPE_CONTROL_QW_WRITE;
 387                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 388         }
 389
 390         ret = intel_ring_begin(ring, 6);
 391         if (ret)
 392                 return ret;
 393
 394         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
 395         intel_ring_emit(ring, flags);
 396         intel_ring_emit(ring, scratch_addr);
 397         intel_ring_emit(ring, 0);
 398         intel_ring_emit(ring, 0);
 399         intel_ring_emit(ring, 0);
 400         intel_ring_advance(ring);
 401
 402         return 0;
 403
 404 }
 405
 406 static void ring_write_tail(struct intel_ring_buffer *ring,
 407                             u32 value)
 408 {
 409         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 410         I915_WRITE_TAIL(ring, value);
 411 }
 412
 413 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
 414 {
 415         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 416         u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
 417                         RING_ACTHD(ring->mmio_base) : ACTHD;
 418
 419         return I915_READ(acthd_reg);
 420 }
 421
 422 static void ring_setup_phys_status_page(struct intel_ring_buffer *ring)
 423 {
 424         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 425         u32 addr;
 426
 427         addr = dev_priv->status_page_dmah->busaddr;
 428         if (INTEL_INFO(ring->dev)->gen >= 4)
 429                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
 430         I915_WRITE(HWS_PGA, addr);
 431 }
 432
 433 static int init_ring_common(struct intel_ring_buffer *ring)
 434 {
 435         struct drm_device *dev = ring->dev;
 436         drm_i915_private_t *dev_priv = dev->dev_private;
 437         struct drm_i915_gem_object *obj = ring->obj;
 438         int ret = 0;
 439         u32 head;
 440
 441         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
 442
 443         /* Stop the ring if it's running. */
 444         I915_WRITE_CTL(ring, 0);
 445         I915_WRITE_HEAD(ring, 0);
 446         ring->write_tail(ring, 0);
 447         if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000))
 448                 DRM_ERROR("%s :timed out trying to stop ring\n", ring->name);
 449
 450         if (I915_NEED_GFX_HWS(dev))
 451                 intel_ring_setup_status_page(ring);
 452         else
 453                 ring_setup_phys_status_page(ring);
 454
 455         head = I915_READ_HEAD(ring) & HEAD_ADDR;
 456
 457         /* G45 ring initialization fails to reset head to zero */
 458         if (head != 0) {
 459                 DRM_DEBUG_KMS("%s head not reset to zero "
 460                               "ctl %08x head %08x tail %08x start %08x\n",
 461                               ring->name,
 462                               I915_READ_CTL(ring),
 463                               I915_READ_HEAD(ring),
 464                               I915_READ_TAIL(ring),
 465                               I915_READ_START(ring));
 466
 467                 I915_WRITE_HEAD(ring, 0);
 468
 469                 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
 470                         DRM_ERROR("failed to set %s head to zero "
 471                                   "ctl %08x head %08x tail %08x start %08x\n",
 472                                   ring->name,
 473                                   I915_READ_CTL(ring),
 474                                   I915_READ_HEAD(ring),
 475                                   I915_READ_TAIL(ring),
 476                                   I915_READ_START(ring));
 477                 }
 478         }
 479
 480         /* Initialize the ring. This must happen _after_ we've cleared the ring
 481          * registers with the above sequence (the readback of the HEAD registers
 482          * also enforces ordering), otherwise the hw might lose the new ring
 483          * register values. */
 484         I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
 485         I915_WRITE_CTL(ring,
 486                         ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
 487                         | RING_VALID);
 488
 489         /* If the head is still not zero, the ring is dead */
 490         if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
 491                      I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
 492                      (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
 493                 DRM_ERROR("%s initialization failed "
 494                                 "ctl %08x head %08x tail %08x start %08x\n",
 495                                 ring->name,
 496                                 I915_READ_CTL(ring),
 497                                 I915_READ_HEAD(ring),
 498                                 I915_READ_TAIL(ring),
 499                                 I915_READ_START(ring));
 500                 ret = -EIO;
 501                 goto out;
 502         }
 503
 504         if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
 505                 i915_kernel_lost_context(ring->dev);
 506         else {
 507                 ring->head = I915_READ_HEAD(ring);
 508                 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 509                 ring->space = ring_space(ring);
 510                 ring->last_retired_head = -1;
 511         }
 512
 513         memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
 514
 515 out:
 516         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
 517
 518         return ret;
 519 }
 520
 521 static int
 522 init_pipe_control(struct intel_ring_buffer *ring)
 523 {
 524         int ret;
 525
 526         if (ring->scratch.obj)
 527                 return 0;
 528
 529         ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
 530         if (ring->scratch.obj == NULL) {
 531                 DRM_ERROR("Failed to allocate seqno page\n");
 532                 ret = -ENOMEM;
 533                 goto err;
 534         }
 535
 536         ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
 537         if (ret)
 538                 goto err_unref;
 539
 540         ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
 541         if (ret)
 542                 goto err_unref;
 543
 544         ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
 545         ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
 546         if (ring->scratch.cpu_page == NULL) {
 547                 ret = -ENOMEM;
 548                 goto err_unpin;
 549         }
 550
 551         DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
 552                          ring->name, ring->scratch.gtt_offset);
 553         return 0;
 554
 555 err_unpin:
 556         i915_gem_object_ggtt_unpin(ring->scratch.obj);
 557 err_unref:
 558         drm_gem_object_unreference(&ring->scratch.obj->base);
 559 err:
 560         return ret;
 561 }
 562
 563 static int init_render_ring(struct intel_ring_buffer *ring)
 564 {
 565         struct drm_device *dev = ring->dev;
 566         struct drm_i915_private *dev_priv = dev->dev_private;
 567         int ret = init_ring_common(ring);
 568
 569         if (INTEL_INFO(dev)->gen > 3)
 570                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
 571
 572         /* We need to disable the AsyncFlip performance optimisations in order
 573          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
 574          * programmed to '1' on all products.
 575          *
 576          * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw
 577          */
 578         if (INTEL_INFO(dev)->gen >= 6)
 579                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
 580
 581         /* Required for the hardware to program scanline values for waiting */
 582         if (INTEL_INFO(dev)->gen == 6)
 583                 I915_WRITE(GFX_MODE,
 584                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_ALWAYS));
 585
 586         if (IS_GEN7(dev))
 587                 I915_WRITE(GFX_MODE_GEN7,
 588                            _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
 589                            _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
 590
 591         if (INTEL_INFO(dev)->gen >= 5) {
 592                 ret = init_pipe_control(ring);
 593                 if (ret)
 594                         return ret;
 595         }
 596
 597         if (IS_GEN6(dev)) {
 598                 /* From the Sandybridge PRM, volume 1 part 3, page 24:
 599                  * "If this bit is set, STCunit will have LRA as replacement
 600                  *  policy. [...] This bit must be reset.  LRA replacement
 601                  *  policy is not supported."
 602                  */
 603                 I915_WRITE(CACHE_MODE_0,
 604                            _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
 605
 606                 /* This is not explicitly set for GEN6, so read the register.
 607                  * see intel_ring_mi_set_context() for why we care.
 608                  * TODO: consider explicitly setting the bit for GEN5
 609                  */
 610                 ring->itlb_before_ctx_switch =
 611                         !!(I915_READ(GFX_MODE) & GFX_TLB_INVALIDATE_ALWAYS);
 612         }
 613
 614         if (INTEL_INFO(dev)->gen >= 6)
 615                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
 616
 617         if (HAS_L3_DPF(dev))
 618                 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
 619
 620         return ret;
 621 }
 622
 623 static void render_ring_cleanup(struct intel_ring_buffer *ring)
 624 {
 625         struct drm_device *dev = ring->dev;
 626
 627         if (ring->scratch.obj == NULL)
 628                 return;
 629
 630         if (INTEL_INFO(dev)->gen >= 5) {
 631                 kunmap(sg_page(ring->scratch.obj->pages->sgl));
 632                 i915_gem_object_ggtt_unpin(ring->scratch.obj);
 633         }
 634
 635         drm_gem_object_unreference(&ring->scratch.obj->base);
 636         ring->scratch.obj = NULL;
 637 }
 638
 639 static void
 640 update_mboxes(struct intel_ring_buffer *ring,
 641               u32 mmio_offset)
 642 {
 643 /* NB: In order to be able to do semaphore MBOX updates for varying number
 644  * of rings, it's easiest if we round up each individual update to a
 645  * multiple of 2 (since ring updates must always be a multiple of 2)
 646  * even though the actual update only requires 3 dwords.
 647  */
 648 #define MBOX_UPDATE_DWORDS 4
 649         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 650         intel_ring_emit(ring, mmio_offset);
 651         intel_ring_emit(ring, ring->outstanding_lazy_seqno);
 652         intel_ring_emit(ring, MI_NOOP);
 653 }
 654
 655 /**
 656  * gen6_add_request - Update the semaphore mailbox registers
 657  *
 658  * @ring - ring that is adding a request
 659  * @seqno - return seqno stuck into the ring
 660  *
 661  * Update the mailbox registers in the *other* rings with the current seqno.
 662  * This acts like a signal in the canonical semaphore.
 663  */
 664 static int
 665 gen6_add_request(struct intel_ring_buffer *ring)
 666 {
 667         struct drm_device *dev = ring->dev;
 668         struct drm_i915_private *dev_priv = dev->dev_private;
 669         struct intel_ring_buffer *useless;
 670         int i, ret, num_dwords = 4;
 671
 672         if (i915_semaphore_is_enabled(dev))
 673                 num_dwords += ((I915_NUM_RINGS-1) * MBOX_UPDATE_DWORDS);
 674 #undef MBOX_UPDATE_DWORDS
 675
 676         ret = intel_ring_begin(ring, num_dwords);
 677         if (ret)
 678                 return ret;
 679
 680         if (i915_semaphore_is_enabled(dev)) {
 681                 for_each_ring(useless, dev_priv, i) {
 682                         u32 mbox_reg = ring->signal_mbox[i];
 683                         if (mbox_reg != GEN6_NOSYNC)
 684                                 update_mboxes(ring, mbox_reg);
 685                 }
 686         }
 687
 688         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
 689         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 690         intel_ring_emit(ring, ring->outstanding_lazy_seqno);
 691         intel_ring_emit(ring, MI_USER_INTERRUPT);
 692         __intel_ring_advance(ring);
 693
 694         return 0;
 695 }
 696
 697 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
 698                                               u32 seqno)
 699 {
 700         struct drm_i915_private *dev_priv = dev->dev_private;
 701         return dev_priv->last_seqno < seqno;
 702 }
 703
 704 /**
 705  * intel_ring_sync - sync the waiter to the signaller on seqno
 706  *
 707  * @waiter - ring that is waiting
 708  * @signaller - ring which has, or will signal
 709  * @seqno - seqno which the waiter will block on
 710  */
 711 static int
 712 gen6_ring_sync(struct intel_ring_buffer *waiter,
 713                struct intel_ring_buffer *signaller,
 714                u32 seqno)
 715 {
 716         int ret;
 717         u32 dw1 = MI_SEMAPHORE_MBOX |
 718                   MI_SEMAPHORE_COMPARE |
 719                   MI_SEMAPHORE_REGISTER;
 720
 721         /* Throughout all of the GEM code, seqno passed implies our current
 722          * seqno is >= the last seqno executed. However for hardware the
 723          * comparison is strictly greater than.
 724          */
 725         seqno -= 1;
 726
 727         WARN_ON(signaller->semaphore_register[waiter->id] ==
 728                 MI_SEMAPHORE_SYNC_INVALID);
 729
 730         ret = intel_ring_begin(waiter, 4);
 731         if (ret)
 732                 return ret;
 733
 734         /* If seqno wrap happened, omit the wait with no-ops */
 735         if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
 736                 intel_ring_emit(waiter,
 737                                 dw1 |
 738                                 signaller->semaphore_register[waiter->id]);
 739                 intel_ring_emit(waiter, seqno);
 740                 intel_ring_emit(waiter, 0);
 741                 intel_ring_emit(waiter, MI_NOOP);
 742         } else {
 743                 intel_ring_emit(waiter, MI_NOOP);
 744                 intel_ring_emit(waiter, MI_NOOP);
 745                 intel_ring_emit(waiter, MI_NOOP);
 746                 intel_ring_emit(waiter, MI_NOOP);
 747         }
 748         intel_ring_advance(waiter);
 749
 750         return 0;
 751 }
 752
 753 #define PIPE_CONTROL_FLUSH(ring__, addr__)                                      \
 754 do {                                                                    \
 755         intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |                \
 756                  PIPE_CONTROL_DEPTH_STALL);                             \
 757         intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);                    \
 758         intel_ring_emit(ring__, 0);                                                     \
 759         intel_ring_emit(ring__, 0);                                                     \
 760 } while (0)
 761
 762 static int
 763 pc_render_add_request(struct intel_ring_buffer *ring)
 764 {
 765         u32 scratch_addr = ring->scratch.gtt_offset + 128;
 766         int ret;
 767
 768         /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
 769          * incoherent with writes to memory, i.e. completely fubar,
 770          * so we need to use PIPE_NOTIFY instead.
 771          *
 772          * However, we also need to workaround the qword write
 773          * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
 774          * memory before requesting an interrupt.
 775          */
 776         ret = intel_ring_begin(ring, 32);
 777         if (ret)
 778                 return ret;
 779
 780         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
 781                         PIPE_CONTROL_WRITE_FLUSH |
 782                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
 783         intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
 784         intel_ring_emit(ring, ring->outstanding_lazy_seqno);
 785         intel_ring_emit(ring, 0);
 786         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 787         scratch_addr += 128; /* write to separate cachelines */
 788         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 789         scratch_addr += 128;
 790         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 791         scratch_addr += 128;
 792         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 793         scratch_addr += 128;
 794         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 795         scratch_addr += 128;
 796         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 797
 798         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
 799                         PIPE_CONTROL_WRITE_FLUSH |
 800                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
 801                         PIPE_CONTROL_NOTIFY);
 802         intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
 803         intel_ring_emit(ring, ring->outstanding_lazy_seqno);
 804         intel_ring_emit(ring, 0);
 805         __intel_ring_advance(ring);
 806
 807         return 0;
 808 }
 809
 810 static u32
 811 gen6_ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
 812 {
 813         /* Workaround to force correct ordering between irq and seqno writes on
 814          * ivb (and maybe also on snb) by reading from a CS register (like
 815          * ACTHD) before reading the status page. */
 816         if (!lazy_coherency)
 817                 intel_ring_get_active_head(ring);
 818         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
 819 }
 820
 821 static u32
 822 ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
 823 {
 824         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
 825 }
 826
 827 static void
 828 ring_set_seqno(struct intel_ring_buffer *ring, u32 seqno)
 829 {
 830         intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
 831 }
 832
 833 static u32
 834 pc_render_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
 835 {
 836         return ring->scratch.cpu_page[0];
 837 }
 838
 839 static void
 840 pc_render_set_seqno(struct intel_ring_buffer *ring, u32 seqno)
 841 {
 842         ring->scratch.cpu_page[0] = seqno;
 843 }
 844
 845 static bool
 846 gen5_ring_get_irq(struct intel_ring_buffer *ring)
 847 {
 848         struct drm_device *dev = ring->dev;
 849         drm_i915_private_t *dev_priv = dev->dev_private;
 850         unsigned long flags;
 851
 852         if (!dev->irq_enabled)
 853                 return false;
 854
 855         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 856         if (ring->irq_refcount++ == 0)
 857                 ilk_enable_gt_irq(dev_priv, ring->irq_enable_mask);
 858         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 859
 860         return true;
 861 }
 862
 863 static void
 864 gen5_ring_put_irq(struct intel_ring_buffer *ring)
 865 {
 866         struct drm_device *dev = ring->dev;
 867         drm_i915_private_t *dev_priv = dev->dev_private;
 868         unsigned long flags;
 869
 870         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 871         if (--ring->irq_refcount == 0)
 872                 ilk_disable_gt_irq(dev_priv, ring->irq_enable_mask);
 873         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 874 }
 875
 876 static bool
 877 i9xx_ring_get_irq(struct intel_ring_buffer *ring)
 878 {
 879         struct drm_device *dev = ring->dev;
 880         drm_i915_private_t *dev_priv = dev->dev_private;
 881         unsigned long flags;
 882
 883         if (!dev->irq_enabled)
 884                 return false;
 885
 886         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 887         if (ring->irq_refcount++ == 0) {
 888                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
 889                 I915_WRITE(IMR, dev_priv->irq_mask);
 890                 POSTING_READ(IMR);
 891         }
 892         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 893
 894         return true;
 895 }
 896
 897 static void
 898 i9xx_ring_put_irq(struct intel_ring_buffer *ring)
 899 {
 900         struct drm_device *dev = ring->dev;
 901         drm_i915_private_t *dev_priv = dev->dev_private;
 902         unsigned long flags;
 903
 904         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 905         if (--ring->irq_refcount == 0) {
 906                 dev_priv->irq_mask |= ring->irq_enable_mask;
 907                 I915_WRITE(IMR, dev_priv->irq_mask);
 908                 POSTING_READ(IMR);
 909         }
 910         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 911 }
 912
 913 static bool
 914 i8xx_ring_get_irq(struct intel_ring_buffer *ring)
 915 {
 916         struct drm_device *dev = ring->dev;
 917         drm_i915_private_t *dev_priv = dev->dev_private;
 918         unsigned long flags;
 919
 920         if (!dev->irq_enabled)
 921                 return false;
 922
 923         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 924         if (ring->irq_refcount++ == 0) {
 925                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
 926                 I915_WRITE16(IMR, dev_priv->irq_mask);
 927                 POSTING_READ16(IMR);
 928         }
 929         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 930
 931         return true;
 932 }
 933
 934 static void
 935 i8xx_ring_put_irq(struct intel_ring_buffer *ring)
 936 {
 937         struct drm_device *dev = ring->dev;
 938         drm_i915_private_t *dev_priv = dev->dev_private;
 939         unsigned long flags;
 940
 941         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 942         if (--ring->irq_refcount == 0) {
 943                 dev_priv->irq_mask |= ring->irq_enable_mask;
 944                 I915_WRITE16(IMR, dev_priv->irq_mask);
 945                 POSTING_READ16(IMR);
 946         }
 947         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 948 }
 949
 950 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
 951 {
 952         struct drm_device *dev = ring->dev;
 953         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 954         u32 mmio = 0;
 955
 956         /* The ring status page addresses are no longer next to the rest of
 957          * the ring registers as of gen7.
 958          */
 959         if (IS_GEN7(dev)) {
 960                 switch (ring->id) {
 961                 case RCS:
 962                         mmio = RENDER_HWS_PGA_GEN7;
 963                         break;
 964                 case BCS:
 965                         mmio = BLT_HWS_PGA_GEN7;
 966                         break;
 967                 case VCS:
 968                         mmio = BSD_HWS_PGA_GEN7;
 969                         break;
 970                 case VECS:
 971                         mmio = VEBOX_HWS_PGA_GEN7;
 972                         break;
 973                 }
 974         } else if (IS_GEN6(ring->dev)) {
 975                 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
 976         } else {
 977                 /* XXX: gen8 returns to sanity */
 978                 mmio = RING_HWS_PGA(ring->mmio_base);
 979         }
 980
 981         I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
 982         POSTING_READ(mmio);
 983
 984         /* Flush the TLB for this page */
 985         if (INTEL_INFO(dev)->gen >= 6) {
 986                 u32 reg = RING_INSTPM(ring->mmio_base);
 987
 988                 /* ring should be idle before issuing a sync flush*/
 989                 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
 990
 991                 I915_WRITE(reg,
 992                            _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
 993                                               INSTPM_SYNC_FLUSH));
 994                 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
 995                              1000))
 996                         DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
 997                                   ring->name);
 998         }
 999 }
1000
1001 static int
1002 bsd_ring_flush(struct intel_ring_buffer *ring,
1003                u32     invalidate_domains,
1004                u32     flush_domains)
1005 {
1006         int ret;
1007
1008         ret = intel_ring_begin(ring, 2);
1009         if (ret)
1010                 return ret;
1011
1012         intel_ring_emit(ring, MI_FLUSH);
1013         intel_ring_emit(ring, MI_NOOP);
1014         intel_ring_advance(ring);
1015         return 0;
1016 }
1017
1018 static int
1019 i9xx_add_request(struct intel_ring_buffer *ring)
1020 {
1021         int ret;
1022
1023         ret = intel_ring_begin(ring, 4);
1024         if (ret)
1025                 return ret;
1026
1027         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1028         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1029         intel_ring_emit(ring, ring->outstanding_lazy_seqno);
1030         intel_ring_emit(ring, MI_USER_INTERRUPT);
1031         __intel_ring_advance(ring);
1032
1033         return 0;
1034 }
1035
1036 static bool
1037 gen6_ring_get_irq(struct intel_ring_buffer *ring)
1038 {
1039         struct drm_device *dev = ring->dev;
1040         drm_i915_private_t *dev_priv = dev->dev_private;
1041         unsigned long flags;
1042
1043         if (!dev->irq_enabled)
1044                return false;
1045
1046         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1047         if (ring->irq_refcount++ == 0) {
1048                 if (HAS_L3_DPF(dev) && ring->id == RCS)
1049                         I915_WRITE_IMR(ring,
1050                                        ~(ring->irq_enable_mask |
1051                                          GT_PARITY_ERROR(dev)));
1052                 else
1053                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1054                 ilk_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1055         }
1056         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1057
1058         return true;
1059 }
1060
1061 static void
1062 gen6_ring_put_irq(struct intel_ring_buffer *ring)
1063 {
1064         struct drm_device *dev = ring->dev;
1065         drm_i915_private_t *dev_priv = dev->dev_private;
1066         unsigned long flags;
1067
1068         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1069         if (--ring->irq_refcount == 0) {
1070                 if (HAS_L3_DPF(dev) && ring->id == RCS)
1071                         I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1072                 else
1073                         I915_WRITE_IMR(ring, ~0);
1074                 ilk_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1075         }
1076         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1077 }
1078
1079 static bool
1080 hsw_vebox_get_irq(struct intel_ring_buffer *ring)
1081 {
1082         struct drm_device *dev = ring->dev;
1083         struct drm_i915_private *dev_priv = dev->dev_private;
1084         unsigned long flags;
1085
1086         if (!dev->irq_enabled)
1087                 return false;
1088
1089         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1090         if (ring->irq_refcount++ == 0) {
1091                 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1092                 snb_enable_pm_irq(dev_priv, ring->irq_enable_mask);
1093         }
1094         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1095
1096         return true;
1097 }
1098
1099 static void
1100 hsw_vebox_put_irq(struct intel_ring_buffer *ring)
1101 {
1102         struct drm_device *dev = ring->dev;
1103         struct drm_i915_private *dev_priv = dev->dev_private;
1104         unsigned long flags;
1105
1106         if (!dev->irq_enabled)
1107                 return;
1108
1109         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1110         if (--ring->irq_refcount == 0) {
1111                 I915_WRITE_IMR(ring, ~0);
1112                 snb_disable_pm_irq(dev_priv, ring->irq_enable_mask);
1113         }
1114         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1115 }
1116
1117 static bool
1118 gen8_ring_get_irq(struct intel_ring_buffer *ring)
1119 {
1120         struct drm_device *dev = ring->dev;
1121         struct drm_i915_private *dev_priv = dev->dev_private;
1122         unsigned long flags;
1123
1124         if (!dev->irq_enabled)
1125                 return false;
1126
1127         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1128         if (ring->irq_refcount++ == 0) {
1129                 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1130                         I915_WRITE_IMR(ring,
1131                                        ~(ring->irq_enable_mask |
1132                                          GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1133                 } else {
1134                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1135                 }
1136                 POSTING_READ(RING_IMR(ring->mmio_base));
1137         }
1138         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1139
1140         return true;
1141 }
1142
1143 static void
1144 gen8_ring_put_irq(struct intel_ring_buffer *ring)
1145 {
1146         struct drm_device *dev = ring->dev;
1147         struct drm_i915_private *dev_priv = dev->dev_private;
1148         unsigned long flags;
1149
1150         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1151         if (--ring->irq_refcount == 0) {
1152                 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1153                         I915_WRITE_IMR(ring,
1154                                        ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1155                 } else {
1156                         I915_WRITE_IMR(ring, ~0);
1157                 }
1158                 POSTING_READ(RING_IMR(ring->mmio_base));
1159         }
1160         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1161 }
1162
1163 static int
1164 i965_dispatch_execbuffer(struct intel_ring_buffer *ring,
1165                          u32 offset, u32 length,
1166                          unsigned flags)
1167 {
1168         int ret;
1169
1170         ret = intel_ring_begin(ring, 2);
1171         if (ret)
1172                 return ret;
1173
1174         intel_ring_emit(ring,
1175                         MI_BATCH_BUFFER_START |
1176                         MI_BATCH_GTT |
1177                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1178         intel_ring_emit(ring, offset);
1179         intel_ring_advance(ring);
1180
1181         return 0;
1182 }
1183
1184 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1185 #define I830_BATCH_LIMIT (256*1024)
1186 static int
1187 i830_dispatch_execbuffer(struct intel_ring_buffer *ring,
1188                                 u32 offset, u32 len,
1189                                 unsigned flags)
1190 {
1191         int ret;
1192
1193         if (flags & I915_DISPATCH_PINNED) {
1194                 ret = intel_ring_begin(ring, 4);
1195                 if (ret)
1196                         return ret;
1197
1198                 intel_ring_emit(ring, MI_BATCH_BUFFER);
1199                 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1200                 intel_ring_emit(ring, offset + len - 8);
1201                 intel_ring_emit(ring, MI_NOOP);
1202                 intel_ring_advance(ring);
1203         } else {
1204                 u32 cs_offset = ring->scratch.gtt_offset;
1205
1206                 if (len > I830_BATCH_LIMIT)
1207                         return -ENOSPC;
1208
1209                 ret = intel_ring_begin(ring, 9+3);
1210                 if (ret)
1211                         return ret;
1212                 /* Blit the batch (which has now all relocs applied) to the stable batch
1213                  * scratch bo area (so that the CS never stumbles over its tlb
1214                  * invalidation bug) ... */
1215                 intel_ring_emit(ring, XY_SRC_COPY_BLT_CMD |
1216                                 XY_SRC_COPY_BLT_WRITE_ALPHA |
1217                                 XY_SRC_COPY_BLT_WRITE_RGB);
1218                 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_GXCOPY | 4096);
1219                 intel_ring_emit(ring, 0);
1220                 intel_ring_emit(ring, (DIV_ROUND_UP(len, 4096) << 16) | 1024);
1221                 intel_ring_emit(ring, cs_offset);
1222                 intel_ring_emit(ring, 0);
1223                 intel_ring_emit(ring, 4096);
1224                 intel_ring_emit(ring, offset);
1225                 intel_ring_emit(ring, MI_FLUSH);
1226
1227                 /* ... and execute it. */
1228                 intel_ring_emit(ring, MI_BATCH_BUFFER);
1229                 intel_ring_emit(ring, cs_offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1230                 intel_ring_emit(ring, cs_offset + len - 8);
1231                 intel_ring_advance(ring);
1232         }
1233
1234         return 0;
1235 }
1236
1237 static int
1238 i915_dispatch_execbuffer(struct intel_ring_buffer *ring,
1239                          u32 offset, u32 len,
1240                          unsigned flags)
1241 {
1242         int ret;
1243
1244         ret = intel_ring_begin(ring, 2);
1245         if (ret)
1246                 return ret;
1247
1248         intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1249         intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1250         intel_ring_advance(ring);
1251
1252         return 0;
1253 }
1254
1255 static void cleanup_status_page(struct intel_ring_buffer *ring)
1256 {
1257         struct drm_i915_gem_object *obj;
1258
1259         obj = ring->status_page.obj;
1260         if (obj == NULL)
1261                 return;
1262
1263         kunmap(sg_page(obj->pages->sgl));
1264         i915_gem_object_ggtt_unpin(obj);
1265         drm_gem_object_unreference(&obj->base);
1266         ring->status_page.obj = NULL;
1267 }
1268
1269 static int init_status_page(struct intel_ring_buffer *ring)
1270 {
1271         struct drm_device *dev = ring->dev;
1272         struct drm_i915_gem_object *obj;
1273         int ret;
1274
1275         obj = i915_gem_alloc_object(dev, 4096);
1276         if (obj == NULL) {
1277                 DRM_ERROR("Failed to allocate status page\n");
1278                 ret = -ENOMEM;
1279                 goto err;
1280         }
1281
1282         ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1283         if (ret)
1284                 goto err_unref;
1285
1286         ret = i915_gem_obj_ggtt_pin(obj, 4096, 0);
1287         if (ret)
1288                 goto err_unref;
1289
1290         ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
1291         ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1292         if (ring->status_page.page_addr == NULL) {
1293                 ret = -ENOMEM;
1294                 goto err_unpin;
1295         }
1296         ring->status_page.obj = obj;
1297         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1298
1299         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1300                         ring->name, ring->status_page.gfx_addr);
1301
1302         return 0;
1303
1304 err_unpin:
1305         i915_gem_object_ggtt_unpin(obj);
1306 err_unref:
1307         drm_gem_object_unreference(&obj->base);
1308 err:
1309         return ret;
1310 }
1311
1312 static int init_phys_status_page(struct intel_ring_buffer *ring)
1313 {
1314         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1315
1316         if (!dev_priv->status_page_dmah) {
1317                 dev_priv->status_page_dmah =
1318                         drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1319                 if (!dev_priv->status_page_dmah)
1320                         return -ENOMEM;
1321         }
1322
1323         ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1324         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1325
1326         return 0;
1327 }
1328
1329 static int intel_init_ring_buffer(struct drm_device *dev,
1330                                   struct intel_ring_buffer *ring)
1331 {
1332         struct drm_i915_gem_object *obj;
1333         struct drm_i915_private *dev_priv = dev->dev_private;
1334         int ret;
1335
1336         ring->dev = dev;
1337         INIT_LIST_HEAD(&ring->active_list);
1338         INIT_LIST_HEAD(&ring->request_list);
1339         ring->size = 32 * PAGE_SIZE;
1340         memset(ring->sync_seqno, 0, sizeof(ring->sync_seqno));
1341
1342         init_waitqueue_head(&ring->irq_queue);
1343
1344         if (I915_NEED_GFX_HWS(dev)) {
1345                 ret = init_status_page(ring);
1346                 if (ret)
1347                         return ret;
1348         } else {
1349                 BUG_ON(ring->id != RCS);
1350                 ret = init_phys_status_page(ring);
1351                 if (ret)
1352                         return ret;
1353         }
1354
1355         obj = NULL;
1356         if (!HAS_LLC(dev))
1357                 obj = i915_gem_object_create_stolen(dev, ring->size);
1358         if (obj == NULL)
1359                 obj = i915_gem_alloc_object(dev, ring->size);
1360         if (obj == NULL) {
1361                 DRM_ERROR("Failed to allocate ringbuffer\n");
1362                 ret = -ENOMEM;
1363                 goto err_hws;
1364         }
1365
1366         ring->obj = obj;
1367
1368         ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
1369         if (ret)
1370                 goto err_unref;
1371
1372         ret = i915_gem_object_set_to_gtt_domain(obj, true);
1373         if (ret)
1374                 goto err_unpin;
1375
1376         ring->virtual_start =
1377                 ioremap_wc(dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj),
1378                            ring->size);
1379         if (ring->virtual_start == NULL) {
1380                 DRM_ERROR("Failed to map ringbuffer.\n");
1381                 ret = -EINVAL;
1382                 goto err_unpin;
1383         }
1384
1385         ret = ring->init(ring);
1386         if (ret)
1387                 goto err_unmap;
1388
1389         /* Workaround an erratum on the i830 which causes a hang if
1390          * the TAIL pointer points to within the last 2 cachelines
1391          * of the buffer.
1392          */
1393         ring->effective_size = ring->size;
1394         if (IS_I830(ring->dev) || IS_845G(ring->dev))
1395                 ring->effective_size -= 128;
1396
1397         i915_cmd_parser_init_ring(ring);
1398
1399         return 0;
1400
1401 err_unmap:
1402         iounmap(ring->virtual_start);
1403 err_unpin:
1404         i915_gem_object_ggtt_unpin(obj);
1405 err_unref:
1406         drm_gem_object_unreference(&obj->base);
1407         ring->obj = NULL;
1408 err_hws:
1409         cleanup_status_page(ring);
1410         return ret;
1411 }
1412
1413 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
1414 {
1415         struct drm_i915_private *dev_priv;
1416         int ret;
1417
1418         if (ring->obj == NULL)
1419                 return;
1420
1421         /* Disable the ring buffer. The ring must be idle at this point */
1422         dev_priv = ring->dev->dev_private;
1423         ret = intel_ring_idle(ring);
1424         if (ret && !i915_reset_in_progress(&dev_priv->gpu_error))
1425                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1426                           ring->name, ret);
1427
1428         I915_WRITE_CTL(ring, 0);
1429
1430         iounmap(ring->virtual_start);
1431
1432         i915_gem_object_ggtt_unpin(ring->obj);
1433         drm_gem_object_unreference(&ring->obj->base);
1434         ring->obj = NULL;
1435         ring->preallocated_lazy_request = NULL;
1436         ring->outstanding_lazy_seqno = 0;
1437
1438         if (ring->cleanup)
1439                 ring->cleanup(ring);
1440
1441         cleanup_status_page(ring);
1442 }
1443
1444 static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n)
1445 {
1446         struct drm_i915_gem_request *request;
1447         u32 seqno = 0, tail;
1448         int ret;
1449
1450         if (ring->last_retired_head != -1) {
1451                 ring->head = ring->last_retired_head;
1452                 ring->last_retired_head = -1;
1453
1454                 ring->space = ring_space(ring);
1455                 if (ring->space >= n)
1456                         return 0;
1457         }
1458
1459         list_for_each_entry(request, &ring->request_list, list) {
1460                 int space;
1461
1462                 if (request->tail == -1)
1463                         continue;
1464
1465                 space = request->tail - (ring->tail + I915_RING_FREE_SPACE);
1466                 if (space < 0)
1467                         space += ring->size;
1468                 if (space >= n) {
1469                         seqno = request->seqno;
1470                         tail = request->tail;
1471                         break;
1472                 }
1473
1474                 /* Consume this request in case we need more space than
1475                  * is available and so need to prevent a race between
1476                  * updating last_retired_head and direct reads of
1477                  * I915_RING_HEAD. It also provides a nice sanity check.
1478                  */
1479                 request->tail = -1;
1480         }
1481
1482         if (seqno == 0)
1483                 return -ENOSPC;
1484
1485         ret = i915_wait_seqno(ring, seqno);
1486         if (ret)
1487                 return ret;
1488
1489         ring->head = tail;
1490         ring->space = ring_space(ring);
1491         if (WARN_ON(ring->space < n))
1492                 return -ENOSPC;
1493
1494         return 0;
1495 }
1496
1497 static int ring_wait_for_space(struct intel_ring_buffer *ring, int n)
1498 {
1499         struct drm_device *dev = ring->dev;
1500         struct drm_i915_private *dev_priv = dev->dev_private;
1501         unsigned long end;
1502         int ret;
1503
1504         ret = intel_ring_wait_request(ring, n);
1505         if (ret != -ENOSPC)
1506                 return ret;
1507
1508         /* force the tail write in case we have been skipping them */
1509         __intel_ring_advance(ring);
1510
1511         trace_i915_ring_wait_begin(ring);
1512         /* With GEM the hangcheck timer should kick us out of the loop,
1513          * leaving it early runs the risk of corrupting GEM state (due
1514          * to running on almost untested codepaths). But on resume
1515          * timers don't work yet, so prevent a complete hang in that
1516          * case by choosing an insanely large timeout. */
1517         end = jiffies + 60 * HZ;
1518
1519         do {
1520                 ring->head = I915_READ_HEAD(ring);
1521                 ring->space = ring_space(ring);
1522                 if (ring->space >= n) {
1523                         trace_i915_ring_wait_end(ring);
1524                         return 0;
1525                 }
1526
1527                 if (!drm_core_check_feature(dev, DRIVER_MODESET) &&
1528                     dev->primary->master) {
1529                         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1530                         if (master_priv->sarea_priv)
1531                                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1532                 }
1533
1534                 msleep(1);
1535
1536                 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1537                                            dev_priv->mm.interruptible);
1538                 if (ret)
1539                         return ret;
1540         } while (!time_after(jiffies, end));
1541         trace_i915_ring_wait_end(ring);
1542         return -EBUSY;
1543 }
1544
1545 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
1546 {
1547         uint32_t __iomem *virt;
1548         int rem = ring->size - ring->tail;
1549
1550         if (ring->space < rem) {
1551                 int ret = ring_wait_for_space(ring, rem);
1552                 if (ret)
1553                         return ret;
1554         }
1555
1556         virt = ring->virtual_start + ring->tail;
1557         rem /= 4;
1558         while (rem--)
1559                 iowrite32(MI_NOOP, virt++);
1560
1561         ring->tail = 0;
1562         ring->space = ring_space(ring);
1563
1564         return 0;
1565 }
1566
1567 int intel_ring_idle(struct intel_ring_buffer *ring)
1568 {
1569         u32 seqno;
1570         int ret;
1571
1572         /* We need to add any requests required to flush the objects and ring */
1573         if (ring->outstanding_lazy_seqno) {
1574                 ret = i915_add_request(ring, NULL);
1575                 if (ret)
1576                         return ret;
1577         }
1578
1579         /* Wait upon the last request to be completed */
1580         if (list_empty(&ring->request_list))
1581                 return 0;
1582
1583         seqno = list_entry(ring->request_list.prev,
1584                            struct drm_i915_gem_request,
1585                            list)->seqno;
1586
1587         return i915_wait_seqno(ring, seqno);
1588 }
1589
1590 static int
1591 intel_ring_alloc_seqno(struct intel_ring_buffer *ring)
1592 {
1593         if (ring->outstanding_lazy_seqno)
1594                 return 0;
1595
1596         if (ring->preallocated_lazy_request == NULL) {
1597                 struct drm_i915_gem_request *request;
1598
1599                 request = kmalloc(sizeof(*request), GFP_KERNEL);
1600                 if (request == NULL)
1601                         return -ENOMEM;
1602
1603                 ring->preallocated_lazy_request = request;
1604         }
1605
1606         return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_seqno);
1607 }
1608
1609 static int __intel_ring_prepare(struct intel_ring_buffer *ring,
1610                                 int bytes)
1611 {
1612         int ret;
1613
1614         if (unlikely(ring->tail + bytes > ring->effective_size)) {
1615                 ret = intel_wrap_ring_buffer(ring);
1616                 if (unlikely(ret))
1617                         return ret;
1618         }
1619
1620         if (unlikely(ring->space < bytes)) {
1621                 ret = ring_wait_for_space(ring, bytes);
1622                 if (unlikely(ret))
1623                         return ret;
1624         }
1625
1626         return 0;
1627 }
1628
1629 int intel_ring_begin(struct intel_ring_buffer *ring,
1630                      int num_dwords)
1631 {
1632         drm_i915_private_t *dev_priv = ring->dev->dev_private;
1633         int ret;
1634
1635         ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1636                                    dev_priv->mm.interruptible);
1637         if (ret)
1638                 return ret;
1639
1640         ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
1641         if (ret)
1642                 return ret;
1643
1644         /* Preallocate the olr before touching the ring */
1645         ret = intel_ring_alloc_seqno(ring);
1646         if (ret)
1647                 return ret;
1648
1649         ring->space -= num_dwords * sizeof(uint32_t);
1650         return 0;
1651 }
1652
1653 /* Align the ring tail to a cacheline boundary */
1654 int intel_ring_cacheline_align(struct intel_ring_buffer *ring)
1655 {
1656         int num_dwords = (64 - (ring->tail & 63)) / sizeof(uint32_t);
1657         int ret;
1658
1659         if (num_dwords == 0)
1660                 return 0;
1661
1662         ret = intel_ring_begin(ring, num_dwords);
1663         if (ret)
1664                 return ret;
1665
1666         while (num_dwords--)
1667                 intel_ring_emit(ring, MI_NOOP);
1668
1669         intel_ring_advance(ring);
1670
1671         return 0;
1672 }
1673
1674 void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno)
1675 {
1676         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1677
1678         BUG_ON(ring->outstanding_lazy_seqno);
1679
1680         if (INTEL_INFO(ring->dev)->gen >= 6) {
1681                 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
1682                 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
1683                 if (HAS_VEBOX(ring->dev))
1684                         I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
1685         }
1686
1687         ring->set_seqno(ring, seqno);
1688         ring->hangcheck.seqno = seqno;
1689 }
1690
1691 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1692                                      u32 value)
1693 {
1694         drm_i915_private_t *dev_priv = ring->dev->dev_private;
1695
1696        /* Every tail move must follow the sequence below */
1697
1698         /* Disable notification that the ring is IDLE. The GT
1699          * will then assume that it is busy and bring it out of rc6.
1700          */
1701         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1702                    _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1703
1704         /* Clear the context id. Here be magic! */
1705         I915_WRITE64(GEN6_BSD_RNCID, 0x0);
1706
1707         /* Wait for the ring not to be idle, i.e. for it to wake up. */
1708         if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1709                       GEN6_BSD_SLEEP_INDICATOR) == 0,
1710                      50))
1711                 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
1712
1713         /* Now that the ring is fully powered up, update the tail */
1714         I915_WRITE_TAIL(ring, value);
1715         POSTING_READ(RING_TAIL(ring->mmio_base));
1716
1717         /* Let the ring send IDLE messages to the GT again,
1718          * and so let it sleep to conserve power when idle.
1719          */
1720         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1721                    _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1722 }
1723
1724 static int gen6_bsd_ring_flush(struct intel_ring_buffer *ring,
1725                                u32 invalidate, u32 flush)
1726 {
1727         uint32_t cmd;
1728         int ret;
1729
1730         ret = intel_ring_begin(ring, 4);
1731         if (ret)
1732                 return ret;
1733
1734         cmd = MI_FLUSH_DW;
1735         if (INTEL_INFO(ring->dev)->gen >= 8)
1736                 cmd += 1;
1737         /*
1738          * Bspec vol 1c.5 - video engine command streamer:
1739          * "If ENABLED, all TLBs will be invalidated once the flush
1740          * operation is complete. This bit is only valid when the
1741          * Post-Sync Operation field is a value of 1h or 3h."
1742          */
1743         if (invalidate & I915_GEM_GPU_DOMAINS)
1744                 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
1745                         MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1746         intel_ring_emit(ring, cmd);
1747         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1748         if (INTEL_INFO(ring->dev)->gen >= 8) {
1749                 intel_ring_emit(ring, 0); /* upper addr */
1750                 intel_ring_emit(ring, 0); /* value */
1751         } else  {
1752                 intel_ring_emit(ring, 0);
1753                 intel_ring_emit(ring, MI_NOOP);
1754         }
1755         intel_ring_advance(ring);
1756         return 0;
1757 }
1758
1759 static int
1760 gen8_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1761                               u32 offset, u32 len,
1762                               unsigned flags)
1763 {
1764         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1765         bool ppgtt = dev_priv->mm.aliasing_ppgtt != NULL &&
1766                 !(flags & I915_DISPATCH_SECURE);
1767         int ret;
1768
1769         ret = intel_ring_begin(ring, 4);
1770         if (ret)
1771                 return ret;
1772
1773         /* FIXME(BDW): Address space and security selectors. */
1774         intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
1775         intel_ring_emit(ring, offset);
1776         intel_ring_emit(ring, 0);
1777         intel_ring_emit(ring, MI_NOOP);
1778         intel_ring_advance(ring);
1779
1780         return 0;
1781 }
1782
1783 static int
1784 hsw_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1785                               u32 offset, u32 len,
1786                               unsigned flags)
1787 {
1788         int ret;
1789
1790         ret = intel_ring_begin(ring, 2);
1791         if (ret)
1792                 return ret;
1793
1794         intel_ring_emit(ring,
1795                         MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW |
1796                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_HSW));
1797         /* bit0-7 is the length on GEN6+ */
1798         intel_ring_emit(ring, offset);
1799         intel_ring_advance(ring);
1800
1801         return 0;
1802 }
1803
1804 static int
1805 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1806                               u32 offset, u32 len,
1807                               unsigned flags)
1808 {
1809         int ret;
1810
1811         ret = intel_ring_begin(ring, 2);
1812         if (ret)
1813                 return ret;
1814
1815         intel_ring_emit(ring,
1816                         MI_BATCH_BUFFER_START |
1817                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1818         /* bit0-7 is the length on GEN6+ */
1819         intel_ring_emit(ring, offset);
1820         intel_ring_advance(ring);
1821
1822         return 0;
1823 }
1824
1825 /* Blitter support (SandyBridge+) */
1826
1827 static int gen6_ring_flush(struct intel_ring_buffer *ring,
1828                            u32 invalidate, u32 flush)
1829 {
1830         struct drm_device *dev = ring->dev;
1831         uint32_t cmd;
1832         int ret;
1833
1834         ret = intel_ring_begin(ring, 4);
1835         if (ret)
1836                 return ret;
1837
1838         cmd = MI_FLUSH_DW;
1839         if (INTEL_INFO(ring->dev)->gen >= 8)
1840                 cmd += 1;
1841         /*
1842          * Bspec vol 1c.3 - blitter engine command streamer:
1843          * "If ENABLED, all TLBs will be invalidated once the flush
1844          * operation is complete. This bit is only valid when the
1845          * Post-Sync Operation field is a value of 1h or 3h."
1846          */
1847         if (invalidate & I915_GEM_DOMAIN_RENDER)
1848                 cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
1849                         MI_FLUSH_DW_OP_STOREDW;
1850         intel_ring_emit(ring, cmd);
1851         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1852         if (INTEL_INFO(ring->dev)->gen >= 8) {
1853                 intel_ring_emit(ring, 0); /* upper addr */
1854                 intel_ring_emit(ring, 0); /* value */
1855         } else  {
1856                 intel_ring_emit(ring, 0);
1857                 intel_ring_emit(ring, MI_NOOP);
1858         }
1859         intel_ring_advance(ring);
1860
1861         if (IS_GEN7(dev) && !invalidate && flush)
1862                 return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN);
1863
1864         return 0;
1865 }
1866
1867 int intel_init_render_ring_buffer(struct drm_device *dev)
1868 {
1869         drm_i915_private_t *dev_priv = dev->dev_private;
1870         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1871
1872         ring->name = "render ring";
1873         ring->id = RCS;
1874         ring->mmio_base = RENDER_RING_BASE;
1875
1876         if (INTEL_INFO(dev)->gen >= 6) {
1877                 ring->add_request = gen6_add_request;
1878                 ring->flush = gen7_render_ring_flush;
1879                 if (INTEL_INFO(dev)->gen == 6)
1880                         ring->flush = gen6_render_ring_flush;
1881                 if (INTEL_INFO(dev)->gen >= 8) {
1882                         ring->flush = gen8_render_ring_flush;
1883                         ring->irq_get = gen8_ring_get_irq;
1884                         ring->irq_put = gen8_ring_put_irq;
1885                 } else {
1886                         ring->irq_get = gen6_ring_get_irq;
1887                         ring->irq_put = gen6_ring_put_irq;
1888                 }
1889                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
1890                 ring->get_seqno = gen6_ring_get_seqno;
1891                 ring->set_seqno = ring_set_seqno;
1892                 ring->sync_to = gen6_ring_sync;
1893                 ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_INVALID;
1894                 ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_RV;
1895                 ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_RB;
1896                 ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_RVE;
1897                 ring->signal_mbox[RCS] = GEN6_NOSYNC;
1898                 ring->signal_mbox[VCS] = GEN6_VRSYNC;
1899                 ring->signal_mbox[BCS] = GEN6_BRSYNC;
1900                 ring->signal_mbox[VECS] = GEN6_VERSYNC;
1901         } else if (IS_GEN5(dev)) {
1902                 ring->add_request = pc_render_add_request;
1903                 ring->flush = gen4_render_ring_flush;
1904                 ring->get_seqno = pc_render_get_seqno;
1905                 ring->set_seqno = pc_render_set_seqno;
1906                 ring->irq_get = gen5_ring_get_irq;
1907                 ring->irq_put = gen5_ring_put_irq;
1908                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
1909                                         GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
1910         } else {
1911                 ring->add_request = i9xx_add_request;
1912                 if (INTEL_INFO(dev)->gen < 4)
1913                         ring->flush = gen2_render_ring_flush;
1914                 else
1915                         ring->flush = gen4_render_ring_flush;
1916                 ring->get_seqno = ring_get_seqno;
1917                 ring->set_seqno = ring_set_seqno;
1918                 if (IS_GEN2(dev)) {
1919                         ring->irq_get = i8xx_ring_get_irq;
1920                         ring->irq_put = i8xx_ring_put_irq;
1921                 } else {
1922                         ring->irq_get = i9xx_ring_get_irq;
1923                         ring->irq_put = i9xx_ring_put_irq;
1924                 }
1925                 ring->irq_enable_mask = I915_USER_INTERRUPT;
1926         }
1927         ring->write_tail = ring_write_tail;
1928         if (IS_HASWELL(dev))
1929                 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
1930         else if (IS_GEN8(dev))
1931                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
1932         else if (INTEL_INFO(dev)->gen >= 6)
1933                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1934         else if (INTEL_INFO(dev)->gen >= 4)
1935                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1936         else if (IS_I830(dev) || IS_845G(dev))
1937                 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1938         else
1939                 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1940         ring->init = init_render_ring;
1941         ring->cleanup = render_ring_cleanup;
1942
1943         /* Workaround batchbuffer to combat CS tlb bug. */
1944         if (HAS_BROKEN_CS_TLB(dev)) {
1945                 struct drm_i915_gem_object *obj;
1946                 int ret;
1947
1948                 obj = i915_gem_alloc_object(dev, I830_BATCH_LIMIT);
1949                 if (obj == NULL) {
1950                         DRM_ERROR("Failed to allocate batch bo\n");
1951                         return -ENOMEM;
1952                 }
1953
1954                 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
1955                 if (ret != 0) {
1956                         drm_gem_object_unreference(&obj->base);
1957                         DRM_ERROR("Failed to ping batch bo\n");
1958                         return ret;
1959                 }
1960
1961                 ring->scratch.obj = obj;
1962                 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
1963         }
1964
1965         return intel_init_ring_buffer(dev, ring);
1966 }
1967
1968 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
1969 {
1970         drm_i915_private_t *dev_priv = dev->dev_private;
1971         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1972         int ret;
1973
1974         ring->name = "render ring";
1975         ring->id = RCS;
1976         ring->mmio_base = RENDER_RING_BASE;
1977
1978         if (INTEL_INFO(dev)->gen >= 6) {
1979                 /* non-kms not supported on gen6+ */
1980                 return -ENODEV;
1981         }
1982
1983         /* Note: gem is not supported on gen5/ilk without kms (the corresponding
1984          * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
1985          * the special gen5 functions. */
1986         ring->add_request = i9xx_add_request;
1987         if (INTEL_INFO(dev)->gen < 4)
1988                 ring->flush = gen2_render_ring_flush;
1989         else
1990                 ring->flush = gen4_render_ring_flush;
1991         ring->get_seqno = ring_get_seqno;
1992         ring->set_seqno = ring_set_seqno;
1993         if (IS_GEN2(dev)) {
1994                 ring->irq_get = i8xx_ring_get_irq;
1995                 ring->irq_put = i8xx_ring_put_irq;
1996         } else {
1997                 ring->irq_get = i9xx_ring_get_irq;
1998                 ring->irq_put = i9xx_ring_put_irq;
1999         }
2000         ring->irq_enable_mask = I915_USER_INTERRUPT;
2001         ring->write_tail = ring_write_tail;
2002         if (INTEL_INFO(dev)->gen >= 4)
2003                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2004         else if (IS_I830(dev) || IS_845G(dev))
2005                 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2006         else
2007                 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
2008         ring->init = init_render_ring;
2009         ring->cleanup = render_ring_cleanup;
2010
2011         ring->dev = dev;
2012         INIT_LIST_HEAD(&ring->active_list);
2013         INIT_LIST_HEAD(&ring->request_list);
2014
2015         ring->size = size;
2016         ring->effective_size = ring->size;
2017         if (IS_I830(ring->dev) || IS_845G(ring->dev))
2018                 ring->effective_size -= 128;
2019
2020         ring->virtual_start = ioremap_wc(start, size);
2021         if (ring->virtual_start == NULL) {
2022                 DRM_ERROR("can not ioremap virtual address for"
2023                           " ring buffer\n");
2024                 return -ENOMEM;
2025         }
2026
2027         if (!I915_NEED_GFX_HWS(dev)) {
2028                 ret = init_phys_status_page(ring);
2029                 if (ret)
2030                         return ret;
2031         }
2032
2033         return 0;
2034 }
2035
2036 int intel_init_bsd_ring_buffer(struct drm_device *dev)
2037 {
2038         drm_i915_private_t *dev_priv = dev->dev_private;
2039         struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
2040
2041         ring->name = "bsd ring";
2042         ring->id = VCS;
2043
2044         ring->write_tail = ring_write_tail;
2045         if (INTEL_INFO(dev)->gen >= 6) {
2046                 ring->mmio_base = GEN6_BSD_RING_BASE;
2047                 /* gen6 bsd needs a special wa for tail updates */
2048                 if (IS_GEN6(dev))
2049                         ring->write_tail = gen6_bsd_ring_write_tail;
2050                 ring->flush = gen6_bsd_ring_flush;
2051                 ring->add_request = gen6_add_request;
2052                 ring->get_seqno = gen6_ring_get_seqno;
2053                 ring->set_seqno = ring_set_seqno;
2054                 if (INTEL_INFO(dev)->gen >= 8) {
2055                         ring->irq_enable_mask =
2056                                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2057                         ring->irq_get = gen8_ring_get_irq;
2058                         ring->irq_put = gen8_ring_put_irq;
2059                         ring->dispatch_execbuffer =
2060                                 gen8_ring_dispatch_execbuffer;
2061                 } else {
2062                         ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2063                         ring->irq_get = gen6_ring_get_irq;
2064                         ring->irq_put = gen6_ring_put_irq;
2065                         ring->dispatch_execbuffer =
2066                                 gen6_ring_dispatch_execbuffer;
2067                 }
2068                 ring->sync_to = gen6_ring_sync;
2069                 ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VR;
2070                 ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2071                 ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VB;
2072                 ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_VVE;
2073                 ring->signal_mbox[RCS] = GEN6_RVSYNC;
2074                 ring->signal_mbox[VCS] = GEN6_NOSYNC;
2075                 ring->signal_mbox[BCS] = GEN6_BVSYNC;
2076                 ring->signal_mbox[VECS] = GEN6_VEVSYNC;
2077         } else {
2078                 ring->mmio_base = BSD_RING_BASE;
2079                 ring->flush = bsd_ring_flush;
2080                 ring->add_request = i9xx_add_request;
2081                 ring->get_seqno = ring_get_seqno;
2082                 ring->set_seqno = ring_set_seqno;
2083                 if (IS_GEN5(dev)) {
2084                         ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2085                         ring->irq_get = gen5_ring_get_irq;
2086                         ring->irq_put = gen5_ring_put_irq;
2087                 } else {
2088                         ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2089                         ring->irq_get = i9xx_ring_get_irq;
2090                         ring->irq_put = i9xx_ring_put_irq;
2091                 }
2092                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2093         }
2094         ring->init = init_ring_common;
2095
2096         return intel_init_ring_buffer(dev, ring);
2097 }
2098
2099 int intel_init_blt_ring_buffer(struct drm_device *dev)
2100 {
2101         drm_i915_private_t *dev_priv = dev->dev_private;
2102         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
2103
2104         ring->name = "blitter ring";
2105         ring->id = BCS;
2106
2107         ring->mmio_base = BLT_RING_BASE;
2108         ring->write_tail = ring_write_tail;
2109         ring->flush = gen6_ring_flush;
2110         ring->add_request = gen6_add_request;
2111         ring->get_seqno = gen6_ring_get_seqno;
2112         ring->set_seqno = ring_set_seqno;
2113         if (INTEL_INFO(dev)->gen >= 8) {
2114                 ring->irq_enable_mask =
2115                         GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2116                 ring->irq_get = gen8_ring_get_irq;
2117                 ring->irq_put = gen8_ring_put_irq;
2118                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2119         } else {
2120                 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2121                 ring->irq_get = gen6_ring_get_irq;
2122                 ring->irq_put = gen6_ring_put_irq;
2123                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2124         }
2125         ring->sync_to = gen6_ring_sync;
2126         ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_BR;
2127         ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_BV;
2128         ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2129         ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_BVE;
2130         ring->signal_mbox[RCS] = GEN6_RBSYNC;
2131         ring->signal_mbox[VCS] = GEN6_VBSYNC;
2132         ring->signal_mbox[BCS] = GEN6_NOSYNC;
2133         ring->signal_mbox[VECS] = GEN6_VEBSYNC;
2134         ring->init = init_ring_common;
2135
2136         return intel_init_ring_buffer(dev, ring);
2137 }
2138
2139 int intel_init_vebox_ring_buffer(struct drm_device *dev)
2140 {
2141         drm_i915_private_t *dev_priv = dev->dev_private;
2142         struct intel_ring_buffer *ring = &dev_priv->ring[VECS];
2143
2144         ring->name = "video enhancement ring";
2145         ring->id = VECS;
2146
2147         ring->mmio_base = VEBOX_RING_BASE;
2148         ring->write_tail = ring_write_tail;
2149         ring->flush = gen6_ring_flush;
2150         ring->add_request = gen6_add_request;
2151         ring->get_seqno = gen6_ring_get_seqno;
2152         ring->set_seqno = ring_set_seqno;
2153
2154         if (INTEL_INFO(dev)->gen >= 8) {
2155                 ring->irq_enable_mask =
2156                         GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
2157                 ring->irq_get = gen8_ring_get_irq;
2158                 ring->irq_put = gen8_ring_put_irq;
2159                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2160         } else {
2161                 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2162                 ring->irq_get = hsw_vebox_get_irq;
2163                 ring->irq_put = hsw_vebox_put_irq;
2164                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2165         }
2166         ring->sync_to = gen6_ring_sync;
2167         ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VER;
2168         ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_VEV;
2169         ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VEB;
2170         ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2171         ring->signal_mbox[RCS] = GEN6_RVESYNC;
2172         ring->signal_mbox[VCS] = GEN6_VVESYNC;
2173         ring->signal_mbox[BCS] = GEN6_BVESYNC;
2174         ring->signal_mbox[VECS] = GEN6_NOSYNC;
2175         ring->init = init_ring_common;
2176
2177         return intel_init_ring_buffer(dev, ring);
2178 }
2179
2180 int
2181 intel_ring_flush_all_caches(struct intel_ring_buffer *ring)
2182 {
2183         int ret;
2184
2185         if (!ring->gpu_caches_dirty)
2186                 return 0;
2187
2188         ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
2189         if (ret)
2190                 return ret;
2191
2192         trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
2193
2194         ring->gpu_caches_dirty = false;
2195         return 0;
2196 }
2197
2198 int
2199 intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring)
2200 {
2201         uint32_t flush_domains;
2202         int ret;
2203
2204         flush_domains = 0;
2205         if (ring->gpu_caches_dirty)
2206                 flush_domains = I915_GEM_GPU_DOMAINS;
2207
2208         ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2209         if (ret)
2210                 return ret;
2211
2212         trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2213
2214         ring->gpu_caches_dirty = false;
2215         return 0;
2216 }