2 * Copyright © 2008-2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
34 #include "i915_trace.h"
35 #include "intel_drv.h"
37 static inline int ring_space(struct intel_ring_buffer *ring)
39 int space = (ring->head & HEAD_ADDR) - (ring->tail + 8);
45 static u32 i915_gem_get_seqno(struct drm_device *dev)
47 drm_i915_private_t *dev_priv = dev->dev_private;
50 seqno = dev_priv->next_seqno;
52 /* reserve 0 for non-seqno */
53 if (++dev_priv->next_seqno == 0)
54 dev_priv->next_seqno = 1;
60 render_ring_flush(struct intel_ring_buffer *ring,
61 u32 invalidate_domains,
64 struct drm_device *dev = ring->dev;
68 if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) {
72 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
73 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
74 * also flushed at 2d versus 3d pipeline switches.
78 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
79 * MI_READ_FLUSH is set, and is always flushed on 965.
81 * I915_GEM_DOMAIN_COMMAND may not exist?
83 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
84 * invalidated when MI_EXE_FLUSH is set.
86 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
87 * invalidated with every MI_FLUSH.
91 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
92 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
93 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
94 * are flushed at any MI_FLUSH.
97 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
98 if ((invalidate_domains|flush_domains) &
99 I915_GEM_DOMAIN_RENDER)
100 cmd &= ~MI_NO_WRITE_FLUSH;
101 if (INTEL_INFO(dev)->gen < 4) {
103 * On the 965, the sampler cache always gets flushed
104 * and this bit is reserved.
106 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
107 cmd |= MI_READ_FLUSH;
109 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
112 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
113 (IS_G4X(dev) || IS_GEN5(dev)))
114 cmd |= MI_INVALIDATE_ISP;
116 ret = intel_ring_begin(ring, 2);
120 intel_ring_emit(ring, cmd);
121 intel_ring_emit(ring, MI_NOOP);
122 intel_ring_advance(ring);
128 static void ring_write_tail(struct intel_ring_buffer *ring,
131 drm_i915_private_t *dev_priv = ring->dev->dev_private;
132 I915_WRITE_TAIL(ring, value);
135 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
137 drm_i915_private_t *dev_priv = ring->dev->dev_private;
138 u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
139 RING_ACTHD(ring->mmio_base) : ACTHD;
141 return I915_READ(acthd_reg);
144 static int init_ring_common(struct intel_ring_buffer *ring)
146 drm_i915_private_t *dev_priv = ring->dev->dev_private;
147 struct drm_i915_gem_object *obj = ring->obj;
150 /* Stop the ring if it's running. */
151 I915_WRITE_CTL(ring, 0);
152 I915_WRITE_HEAD(ring, 0);
153 ring->write_tail(ring, 0);
155 /* Initialize the ring. */
156 I915_WRITE_START(ring, obj->gtt_offset);
157 head = I915_READ_HEAD(ring) & HEAD_ADDR;
159 /* G45 ring initialization fails to reset head to zero */
161 DRM_DEBUG_KMS("%s head not reset to zero "
162 "ctl %08x head %08x tail %08x start %08x\n",
165 I915_READ_HEAD(ring),
166 I915_READ_TAIL(ring),
167 I915_READ_START(ring));
169 I915_WRITE_HEAD(ring, 0);
171 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
172 DRM_ERROR("failed to set %s head to zero "
173 "ctl %08x head %08x tail %08x start %08x\n",
176 I915_READ_HEAD(ring),
177 I915_READ_TAIL(ring),
178 I915_READ_START(ring));
183 ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
184 | RING_REPORT_64K | RING_VALID);
186 /* If the head is still not zero, the ring is dead */
187 if ((I915_READ_CTL(ring) & RING_VALID) == 0 ||
188 I915_READ_START(ring) != obj->gtt_offset ||
189 (I915_READ_HEAD(ring) & HEAD_ADDR) != 0) {
190 DRM_ERROR("%s initialization failed "
191 "ctl %08x head %08x tail %08x start %08x\n",
194 I915_READ_HEAD(ring),
195 I915_READ_TAIL(ring),
196 I915_READ_START(ring));
200 if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
201 i915_kernel_lost_context(ring->dev);
203 ring->head = I915_READ_HEAD(ring);
204 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
205 ring->space = ring_space(ring);
212 * 965+ support PIPE_CONTROL commands, which provide finer grained control
213 * over cache flushing.
215 struct pipe_control {
216 struct drm_i915_gem_object *obj;
217 volatile u32 *cpu_page;
222 init_pipe_control(struct intel_ring_buffer *ring)
224 struct pipe_control *pc;
225 struct drm_i915_gem_object *obj;
231 pc = kmalloc(sizeof(*pc), GFP_KERNEL);
235 obj = i915_gem_alloc_object(ring->dev, 4096);
237 DRM_ERROR("Failed to allocate seqno page\n");
241 obj->agp_type = AGP_USER_CACHED_MEMORY;
243 ret = i915_gem_object_pin(obj, 4096, true);
247 pc->gtt_offset = obj->gtt_offset;
248 pc->cpu_page = kmap(obj->pages[0]);
249 if (pc->cpu_page == NULL)
257 i915_gem_object_unpin(obj);
259 drm_gem_object_unreference(&obj->base);
266 cleanup_pipe_control(struct intel_ring_buffer *ring)
268 struct pipe_control *pc = ring->private;
269 struct drm_i915_gem_object *obj;
275 kunmap(obj->pages[0]);
276 i915_gem_object_unpin(obj);
277 drm_gem_object_unreference(&obj->base);
280 ring->private = NULL;
283 static int init_render_ring(struct intel_ring_buffer *ring)
285 struct drm_device *dev = ring->dev;
286 struct drm_i915_private *dev_priv = dev->dev_private;
287 int ret = init_ring_common(ring);
289 if (INTEL_INFO(dev)->gen > 3) {
290 int mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH;
292 mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE;
293 I915_WRITE(MI_MODE, mode);
296 if (INTEL_INFO(dev)->gen >= 6) {
297 } else if (IS_GEN5(dev)) {
298 ret = init_pipe_control(ring);
306 static void render_ring_cleanup(struct intel_ring_buffer *ring)
311 cleanup_pipe_control(ring);
315 update_semaphore(struct intel_ring_buffer *ring, int i, u32 seqno)
317 struct drm_device *dev = ring->dev;
318 struct drm_i915_private *dev_priv = dev->dev_private;
322 * cs -> 1 = vcs, 0 = bcs
323 * vcs -> 1 = bcs, 0 = cs,
324 * bcs -> 1 = cs, 0 = vcs.
326 id = ring - dev_priv->ring;
330 intel_ring_emit(ring,
332 MI_SEMAPHORE_REGISTER |
333 MI_SEMAPHORE_UPDATE);
334 intel_ring_emit(ring, seqno);
335 intel_ring_emit(ring,
336 RING_SYNC_0(dev_priv->ring[id].mmio_base) + 4*i);
340 gen6_add_request(struct intel_ring_buffer *ring,
346 ret = intel_ring_begin(ring, 10);
350 seqno = i915_gem_get_seqno(ring->dev);
351 update_semaphore(ring, 0, seqno);
352 update_semaphore(ring, 1, seqno);
354 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
355 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
356 intel_ring_emit(ring, seqno);
357 intel_ring_emit(ring, MI_USER_INTERRUPT);
358 intel_ring_advance(ring);
365 intel_ring_sync(struct intel_ring_buffer *ring,
366 struct intel_ring_buffer *to,
371 ret = intel_ring_begin(ring, 4);
375 intel_ring_emit(ring,
377 MI_SEMAPHORE_REGISTER |
378 intel_ring_sync_index(ring, to) << 17 |
379 MI_SEMAPHORE_COMPARE);
380 intel_ring_emit(ring, seqno);
381 intel_ring_emit(ring, 0);
382 intel_ring_emit(ring, MI_NOOP);
383 intel_ring_advance(ring);
388 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
390 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE | \
391 PIPE_CONTROL_DEPTH_STALL | 2); \
392 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
393 intel_ring_emit(ring__, 0); \
394 intel_ring_emit(ring__, 0); \
398 pc_render_add_request(struct intel_ring_buffer *ring,
401 struct drm_device *dev = ring->dev;
402 u32 seqno = i915_gem_get_seqno(dev);
403 struct pipe_control *pc = ring->private;
404 u32 scratch_addr = pc->gtt_offset + 128;
407 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
408 * incoherent with writes to memory, i.e. completely fubar,
409 * so we need to use PIPE_NOTIFY instead.
411 * However, we also need to workaround the qword write
412 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
413 * memory before requesting an interrupt.
415 ret = intel_ring_begin(ring, 32);
419 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
420 PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH);
421 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
422 intel_ring_emit(ring, seqno);
423 intel_ring_emit(ring, 0);
424 PIPE_CONTROL_FLUSH(ring, scratch_addr);
425 scratch_addr += 128; /* write to separate cachelines */
426 PIPE_CONTROL_FLUSH(ring, scratch_addr);
428 PIPE_CONTROL_FLUSH(ring, scratch_addr);
430 PIPE_CONTROL_FLUSH(ring, scratch_addr);
432 PIPE_CONTROL_FLUSH(ring, scratch_addr);
434 PIPE_CONTROL_FLUSH(ring, scratch_addr);
435 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
436 PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH |
437 PIPE_CONTROL_NOTIFY);
438 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
439 intel_ring_emit(ring, seqno);
440 intel_ring_emit(ring, 0);
441 intel_ring_advance(ring);
448 render_ring_add_request(struct intel_ring_buffer *ring,
451 struct drm_device *dev = ring->dev;
452 u32 seqno = i915_gem_get_seqno(dev);
455 ret = intel_ring_begin(ring, 4);
459 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
460 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
461 intel_ring_emit(ring, seqno);
462 intel_ring_emit(ring, MI_USER_INTERRUPT);
463 intel_ring_advance(ring);
470 ring_get_seqno(struct intel_ring_buffer *ring)
472 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
476 pc_render_get_seqno(struct intel_ring_buffer *ring)
478 struct pipe_control *pc = ring->private;
479 return pc->cpu_page[0];
483 ironlake_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
485 dev_priv->gt_irq_mask &= ~mask;
486 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
491 ironlake_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
493 dev_priv->gt_irq_mask |= mask;
494 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
499 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
501 dev_priv->irq_mask &= ~mask;
502 I915_WRITE(IMR, dev_priv->irq_mask);
507 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
509 dev_priv->irq_mask |= mask;
510 I915_WRITE(IMR, dev_priv->irq_mask);
515 render_ring_get_irq(struct intel_ring_buffer *ring)
517 struct drm_device *dev = ring->dev;
518 drm_i915_private_t *dev_priv = dev->dev_private;
520 if (!dev->irq_enabled)
523 spin_lock(&ring->irq_lock);
524 if (ring->irq_refcount++ == 0) {
525 if (HAS_PCH_SPLIT(dev))
526 ironlake_enable_irq(dev_priv,
527 GT_PIPE_NOTIFY | GT_USER_INTERRUPT);
529 i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
531 spin_unlock(&ring->irq_lock);
537 render_ring_put_irq(struct intel_ring_buffer *ring)
539 struct drm_device *dev = ring->dev;
540 drm_i915_private_t *dev_priv = dev->dev_private;
542 spin_lock(&ring->irq_lock);
543 if (--ring->irq_refcount == 0) {
544 if (HAS_PCH_SPLIT(dev))
545 ironlake_disable_irq(dev_priv,
549 i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
551 spin_unlock(&ring->irq_lock);
554 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
556 drm_i915_private_t *dev_priv = ring->dev->dev_private;
557 u32 mmio = IS_GEN6(ring->dev) ?
558 RING_HWS_PGA_GEN6(ring->mmio_base) :
559 RING_HWS_PGA(ring->mmio_base);
560 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
565 bsd_ring_flush(struct intel_ring_buffer *ring,
566 u32 invalidate_domains,
571 if ((flush_domains & I915_GEM_DOMAIN_RENDER) == 0)
574 ret = intel_ring_begin(ring, 2);
578 intel_ring_emit(ring, MI_FLUSH);
579 intel_ring_emit(ring, MI_NOOP);
580 intel_ring_advance(ring);
585 ring_add_request(struct intel_ring_buffer *ring,
591 ret = intel_ring_begin(ring, 4);
595 seqno = i915_gem_get_seqno(ring->dev);
597 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
598 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
599 intel_ring_emit(ring, seqno);
600 intel_ring_emit(ring, MI_USER_INTERRUPT);
601 intel_ring_advance(ring);
608 ring_get_irq(struct intel_ring_buffer *ring, u32 flag)
610 struct drm_device *dev = ring->dev;
611 drm_i915_private_t *dev_priv = dev->dev_private;
613 if (!dev->irq_enabled)
616 spin_lock(&ring->irq_lock);
617 if (ring->irq_refcount++ == 0)
618 ironlake_enable_irq(dev_priv, flag);
619 spin_unlock(&ring->irq_lock);
625 ring_put_irq(struct intel_ring_buffer *ring, u32 flag)
627 struct drm_device *dev = ring->dev;
628 drm_i915_private_t *dev_priv = dev->dev_private;
630 spin_lock(&ring->irq_lock);
631 if (--ring->irq_refcount == 0)
632 ironlake_disable_irq(dev_priv, flag);
633 spin_unlock(&ring->irq_lock);
637 gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
639 struct drm_device *dev = ring->dev;
640 drm_i915_private_t *dev_priv = dev->dev_private;
642 if (!dev->irq_enabled)
645 spin_lock(&ring->irq_lock);
646 if (ring->irq_refcount++ == 0) {
647 ring->irq_mask &= ~rflag;
648 I915_WRITE_IMR(ring, ring->irq_mask);
649 ironlake_enable_irq(dev_priv, gflag);
651 spin_unlock(&ring->irq_lock);
657 gen6_ring_put_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
659 struct drm_device *dev = ring->dev;
660 drm_i915_private_t *dev_priv = dev->dev_private;
662 spin_lock(&ring->irq_lock);
663 if (--ring->irq_refcount == 0) {
664 ring->irq_mask |= rflag;
665 I915_WRITE_IMR(ring, ring->irq_mask);
666 ironlake_disable_irq(dev_priv, gflag);
668 spin_unlock(&ring->irq_lock);
672 bsd_ring_get_irq(struct intel_ring_buffer *ring)
674 return ring_get_irq(ring, GT_BSD_USER_INTERRUPT);
677 bsd_ring_put_irq(struct intel_ring_buffer *ring)
679 ring_put_irq(ring, GT_BSD_USER_INTERRUPT);
683 ring_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length)
687 ret = intel_ring_begin(ring, 2);
691 intel_ring_emit(ring,
692 MI_BATCH_BUFFER_START | (2 << 6) |
693 MI_BATCH_NON_SECURE_I965);
694 intel_ring_emit(ring, offset);
695 intel_ring_advance(ring);
701 render_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
704 struct drm_device *dev = ring->dev;
707 if (IS_I830(dev) || IS_845G(dev)) {
708 ret = intel_ring_begin(ring, 4);
712 intel_ring_emit(ring, MI_BATCH_BUFFER);
713 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
714 intel_ring_emit(ring, offset + len - 8);
715 intel_ring_emit(ring, 0);
717 ret = intel_ring_begin(ring, 2);
721 if (INTEL_INFO(dev)->gen >= 4) {
722 intel_ring_emit(ring,
723 MI_BATCH_BUFFER_START | (2 << 6) |
724 MI_BATCH_NON_SECURE_I965);
725 intel_ring_emit(ring, offset);
727 intel_ring_emit(ring,
728 MI_BATCH_BUFFER_START | (2 << 6));
729 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
732 intel_ring_advance(ring);
737 static void cleanup_status_page(struct intel_ring_buffer *ring)
739 drm_i915_private_t *dev_priv = ring->dev->dev_private;
740 struct drm_i915_gem_object *obj;
742 obj = ring->status_page.obj;
746 kunmap(obj->pages[0]);
747 i915_gem_object_unpin(obj);
748 drm_gem_object_unreference(&obj->base);
749 ring->status_page.obj = NULL;
751 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
754 static int init_status_page(struct intel_ring_buffer *ring)
756 struct drm_device *dev = ring->dev;
757 drm_i915_private_t *dev_priv = dev->dev_private;
758 struct drm_i915_gem_object *obj;
761 obj = i915_gem_alloc_object(dev, 4096);
763 DRM_ERROR("Failed to allocate status page\n");
767 obj->agp_type = AGP_USER_CACHED_MEMORY;
769 ret = i915_gem_object_pin(obj, 4096, true);
774 ring->status_page.gfx_addr = obj->gtt_offset;
775 ring->status_page.page_addr = kmap(obj->pages[0]);
776 if (ring->status_page.page_addr == NULL) {
777 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
780 ring->status_page.obj = obj;
781 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
783 intel_ring_setup_status_page(ring);
784 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
785 ring->name, ring->status_page.gfx_addr);
790 i915_gem_object_unpin(obj);
792 drm_gem_object_unreference(&obj->base);
797 int intel_init_ring_buffer(struct drm_device *dev,
798 struct intel_ring_buffer *ring)
800 struct drm_i915_gem_object *obj;
804 INIT_LIST_HEAD(&ring->active_list);
805 INIT_LIST_HEAD(&ring->request_list);
806 INIT_LIST_HEAD(&ring->gpu_write_list);
808 spin_lock_init(&ring->irq_lock);
811 if (I915_NEED_GFX_HWS(dev)) {
812 ret = init_status_page(ring);
817 obj = i915_gem_alloc_object(dev, ring->size);
819 DRM_ERROR("Failed to allocate ringbuffer\n");
826 ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
830 ring->map.size = ring->size;
831 ring->map.offset = dev->agp->base + obj->gtt_offset;
836 drm_core_ioremap_wc(&ring->map, dev);
837 if (ring->map.handle == NULL) {
838 DRM_ERROR("Failed to map ringbuffer.\n");
843 ring->virtual_start = ring->map.handle;
844 ret = ring->init(ring);
848 /* Workaround an erratum on the i830 which causes a hang if
849 * the TAIL pointer points to within the last 2 cachelines
852 ring->effective_size = ring->size;
853 if (IS_I830(ring->dev))
854 ring->effective_size -= 128;
859 drm_core_ioremapfree(&ring->map, dev);
861 i915_gem_object_unpin(obj);
863 drm_gem_object_unreference(&obj->base);
866 cleanup_status_page(ring);
870 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
872 struct drm_i915_private *dev_priv;
875 if (ring->obj == NULL)
878 /* Disable the ring buffer. The ring must be idle at this point */
879 dev_priv = ring->dev->dev_private;
880 ret = intel_wait_ring_buffer(ring, ring->size - 8);
882 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
885 I915_WRITE_CTL(ring, 0);
887 drm_core_ioremapfree(&ring->map, ring->dev);
889 i915_gem_object_unpin(ring->obj);
890 drm_gem_object_unreference(&ring->obj->base);
896 cleanup_status_page(ring);
899 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
902 int rem = ring->size - ring->tail;
904 if (ring->space < rem) {
905 int ret = intel_wait_ring_buffer(ring, rem);
910 virt = (unsigned int *)(ring->virtual_start + ring->tail);
918 ring->space = ring_space(ring);
923 int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n)
925 struct drm_device *dev = ring->dev;
926 struct drm_i915_private *dev_priv = dev->dev_private;
930 /* If the reported head position has wrapped or hasn't advanced,
931 * fallback to the slow and accurate path.
933 head = intel_read_status_page(ring, 4);
934 if (head > ring->head) {
936 ring->space = ring_space(ring);
937 if (ring->space >= n)
941 trace_i915_ring_wait_begin(ring);
942 end = jiffies + 3 * HZ;
944 ring->head = I915_READ_HEAD(ring);
945 ring->space = ring_space(ring);
946 if (ring->space >= n) {
947 trace_i915_ring_wait_end(ring);
951 if (dev->primary->master) {
952 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
953 if (master_priv->sarea_priv)
954 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
958 if (atomic_read(&dev_priv->mm.wedged))
960 } while (!time_after(jiffies, end));
961 trace_i915_ring_wait_end(ring);
965 int intel_ring_begin(struct intel_ring_buffer *ring,
968 struct drm_i915_private *dev_priv = ring->dev->dev_private;
969 int n = 4*num_dwords;
972 if (unlikely(atomic_read(&dev_priv->mm.wedged)))
975 if (unlikely(ring->tail + n > ring->effective_size)) {
976 ret = intel_wrap_ring_buffer(ring);
981 if (unlikely(ring->space < n)) {
982 ret = intel_wait_ring_buffer(ring, n);
991 void intel_ring_advance(struct intel_ring_buffer *ring)
993 ring->tail &= ring->size - 1;
994 ring->write_tail(ring, ring->tail);
997 static const struct intel_ring_buffer render_ring = {
998 .name = "render ring",
1000 .mmio_base = RENDER_RING_BASE,
1001 .size = 32 * PAGE_SIZE,
1002 .init = init_render_ring,
1003 .write_tail = ring_write_tail,
1004 .flush = render_ring_flush,
1005 .add_request = render_ring_add_request,
1006 .get_seqno = ring_get_seqno,
1007 .irq_get = render_ring_get_irq,
1008 .irq_put = render_ring_put_irq,
1009 .dispatch_execbuffer = render_ring_dispatch_execbuffer,
1010 .cleanup = render_ring_cleanup,
1013 /* ring buffer for bit-stream decoder */
1015 static const struct intel_ring_buffer bsd_ring = {
1018 .mmio_base = BSD_RING_BASE,
1019 .size = 32 * PAGE_SIZE,
1020 .init = init_ring_common,
1021 .write_tail = ring_write_tail,
1022 .flush = bsd_ring_flush,
1023 .add_request = ring_add_request,
1024 .get_seqno = ring_get_seqno,
1025 .irq_get = bsd_ring_get_irq,
1026 .irq_put = bsd_ring_put_irq,
1027 .dispatch_execbuffer = ring_dispatch_execbuffer,
1031 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1034 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1036 /* Every tail move must follow the sequence below */
1037 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1038 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
1039 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE);
1040 I915_WRITE(GEN6_BSD_RNCID, 0x0);
1042 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1043 GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR) == 0,
1045 DRM_ERROR("timed out waiting for IDLE Indicator\n");
1047 I915_WRITE_TAIL(ring, value);
1048 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1049 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
1050 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE);
1053 static int gen6_ring_flush(struct intel_ring_buffer *ring,
1054 u32 invalidate_domains,
1059 if ((flush_domains & I915_GEM_DOMAIN_RENDER) == 0)
1062 ret = intel_ring_begin(ring, 4);
1066 intel_ring_emit(ring, MI_FLUSH_DW);
1067 intel_ring_emit(ring, 0);
1068 intel_ring_emit(ring, 0);
1069 intel_ring_emit(ring, 0);
1070 intel_ring_advance(ring);
1075 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1076 u32 offset, u32 len)
1080 ret = intel_ring_begin(ring, 2);
1084 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965);
1085 /* bit0-7 is the length on GEN6+ */
1086 intel_ring_emit(ring, offset);
1087 intel_ring_advance(ring);
1093 gen6_render_ring_get_irq(struct intel_ring_buffer *ring)
1095 return gen6_ring_get_irq(ring,
1097 GEN6_RENDER_USER_INTERRUPT);
1101 gen6_render_ring_put_irq(struct intel_ring_buffer *ring)
1103 return gen6_ring_put_irq(ring,
1105 GEN6_RENDER_USER_INTERRUPT);
1109 gen6_bsd_ring_get_irq(struct intel_ring_buffer *ring)
1111 return gen6_ring_get_irq(ring,
1112 GT_GEN6_BSD_USER_INTERRUPT,
1113 GEN6_BSD_USER_INTERRUPT);
1117 gen6_bsd_ring_put_irq(struct intel_ring_buffer *ring)
1119 return gen6_ring_put_irq(ring,
1120 GT_GEN6_BSD_USER_INTERRUPT,
1121 GEN6_BSD_USER_INTERRUPT);
1124 /* ring buffer for Video Codec for Gen6+ */
1125 static const struct intel_ring_buffer gen6_bsd_ring = {
1126 .name = "gen6 bsd ring",
1128 .mmio_base = GEN6_BSD_RING_BASE,
1129 .size = 32 * PAGE_SIZE,
1130 .init = init_ring_common,
1131 .write_tail = gen6_bsd_ring_write_tail,
1132 .flush = gen6_ring_flush,
1133 .add_request = gen6_add_request,
1134 .get_seqno = ring_get_seqno,
1135 .irq_get = gen6_bsd_ring_get_irq,
1136 .irq_put = gen6_bsd_ring_put_irq,
1137 .dispatch_execbuffer = gen6_ring_dispatch_execbuffer,
1140 /* Blitter support (SandyBridge+) */
1143 blt_ring_get_irq(struct intel_ring_buffer *ring)
1145 return gen6_ring_get_irq(ring,
1146 GT_BLT_USER_INTERRUPT,
1147 GEN6_BLITTER_USER_INTERRUPT);
1151 blt_ring_put_irq(struct intel_ring_buffer *ring)
1153 gen6_ring_put_irq(ring,
1154 GT_BLT_USER_INTERRUPT,
1155 GEN6_BLITTER_USER_INTERRUPT);
1159 /* Workaround for some stepping of SNB,
1160 * each time when BLT engine ring tail moved,
1161 * the first command in the ring to be parsed
1162 * should be MI_BATCH_BUFFER_START
1164 #define NEED_BLT_WORKAROUND(dev) \
1165 (IS_GEN6(dev) && (dev->pdev->revision < 8))
1167 static inline struct drm_i915_gem_object *
1168 to_blt_workaround(struct intel_ring_buffer *ring)
1170 return ring->private;
1173 static int blt_ring_init(struct intel_ring_buffer *ring)
1175 if (NEED_BLT_WORKAROUND(ring->dev)) {
1176 struct drm_i915_gem_object *obj;
1180 obj = i915_gem_alloc_object(ring->dev, 4096);
1184 ret = i915_gem_object_pin(obj, 4096, true);
1186 drm_gem_object_unreference(&obj->base);
1190 ptr = kmap(obj->pages[0]);
1191 *ptr++ = MI_BATCH_BUFFER_END;
1193 kunmap(obj->pages[0]);
1195 ret = i915_gem_object_set_to_gtt_domain(obj, false);
1197 i915_gem_object_unpin(obj);
1198 drm_gem_object_unreference(&obj->base);
1202 ring->private = obj;
1205 return init_ring_common(ring);
1208 static int blt_ring_begin(struct intel_ring_buffer *ring,
1211 if (ring->private) {
1212 int ret = intel_ring_begin(ring, num_dwords+2);
1216 intel_ring_emit(ring, MI_BATCH_BUFFER_START);
1217 intel_ring_emit(ring, to_blt_workaround(ring)->gtt_offset);
1221 return intel_ring_begin(ring, 4);
1224 static int blt_ring_flush(struct intel_ring_buffer *ring,
1225 u32 invalidate_domains,
1230 if ((flush_domains & I915_GEM_DOMAIN_RENDER) == 0)
1233 ret = blt_ring_begin(ring, 4);
1237 intel_ring_emit(ring, MI_FLUSH_DW);
1238 intel_ring_emit(ring, 0);
1239 intel_ring_emit(ring, 0);
1240 intel_ring_emit(ring, 0);
1241 intel_ring_advance(ring);
1245 static void blt_ring_cleanup(struct intel_ring_buffer *ring)
1250 i915_gem_object_unpin(ring->private);
1251 drm_gem_object_unreference(ring->private);
1252 ring->private = NULL;
1255 static const struct intel_ring_buffer gen6_blt_ring = {
1258 .mmio_base = BLT_RING_BASE,
1259 .size = 32 * PAGE_SIZE,
1260 .init = blt_ring_init,
1261 .write_tail = ring_write_tail,
1262 .flush = blt_ring_flush,
1263 .add_request = gen6_add_request,
1264 .get_seqno = ring_get_seqno,
1265 .irq_get = blt_ring_get_irq,
1266 .irq_put = blt_ring_put_irq,
1267 .dispatch_execbuffer = gen6_ring_dispatch_execbuffer,
1268 .cleanup = blt_ring_cleanup,
1271 int intel_init_render_ring_buffer(struct drm_device *dev)
1273 drm_i915_private_t *dev_priv = dev->dev_private;
1274 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1276 *ring = render_ring;
1277 if (INTEL_INFO(dev)->gen >= 6) {
1278 ring->add_request = gen6_add_request;
1279 ring->irq_get = gen6_render_ring_get_irq;
1280 ring->irq_put = gen6_render_ring_put_irq;
1281 } else if (IS_GEN5(dev)) {
1282 ring->add_request = pc_render_add_request;
1283 ring->get_seqno = pc_render_get_seqno;
1286 if (!I915_NEED_GFX_HWS(dev)) {
1287 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1288 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1291 return intel_init_ring_buffer(dev, ring);
1294 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
1296 drm_i915_private_t *dev_priv = dev->dev_private;
1297 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1299 *ring = render_ring;
1300 if (INTEL_INFO(dev)->gen >= 6) {
1301 ring->add_request = gen6_add_request;
1302 ring->irq_get = gen6_render_ring_get_irq;
1303 ring->irq_put = gen6_render_ring_put_irq;
1304 } else if (IS_GEN5(dev)) {
1305 ring->add_request = pc_render_add_request;
1306 ring->get_seqno = pc_render_get_seqno;
1310 INIT_LIST_HEAD(&ring->active_list);
1311 INIT_LIST_HEAD(&ring->request_list);
1312 INIT_LIST_HEAD(&ring->gpu_write_list);
1315 ring->effective_size = ring->size;
1316 if (IS_I830(ring->dev))
1317 ring->effective_size -= 128;
1319 ring->map.offset = start;
1320 ring->map.size = size;
1322 ring->map.flags = 0;
1325 drm_core_ioremap_wc(&ring->map, dev);
1326 if (ring->map.handle == NULL) {
1327 DRM_ERROR("can not ioremap virtual address for"
1332 ring->virtual_start = (void __force __iomem *)ring->map.handle;
1336 int intel_init_bsd_ring_buffer(struct drm_device *dev)
1338 drm_i915_private_t *dev_priv = dev->dev_private;
1339 struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
1342 *ring = gen6_bsd_ring;
1346 return intel_init_ring_buffer(dev, ring);
1349 int intel_init_blt_ring_buffer(struct drm_device *dev)
1351 drm_i915_private_t *dev_priv = dev->dev_private;
1352 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
1354 *ring = gen6_blt_ring;
1356 return intel_init_ring_buffer(dev, ring);