drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Zou Nan hai <nanhai.zou@intel.com>
  26  *    Xiang Hai hao<haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 #include <drm/drmP.h>
  31 #include "i915_drv.h"
  32 #include <drm/i915_drm.h>
  33 #include "i915_trace.h"
  34 #include "intel_drv.h"
  35
  36 bool
  37 intel_ring_initialized(struct intel_engine_cs *ring)
  38 {
  39         struct drm_device *dev = ring->dev;
  40
  41         if (!dev)
  42                 return false;
  43
  44         if (i915.enable_execlists) {
  45                 struct intel_context *dctx = ring->default_context;
  46                 struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf;
  47
  48                 return ringbuf->obj;
  49         } else
  50                 return ring->buffer && ring->buffer->obj;
  51 }
  52
  53 int __intel_ring_space(int head, int tail, int size)
  54 {
  55         int space = head - tail;
  56         if (space <= 0)
  57                 space += size;
  58         return space - I915_RING_FREE_SPACE;
  59 }
  60
  61 void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
  62 {
  63         if (ringbuf->last_retired_head != -1) {
  64                 ringbuf->head = ringbuf->last_retired_head;
  65                 ringbuf->last_retired_head = -1;
  66         }
  67
  68         ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
  69                                             ringbuf->tail, ringbuf->size);
  70 }
  71
  72 int intel_ring_space(struct intel_ringbuffer *ringbuf)
  73 {
  74         intel_ring_update_space(ringbuf);
  75         return ringbuf->space;
  76 }
  77
  78 bool intel_ring_stopped(struct intel_engine_cs *ring)
  79 {
  80         struct drm_i915_private *dev_priv = ring->dev->dev_private;
  81         return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring);
  82 }
  83
  84 static void __intel_ring_advance(struct intel_engine_cs *ring)
  85 {
  86         struct intel_ringbuffer *ringbuf = ring->buffer;
  87         ringbuf->tail &= ringbuf->size - 1;
  88         if (intel_ring_stopped(ring))
  89                 return;
  90         ring->write_tail(ring, ringbuf->tail);
  91 }
  92
  93 static int
  94 gen2_render_ring_flush(struct drm_i915_gem_request *req,
  95                        u32      invalidate_domains,
  96                        u32      flush_domains)
  97 {
  98         struct intel_engine_cs *ring = req->ring;
  99         u32 cmd;
 100         int ret;
 101
 102         cmd = MI_FLUSH;
 103         if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
 104                 cmd |= MI_NO_WRITE_FLUSH;
 105
 106         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
 107                 cmd |= MI_READ_FLUSH;
 108
 109         ret = intel_ring_begin(req, 2);
 110         if (ret)
 111                 return ret;
 112
 113         intel_ring_emit(ring, cmd);
 114         intel_ring_emit(ring, MI_NOOP);
 115         intel_ring_advance(ring);
 116
 117         return 0;
 118 }
 119
 120 static int
 121 gen4_render_ring_flush(struct drm_i915_gem_request *req,
 122                        u32      invalidate_domains,
 123                        u32      flush_domains)
 124 {
 125         struct intel_engine_cs *ring = req->ring;
 126         struct drm_device *dev = ring->dev;
 127         u32 cmd;
 128         int ret;
 129
 130         /*
 131          * read/write caches:
 132          *
 133          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
 134          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
 135          * also flushed at 2d versus 3d pipeline switches.
 136          *
 137          * read-only caches:
 138          *
 139          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
 140          * MI_READ_FLUSH is set, and is always flushed on 965.
 141          *
 142          * I915_GEM_DOMAIN_COMMAND may not exist?
 143          *
 144          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
 145          * invalidated when MI_EXE_FLUSH is set.
 146          *
 147          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
 148          * invalidated with every MI_FLUSH.
 149          *
 150          * TLBs:
 151          *
 152          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 153          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 154          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 155          * are flushed at any MI_FLUSH.
 156          */
 157
 158         cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
 159         if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
 160                 cmd &= ~MI_NO_WRITE_FLUSH;
 161         if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 162                 cmd |= MI_EXE_FLUSH;
 163
 164         if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
 165             (IS_G4X(dev) || IS_GEN5(dev)))
 166                 cmd |= MI_INVALIDATE_ISP;
 167
 168         ret = intel_ring_begin(req, 2);
 169         if (ret)
 170                 return ret;
 171
 172         intel_ring_emit(ring, cmd);
 173         intel_ring_emit(ring, MI_NOOP);
 174         intel_ring_advance(ring);
 175
 176         return 0;
 177 }
 178
 179 /**
 180  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 181  * implementing two workarounds on gen6.  From section 1.4.7.1
 182  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 183  *
 184  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 185  * produced by non-pipelined state commands), software needs to first
 186  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 187  * 0.
 188  *
 189  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 190  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 191  *
 192  * And the workaround for these two requires this workaround first:
 193  *
 194  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 195  * BEFORE the pipe-control with a post-sync op and no write-cache
 196  * flushes.
 197  *
 198  * And this last workaround is tricky because of the requirements on
 199  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 200  * volume 2 part 1:
 201  *
 202  *     "1 of the following must also be set:
 203  *      - Render Target Cache Flush Enable ([12] of DW1)
 204  *      - Depth Cache Flush Enable ([0] of DW1)
 205  *      - Stall at Pixel Scoreboard ([1] of DW1)
 206  *      - Depth Stall ([13] of DW1)
 207  *      - Post-Sync Operation ([13] of DW1)
 208  *      - Notify Enable ([8] of DW1)"
 209  *
 210  * The cache flushes require the workaround flush that triggered this
 211  * one, so we can't use it.  Depth stall would trigger the same.
 212  * Post-sync nonzero is what triggered this second workaround, so we
 213  * can't use that one either.  Notify enable is IRQs, which aren't
 214  * really our business.  That leaves only stall at scoreboard.
 215  */
 216 static int
 217 intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req)
 218 {
 219         struct intel_engine_cs *ring = req->ring;
 220         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 221         int ret;
 222
 223         ret = intel_ring_begin(req, 6);
 224         if (ret)
 225                 return ret;
 226
 227         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 228         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 229                         PIPE_CONTROL_STALL_AT_SCOREBOARD);
 230         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 231         intel_ring_emit(ring, 0); /* low dword */
 232         intel_ring_emit(ring, 0); /* high dword */
 233         intel_ring_emit(ring, MI_NOOP);
 234         intel_ring_advance(ring);
 235
 236         ret = intel_ring_begin(req, 6);
 237         if (ret)
 238                 return ret;
 239
 240         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 241         intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
 242         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 243         intel_ring_emit(ring, 0);
 244         intel_ring_emit(ring, 0);
 245         intel_ring_emit(ring, MI_NOOP);
 246         intel_ring_advance(ring);
 247
 248         return 0;
 249 }
 250
 251 static int
 252 gen6_render_ring_flush(struct drm_i915_gem_request *req,
 253                        u32 invalidate_domains, u32 flush_domains)
 254 {
 255         struct intel_engine_cs *ring = req->ring;
 256         u32 flags = 0;
 257         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 258         int ret;
 259
 260         /* Force SNB workarounds for PIPE_CONTROL flushes */
 261         ret = intel_emit_post_sync_nonzero_flush(req);
 262         if (ret)
 263                 return ret;
 264
 265         /* Just flush everything.  Experiments have shown that reducing the
 266          * number of bits based on the write domains has little performance
 267          * impact.
 268          */
 269         if (flush_domains) {
 270                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 271                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 272                 /*
 273                  * Ensure that any following seqno writes only happen
 274                  * when the render cache is indeed flushed.
 275                  */
 276                 flags |= PIPE_CONTROL_CS_STALL;
 277         }
 278         if (invalidate_domains) {
 279                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 280                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 281                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 282                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 283                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 284                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 285                 /*
 286                  * TLB invalidate requires a post-sync write.
 287                  */
 288                 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
 289         }
 290
 291         ret = intel_ring_begin(req, 4);
 292         if (ret)
 293                 return ret;
 294
 295         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 296         intel_ring_emit(ring, flags);
 297         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
 298         intel_ring_emit(ring, 0);
 299         intel_ring_advance(ring);
 300
 301         return 0;
 302 }
 303
 304 static int
 305 gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req)
 306 {
 307         struct intel_engine_cs *ring = req->ring;
 308         int ret;
 309
 310         ret = intel_ring_begin(req, 4);
 311         if (ret)
 312                 return ret;
 313
 314         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 315         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 316                               PIPE_CONTROL_STALL_AT_SCOREBOARD);
 317         intel_ring_emit(ring, 0);
 318         intel_ring_emit(ring, 0);
 319         intel_ring_advance(ring);
 320
 321         return 0;
 322 }
 323
 324 static int
 325 gen7_render_ring_flush(struct drm_i915_gem_request *req,
 326                        u32 invalidate_domains, u32 flush_domains)
 327 {
 328         struct intel_engine_cs *ring = req->ring;
 329         u32 flags = 0;
 330         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 331         int ret;
 332
 333         /*
 334          * Ensure that any following seqno writes only happen when the render
 335          * cache is indeed flushed.
 336          *
 337          * Workaround: 4th PIPE_CONTROL command (except the ones with only
 338          * read-cache invalidate bits set) must have the CS_STALL bit set. We
 339          * don't try to be clever and just set it unconditionally.
 340          */
 341         flags |= PIPE_CONTROL_CS_STALL;
 342
 343         /* Just flush everything.  Experiments have shown that reducing the
 344          * number of bits based on the write domains has little performance
 345          * impact.
 346          */
 347         if (flush_domains) {
 348                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 349                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 350         }
 351         if (invalidate_domains) {
 352                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 353                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 354                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 355                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 356                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 357                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 358                 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
 359                 /*
 360                  * TLB invalidate requires a post-sync write.
 361                  */
 362                 flags |= PIPE_CONTROL_QW_WRITE;
 363                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 364
 365                 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
 366
 367                 /* Workaround: we must issue a pipe_control with CS-stall bit
 368                  * set before a pipe_control command that has the state cache
 369                  * invalidate bit set. */
 370                 gen7_render_ring_cs_stall_wa(req);
 371         }
 372
 373         ret = intel_ring_begin(req, 4);
 374         if (ret)
 375                 return ret;
 376
 377         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 378         intel_ring_emit(ring, flags);
 379         intel_ring_emit(ring, scratch_addr);
 380         intel_ring_emit(ring, 0);
 381         intel_ring_advance(ring);
 382
 383         return 0;
 384 }
 385
 386 static int
 387 gen8_emit_pipe_control(struct drm_i915_gem_request *req,
 388                        u32 flags, u32 scratch_addr)
 389 {
 390         struct intel_engine_cs *ring = req->ring;
 391         int ret;
 392
 393         ret = intel_ring_begin(req, 6);
 394         if (ret)
 395                 return ret;
 396
 397         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
 398         intel_ring_emit(ring, flags);
 399         intel_ring_emit(ring, scratch_addr);
 400         intel_ring_emit(ring, 0);
 401         intel_ring_emit(ring, 0);
 402         intel_ring_emit(ring, 0);
 403         intel_ring_advance(ring);
 404
 405         return 0;
 406 }
 407
 408 static int
 409 gen8_render_ring_flush(struct drm_i915_gem_request *req,
 410                        u32 invalidate_domains, u32 flush_domains)
 411 {
 412         u32 flags = 0;
 413         u32 scratch_addr = req->ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 414         int ret;
 415
 416         flags |= PIPE_CONTROL_CS_STALL;
 417
 418         if (flush_domains) {
 419                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 420                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 421         }
 422         if (invalidate_domains) {
 423                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 424                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 425                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 426                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 427                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 428                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 429                 flags |= PIPE_CONTROL_QW_WRITE;
 430                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 431
 432                 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
 433                 ret = gen8_emit_pipe_control(req,
 434                                              PIPE_CONTROL_CS_STALL |
 435                                              PIPE_CONTROL_STALL_AT_SCOREBOARD,
 436                                              0);
 437                 if (ret)
 438                         return ret;
 439         }
 440
 441         return gen8_emit_pipe_control(req, flags, scratch_addr);
 442 }
 443
 444 static void ring_write_tail(struct intel_engine_cs *ring,
 445                             u32 value)
 446 {
 447         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 448         I915_WRITE_TAIL(ring, value);
 449 }
 450
 451 u64 intel_ring_get_active_head(struct intel_engine_cs *ring)
 452 {
 453         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 454         u64 acthd;
 455
 456         if (INTEL_INFO(ring->dev)->gen >= 8)
 457                 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
 458                                          RING_ACTHD_UDW(ring->mmio_base));
 459         else if (INTEL_INFO(ring->dev)->gen >= 4)
 460                 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
 461         else
 462                 acthd = I915_READ(ACTHD);
 463
 464         return acthd;
 465 }
 466
 467 static void ring_setup_phys_status_page(struct intel_engine_cs *ring)
 468 {
 469         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 470         u32 addr;
 471
 472         addr = dev_priv->status_page_dmah->busaddr;
 473         if (INTEL_INFO(ring->dev)->gen >= 4)
 474                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
 475         I915_WRITE(HWS_PGA, addr);
 476 }
 477
 478 static void intel_ring_setup_status_page(struct intel_engine_cs *ring)
 479 {
 480         struct drm_device *dev = ring->dev;
 481         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 482         u32 mmio = 0;
 483
 484         /* The ring status page addresses are no longer next to the rest of
 485          * the ring registers as of gen7.
 486          */
 487         if (IS_GEN7(dev)) {
 488                 switch (ring->id) {
 489                 case RCS:
 490                         mmio = RENDER_HWS_PGA_GEN7;
 491                         break;
 492                 case BCS:
 493                         mmio = BLT_HWS_PGA_GEN7;
 494                         break;
 495                 /*
 496                  * VCS2 actually doesn't exist on Gen7. Only shut up
 497                  * gcc switch check warning
 498                  */
 499                 case VCS2:
 500                 case VCS:
 501                         mmio = BSD_HWS_PGA_GEN7;
 502                         break;
 503                 case VECS:
 504                         mmio = VEBOX_HWS_PGA_GEN7;
 505                         break;
 506                 }
 507         } else if (IS_GEN6(ring->dev)) {
 508                 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
 509         } else {
 510                 /* XXX: gen8 returns to sanity */
 511                 mmio = RING_HWS_PGA(ring->mmio_base);
 512         }
 513
 514         I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
 515         POSTING_READ(mmio);
 516
 517         /*
 518          * Flush the TLB for this page
 519          *
 520          * FIXME: These two bits have disappeared on gen8, so a question
 521          * arises: do we still need this and if so how should we go about
 522          * invalidating the TLB?
 523          */
 524         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
 525                 u32 reg = RING_INSTPM(ring->mmio_base);
 526
 527                 /* ring should be idle before issuing a sync flush*/
 528                 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
 529
 530                 I915_WRITE(reg,
 531                            _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
 532                                               INSTPM_SYNC_FLUSH));
 533                 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
 534                              1000))
 535                         DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
 536                                   ring->name);
 537         }
 538 }
 539
 540 static bool stop_ring(struct intel_engine_cs *ring)
 541 {
 542         struct drm_i915_private *dev_priv = to_i915(ring->dev);
 543
 544         if (!IS_GEN2(ring->dev)) {
 545                 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
 546                 if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
 547                         DRM_ERROR("%s : timed out trying to stop ring\n", ring->name);
 548                         /* Sometimes we observe that the idle flag is not
 549                          * set even though the ring is empty. So double
 550                          * check before giving up.
 551                          */
 552                         if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring))
 553                                 return false;
 554                 }
 555         }
 556
 557         I915_WRITE_CTL(ring, 0);
 558         I915_WRITE_HEAD(ring, 0);
 559         ring->write_tail(ring, 0);
 560
 561         if (!IS_GEN2(ring->dev)) {
 562                 (void)I915_READ_CTL(ring);
 563                 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
 564         }
 565
 566         return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
 567 }
 568
 569 static int init_ring_common(struct intel_engine_cs *ring)
 570 {
 571         struct drm_device *dev = ring->dev;
 572         struct drm_i915_private *dev_priv = dev->dev_private;
 573         struct intel_ringbuffer *ringbuf = ring->buffer;
 574         struct drm_i915_gem_object *obj = ringbuf->obj;
 575         int ret = 0;
 576
 577         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 578
 579         if (!stop_ring(ring)) {
 580                 /* G45 ring initialization often fails to reset head to zero */
 581                 DRM_DEBUG_KMS("%s head not reset to zero "
 582                               "ctl %08x head %08x tail %08x start %08x\n",
 583                               ring->name,
 584                               I915_READ_CTL(ring),
 585                               I915_READ_HEAD(ring),
 586                               I915_READ_TAIL(ring),
 587                               I915_READ_START(ring));
 588
 589                 if (!stop_ring(ring)) {
 590                         DRM_ERROR("failed to set %s head to zero "
 591                                   "ctl %08x head %08x tail %08x start %08x\n",
 592                                   ring->name,
 593                                   I915_READ_CTL(ring),
 594                                   I915_READ_HEAD(ring),
 595                                   I915_READ_TAIL(ring),
 596                                   I915_READ_START(ring));
 597                         ret = -EIO;
 598                         goto out;
 599                 }
 600         }
 601
 602         if (I915_NEED_GFX_HWS(dev))
 603                 intel_ring_setup_status_page(ring);
 604         else
 605                 ring_setup_phys_status_page(ring);
 606
 607         /* Enforce ordering by reading HEAD register back */
 608         I915_READ_HEAD(ring);
 609
 610         /* Initialize the ring. This must happen _after_ we've cleared the ring
 611          * registers with the above sequence (the readback of the HEAD registers
 612          * also enforces ordering), otherwise the hw might lose the new ring
 613          * register values. */
 614         I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
 615
 616         /* WaClearRingBufHeadRegAtInit:ctg,elk */
 617         if (I915_READ_HEAD(ring))
 618                 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
 619                           ring->name, I915_READ_HEAD(ring));
 620         I915_WRITE_HEAD(ring, 0);
 621         (void)I915_READ_HEAD(ring);
 622
 623         I915_WRITE_CTL(ring,
 624                         ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
 625                         | RING_VALID);
 626
 627         /* If the head is still not zero, the ring is dead */
 628         if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
 629                      I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
 630                      (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
 631                 DRM_ERROR("%s initialization failed "
 632                           "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
 633                           ring->name,
 634                           I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID,
 635                           I915_READ_HEAD(ring), I915_READ_TAIL(ring),
 636                           I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj));
 637                 ret = -EIO;
 638                 goto out;
 639         }
 640
 641         ringbuf->last_retired_head = -1;
 642         ringbuf->head = I915_READ_HEAD(ring);
 643         ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 644         intel_ring_update_space(ringbuf);
 645
 646         memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
 647
 648 out:
 649         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 650
 651         return ret;
 652 }
 653
 654 void
 655 intel_fini_pipe_control(struct intel_engine_cs *ring)
 656 {
 657         struct drm_device *dev = ring->dev;
 658
 659         if (ring->scratch.obj == NULL)
 660                 return;
 661
 662         if (INTEL_INFO(dev)->gen >= 5) {
 663                 kunmap(sg_page(ring->scratch.obj->pages->sgl));
 664                 i915_gem_object_ggtt_unpin(ring->scratch.obj);
 665         }
 666
 667         drm_gem_object_unreference(&ring->scratch.obj->base);
 668         ring->scratch.obj = NULL;
 669 }
 670
 671 int
 672 intel_init_pipe_control(struct intel_engine_cs *ring)
 673 {
 674         int ret;
 675
 676         WARN_ON(ring->scratch.obj);
 677
 678         ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
 679         if (ring->scratch.obj == NULL) {
 680                 DRM_ERROR("Failed to allocate seqno page\n");
 681                 ret = -ENOMEM;
 682                 goto err;
 683         }
 684
 685         ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
 686         if (ret)
 687                 goto err_unref;
 688
 689         ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
 690         if (ret)
 691                 goto err_unref;
 692
 693         ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
 694         ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
 695         if (ring->scratch.cpu_page == NULL) {
 696                 ret = -ENOMEM;
 697                 goto err_unpin;
 698         }
 699
 700         DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
 701                          ring->name, ring->scratch.gtt_offset);
 702         return 0;
 703
 704 err_unpin:
 705         i915_gem_object_ggtt_unpin(ring->scratch.obj);
 706 err_unref:
 707         drm_gem_object_unreference(&ring->scratch.obj->base);
 708 err:
 709         return ret;
 710 }
 711
 712 static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
 713 {
 714         int ret, i;
 715         struct intel_engine_cs *ring = req->ring;
 716         struct drm_device *dev = ring->dev;
 717         struct drm_i915_private *dev_priv = dev->dev_private;
 718         struct i915_workarounds *w = &dev_priv->workarounds;
 719
 720         if (WARN_ON_ONCE(w->count == 0))
 721                 return 0;
 722
 723         ring->gpu_caches_dirty = true;
 724         ret = intel_ring_flush_all_caches(req);
 725         if (ret)
 726                 return ret;
 727
 728         ret = intel_ring_begin(req, (w->count * 2 + 2));
 729         if (ret)
 730                 return ret;
 731
 732         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
 733         for (i = 0; i < w->count; i++) {
 734                 intel_ring_emit(ring, w->reg[i].addr);
 735                 intel_ring_emit(ring, w->reg[i].value);
 736         }
 737         intel_ring_emit(ring, MI_NOOP);
 738
 739         intel_ring_advance(ring);
 740
 741         ring->gpu_caches_dirty = true;
 742         ret = intel_ring_flush_all_caches(req);
 743         if (ret)
 744                 return ret;
 745
 746         DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
 747
 748         return 0;
 749 }
 750
 751 static int intel_rcs_ctx_init(struct drm_i915_gem_request *req)
 752 {
 753         int ret;
 754
 755         ret = intel_ring_workarounds_emit(req);
 756         if (ret != 0)
 757                 return ret;
 758
 759         ret = i915_gem_render_state_init(req);
 760         if (ret)
 761                 DRM_ERROR("init render state: %d\n", ret);
 762
 763         return ret;
 764 }
 765
 766 static int wa_add(struct drm_i915_private *dev_priv,
 767                   const u32 addr, const u32 mask, const u32 val)
 768 {
 769         const u32 idx = dev_priv->workarounds.count;
 770
 771         if (WARN_ON(idx >= I915_MAX_WA_REGS))
 772                 return -ENOSPC;
 773
 774         dev_priv->workarounds.reg[idx].addr = addr;
 775         dev_priv->workarounds.reg[idx].value = val;
 776         dev_priv->workarounds.reg[idx].mask = mask;
 777
 778         dev_priv->workarounds.count++;
 779
 780         return 0;
 781 }
 782
 783 #define WA_REG(addr, mask, val) do { \
 784                 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
 785                 if (r) \
 786                         return r; \
 787         } while (0)
 788
 789 #define WA_SET_BIT_MASKED(addr, mask) \
 790         WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
 791
 792 #define WA_CLR_BIT_MASKED(addr, mask) \
 793         WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
 794
 795 #define WA_SET_FIELD_MASKED(addr, mask, value) \
 796         WA_REG(addr, mask, _MASKED_FIELD(mask, value))
 797
 798 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
 799 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
 800
 801 #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
 802
 803 static int gen8_init_workarounds(struct intel_engine_cs *ring)
 804 {
 805         struct drm_device *dev = ring->dev;
 806         struct drm_i915_private *dev_priv = dev->dev_private;
 807
 808         WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
 809
 810         /* WaDisableAsyncFlipPerfMode:bdw,chv */
 811         WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
 812
 813         /* WaDisablePartialInstShootdown:bdw,chv */
 814         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 815                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 816
 817         /* Use Force Non-Coherent whenever executing a 3D context. This is a
 818          * workaround for for a possible hang in the unlikely event a TLB
 819          * invalidation occurs during a PSD flush.
 820          */
 821         /* WaForceEnableNonCoherent:bdw,chv */
 822         /* WaHdcDisableFetchWhenMasked:bdw,chv */
 823         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 824                           HDC_DONOT_FETCH_MEM_WHEN_MASKED |
 825                           HDC_FORCE_NON_COHERENT);
 826
 827         /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
 828          * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
 829          *  polygons in the same 8x4 pixel/sample area to be processed without
 830          *  stalling waiting for the earlier ones to write to Hierarchical Z
 831          *  buffer."
 832          *
 833          * This optimization is off by default for BDW and CHV; turn it on.
 834          */
 835         WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
 836
 837         /* Wa4x4STCOptimizationDisable:bdw,chv */
 838         WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
 839
 840         /*
 841          * BSpec recommends 8x4 when MSAA is used,
 842          * however in practice 16x4 seems fastest.
 843          *
 844          * Note that PS/WM thread counts depend on the WIZ hashing
 845          * disable bit, which we don't touch here, but it's good
 846          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
 847          */
 848         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
 849                             GEN6_WIZ_HASHING_MASK,
 850                             GEN6_WIZ_HASHING_16x4);
 851
 852         return 0;
 853 }
 854
 855 static int bdw_init_workarounds(struct intel_engine_cs *ring)
 856 {
 857         int ret;
 858         struct drm_device *dev = ring->dev;
 859         struct drm_i915_private *dev_priv = dev->dev_private;
 860
 861         ret = gen8_init_workarounds(ring);
 862         if (ret)
 863                 return ret;
 864
 865         /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
 866         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
 867
 868         /* WaDisableDopClockGating:bdw */
 869         WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
 870                           DOP_CLOCK_GATING_DISABLE);
 871
 872         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 873                           GEN8_SAMPLER_POWER_BYPASS_DIS);
 874
 875         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 876                           /* WaForceContextSaveRestoreNonCoherent:bdw */
 877                           HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
 878                           /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
 879                           (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
 880
 881         return 0;
 882 }
 883
 884 static int chv_init_workarounds(struct intel_engine_cs *ring)
 885 {
 886         int ret;
 887         struct drm_device *dev = ring->dev;
 888         struct drm_i915_private *dev_priv = dev->dev_private;
 889
 890         ret = gen8_init_workarounds(ring);
 891         if (ret)
 892                 return ret;
 893
 894         /* WaDisableThreadStallDopClockGating:chv */
 895         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
 896
 897         /* Improve HiZ throughput on CHV. */
 898         WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
 899
 900         return 0;
 901 }
 902
 903 static int gen9_init_workarounds(struct intel_engine_cs *ring)
 904 {
 905         struct drm_device *dev = ring->dev;
 906         struct drm_i915_private *dev_priv = dev->dev_private;
 907         uint32_t tmp;
 908
 909         /* WaDisablePartialInstShootdown:skl,bxt */
 910         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 911                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 912
 913         /* Syncing dependencies between camera and graphics:skl,bxt */
 914         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 915                           GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
 916
 917         if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) == SKL_REVID_A0 ||
 918             INTEL_REVID(dev) == SKL_REVID_B0)) ||
 919             (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) {
 920                 /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
 921                 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
 922                                   GEN9_DG_MIRROR_FIX_ENABLE);
 923         }
 924
 925         if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) ||
 926             (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) {
 927                 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
 928                 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
 929                                   GEN9_RHWO_OPTIMIZATION_DISABLE);
 930                 /*
 931                  * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
 932                  * but we do that in per ctx batchbuffer as there is an issue
 933                  * with this register not getting restored on ctx restore
 934                  */
 935         }
 936
 937         if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) >= SKL_REVID_C0) ||
 938             IS_BROXTON(dev)) {
 939                 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */
 940                 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
 941                                   GEN9_ENABLE_YV12_BUGFIX);
 942         }
 943
 944         /* Wa4x4STCOptimizationDisable:skl,bxt */
 945         /* WaDisablePartialResolveInVc:skl,bxt */
 946         WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE |
 947                                          GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE));
 948
 949         /* WaCcsTlbPrefetchDisable:skl,bxt */
 950         WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
 951                           GEN9_CCS_TLB_PREFETCH_ENABLE);
 952
 953         /* WaDisableMaskBasedCammingInRCC:skl,bxt */
 954         if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_C0) ||
 955             (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0))
 956                 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
 957                                   PIXEL_MASK_CAMMING_DISABLE);
 958
 959         /* WaForceContextSaveRestoreNonCoherent:skl,bxt */
 960         tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
 961         if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_F0) ||
 962             (IS_BROXTON(dev) && INTEL_REVID(dev) >= BXT_REVID_B0))
 963                 tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
 964         WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
 965
 966         /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt */
 967         if (IS_SKYLAKE(dev) ||
 968             (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_B0)) {
 969                 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 970                                   GEN8_SAMPLER_POWER_BYPASS_DIS);
 971         }
 972
 973         /* WaDisableSTUnitPowerOptimization:skl,bxt */
 974         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
 975
 976         return 0;
 977 }
 978
 979 static int skl_tune_iz_hashing(struct intel_engine_cs *ring)
 980 {
 981         struct drm_device *dev = ring->dev;
 982         struct drm_i915_private *dev_priv = dev->dev_private;
 983         u8 vals[3] = { 0, 0, 0 };
 984         unsigned int i;
 985
 986         for (i = 0; i < 3; i++) {
 987                 u8 ss;
 988
 989                 /*
 990                  * Only consider slices where one, and only one, subslice has 7
 991                  * EUs
 992                  */
 993                 if (hweight8(dev_priv->info.subslice_7eu[i]) != 1)
 994                         continue;
 995
 996                 /*
 997                  * subslice_7eu[i] != 0 (because of the check above) and
 998                  * ss_max == 4 (maximum number of subslices possible per slice)
 999                  *
1000                  * ->    0 <= ss <= 3;
1001                  */
1002                 ss = ffs(dev_priv->info.subslice_7eu[i]) - 1;
1003                 vals[i] = 3 - ss;
1004         }
1005
1006         if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
1007                 return 0;
1008
1009         /* Tune IZ hashing. See intel_device_info_runtime_init() */
1010         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
1011                             GEN9_IZ_HASHING_MASK(2) |
1012                             GEN9_IZ_HASHING_MASK(1) |
1013                             GEN9_IZ_HASHING_MASK(0),
1014                             GEN9_IZ_HASHING(2, vals[2]) |
1015                             GEN9_IZ_HASHING(1, vals[1]) |
1016                             GEN9_IZ_HASHING(0, vals[0]));
1017
1018         return 0;
1019 }
1020
1021
1022 static int skl_init_workarounds(struct intel_engine_cs *ring)
1023 {
1024         int ret;
1025         struct drm_device *dev = ring->dev;
1026         struct drm_i915_private *dev_priv = dev->dev_private;
1027
1028         ret = gen9_init_workarounds(ring);
1029         if (ret)
1030                 return ret;
1031
1032         /* WaDisablePowerCompilerClockGating:skl */
1033         if (INTEL_REVID(dev) == SKL_REVID_B0)
1034                 WA_SET_BIT_MASKED(HIZ_CHICKEN,
1035                                   BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
1036
1037         if (INTEL_REVID(dev) <= SKL_REVID_D0) {
1038                 /*
1039                  *Use Force Non-Coherent whenever executing a 3D context. This
1040                  * is a workaround for a possible hang in the unlikely event
1041                  * a TLB invalidation occurs during a PSD flush.
1042                  */
1043                 /* WaForceEnableNonCoherent:skl */
1044                 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1045                                   HDC_FORCE_NON_COHERENT);
1046         }
1047
1048         if (INTEL_REVID(dev) == SKL_REVID_C0 ||
1049             INTEL_REVID(dev) == SKL_REVID_D0)
1050                 /* WaBarrierPerformanceFixDisable:skl */
1051                 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1052                                   HDC_FENCE_DEST_SLM_DISABLE |
1053                                   HDC_BARRIER_PERFORMANCE_DISABLE);
1054
1055         /* WaDisableSbeCacheDispatchPortSharing:skl */
1056         if (INTEL_REVID(dev) <= SKL_REVID_F0) {
1057                 WA_SET_BIT_MASKED(
1058                         GEN7_HALF_SLICE_CHICKEN1,
1059                         GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1060         }
1061
1062         return skl_tune_iz_hashing(ring);
1063 }
1064
1065 static int bxt_init_workarounds(struct intel_engine_cs *ring)
1066 {
1067         int ret;
1068         struct drm_device *dev = ring->dev;
1069         struct drm_i915_private *dev_priv = dev->dev_private;
1070
1071         ret = gen9_init_workarounds(ring);
1072         if (ret)
1073                 return ret;
1074
1075         /* WaDisableThreadStallDopClockGating:bxt */
1076         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
1077                           STALL_DOP_GATING_DISABLE);
1078
1079         /* WaDisableSbeCacheDispatchPortSharing:bxt */
1080         if (INTEL_REVID(dev) <= BXT_REVID_B0) {
1081                 WA_SET_BIT_MASKED(
1082                         GEN7_HALF_SLICE_CHICKEN1,
1083                         GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1084         }
1085
1086         return 0;
1087 }
1088
1089 int init_workarounds_ring(struct intel_engine_cs *ring)
1090 {
1091         struct drm_device *dev = ring->dev;
1092         struct drm_i915_private *dev_priv = dev->dev_private;
1093
1094         WARN_ON(ring->id != RCS);
1095
1096         dev_priv->workarounds.count = 0;
1097
1098         if (IS_BROADWELL(dev))
1099                 return bdw_init_workarounds(ring);
1100
1101         if (IS_CHERRYVIEW(dev))
1102                 return chv_init_workarounds(ring);
1103
1104         if (IS_SKYLAKE(dev))
1105                 return skl_init_workarounds(ring);
1106
1107         if (IS_BROXTON(dev))
1108                 return bxt_init_workarounds(ring);
1109
1110         return 0;
1111 }
1112
1113 static int init_render_ring(struct intel_engine_cs *ring)
1114 {
1115         struct drm_device *dev = ring->dev;
1116         struct drm_i915_private *dev_priv = dev->dev_private;
1117         int ret = init_ring_common(ring);
1118         if (ret)
1119                 return ret;
1120
1121         /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1122         if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
1123                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1124
1125         /* We need to disable the AsyncFlip performance optimisations in order
1126          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1127          * programmed to '1' on all products.
1128          *
1129          * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
1130          */
1131         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
1132                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1133
1134         /* Required for the hardware to program scanline values for waiting */
1135         /* WaEnableFlushTlbInvalidationMode:snb */
1136         if (INTEL_INFO(dev)->gen == 6)
1137                 I915_WRITE(GFX_MODE,
1138                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
1139
1140         /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1141         if (IS_GEN7(dev))
1142                 I915_WRITE(GFX_MODE_GEN7,
1143                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1144                            _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
1145
1146         if (IS_GEN6(dev)) {
1147                 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1148                  * "If this bit is set, STCunit will have LRA as replacement
1149                  *  policy. [...] This bit must be reset.  LRA replacement
1150                  *  policy is not supported."
1151                  */
1152                 I915_WRITE(CACHE_MODE_0,
1153                            _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
1154         }
1155
1156         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
1157                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1158
1159         if (HAS_L3_DPF(dev))
1160                 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1161
1162         return init_workarounds_ring(ring);
1163 }
1164
1165 static void render_ring_cleanup(struct intel_engine_cs *ring)
1166 {
1167         struct drm_device *dev = ring->dev;
1168         struct drm_i915_private *dev_priv = dev->dev_private;
1169
1170         if (dev_priv->semaphore_obj) {
1171                 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
1172                 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
1173                 dev_priv->semaphore_obj = NULL;
1174         }
1175
1176         intel_fini_pipe_control(ring);
1177 }
1178
1179 static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
1180                            unsigned int num_dwords)
1181 {
1182 #define MBOX_UPDATE_DWORDS 8
1183         struct intel_engine_cs *signaller = signaller_req->ring;
1184         struct drm_device *dev = signaller->dev;
1185         struct drm_i915_private *dev_priv = dev->dev_private;
1186         struct intel_engine_cs *waiter;
1187         int i, ret, num_rings;
1188
1189         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1190         num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1191 #undef MBOX_UPDATE_DWORDS
1192
1193         ret = intel_ring_begin(signaller_req, num_dwords);
1194         if (ret)
1195                 return ret;
1196
1197         for_each_ring(waiter, dev_priv, i) {
1198                 u32 seqno;
1199                 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1200                 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1201                         continue;
1202
1203                 seqno = i915_gem_request_get_seqno(signaller_req);
1204                 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
1205                 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
1206                                            PIPE_CONTROL_QW_WRITE |
1207                                            PIPE_CONTROL_FLUSH_ENABLE);
1208                 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
1209                 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1210                 intel_ring_emit(signaller, seqno);
1211                 intel_ring_emit(signaller, 0);
1212                 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1213                                            MI_SEMAPHORE_TARGET(waiter->id));
1214                 intel_ring_emit(signaller, 0);
1215         }
1216
1217         return 0;
1218 }
1219
1220 static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
1221                            unsigned int num_dwords)
1222 {
1223 #define MBOX_UPDATE_DWORDS 6
1224         struct intel_engine_cs *signaller = signaller_req->ring;
1225         struct drm_device *dev = signaller->dev;
1226         struct drm_i915_private *dev_priv = dev->dev_private;
1227         struct intel_engine_cs *waiter;
1228         int i, ret, num_rings;
1229
1230         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1231         num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1232 #undef MBOX_UPDATE_DWORDS
1233
1234         ret = intel_ring_begin(signaller_req, num_dwords);
1235         if (ret)
1236                 return ret;
1237
1238         for_each_ring(waiter, dev_priv, i) {
1239                 u32 seqno;
1240                 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1241                 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1242                         continue;
1243
1244                 seqno = i915_gem_request_get_seqno(signaller_req);
1245                 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
1246                                            MI_FLUSH_DW_OP_STOREDW);
1247                 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
1248                                            MI_FLUSH_DW_USE_GTT);
1249                 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1250                 intel_ring_emit(signaller, seqno);
1251                 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1252                                            MI_SEMAPHORE_TARGET(waiter->id));
1253                 intel_ring_emit(signaller, 0);
1254         }
1255
1256         return 0;
1257 }
1258
1259 static int gen6_signal(struct drm_i915_gem_request *signaller_req,
1260                        unsigned int num_dwords)
1261 {
1262         struct intel_engine_cs *signaller = signaller_req->ring;
1263         struct drm_device *dev = signaller->dev;
1264         struct drm_i915_private *dev_priv = dev->dev_private;
1265         struct intel_engine_cs *useless;
1266         int i, ret, num_rings;
1267
1268 #define MBOX_UPDATE_DWORDS 3
1269         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1270         num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1271 #undef MBOX_UPDATE_DWORDS
1272
1273         ret = intel_ring_begin(signaller_req, num_dwords);
1274         if (ret)
1275                 return ret;
1276
1277         for_each_ring(useless, dev_priv, i) {
1278                 u32 mbox_reg = signaller->semaphore.mbox.signal[i];
1279                 if (mbox_reg != GEN6_NOSYNC) {
1280                         u32 seqno = i915_gem_request_get_seqno(signaller_req);
1281                         intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
1282                         intel_ring_emit(signaller, mbox_reg);
1283                         intel_ring_emit(signaller, seqno);
1284                 }
1285         }
1286
1287         /* If num_dwords was rounded, make sure the tail pointer is correct */
1288         if (num_rings % 2 == 0)
1289                 intel_ring_emit(signaller, MI_NOOP);
1290
1291         return 0;
1292 }
1293
1294 /**
1295  * gen6_add_request - Update the semaphore mailbox registers
1296  *
1297  * @request - request to write to the ring
1298  *
1299  * Update the mailbox registers in the *other* rings with the current seqno.
1300  * This acts like a signal in the canonical semaphore.
1301  */
1302 static int
1303 gen6_add_request(struct drm_i915_gem_request *req)
1304 {
1305         struct intel_engine_cs *ring = req->ring;
1306         int ret;
1307
1308         if (ring->semaphore.signal)
1309                 ret = ring->semaphore.signal(req, 4);
1310         else
1311                 ret = intel_ring_begin(req, 4);
1312
1313         if (ret)
1314                 return ret;
1315
1316         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1317         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1318         intel_ring_emit(ring, i915_gem_request_get_seqno(req));
1319         intel_ring_emit(ring, MI_USER_INTERRUPT);
1320         __intel_ring_advance(ring);
1321
1322         return 0;
1323 }
1324
1325 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1326                                               u32 seqno)
1327 {
1328         struct drm_i915_private *dev_priv = dev->dev_private;
1329         return dev_priv->last_seqno < seqno;
1330 }
1331
1332 /**
1333  * intel_ring_sync - sync the waiter to the signaller on seqno
1334  *
1335  * @waiter - ring that is waiting
1336  * @signaller - ring which has, or will signal
1337  * @seqno - seqno which the waiter will block on
1338  */
1339
1340 static int
1341 gen8_ring_sync(struct drm_i915_gem_request *waiter_req,
1342                struct intel_engine_cs *signaller,
1343                u32 seqno)
1344 {
1345         struct intel_engine_cs *waiter = waiter_req->ring;
1346         struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1347         int ret;
1348
1349         ret = intel_ring_begin(waiter_req, 4);
1350         if (ret)
1351                 return ret;
1352
1353         intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1354                                 MI_SEMAPHORE_GLOBAL_GTT |
1355                                 MI_SEMAPHORE_POLL |
1356                                 MI_SEMAPHORE_SAD_GTE_SDD);
1357         intel_ring_emit(waiter, seqno);
1358         intel_ring_emit(waiter,
1359                         lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1360         intel_ring_emit(waiter,
1361                         upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1362         intel_ring_advance(waiter);
1363         return 0;
1364 }
1365
1366 static int
1367 gen6_ring_sync(struct drm_i915_gem_request *waiter_req,
1368                struct intel_engine_cs *signaller,
1369                u32 seqno)
1370 {
1371         struct intel_engine_cs *waiter = waiter_req->ring;
1372         u32 dw1 = MI_SEMAPHORE_MBOX |
1373                   MI_SEMAPHORE_COMPARE |
1374                   MI_SEMAPHORE_REGISTER;
1375         u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1376         int ret;
1377
1378         /* Throughout all of the GEM code, seqno passed implies our current
1379          * seqno is >= the last seqno executed. However for hardware the
1380          * comparison is strictly greater than.
1381          */
1382         seqno -= 1;
1383
1384         WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
1385
1386         ret = intel_ring_begin(waiter_req, 4);
1387         if (ret)
1388                 return ret;
1389
1390         /* If seqno wrap happened, omit the wait with no-ops */
1391         if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
1392                 intel_ring_emit(waiter, dw1 | wait_mbox);
1393                 intel_ring_emit(waiter, seqno);
1394                 intel_ring_emit(waiter, 0);
1395                 intel_ring_emit(waiter, MI_NOOP);
1396         } else {
1397                 intel_ring_emit(waiter, MI_NOOP);
1398                 intel_ring_emit(waiter, MI_NOOP);
1399                 intel_ring_emit(waiter, MI_NOOP);
1400                 intel_ring_emit(waiter, MI_NOOP);
1401         }
1402         intel_ring_advance(waiter);
1403
1404         return 0;
1405 }
1406
1407 #define PIPE_CONTROL_FLUSH(ring__, addr__)                                      \
1408 do {                                                                    \
1409         intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |                \
1410                  PIPE_CONTROL_DEPTH_STALL);                             \
1411         intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);                    \
1412         intel_ring_emit(ring__, 0);                                                     \
1413         intel_ring_emit(ring__, 0);                                                     \
1414 } while (0)
1415
1416 static int
1417 pc_render_add_request(struct drm_i915_gem_request *req)
1418 {
1419         struct intel_engine_cs *ring = req->ring;
1420         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1421         int ret;
1422
1423         /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1424          * incoherent with writes to memory, i.e. completely fubar,
1425          * so we need to use PIPE_NOTIFY instead.
1426          *
1427          * However, we also need to workaround the qword write
1428          * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1429          * memory before requesting an interrupt.
1430          */
1431         ret = intel_ring_begin(req, 32);
1432         if (ret)
1433                 return ret;
1434
1435         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1436                         PIPE_CONTROL_WRITE_FLUSH |
1437                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
1438         intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1439         intel_ring_emit(ring, i915_gem_request_get_seqno(req));
1440         intel_ring_emit(ring, 0);
1441         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1442         scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
1443         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1444         scratch_addr += 2 * CACHELINE_BYTES;
1445         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1446         scratch_addr += 2 * CACHELINE_BYTES;
1447         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1448         scratch_addr += 2 * CACHELINE_BYTES;
1449         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1450         scratch_addr += 2 * CACHELINE_BYTES;
1451         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1452
1453         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1454                         PIPE_CONTROL_WRITE_FLUSH |
1455                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
1456                         PIPE_CONTROL_NOTIFY);
1457         intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1458         intel_ring_emit(ring, i915_gem_request_get_seqno(req));
1459         intel_ring_emit(ring, 0);
1460         __intel_ring_advance(ring);
1461
1462         return 0;
1463 }
1464
1465 static u32
1466 gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1467 {
1468         /* Workaround to force correct ordering between irq and seqno writes on
1469          * ivb (and maybe also on snb) by reading from a CS register (like
1470          * ACTHD) before reading the status page. */
1471         if (!lazy_coherency) {
1472                 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1473                 POSTING_READ(RING_ACTHD(ring->mmio_base));
1474         }
1475
1476         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1477 }
1478
1479 static u32
1480 ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1481 {
1482         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1483 }
1484
1485 static void
1486 ring_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1487 {
1488         intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1489 }
1490
1491 static u32
1492 pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1493 {
1494         return ring->scratch.cpu_page[0];
1495 }
1496
1497 static void
1498 pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1499 {
1500         ring->scratch.cpu_page[0] = seqno;
1501 }
1502
1503 static bool
1504 gen5_ring_get_irq(struct intel_engine_cs *ring)
1505 {
1506         struct drm_device *dev = ring->dev;
1507         struct drm_i915_private *dev_priv = dev->dev_private;
1508         unsigned long flags;
1509
1510         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1511                 return false;
1512
1513         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1514         if (ring->irq_refcount++ == 0)
1515                 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1516         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1517
1518         return true;
1519 }
1520
1521 static void
1522 gen5_ring_put_irq(struct intel_engine_cs *ring)
1523 {
1524         struct drm_device *dev = ring->dev;
1525         struct drm_i915_private *dev_priv = dev->dev_private;
1526         unsigned long flags;
1527
1528         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1529         if (--ring->irq_refcount == 0)
1530                 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1531         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1532 }
1533
1534 static bool
1535 i9xx_ring_get_irq(struct intel_engine_cs *ring)
1536 {
1537         struct drm_device *dev = ring->dev;
1538         struct drm_i915_private *dev_priv = dev->dev_private;
1539         unsigned long flags;
1540
1541         if (!intel_irqs_enabled(dev_priv))
1542                 return false;
1543
1544         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1545         if (ring->irq_refcount++ == 0) {
1546                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1547                 I915_WRITE(IMR, dev_priv->irq_mask);
1548                 POSTING_READ(IMR);
1549         }
1550         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1551
1552         return true;
1553 }
1554
1555 static void
1556 i9xx_ring_put_irq(struct intel_engine_cs *ring)
1557 {
1558         struct drm_device *dev = ring->dev;
1559         struct drm_i915_private *dev_priv = dev->dev_private;
1560         unsigned long flags;
1561
1562         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1563         if (--ring->irq_refcount == 0) {
1564                 dev_priv->irq_mask |= ring->irq_enable_mask;
1565                 I915_WRITE(IMR, dev_priv->irq_mask);
1566                 POSTING_READ(IMR);
1567         }
1568         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1569 }
1570
1571 static bool
1572 i8xx_ring_get_irq(struct intel_engine_cs *ring)
1573 {
1574         struct drm_device *dev = ring->dev;
1575         struct drm_i915_private *dev_priv = dev->dev_private;
1576         unsigned long flags;
1577
1578         if (!intel_irqs_enabled(dev_priv))
1579                 return false;
1580
1581         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1582         if (ring->irq_refcount++ == 0) {
1583                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1584                 I915_WRITE16(IMR, dev_priv->irq_mask);
1585                 POSTING_READ16(IMR);
1586         }
1587         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1588
1589         return true;
1590 }
1591
1592 static void
1593 i8xx_ring_put_irq(struct intel_engine_cs *ring)
1594 {
1595         struct drm_device *dev = ring->dev;
1596         struct drm_i915_private *dev_priv = dev->dev_private;
1597         unsigned long flags;
1598
1599         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1600         if (--ring->irq_refcount == 0) {
1601                 dev_priv->irq_mask |= ring->irq_enable_mask;
1602                 I915_WRITE16(IMR, dev_priv->irq_mask);
1603                 POSTING_READ16(IMR);
1604         }
1605         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1606 }
1607
1608 static int
1609 bsd_ring_flush(struct drm_i915_gem_request *req,
1610                u32     invalidate_domains,
1611                u32     flush_domains)
1612 {
1613         struct intel_engine_cs *ring = req->ring;
1614         int ret;
1615
1616         ret = intel_ring_begin(req, 2);
1617         if (ret)
1618                 return ret;
1619
1620         intel_ring_emit(ring, MI_FLUSH);
1621         intel_ring_emit(ring, MI_NOOP);
1622         intel_ring_advance(ring);
1623         return 0;
1624 }
1625
1626 static int
1627 i9xx_add_request(struct drm_i915_gem_request *req)
1628 {
1629         struct intel_engine_cs *ring = req->ring;
1630         int ret;
1631
1632         ret = intel_ring_begin(req, 4);
1633         if (ret)
1634                 return ret;
1635
1636         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1637         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1638         intel_ring_emit(ring, i915_gem_request_get_seqno(req));
1639         intel_ring_emit(ring, MI_USER_INTERRUPT);
1640         __intel_ring_advance(ring);
1641
1642         return 0;
1643 }
1644
1645 static bool
1646 gen6_ring_get_irq(struct intel_engine_cs *ring)
1647 {
1648         struct drm_device *dev = ring->dev;
1649         struct drm_i915_private *dev_priv = dev->dev_private;
1650         unsigned long flags;
1651
1652         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1653                 return false;
1654
1655         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1656         if (ring->irq_refcount++ == 0) {
1657                 if (HAS_L3_DPF(dev) && ring->id == RCS)
1658                         I915_WRITE_IMR(ring,
1659                                        ~(ring->irq_enable_mask |
1660                                          GT_PARITY_ERROR(dev)));
1661                 else
1662                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1663                 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1664         }
1665         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1666
1667         return true;
1668 }
1669
1670 static void
1671 gen6_ring_put_irq(struct intel_engine_cs *ring)
1672 {
1673         struct drm_device *dev = ring->dev;
1674         struct drm_i915_private *dev_priv = dev->dev_private;
1675         unsigned long flags;
1676
1677         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1678         if (--ring->irq_refcount == 0) {
1679                 if (HAS_L3_DPF(dev) && ring->id == RCS)
1680                         I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1681                 else
1682                         I915_WRITE_IMR(ring, ~0);
1683                 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1684         }
1685         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1686 }
1687
1688 static bool
1689 hsw_vebox_get_irq(struct intel_engine_cs *ring)
1690 {
1691         struct drm_device *dev = ring->dev;
1692         struct drm_i915_private *dev_priv = dev->dev_private;
1693         unsigned long flags;
1694
1695         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1696                 return false;
1697
1698         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1699         if (ring->irq_refcount++ == 0) {
1700                 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1701                 gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask);
1702         }
1703         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1704
1705         return true;
1706 }
1707
1708 static void
1709 hsw_vebox_put_irq(struct intel_engine_cs *ring)
1710 {
1711         struct drm_device *dev = ring->dev;
1712         struct drm_i915_private *dev_priv = dev->dev_private;
1713         unsigned long flags;
1714
1715         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1716         if (--ring->irq_refcount == 0) {
1717                 I915_WRITE_IMR(ring, ~0);
1718                 gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask);
1719         }
1720         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1721 }
1722
1723 static bool
1724 gen8_ring_get_irq(struct intel_engine_cs *ring)
1725 {
1726         struct drm_device *dev = ring->dev;
1727         struct drm_i915_private *dev_priv = dev->dev_private;
1728         unsigned long flags;
1729
1730         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1731                 return false;
1732
1733         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1734         if (ring->irq_refcount++ == 0) {
1735                 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1736                         I915_WRITE_IMR(ring,
1737                                        ~(ring->irq_enable_mask |
1738                                          GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1739                 } else {
1740                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1741                 }
1742                 POSTING_READ(RING_IMR(ring->mmio_base));
1743         }
1744         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1745
1746         return true;
1747 }
1748
1749 static void
1750 gen8_ring_put_irq(struct intel_engine_cs *ring)
1751 {
1752         struct drm_device *dev = ring->dev;
1753         struct drm_i915_private *dev_priv = dev->dev_private;
1754         unsigned long flags;
1755
1756         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1757         if (--ring->irq_refcount == 0) {
1758                 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1759                         I915_WRITE_IMR(ring,
1760                                        ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1761                 } else {
1762                         I915_WRITE_IMR(ring, ~0);
1763                 }
1764                 POSTING_READ(RING_IMR(ring->mmio_base));
1765         }
1766         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1767 }
1768
1769 static int
1770 i965_dispatch_execbuffer(struct drm_i915_gem_request *req,
1771                          u64 offset, u32 length,
1772                          unsigned dispatch_flags)
1773 {
1774         struct intel_engine_cs *ring = req->ring;
1775         int ret;
1776
1777         ret = intel_ring_begin(req, 2);
1778         if (ret)
1779                 return ret;
1780
1781         intel_ring_emit(ring,
1782                         MI_BATCH_BUFFER_START |
1783                         MI_BATCH_GTT |
1784                         (dispatch_flags & I915_DISPATCH_SECURE ?
1785                          0 : MI_BATCH_NON_SECURE_I965));
1786         intel_ring_emit(ring, offset);
1787         intel_ring_advance(ring);
1788
1789         return 0;
1790 }
1791
1792 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1793 #define I830_BATCH_LIMIT (256*1024)
1794 #define I830_TLB_ENTRIES (2)
1795 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1796 static int
1797 i830_dispatch_execbuffer(struct drm_i915_gem_request *req,
1798                          u64 offset, u32 len,
1799                          unsigned dispatch_flags)
1800 {
1801         struct intel_engine_cs *ring = req->ring;
1802         u32 cs_offset = ring->scratch.gtt_offset;
1803         int ret;
1804
1805         ret = intel_ring_begin(req, 6);
1806         if (ret)
1807                 return ret;
1808
1809         /* Evict the invalid PTE TLBs */
1810         intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1811         intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1812         intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1813         intel_ring_emit(ring, cs_offset);
1814         intel_ring_emit(ring, 0xdeadbeef);
1815         intel_ring_emit(ring, MI_NOOP);
1816         intel_ring_advance(ring);
1817
1818         if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
1819                 if (len > I830_BATCH_LIMIT)
1820                         return -ENOSPC;
1821
1822                 ret = intel_ring_begin(req, 6 + 2);
1823                 if (ret)
1824                         return ret;
1825
1826                 /* Blit the batch (which has now all relocs applied) to the
1827                  * stable batch scratch bo area (so that the CS never
1828                  * stumbles over its tlb invalidation bug) ...
1829                  */
1830                 intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1831                 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
1832                 intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096);
1833                 intel_ring_emit(ring, cs_offset);
1834                 intel_ring_emit(ring, 4096);
1835                 intel_ring_emit(ring, offset);
1836
1837                 intel_ring_emit(ring, MI_FLUSH);
1838                 intel_ring_emit(ring, MI_NOOP);
1839                 intel_ring_advance(ring);
1840
1841                 /* ... and execute it. */
1842                 offset = cs_offset;
1843         }
1844
1845         ret = intel_ring_begin(req, 4);
1846         if (ret)
1847                 return ret;
1848
1849         intel_ring_emit(ring, MI_BATCH_BUFFER);
1850         intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1851                                         0 : MI_BATCH_NON_SECURE));
1852         intel_ring_emit(ring, offset + len - 8);
1853         intel_ring_emit(ring, MI_NOOP);
1854         intel_ring_advance(ring);
1855
1856         return 0;
1857 }
1858
1859 static int
1860 i915_dispatch_execbuffer(struct drm_i915_gem_request *req,
1861                          u64 offset, u32 len,
1862                          unsigned dispatch_flags)
1863 {
1864         struct intel_engine_cs *ring = req->ring;
1865         int ret;
1866
1867         ret = intel_ring_begin(req, 2);
1868         if (ret)
1869                 return ret;
1870
1871         intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1872         intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1873                                         0 : MI_BATCH_NON_SECURE));
1874         intel_ring_advance(ring);
1875
1876         return 0;
1877 }
1878
1879 static void cleanup_status_page(struct intel_engine_cs *ring)
1880 {
1881         struct drm_i915_gem_object *obj;
1882
1883         obj = ring->status_page.obj;
1884         if (obj == NULL)
1885                 return;
1886
1887         kunmap(sg_page(obj->pages->sgl));
1888         i915_gem_object_ggtt_unpin(obj);
1889         drm_gem_object_unreference(&obj->base);
1890         ring->status_page.obj = NULL;
1891 }
1892
1893 static int init_status_page(struct intel_engine_cs *ring)
1894 {
1895         struct drm_i915_gem_object *obj;
1896
1897         if ((obj = ring->status_page.obj) == NULL) {
1898                 unsigned flags;
1899                 int ret;
1900
1901                 obj = i915_gem_alloc_object(ring->dev, 4096);
1902                 if (obj == NULL) {
1903                         DRM_ERROR("Failed to allocate status page\n");
1904                         return -ENOMEM;
1905                 }
1906
1907                 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1908                 if (ret)
1909                         goto err_unref;
1910
1911                 flags = 0;
1912                 if (!HAS_LLC(ring->dev))
1913                         /* On g33, we cannot place HWS above 256MiB, so
1914                          * restrict its pinning to the low mappable arena.
1915                          * Though this restriction is not documented for
1916                          * gen4, gen5, or byt, they also behave similarly
1917                          * and hang if the HWS is placed at the top of the
1918                          * GTT. To generalise, it appears that all !llc
1919                          * platforms have issues with us placing the HWS
1920                          * above the mappable region (even though we never
1921                          * actualy map it).
1922                          */
1923                         flags |= PIN_MAPPABLE;
1924                 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
1925                 if (ret) {
1926 err_unref:
1927                         drm_gem_object_unreference(&obj->base);
1928                         return ret;
1929                 }
1930
1931                 ring->status_page.obj = obj;
1932         }
1933
1934         ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
1935         ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1936         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1937
1938         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1939                         ring->name, ring->status_page.gfx_addr);
1940
1941         return 0;
1942 }
1943
1944 static int init_phys_status_page(struct intel_engine_cs *ring)
1945 {
1946         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1947
1948         if (!dev_priv->status_page_dmah) {
1949                 dev_priv->status_page_dmah =
1950                         drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1951                 if (!dev_priv->status_page_dmah)
1952                         return -ENOMEM;
1953         }
1954
1955         ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1956         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1957
1958         return 0;
1959 }
1960
1961 void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1962 {
1963         iounmap(ringbuf->virtual_start);
1964         ringbuf->virtual_start = NULL;
1965         i915_gem_object_ggtt_unpin(ringbuf->obj);
1966 }
1967
1968 int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
1969                                      struct intel_ringbuffer *ringbuf)
1970 {
1971         struct drm_i915_private *dev_priv = to_i915(dev);
1972         struct drm_i915_gem_object *obj = ringbuf->obj;
1973         int ret;
1974
1975         ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
1976         if (ret)
1977                 return ret;
1978
1979         ret = i915_gem_object_set_to_gtt_domain(obj, true);
1980         if (ret) {
1981                 i915_gem_object_ggtt_unpin(obj);
1982                 return ret;
1983         }
1984
1985         ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base +
1986                         i915_gem_obj_ggtt_offset(obj), ringbuf->size);
1987         if (ringbuf->virtual_start == NULL) {
1988                 i915_gem_object_ggtt_unpin(obj);
1989                 return -EINVAL;
1990         }
1991
1992         return 0;
1993 }
1994
1995 static void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1996 {
1997         drm_gem_object_unreference(&ringbuf->obj->base);
1998         ringbuf->obj = NULL;
1999 }
2000
2001 static int intel_alloc_ringbuffer_obj(struct drm_device *dev,
2002                                       struct intel_ringbuffer *ringbuf)
2003 {
2004         struct drm_i915_gem_object *obj;
2005
2006         obj = NULL;
2007         if (!HAS_LLC(dev))
2008                 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
2009         if (obj == NULL)
2010                 obj = i915_gem_alloc_object(dev, ringbuf->size);
2011         if (obj == NULL)
2012                 return -ENOMEM;
2013
2014         /* mark ring buffers as read-only from GPU side by default */
2015         obj->gt_ro = 1;
2016
2017         ringbuf->obj = obj;
2018
2019         return 0;
2020 }
2021
2022 struct intel_ringbuffer *
2023 intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size)
2024 {
2025         struct intel_ringbuffer *ring;
2026         int ret;
2027
2028         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
2029         if (ring == NULL)
2030                 return ERR_PTR(-ENOMEM);
2031
2032         ring->ring = engine;
2033
2034         ring->size = size;
2035         /* Workaround an erratum on the i830 which causes a hang if
2036          * the TAIL pointer points to within the last 2 cachelines
2037          * of the buffer.
2038          */
2039         ring->effective_size = size;
2040         if (IS_I830(engine->dev) || IS_845G(engine->dev))
2041                 ring->effective_size -= 2 * CACHELINE_BYTES;
2042
2043         ring->last_retired_head = -1;
2044         intel_ring_update_space(ring);
2045
2046         ret = intel_alloc_ringbuffer_obj(engine->dev, ring);
2047         if (ret) {
2048                 DRM_ERROR("Failed to allocate ringbuffer %s: %d\n",
2049                           engine->name, ret);
2050                 kfree(ring);
2051                 return ERR_PTR(ret);
2052         }
2053
2054         return ring;
2055 }
2056
2057 void
2058 intel_ringbuffer_free(struct intel_ringbuffer *ring)
2059 {
2060         intel_destroy_ringbuffer_obj(ring);
2061         kfree(ring);
2062 }
2063
2064 static int intel_init_ring_buffer(struct drm_device *dev,
2065                                   struct intel_engine_cs *ring)
2066 {
2067         struct intel_ringbuffer *ringbuf;
2068         int ret;
2069
2070         WARN_ON(ring->buffer);
2071
2072         ring->dev = dev;
2073         INIT_LIST_HEAD(&ring->active_list);
2074         INIT_LIST_HEAD(&ring->request_list);
2075         INIT_LIST_HEAD(&ring->execlist_queue);
2076         i915_gem_batch_pool_init(dev, &ring->batch_pool);
2077         memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));
2078
2079         init_waitqueue_head(&ring->irq_queue);
2080
2081         ringbuf = intel_engine_create_ringbuffer(ring, 32 * PAGE_SIZE);
2082         if (IS_ERR(ringbuf))
2083                 return PTR_ERR(ringbuf);
2084         ring->buffer = ringbuf;
2085
2086         if (I915_NEED_GFX_HWS(dev)) {
2087                 ret = init_status_page(ring);
2088                 if (ret)
2089                         goto error;
2090         } else {
2091                 BUG_ON(ring->id != RCS);
2092                 ret = init_phys_status_page(ring);
2093                 if (ret)
2094                         goto error;
2095         }
2096
2097         ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
2098         if (ret) {
2099                 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
2100                                 ring->name, ret);
2101                 intel_destroy_ringbuffer_obj(ringbuf);
2102                 goto error;
2103         }
2104
2105         ret = i915_cmd_parser_init_ring(ring);
2106         if (ret)
2107                 goto error;
2108
2109         return 0;
2110
2111 error:
2112         intel_ringbuffer_free(ringbuf);
2113         ring->buffer = NULL;
2114         return ret;
2115 }
2116
2117 void intel_cleanup_ring_buffer(struct intel_engine_cs *ring)
2118 {
2119         struct drm_i915_private *dev_priv;
2120
2121         if (!intel_ring_initialized(ring))
2122                 return;
2123
2124         dev_priv = to_i915(ring->dev);
2125
2126         intel_stop_ring_buffer(ring);
2127         WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0);
2128
2129         intel_unpin_ringbuffer_obj(ring->buffer);
2130         intel_ringbuffer_free(ring->buffer);
2131         ring->buffer = NULL;
2132
2133         if (ring->cleanup)
2134                 ring->cleanup(ring);
2135
2136         cleanup_status_page(ring);
2137
2138         i915_cmd_parser_fini_ring(ring);
2139         i915_gem_batch_pool_fini(&ring->batch_pool);
2140 }
2141
2142 static int ring_wait_for_space(struct intel_engine_cs *ring, int n)
2143 {
2144         struct intel_ringbuffer *ringbuf = ring->buffer;
2145         struct drm_i915_gem_request *request;
2146         unsigned space;
2147         int ret;
2148
2149         if (intel_ring_space(ringbuf) >= n)
2150                 return 0;
2151
2152         /* The whole point of reserving space is to not wait! */
2153         WARN_ON(ringbuf->reserved_in_use);
2154
2155         list_for_each_entry(request, &ring->request_list, list) {
2156                 space = __intel_ring_space(request->postfix, ringbuf->tail,
2157                                            ringbuf->size);
2158                 if (space >= n)
2159                         break;
2160         }
2161
2162         if (WARN_ON(&request->list == &ring->request_list))
2163                 return -ENOSPC;
2164
2165         ret = i915_wait_request(request);
2166         if (ret)
2167                 return ret;
2168
2169         ringbuf->space = space;
2170         return 0;
2171 }
2172
2173 static void __wrap_ring_buffer(struct intel_ringbuffer *ringbuf)
2174 {
2175         uint32_t __iomem *virt;
2176         int rem = ringbuf->size - ringbuf->tail;
2177
2178         virt = ringbuf->virtual_start + ringbuf->tail;
2179         rem /= 4;
2180         while (rem--)
2181                 iowrite32(MI_NOOP, virt++);
2182
2183         ringbuf->tail = 0;
2184         intel_ring_update_space(ringbuf);
2185 }
2186
2187 int intel_ring_idle(struct intel_engine_cs *ring)
2188 {
2189         struct drm_i915_gem_request *req;
2190
2191         /* Wait upon the last request to be completed */
2192         if (list_empty(&ring->request_list))
2193                 return 0;
2194
2195         req = list_entry(ring->request_list.prev,
2196                         struct drm_i915_gem_request,
2197                         list);
2198
2199         /* Make sure we do not trigger any retires */
2200         return __i915_wait_request(req,
2201                                    atomic_read(&to_i915(ring->dev)->gpu_error.reset_counter),
2202                                    to_i915(ring->dev)->mm.interruptible,
2203                                    NULL, NULL);
2204 }
2205
2206 int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
2207 {
2208         request->ringbuf = request->ring->buffer;
2209         return 0;
2210 }
2211
2212 int intel_ring_reserve_space(struct drm_i915_gem_request *request)
2213 {
2214         /*
2215          * The first call merely notes the reserve request and is common for
2216          * all back ends. The subsequent localised _begin() call actually
2217          * ensures that the reservation is available. Without the begin, if
2218          * the request creator immediately submitted the request without
2219          * adding any commands to it then there might not actually be
2220          * sufficient room for the submission commands.
2221          */
2222         intel_ring_reserved_space_reserve(request->ringbuf, MIN_SPACE_FOR_ADD_REQUEST);
2223
2224         return intel_ring_begin(request, 0);
2225 }
2226
2227 void intel_ring_reserved_space_reserve(struct intel_ringbuffer *ringbuf, int size)
2228 {
2229         WARN_ON(ringbuf->reserved_size);
2230         WARN_ON(ringbuf->reserved_in_use);
2231
2232         ringbuf->reserved_size = size;
2233 }
2234
2235 void intel_ring_reserved_space_cancel(struct intel_ringbuffer *ringbuf)
2236 {
2237         WARN_ON(ringbuf->reserved_in_use);
2238
2239         ringbuf->reserved_size   = 0;
2240         ringbuf->reserved_in_use = false;
2241 }
2242
2243 void intel_ring_reserved_space_use(struct intel_ringbuffer *ringbuf)
2244 {
2245         WARN_ON(ringbuf->reserved_in_use);
2246
2247         ringbuf->reserved_in_use = true;
2248         ringbuf->reserved_tail   = ringbuf->tail;
2249 }
2250
2251 void intel_ring_reserved_space_end(struct intel_ringbuffer *ringbuf)
2252 {
2253         WARN_ON(!ringbuf->reserved_in_use);
2254         if (ringbuf->tail > ringbuf->reserved_tail) {
2255                 WARN(ringbuf->tail > ringbuf->reserved_tail + ringbuf->reserved_size,
2256                      "request reserved size too small: %d vs %d!\n",
2257                      ringbuf->tail - ringbuf->reserved_tail, ringbuf->reserved_size);
2258         } else {
2259                 /*
2260                  * The ring was wrapped while the reserved space was in use.
2261                  * That means that some unknown amount of the ring tail was
2262                  * no-op filled and skipped. Thus simply adding the ring size
2263                  * to the tail and doing the above space check will not work.
2264                  * Rather than attempt to track how much tail was skipped,
2265                  * it is much simpler to say that also skipping the sanity
2266                  * check every once in a while is not a big issue.
2267                  */
2268         }
2269
2270         ringbuf->reserved_size   = 0;
2271         ringbuf->reserved_in_use = false;
2272 }
2273
2274 static int __intel_ring_prepare(struct intel_engine_cs *ring, int bytes)
2275 {
2276         struct intel_ringbuffer *ringbuf = ring->buffer;
2277         int remain_usable = ringbuf->effective_size - ringbuf->tail;
2278         int remain_actual = ringbuf->size - ringbuf->tail;
2279         int ret, total_bytes, wait_bytes = 0;
2280         bool need_wrap = false;
2281
2282         if (ringbuf->reserved_in_use)
2283                 total_bytes = bytes;
2284         else
2285                 total_bytes = bytes + ringbuf->reserved_size;
2286
2287         if (unlikely(bytes > remain_usable)) {
2288                 /*
2289                  * Not enough space for the basic request. So need to flush
2290                  * out the remainder and then wait for base + reserved.
2291                  */
2292                 wait_bytes = remain_actual + total_bytes;
2293                 need_wrap = true;
2294         } else {
2295                 if (unlikely(total_bytes > remain_usable)) {
2296                         /*
2297                          * The base request will fit but the reserved space
2298                          * falls off the end. So only need to to wait for the
2299                          * reserved size after flushing out the remainder.
2300                          */
2301                         wait_bytes = remain_actual + ringbuf->reserved_size;
2302                         need_wrap = true;
2303                 } else if (total_bytes > ringbuf->space) {
2304                         /* No wrapping required, just waiting. */
2305                         wait_bytes = total_bytes;
2306                 }
2307         }
2308
2309         if (wait_bytes) {
2310                 ret = ring_wait_for_space(ring, wait_bytes);
2311                 if (unlikely(ret))
2312                         return ret;
2313
2314                 if (need_wrap)
2315                         __wrap_ring_buffer(ringbuf);
2316         }
2317
2318         return 0;
2319 }
2320
2321 int intel_ring_begin(struct drm_i915_gem_request *req,
2322                      int num_dwords)
2323 {
2324         struct intel_engine_cs *ring;
2325         struct drm_i915_private *dev_priv;
2326         int ret;
2327
2328         WARN_ON(req == NULL);
2329         ring = req->ring;
2330         dev_priv = ring->dev->dev_private;
2331
2332         ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2333                                    dev_priv->mm.interruptible);
2334         if (ret)
2335                 return ret;
2336
2337         ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
2338         if (ret)
2339                 return ret;
2340
2341         ring->buffer->space -= num_dwords * sizeof(uint32_t);
2342         return 0;
2343 }
2344
2345 /* Align the ring tail to a cacheline boundary */
2346 int intel_ring_cacheline_align(struct drm_i915_gem_request *req)
2347 {
2348         struct intel_engine_cs *ring = req->ring;
2349         int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
2350         int ret;
2351
2352         if (num_dwords == 0)
2353                 return 0;
2354
2355         num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
2356         ret = intel_ring_begin(req, num_dwords);
2357         if (ret)
2358                 return ret;
2359
2360         while (num_dwords--)
2361                 intel_ring_emit(ring, MI_NOOP);
2362
2363         intel_ring_advance(ring);
2364
2365         return 0;
2366 }
2367
2368 void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno)
2369 {
2370         struct drm_device *dev = ring->dev;
2371         struct drm_i915_private *dev_priv = dev->dev_private;
2372
2373         if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) {
2374                 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
2375                 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
2376                 if (HAS_VEBOX(dev))
2377                         I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
2378         }
2379
2380         ring->set_seqno(ring, seqno);
2381         ring->hangcheck.seqno = seqno;
2382 }
2383
2384 static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring,
2385                                      u32 value)
2386 {
2387         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2388
2389        /* Every tail move must follow the sequence below */
2390
2391         /* Disable notification that the ring is IDLE. The GT
2392          * will then assume that it is busy and bring it out of rc6.
2393          */
2394         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2395                    _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2396
2397         /* Clear the context id. Here be magic! */
2398         I915_WRITE64(GEN6_BSD_RNCID, 0x0);
2399
2400         /* Wait for the ring not to be idle, i.e. for it to wake up. */
2401         if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
2402                       GEN6_BSD_SLEEP_INDICATOR) == 0,
2403                      50))
2404                 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2405
2406         /* Now that the ring is fully powered up, update the tail */
2407         I915_WRITE_TAIL(ring, value);
2408         POSTING_READ(RING_TAIL(ring->mmio_base));
2409
2410         /* Let the ring send IDLE messages to the GT again,
2411          * and so let it sleep to conserve power when idle.
2412          */
2413         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2414                    _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2415 }
2416
2417 static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
2418                                u32 invalidate, u32 flush)
2419 {
2420         struct intel_engine_cs *ring = req->ring;
2421         uint32_t cmd;
2422         int ret;
2423
2424         ret = intel_ring_begin(req, 4);
2425         if (ret)
2426                 return ret;
2427
2428         cmd = MI_FLUSH_DW;
2429         if (INTEL_INFO(ring->dev)->gen >= 8)
2430                 cmd += 1;
2431
2432         /* We always require a command barrier so that subsequent
2433          * commands, such as breadcrumb interrupts, are strictly ordered
2434          * wrt the contents of the write cache being flushed to memory
2435          * (and thus being coherent from the CPU).
2436          */
2437         cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2438
2439         /*
2440          * Bspec vol 1c.5 - video engine command streamer:
2441          * "If ENABLED, all TLBs will be invalidated once the flush
2442          * operation is complete. This bit is only valid when the
2443          * Post-Sync Operation field is a value of 1h or 3h."
2444          */
2445         if (invalidate & I915_GEM_GPU_DOMAINS)
2446                 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
2447
2448         intel_ring_emit(ring, cmd);
2449         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2450         if (INTEL_INFO(ring->dev)->gen >= 8) {
2451                 intel_ring_emit(ring, 0); /* upper addr */
2452                 intel_ring_emit(ring, 0); /* value */
2453         } else  {
2454                 intel_ring_emit(ring, 0);
2455                 intel_ring_emit(ring, MI_NOOP);
2456         }
2457         intel_ring_advance(ring);
2458         return 0;
2459 }
2460
2461 static int
2462 gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2463                               u64 offset, u32 len,
2464                               unsigned dispatch_flags)
2465 {
2466         struct intel_engine_cs *ring = req->ring;
2467         bool ppgtt = USES_PPGTT(ring->dev) &&
2468                         !(dispatch_flags & I915_DISPATCH_SECURE);
2469         int ret;
2470
2471         ret = intel_ring_begin(req, 4);
2472         if (ret)
2473                 return ret;
2474
2475         /* FIXME(BDW): Address space and security selectors. */
2476         intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) |
2477                         (dispatch_flags & I915_DISPATCH_RS ?
2478                          MI_BATCH_RESOURCE_STREAMER : 0));
2479         intel_ring_emit(ring, lower_32_bits(offset));
2480         intel_ring_emit(ring, upper_32_bits(offset));
2481         intel_ring_emit(ring, MI_NOOP);
2482         intel_ring_advance(ring);
2483
2484         return 0;
2485 }
2486
2487 static int
2488 hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2489                              u64 offset, u32 len,
2490                              unsigned dispatch_flags)
2491 {
2492         struct intel_engine_cs *ring = req->ring;
2493         int ret;
2494
2495         ret = intel_ring_begin(req, 2);
2496         if (ret)
2497                 return ret;
2498
2499         intel_ring_emit(ring,
2500                         MI_BATCH_BUFFER_START |
2501                         (dispatch_flags & I915_DISPATCH_SECURE ?
2502                          0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) |
2503                         (dispatch_flags & I915_DISPATCH_RS ?
2504                          MI_BATCH_RESOURCE_STREAMER : 0));
2505         /* bit0-7 is the length on GEN6+ */
2506         intel_ring_emit(ring, offset);
2507         intel_ring_advance(ring);
2508
2509         return 0;
2510 }
2511
2512 static int
2513 gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2514                               u64 offset, u32 len,
2515                               unsigned dispatch_flags)
2516 {
2517         struct intel_engine_cs *ring = req->ring;
2518         int ret;
2519
2520         ret = intel_ring_begin(req, 2);
2521         if (ret)
2522                 return ret;
2523
2524         intel_ring_emit(ring,
2525                         MI_BATCH_BUFFER_START |
2526                         (dispatch_flags & I915_DISPATCH_SECURE ?
2527                          0 : MI_BATCH_NON_SECURE_I965));
2528         /* bit0-7 is the length on GEN6+ */
2529         intel_ring_emit(ring, offset);
2530         intel_ring_advance(ring);
2531
2532         return 0;
2533 }
2534
2535 /* Blitter support (SandyBridge+) */
2536
2537 static int gen6_ring_flush(struct drm_i915_gem_request *req,
2538                            u32 invalidate, u32 flush)
2539 {
2540         struct intel_engine_cs *ring = req->ring;
2541         struct drm_device *dev = ring->dev;
2542         uint32_t cmd;
2543         int ret;
2544
2545         ret = intel_ring_begin(req, 4);
2546         if (ret)
2547                 return ret;
2548
2549         cmd = MI_FLUSH_DW;
2550         if (INTEL_INFO(dev)->gen >= 8)
2551                 cmd += 1;
2552
2553         /* We always require a command barrier so that subsequent
2554          * commands, such as breadcrumb interrupts, are strictly ordered
2555          * wrt the contents of the write cache being flushed to memory
2556          * (and thus being coherent from the CPU).
2557          */
2558         cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2559
2560         /*
2561          * Bspec vol 1c.3 - blitter engine command streamer:
2562          * "If ENABLED, all TLBs will be invalidated once the flush
2563          * operation is complete. This bit is only valid when the
2564          * Post-Sync Operation field is a value of 1h or 3h."
2565          */
2566         if (invalidate & I915_GEM_DOMAIN_RENDER)
2567                 cmd |= MI_INVALIDATE_TLB;
2568         intel_ring_emit(ring, cmd);
2569         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2570         if (INTEL_INFO(dev)->gen >= 8) {
2571                 intel_ring_emit(ring, 0); /* upper addr */
2572                 intel_ring_emit(ring, 0); /* value */
2573         } else  {
2574                 intel_ring_emit(ring, 0);
2575                 intel_ring_emit(ring, MI_NOOP);
2576         }
2577         intel_ring_advance(ring);
2578
2579         return 0;
2580 }
2581
2582 int intel_init_render_ring_buffer(struct drm_device *dev)
2583 {
2584         struct drm_i915_private *dev_priv = dev->dev_private;
2585         struct intel_engine_cs *ring = &dev_priv->ring[RCS];
2586         struct drm_i915_gem_object *obj;
2587         int ret;
2588
2589         ring->name = "render ring";
2590         ring->id = RCS;
2591         ring->mmio_base = RENDER_RING_BASE;
2592
2593         if (INTEL_INFO(dev)->gen >= 8) {
2594                 if (i915_semaphore_is_enabled(dev)) {
2595                         obj = i915_gem_alloc_object(dev, 4096);
2596                         if (obj == NULL) {
2597                                 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2598                                 i915.semaphores = 0;
2599                         } else {
2600                                 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2601                                 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2602                                 if (ret != 0) {
2603                                         drm_gem_object_unreference(&obj->base);
2604                                         DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2605                                         i915.semaphores = 0;
2606                                 } else
2607                                         dev_priv->semaphore_obj = obj;
2608                         }
2609                 }
2610
2611                 ring->init_context = intel_rcs_ctx_init;
2612                 ring->add_request = gen6_add_request;
2613                 ring->flush = gen8_render_ring_flush;
2614                 ring->irq_get = gen8_ring_get_irq;
2615                 ring->irq_put = gen8_ring_put_irq;
2616                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2617                 ring->get_seqno = gen6_ring_get_seqno;
2618                 ring->set_seqno = ring_set_seqno;
2619                 if (i915_semaphore_is_enabled(dev)) {
2620                         WARN_ON(!dev_priv->semaphore_obj);
2621                         ring->semaphore.sync_to = gen8_ring_sync;
2622                         ring->semaphore.signal = gen8_rcs_signal;
2623                         GEN8_RING_SEMAPHORE_INIT;
2624                 }
2625         } else if (INTEL_INFO(dev)->gen >= 6) {
2626                 ring->init_context = i915_gem_render_state_init;
2627                 ring->add_request = gen6_add_request;
2628                 ring->flush = gen7_render_ring_flush;
2629                 if (INTEL_INFO(dev)->gen == 6)
2630                         ring->flush = gen6_render_ring_flush;
2631                 ring->irq_get = gen6_ring_get_irq;
2632                 ring->irq_put = gen6_ring_put_irq;
2633                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2634                 ring->get_seqno = gen6_ring_get_seqno;
2635                 ring->set_seqno = ring_set_seqno;
2636                 if (i915_semaphore_is_enabled(dev)) {
2637                         ring->semaphore.sync_to = gen6_ring_sync;
2638                         ring->semaphore.signal = gen6_signal;
2639                         /*
2640                          * The current semaphore is only applied on pre-gen8
2641                          * platform.  And there is no VCS2 ring on the pre-gen8
2642                          * platform. So the semaphore between RCS and VCS2 is
2643                          * initialized as INVALID.  Gen8 will initialize the
2644                          * sema between VCS2 and RCS later.
2645                          */
2646                         ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2647                         ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2648                         ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2649                         ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2650                         ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2651                         ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2652                         ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2653                         ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2654                         ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2655                         ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2656                 }
2657         } else if (IS_GEN5(dev)) {
2658                 ring->add_request = pc_render_add_request;
2659                 ring->flush = gen4_render_ring_flush;
2660                 ring->get_seqno = pc_render_get_seqno;
2661                 ring->set_seqno = pc_render_set_seqno;
2662                 ring->irq_get = gen5_ring_get_irq;
2663                 ring->irq_put = gen5_ring_put_irq;
2664                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2665                                         GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
2666         } else {
2667                 ring->add_request = i9xx_add_request;
2668                 if (INTEL_INFO(dev)->gen < 4)
2669                         ring->flush = gen2_render_ring_flush;
2670                 else
2671                         ring->flush = gen4_render_ring_flush;
2672                 ring->get_seqno = ring_get_seqno;
2673                 ring->set_seqno = ring_set_seqno;
2674                 if (IS_GEN2(dev)) {
2675                         ring->irq_get = i8xx_ring_get_irq;
2676                         ring->irq_put = i8xx_ring_put_irq;
2677                 } else {
2678                         ring->irq_get = i9xx_ring_get_irq;
2679                         ring->irq_put = i9xx_ring_put_irq;
2680                 }
2681                 ring->irq_enable_mask = I915_USER_INTERRUPT;
2682         }
2683         ring->write_tail = ring_write_tail;
2684
2685         if (IS_HASWELL(dev))
2686                 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
2687         else if (IS_GEN8(dev))
2688                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2689         else if (INTEL_INFO(dev)->gen >= 6)
2690                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2691         else if (INTEL_INFO(dev)->gen >= 4)
2692                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2693         else if (IS_I830(dev) || IS_845G(dev))
2694                 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2695         else
2696                 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
2697         ring->init_hw = init_render_ring;
2698         ring->cleanup = render_ring_cleanup;
2699
2700         /* Workaround batchbuffer to combat CS tlb bug. */
2701         if (HAS_BROKEN_CS_TLB(dev)) {
2702                 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
2703                 if (obj == NULL) {
2704                         DRM_ERROR("Failed to allocate batch bo\n");
2705                         return -ENOMEM;
2706                 }
2707
2708                 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
2709                 if (ret != 0) {
2710                         drm_gem_object_unreference(&obj->base);
2711                         DRM_ERROR("Failed to ping batch bo\n");
2712                         return ret;
2713                 }
2714
2715                 ring->scratch.obj = obj;
2716                 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
2717         }
2718
2719         ret = intel_init_ring_buffer(dev, ring);
2720         if (ret)
2721                 return ret;
2722
2723         if (INTEL_INFO(dev)->gen >= 5) {
2724                 ret = intel_init_pipe_control(ring);
2725                 if (ret)
2726                         return ret;
2727         }
2728
2729         return 0;
2730 }
2731
2732 int intel_init_bsd_ring_buffer(struct drm_device *dev)
2733 {
2734         struct drm_i915_private *dev_priv = dev->dev_private;
2735         struct intel_engine_cs *ring = &dev_priv->ring[VCS];
2736
2737         ring->name = "bsd ring";
2738         ring->id = VCS;
2739
2740         ring->write_tail = ring_write_tail;
2741         if (INTEL_INFO(dev)->gen >= 6) {
2742                 ring->mmio_base = GEN6_BSD_RING_BASE;
2743                 /* gen6 bsd needs a special wa for tail updates */
2744                 if (IS_GEN6(dev))
2745                         ring->write_tail = gen6_bsd_ring_write_tail;
2746                 ring->flush = gen6_bsd_ring_flush;
2747                 ring->add_request = gen6_add_request;
2748                 ring->get_seqno = gen6_ring_get_seqno;
2749                 ring->set_seqno = ring_set_seqno;
2750                 if (INTEL_INFO(dev)->gen >= 8) {
2751                         ring->irq_enable_mask =
2752                                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2753                         ring->irq_get = gen8_ring_get_irq;
2754                         ring->irq_put = gen8_ring_put_irq;
2755                         ring->dispatch_execbuffer =
2756                                 gen8_ring_dispatch_execbuffer;
2757                         if (i915_semaphore_is_enabled(dev)) {
2758                                 ring->semaphore.sync_to = gen8_ring_sync;
2759                                 ring->semaphore.signal = gen8_xcs_signal;
2760                                 GEN8_RING_SEMAPHORE_INIT;
2761                         }
2762                 } else {
2763                         ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2764                         ring->irq_get = gen6_ring_get_irq;
2765                         ring->irq_put = gen6_ring_put_irq;
2766                         ring->dispatch_execbuffer =
2767                                 gen6_ring_dispatch_execbuffer;
2768                         if (i915_semaphore_is_enabled(dev)) {
2769                                 ring->semaphore.sync_to = gen6_ring_sync;
2770                                 ring->semaphore.signal = gen6_signal;
2771                                 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2772                                 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2773                                 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2774                                 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2775                                 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2776                                 ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2777                                 ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2778                                 ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2779                                 ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2780                                 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2781                         }
2782                 }
2783         } else {
2784                 ring->mmio_base = BSD_RING_BASE;
2785                 ring->flush = bsd_ring_flush;
2786                 ring->add_request = i9xx_add_request;
2787                 ring->get_seqno = ring_get_seqno;
2788                 ring->set_seqno = ring_set_seqno;
2789                 if (IS_GEN5(dev)) {
2790                         ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2791                         ring->irq_get = gen5_ring_get_irq;
2792                         ring->irq_put = gen5_ring_put_irq;
2793                 } else {
2794                         ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2795                         ring->irq_get = i9xx_ring_get_irq;
2796                         ring->irq_put = i9xx_ring_put_irq;
2797                 }
2798                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2799         }
2800         ring->init_hw = init_ring_common;
2801
2802         return intel_init_ring_buffer(dev, ring);
2803 }
2804
2805 /**
2806  * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
2807  */
2808 int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2809 {
2810         struct drm_i915_private *dev_priv = dev->dev_private;
2811         struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
2812
2813         ring->name = "bsd2 ring";
2814         ring->id = VCS2;
2815
2816         ring->write_tail = ring_write_tail;
2817         ring->mmio_base = GEN8_BSD2_RING_BASE;
2818         ring->flush = gen6_bsd_ring_flush;
2819         ring->add_request = gen6_add_request;
2820         ring->get_seqno = gen6_ring_get_seqno;
2821         ring->set_seqno = ring_set_seqno;
2822         ring->irq_enable_mask =
2823                         GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2824         ring->irq_get = gen8_ring_get_irq;
2825         ring->irq_put = gen8_ring_put_irq;
2826         ring->dispatch_execbuffer =
2827                         gen8_ring_dispatch_execbuffer;
2828         if (i915_semaphore_is_enabled(dev)) {
2829                 ring->semaphore.sync_to = gen8_ring_sync;
2830                 ring->semaphore.signal = gen8_xcs_signal;
2831                 GEN8_RING_SEMAPHORE_INIT;
2832         }
2833         ring->init_hw = init_ring_common;
2834
2835         return intel_init_ring_buffer(dev, ring);
2836 }
2837
2838 int intel_init_blt_ring_buffer(struct drm_device *dev)
2839 {
2840         struct drm_i915_private *dev_priv = dev->dev_private;
2841         struct intel_engine_cs *ring = &dev_priv->ring[BCS];
2842
2843         ring->name = "blitter ring";
2844         ring->id = BCS;
2845
2846         ring->mmio_base = BLT_RING_BASE;
2847         ring->write_tail = ring_write_tail;
2848         ring->flush = gen6_ring_flush;
2849         ring->add_request = gen6_add_request;
2850         ring->get_seqno = gen6_ring_get_seqno;
2851         ring->set_seqno = ring_set_seqno;
2852         if (INTEL_INFO(dev)->gen >= 8) {
2853                 ring->irq_enable_mask =
2854                         GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2855                 ring->irq_get = gen8_ring_get_irq;
2856                 ring->irq_put = gen8_ring_put_irq;
2857                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2858                 if (i915_semaphore_is_enabled(dev)) {
2859                         ring->semaphore.sync_to = gen8_ring_sync;
2860                         ring->semaphore.signal = gen8_xcs_signal;
2861                         GEN8_RING_SEMAPHORE_INIT;
2862                 }
2863         } else {
2864                 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2865                 ring->irq_get = gen6_ring_get_irq;
2866                 ring->irq_put = gen6_ring_put_irq;
2867                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2868                 if (i915_semaphore_is_enabled(dev)) {
2869                         ring->semaphore.signal = gen6_signal;
2870                         ring->semaphore.sync_to = gen6_ring_sync;
2871                         /*
2872                          * The current semaphore is only applied on pre-gen8
2873                          * platform.  And there is no VCS2 ring on the pre-gen8
2874                          * platform. So the semaphore between BCS and VCS2 is
2875                          * initialized as INVALID.  Gen8 will initialize the
2876                          * sema between BCS and VCS2 later.
2877                          */
2878                         ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
2879                         ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
2880                         ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2881                         ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
2882                         ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2883                         ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
2884                         ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
2885                         ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
2886                         ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
2887                         ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2888                 }
2889         }
2890         ring->init_hw = init_ring_common;
2891
2892         return intel_init_ring_buffer(dev, ring);
2893 }
2894
2895 int intel_init_vebox_ring_buffer(struct drm_device *dev)
2896 {
2897         struct drm_i915_private *dev_priv = dev->dev_private;
2898         struct intel_engine_cs *ring = &dev_priv->ring[VECS];
2899
2900         ring->name = "video enhancement ring";
2901         ring->id = VECS;
2902
2903         ring->mmio_base = VEBOX_RING_BASE;
2904         ring->write_tail = ring_write_tail;
2905         ring->flush = gen6_ring_flush;
2906         ring->add_request = gen6_add_request;
2907         ring->get_seqno = gen6_ring_get_seqno;
2908         ring->set_seqno = ring_set_seqno;
2909
2910         if (INTEL_INFO(dev)->gen >= 8) {
2911                 ring->irq_enable_mask =
2912                         GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
2913                 ring->irq_get = gen8_ring_get_irq;
2914                 ring->irq_put = gen8_ring_put_irq;
2915                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2916                 if (i915_semaphore_is_enabled(dev)) {
2917                         ring->semaphore.sync_to = gen8_ring_sync;
2918                         ring->semaphore.signal = gen8_xcs_signal;
2919                         GEN8_RING_SEMAPHORE_INIT;
2920                 }
2921         } else {
2922                 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2923                 ring->irq_get = hsw_vebox_get_irq;
2924                 ring->irq_put = hsw_vebox_put_irq;
2925                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2926                 if (i915_semaphore_is_enabled(dev)) {
2927                         ring->semaphore.sync_to = gen6_ring_sync;
2928                         ring->semaphore.signal = gen6_signal;
2929                         ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
2930                         ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
2931                         ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
2932                         ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2933                         ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2934                         ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
2935                         ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
2936                         ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
2937                         ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
2938                         ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2939                 }
2940         }
2941         ring->init_hw = init_ring_common;
2942
2943         return intel_init_ring_buffer(dev, ring);
2944 }
2945
2946 int
2947 intel_ring_flush_all_caches(struct drm_i915_gem_request *req)
2948 {
2949         struct intel_engine_cs *ring = req->ring;
2950         int ret;
2951
2952         if (!ring->gpu_caches_dirty)
2953                 return 0;
2954
2955         ret = ring->flush(req, 0, I915_GEM_GPU_DOMAINS);
2956         if (ret)
2957                 return ret;
2958
2959         trace_i915_gem_ring_flush(req, 0, I915_GEM_GPU_DOMAINS);
2960
2961         ring->gpu_caches_dirty = false;
2962         return 0;
2963 }
2964
2965 int
2966 intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
2967 {
2968         struct intel_engine_cs *ring = req->ring;
2969         uint32_t flush_domains;
2970         int ret;
2971
2972         flush_domains = 0;
2973         if (ring->gpu_caches_dirty)
2974                 flush_domains = I915_GEM_GPU_DOMAINS;
2975
2976         ret = ring->flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
2977         if (ret)
2978                 return ret;
2979
2980         trace_i915_gem_ring_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
2981
2982         ring->gpu_caches_dirty = false;
2983         return 0;
2984 }
2985
2986 void
2987 intel_stop_ring_buffer(struct intel_engine_cs *ring)
2988 {
2989         int ret;
2990
2991         if (!intel_ring_initialized(ring))
2992                 return;
2993
2994         ret = intel_ring_idle(ring);
2995         if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
2996                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
2997                           ring->name, ret);
2998
2999         stop_ring(ring);
3000 }