drivers/gpu/drm/i915/intel_psr.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * DOC: Panel Self Refresh (PSR/SRD)
  26  *
  27  * Since Haswell Display controller supports Panel Self-Refresh on display
  28  * panels witch have a remote frame buffer (RFB) implemented according to PSR
  29  * spec in eDP1.3. PSR feature allows the display to go to lower standby states
  30  * when system is idle but display is on as it eliminates display refresh
  31  * request to DDR memory completely as long as the frame buffer for that
  32  * display is unchanged.
  33  *
  34  * Panel Self Refresh must be supported by both Hardware (source) and
  35  * Panel (sink).
  36  *
  37  * PSR saves power by caching the framebuffer in the panel RFB, which allows us
  38  * to power down the link and memory controller. For DSI panels the same idea
  39  * is called "manual mode".
  40  *
  41  * The implementation uses the hardware-based PSR support which automatically
  42  * enters/exits self-refresh mode. The hardware takes care of sending the
  43  * required DP aux message and could even retrain the link (that part isn't
  44  * enabled yet though). The hardware also keeps track of any frontbuffer
  45  * changes to know when to exit self-refresh mode again. Unfortunately that
  46  * part doesn't work too well, hence why the i915 PSR support uses the
  47  * software frontbuffer tracking to make sure it doesn't miss a screen
  48  * update. For this integration intel_psr_invalidate() and intel_psr_flush()
  49  * get called by the frontbuffer tracking code. Note that because of locking
  50  * issues the self-refresh re-enable code is done from a work queue, which
  51  * must be correctly synchronized/cancelled when shutting down the pipe."
  52  */
  53
  54 #include <drm/drmP.h>
  55
  56 #include "intel_drv.h"
  57 #include "i915_drv.h"
  58
  59 void intel_psr_irq_control(struct drm_i915_private *dev_priv, bool debug)
  60 {
  61         u32 debug_mask, mask;
  62
  63         mask = EDP_PSR_ERROR(TRANSCODER_EDP);
  64         debug_mask = EDP_PSR_POST_EXIT(TRANSCODER_EDP) |
  65                      EDP_PSR_PRE_ENTRY(TRANSCODER_EDP);
  66
  67         if (INTEL_GEN(dev_priv) >= 8) {
  68                 mask |= EDP_PSR_ERROR(TRANSCODER_A) |
  69                         EDP_PSR_ERROR(TRANSCODER_B) |
  70                         EDP_PSR_ERROR(TRANSCODER_C);
  71
  72                 debug_mask |= EDP_PSR_POST_EXIT(TRANSCODER_A) |
  73                               EDP_PSR_PRE_ENTRY(TRANSCODER_A) |
  74                               EDP_PSR_POST_EXIT(TRANSCODER_B) |
  75                               EDP_PSR_PRE_ENTRY(TRANSCODER_B) |
  76                               EDP_PSR_POST_EXIT(TRANSCODER_C) |
  77                               EDP_PSR_PRE_ENTRY(TRANSCODER_C);
  78         }
  79
  80         if (debug)
  81                 mask |= debug_mask;
  82
  83         WRITE_ONCE(dev_priv->psr.debug, debug);
  84         I915_WRITE(EDP_PSR_IMR, ~mask);
  85 }
  86
  87 static void psr_event_print(u32 val, bool psr2_enabled)
  88 {
  89         DRM_DEBUG_KMS("PSR exit events: 0x%x\n", val);
  90         if (val & PSR_EVENT_PSR2_WD_TIMER_EXPIRE)
  91                 DRM_DEBUG_KMS("\tPSR2 watchdog timer expired\n");
  92         if ((val & PSR_EVENT_PSR2_DISABLED) && psr2_enabled)
  93                 DRM_DEBUG_KMS("\tPSR2 disabled\n");
  94         if (val & PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN)
  95                 DRM_DEBUG_KMS("\tSU dirty FIFO underrun\n");
  96         if (val & PSR_EVENT_SU_CRC_FIFO_UNDERRUN)
  97                 DRM_DEBUG_KMS("\tSU CRC FIFO underrun\n");
  98         if (val & PSR_EVENT_GRAPHICS_RESET)
  99                 DRM_DEBUG_KMS("\tGraphics reset\n");
 100         if (val & PSR_EVENT_PCH_INTERRUPT)
 101                 DRM_DEBUG_KMS("\tPCH interrupt\n");
 102         if (val & PSR_EVENT_MEMORY_UP)
 103                 DRM_DEBUG_KMS("\tMemory up\n");
 104         if (val & PSR_EVENT_FRONT_BUFFER_MODIFY)
 105                 DRM_DEBUG_KMS("\tFront buffer modification\n");
 106         if (val & PSR_EVENT_WD_TIMER_EXPIRE)
 107                 DRM_DEBUG_KMS("\tPSR watchdog timer expired\n");
 108         if (val & PSR_EVENT_PIPE_REGISTERS_UPDATE)
 109                 DRM_DEBUG_KMS("\tPIPE registers updated\n");
 110         if (val & PSR_EVENT_REGISTER_UPDATE)
 111                 DRM_DEBUG_KMS("\tRegister updated\n");
 112         if (val & PSR_EVENT_HDCP_ENABLE)
 113                 DRM_DEBUG_KMS("\tHDCP enabled\n");
 114         if (val & PSR_EVENT_KVMR_SESSION_ENABLE)
 115                 DRM_DEBUG_KMS("\tKVMR session enabled\n");
 116         if (val & PSR_EVENT_VBI_ENABLE)
 117                 DRM_DEBUG_KMS("\tVBI enabled\n");
 118         if (val & PSR_EVENT_LPSP_MODE_EXIT)
 119                 DRM_DEBUG_KMS("\tLPSP mode exited\n");
 120         if ((val & PSR_EVENT_PSR_DISABLE) && !psr2_enabled)
 121                 DRM_DEBUG_KMS("\tPSR disabled\n");
 122 }
 123
 124 void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir)
 125 {
 126         u32 transcoders = BIT(TRANSCODER_EDP);
 127         enum transcoder cpu_transcoder;
 128         ktime_t time_ns =  ktime_get();
 129
 130         if (INTEL_GEN(dev_priv) >= 8)
 131                 transcoders |= BIT(TRANSCODER_A) |
 132                                BIT(TRANSCODER_B) |
 133                                BIT(TRANSCODER_C);
 134
 135         for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
 136                 /* FIXME: Exit PSR and link train manually when this happens. */
 137                 if (psr_iir & EDP_PSR_ERROR(cpu_transcoder))
 138                         DRM_DEBUG_KMS("[transcoder %s] PSR aux error\n",
 139                                       transcoder_name(cpu_transcoder));
 140
 141                 if (psr_iir & EDP_PSR_PRE_ENTRY(cpu_transcoder)) {
 142                         dev_priv->psr.last_entry_attempt = time_ns;
 143                         DRM_DEBUG_KMS("[transcoder %s] PSR entry attempt in 2 vblanks\n",
 144                                       transcoder_name(cpu_transcoder));
 145                 }
 146
 147                 if (psr_iir & EDP_PSR_POST_EXIT(cpu_transcoder)) {
 148                         dev_priv->psr.last_exit = time_ns;
 149                         DRM_DEBUG_KMS("[transcoder %s] PSR exit completed\n",
 150                                       transcoder_name(cpu_transcoder));
 151
 152                         if (INTEL_GEN(dev_priv) >= 9) {
 153                                 u32 val = I915_READ(PSR_EVENT(cpu_transcoder));
 154                                 bool psr2_enabled = dev_priv->psr.psr2_enabled;
 155
 156                                 I915_WRITE(PSR_EVENT(cpu_transcoder), val);
 157                                 psr_event_print(val, psr2_enabled);
 158                         }
 159                 }
 160         }
 161 }
 162
 163 static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
 164 {
 165         uint8_t dprx = 0;
 166
 167         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
 168                               &dprx) != 1)
 169                 return false;
 170         return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
 171 }
 172
 173 static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp)
 174 {
 175         uint8_t alpm_caps = 0;
 176
 177         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP,
 178                               &alpm_caps) != 1)
 179                 return false;
 180         return alpm_caps & DP_ALPM_CAP;
 181 }
 182
 183 static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp)
 184 {
 185         u8 val = 8; /* assume the worst if we can't read the value */
 186
 187         if (drm_dp_dpcd_readb(&intel_dp->aux,
 188                               DP_SYNCHRONIZATION_LATENCY_IN_SINK, &val) == 1)
 189                 val &= DP_MAX_RESYNC_FRAME_COUNT_MASK;
 190         else
 191                 DRM_DEBUG_KMS("Unable to get sink synchronization latency, assuming 8 frames\n");
 192         return val;
 193 }
 194
 195 void intel_psr_init_dpcd(struct intel_dp *intel_dp)
 196 {
 197         struct drm_i915_private *dev_priv =
 198                 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
 199
 200         drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd,
 201                          sizeof(intel_dp->psr_dpcd));
 202
 203         if (!intel_dp->psr_dpcd[0])
 204                 return;
 205         DRM_DEBUG_KMS("eDP panel supports PSR version %x\n",
 206                       intel_dp->psr_dpcd[0]);
 207
 208         if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) {
 209                 DRM_DEBUG_KMS("Panel lacks power state control, PSR cannot be enabled\n");
 210                 return;
 211         }
 212         dev_priv->psr.sink_support = true;
 213         dev_priv->psr.sink_sync_latency =
 214                 intel_dp_get_sink_sync_latency(intel_dp);
 215
 216         if (INTEL_GEN(dev_priv) >= 9 &&
 217             (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) {
 218                 bool y_req = intel_dp->psr_dpcd[1] &
 219                              DP_PSR2_SU_Y_COORDINATE_REQUIRED;
 220                 bool alpm = intel_dp_get_alpm_status(intel_dp);
 221
 222                 /*
 223                  * All panels that supports PSR version 03h (PSR2 +
 224                  * Y-coordinate) can handle Y-coordinates in VSC but we are
 225                  * only sure that it is going to be used when required by the
 226                  * panel. This way panel is capable to do selective update
 227                  * without a aux frame sync.
 228                  *
 229                  * To support PSR version 02h and PSR version 03h without
 230                  * Y-coordinate requirement panels we would need to enable
 231                  * GTC first.
 232                  */
 233                 dev_priv->psr.sink_psr2_support = y_req && alpm;
 234                 DRM_DEBUG_KMS("PSR2 %ssupported\n",
 235                               dev_priv->psr.sink_psr2_support ? "" : "not ");
 236
 237                 if (dev_priv->psr.sink_psr2_support) {
 238                         dev_priv->psr.colorimetry_support =
 239                                 intel_dp_get_colorimetry_status(intel_dp);
 240                 }
 241         }
 242 }
 243
 244 static void intel_psr_setup_vsc(struct intel_dp *intel_dp,
 245                                 const struct intel_crtc_state *crtc_state)
 246 {
 247         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 248         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 249         struct edp_vsc_psr psr_vsc;
 250
 251         if (dev_priv->psr.psr2_enabled) {
 252                 /* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */
 253                 memset(&psr_vsc, 0, sizeof(psr_vsc));
 254                 psr_vsc.sdp_header.HB0 = 0;
 255                 psr_vsc.sdp_header.HB1 = 0x7;
 256                 if (dev_priv->psr.colorimetry_support) {
 257                         psr_vsc.sdp_header.HB2 = 0x5;
 258                         psr_vsc.sdp_header.HB3 = 0x13;
 259                 } else {
 260                         psr_vsc.sdp_header.HB2 = 0x4;
 261                         psr_vsc.sdp_header.HB3 = 0xe;
 262                 }
 263         } else {
 264                 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
 265                 memset(&psr_vsc, 0, sizeof(psr_vsc));
 266                 psr_vsc.sdp_header.HB0 = 0;
 267                 psr_vsc.sdp_header.HB1 = 0x7;
 268                 psr_vsc.sdp_header.HB2 = 0x2;
 269                 psr_vsc.sdp_header.HB3 = 0x8;
 270         }
 271
 272         intel_dig_port->write_infoframe(&intel_dig_port->base.base, crtc_state,
 273                                         DP_SDP_VSC, &psr_vsc, sizeof(psr_vsc));
 274 }
 275
 276 static void hsw_psr_setup_aux(struct intel_dp *intel_dp)
 277 {
 278         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 279         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 280         u32 aux_clock_divider, aux_ctl;
 281         int i;
 282         static const uint8_t aux_msg[] = {
 283                 [0] = DP_AUX_NATIVE_WRITE << 4,
 284                 [1] = DP_SET_POWER >> 8,
 285                 [2] = DP_SET_POWER & 0xff,
 286                 [3] = 1 - 1,
 287                 [4] = DP_SET_POWER_D0,
 288         };
 289         u32 psr_aux_mask = EDP_PSR_AUX_CTL_TIME_OUT_MASK |
 290                            EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK |
 291                            EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK |
 292                            EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK;
 293
 294         BUILD_BUG_ON(sizeof(aux_msg) > 20);
 295         for (i = 0; i < sizeof(aux_msg); i += 4)
 296                 I915_WRITE(EDP_PSR_AUX_DATA(i >> 2),
 297                            intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i));
 298
 299         aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
 300
 301         /* Start with bits set for DDI_AUX_CTL register */
 302         aux_ctl = intel_dp->get_aux_send_ctl(intel_dp, sizeof(aux_msg),
 303                                              aux_clock_divider);
 304
 305         /* Select only valid bits for SRD_AUX_CTL */
 306         aux_ctl &= psr_aux_mask;
 307         I915_WRITE(EDP_PSR_AUX_CTL, aux_ctl);
 308 }
 309
 310 static void intel_psr_enable_sink(struct intel_dp *intel_dp)
 311 {
 312         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 313         struct drm_device *dev = dig_port->base.base.dev;
 314         struct drm_i915_private *dev_priv = to_i915(dev);
 315         u8 dpcd_val = DP_PSR_ENABLE;
 316
 317         /* Enable ALPM at sink for psr2 */
 318         if (dev_priv->psr.psr2_enabled) {
 319                 drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG,
 320                                    DP_ALPM_ENABLE);
 321                 dpcd_val |= DP_PSR_ENABLE_PSR2;
 322         }
 323
 324         if (dev_priv->psr.link_standby)
 325                 dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE;
 326         drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val);
 327
 328         drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
 329 }
 330
 331 static void hsw_activate_psr1(struct intel_dp *intel_dp)
 332 {
 333         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 334         struct drm_device *dev = dig_port->base.base.dev;
 335         struct drm_i915_private *dev_priv = to_i915(dev);
 336         u32 max_sleep_time = 0x1f;
 337         u32 val = EDP_PSR_ENABLE;
 338
 339         /* Let's use 6 as the minimum to cover all known cases including the
 340          * off-by-one issue that HW has in some cases.
 341          */
 342         int idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
 343
 344         /* sink_sync_latency of 8 means source has to wait for more than 8
 345          * frames, we'll go with 9 frames for now
 346          */
 347         idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1);
 348         val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
 349
 350         val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;
 351         if (IS_HASWELL(dev_priv))
 352                 val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
 353
 354         if (dev_priv->psr.link_standby)
 355                 val |= EDP_PSR_LINK_STANDBY;
 356
 357         if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0)
 358                 val |=  EDP_PSR_TP1_TIME_0us;
 359         else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100)
 360                 val |= EDP_PSR_TP1_TIME_100us;
 361         else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500)
 362                 val |= EDP_PSR_TP1_TIME_500us;
 363         else
 364                 val |= EDP_PSR_TP1_TIME_2500us;
 365
 366         if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0)
 367                 val |=  EDP_PSR_TP2_TP3_TIME_0us;
 368         else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
 369                 val |= EDP_PSR_TP2_TP3_TIME_100us;
 370         else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
 371                 val |= EDP_PSR_TP2_TP3_TIME_500us;
 372         else
 373                 val |= EDP_PSR_TP2_TP3_TIME_2500us;
 374
 375         if (intel_dp_source_supports_hbr2(intel_dp) &&
 376             drm_dp_tps3_supported(intel_dp->dpcd))
 377                 val |= EDP_PSR_TP1_TP3_SEL;
 378         else
 379                 val |= EDP_PSR_TP1_TP2_SEL;
 380
 381         val |= I915_READ(EDP_PSR_CTL) & EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK;
 382         I915_WRITE(EDP_PSR_CTL, val);
 383 }
 384
 385 static void hsw_activate_psr2(struct intel_dp *intel_dp)
 386 {
 387         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 388         struct drm_device *dev = dig_port->base.base.dev;
 389         struct drm_i915_private *dev_priv = to_i915(dev);
 390         u32 val;
 391
 392         /* Let's use 6 as the minimum to cover all known cases including the
 393          * off-by-one issue that HW has in some cases.
 394          */
 395         int idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
 396
 397         idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1);
 398         val = idle_frames << EDP_PSR2_IDLE_FRAME_SHIFT;
 399
 400         /* FIXME: selective update is probably totally broken because it doesn't
 401          * mesh at all with our frontbuffer tracking. And the hw alone isn't
 402          * good enough. */
 403         val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE;
 404         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
 405                 val |= EDP_Y_COORDINATE_ENABLE;
 406
 407         val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1);
 408
 409         if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us >= 0 &&
 410             dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 50)
 411                 val |= EDP_PSR2_TP2_TIME_50us;
 412         else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
 413                 val |= EDP_PSR2_TP2_TIME_100us;
 414         else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
 415                 val |= EDP_PSR2_TP2_TIME_500us;
 416         else
 417                 val |= EDP_PSR2_TP2_TIME_2500us;
 418
 419         I915_WRITE(EDP_PSR2_CTL, val);
 420 }
 421
 422 static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 423                                     struct intel_crtc_state *crtc_state)
 424 {
 425         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 426         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 427         int crtc_hdisplay = crtc_state->base.adjusted_mode.crtc_hdisplay;
 428         int crtc_vdisplay = crtc_state->base.adjusted_mode.crtc_vdisplay;
 429         int psr_max_h = 0, psr_max_v = 0;
 430
 431         /*
 432          * FIXME psr2_support is messed up. It's both computed
 433          * dynamically during PSR enable, and extracted from sink
 434          * caps during eDP detection.
 435          */
 436         if (!dev_priv->psr.sink_psr2_support)
 437                 return false;
 438
 439         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
 440                 psr_max_h = 4096;
 441                 psr_max_v = 2304;
 442         } else if (IS_GEN9(dev_priv)) {
 443                 psr_max_h = 3640;
 444                 psr_max_v = 2304;
 445         }
 446
 447         if (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v) {
 448                 DRM_DEBUG_KMS("PSR2 not enabled, resolution %dx%d > max supported %dx%d\n",
 449                               crtc_hdisplay, crtc_vdisplay,
 450                               psr_max_h, psr_max_v);
 451                 return false;
 452         }
 453
 454         return true;
 455 }
 456
 457 void intel_psr_compute_config(struct intel_dp *intel_dp,
 458                               struct intel_crtc_state *crtc_state)
 459 {
 460         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 461         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 462         const struct drm_display_mode *adjusted_mode =
 463                 &crtc_state->base.adjusted_mode;
 464         int psr_setup_time;
 465
 466         if (!CAN_PSR(dev_priv))
 467                 return;
 468
 469         if (!i915_modparams.enable_psr) {
 470                 DRM_DEBUG_KMS("PSR disable by flag\n");
 471                 return;
 472         }
 473
 474         /*
 475          * HSW spec explicitly says PSR is tied to port A.
 476          * BDW+ platforms with DDI implementation of PSR have different
 477          * PSR registers per transcoder and we only implement transcoder EDP
 478          * ones. Since by Display design transcoder EDP is tied to port A
 479          * we can safely escape based on the port A.
 480          */
 481         if (dig_port->base.port != PORT_A) {
 482                 DRM_DEBUG_KMS("PSR condition failed: Port not supported\n");
 483                 return;
 484         }
 485
 486         if (IS_HASWELL(dev_priv) &&
 487             I915_READ(HSW_STEREO_3D_CTL(crtc_state->cpu_transcoder)) &
 488                       S3D_ENABLE) {
 489                 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
 490                 return;
 491         }
 492
 493         if (IS_HASWELL(dev_priv) &&
 494             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
 495                 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
 496                 return;
 497         }
 498
 499         psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd);
 500         if (psr_setup_time < 0) {
 501                 DRM_DEBUG_KMS("PSR condition failed: Invalid PSR setup time (0x%02x)\n",
 502                               intel_dp->psr_dpcd[1]);
 503                 return;
 504         }
 505
 506         if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) >
 507             adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) {
 508                 DRM_DEBUG_KMS("PSR condition failed: PSR setup time (%d us) too long\n",
 509                               psr_setup_time);
 510                 return;
 511         }
 512
 513         crtc_state->has_psr = true;
 514         crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state);
 515         DRM_DEBUG_KMS("Enabling PSR%s\n", crtc_state->has_psr2 ? "2" : "");
 516 }
 517
 518 static void intel_psr_activate(struct intel_dp *intel_dp)
 519 {
 520         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 521         struct drm_device *dev = intel_dig_port->base.base.dev;
 522         struct drm_i915_private *dev_priv = to_i915(dev);
 523
 524         if (INTEL_GEN(dev_priv) >= 9)
 525                 WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE);
 526         WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
 527         WARN_ON(dev_priv->psr.active);
 528         lockdep_assert_held(&dev_priv->psr.lock);
 529
 530         /* psr1 and psr2 are mutually exclusive.*/
 531         if (dev_priv->psr.psr2_enabled)
 532                 hsw_activate_psr2(intel_dp);
 533         else
 534                 hsw_activate_psr1(intel_dp);
 535
 536         dev_priv->psr.active = true;
 537 }
 538
 539 static void intel_psr_enable_source(struct intel_dp *intel_dp,
 540                                     const struct intel_crtc_state *crtc_state)
 541 {
 542         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 543         struct drm_device *dev = dig_port->base.base.dev;
 544         struct drm_i915_private *dev_priv = to_i915(dev);
 545         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 546
 547         /* Only HSW and BDW have PSR AUX registers that need to be setup. SKL+
 548          * use hardcoded values PSR AUX transactions
 549          */
 550         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 551                 hsw_psr_setup_aux(intel_dp);
 552
 553         if (dev_priv->psr.psr2_enabled) {
 554                 u32 chicken = I915_READ(CHICKEN_TRANS(cpu_transcoder));
 555
 556                 if (INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv))
 557                         chicken |= (PSR2_VSC_ENABLE_PROG_HEADER
 558                                    | PSR2_ADD_VERTICAL_LINE_COUNT);
 559
 560                 else
 561                         chicken &= ~VSC_DATA_SEL_SOFTWARE_CONTROL;
 562                 I915_WRITE(CHICKEN_TRANS(cpu_transcoder), chicken);
 563
 564                 I915_WRITE(EDP_PSR_DEBUG,
 565                            EDP_PSR_DEBUG_MASK_MEMUP |
 566                            EDP_PSR_DEBUG_MASK_HPD |
 567                            EDP_PSR_DEBUG_MASK_LPSP |
 568                            EDP_PSR_DEBUG_MASK_MAX_SLEEP |
 569                            EDP_PSR_DEBUG_MASK_DISP_REG_WRITE);
 570         } else {
 571                 /*
 572                  * Per Spec: Avoid continuous PSR exit by masking MEMUP
 573                  * and HPD. also mask LPSP to avoid dependency on other
 574                  * drivers that might block runtime_pm besides
 575                  * preventing  other hw tracking issues now we can rely
 576                  * on frontbuffer tracking.
 577                  */
 578                 I915_WRITE(EDP_PSR_DEBUG,
 579                            EDP_PSR_DEBUG_MASK_MEMUP |
 580                            EDP_PSR_DEBUG_MASK_HPD |
 581                            EDP_PSR_DEBUG_MASK_LPSP |
 582                            EDP_PSR_DEBUG_MASK_DISP_REG_WRITE |
 583                            EDP_PSR_DEBUG_MASK_MAX_SLEEP);
 584         }
 585 }
 586
 587 /**
 588  * intel_psr_enable - Enable PSR
 589  * @intel_dp: Intel DP
 590  * @crtc_state: new CRTC state
 591  *
 592  * This function can only be called after the pipe is fully trained and enabled.
 593  */
 594 void intel_psr_enable(struct intel_dp *intel_dp,
 595                       const struct intel_crtc_state *crtc_state)
 596 {
 597         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 598         struct drm_device *dev = intel_dig_port->base.base.dev;
 599         struct drm_i915_private *dev_priv = to_i915(dev);
 600
 601         if (!crtc_state->has_psr)
 602                 return;
 603
 604         if (WARN_ON(!CAN_PSR(dev_priv)))
 605                 return;
 606
 607         WARN_ON(dev_priv->drrs.dp);
 608         mutex_lock(&dev_priv->psr.lock);
 609         if (dev_priv->psr.enabled) {
 610                 DRM_DEBUG_KMS("PSR already in use\n");
 611                 goto unlock;
 612         }
 613
 614         dev_priv->psr.psr2_enabled = crtc_state->has_psr2;
 615         dev_priv->psr.busy_frontbuffer_bits = 0;
 616
 617         intel_psr_setup_vsc(intel_dp, crtc_state);
 618         intel_psr_enable_sink(intel_dp);
 619         intel_psr_enable_source(intel_dp, crtc_state);
 620         dev_priv->psr.enabled = intel_dp;
 621
 622         intel_psr_activate(intel_dp);
 623
 624 unlock:
 625         mutex_unlock(&dev_priv->psr.lock);
 626 }
 627
 628 static void
 629 intel_psr_disable_source(struct intel_dp *intel_dp)
 630 {
 631         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 632         struct drm_device *dev = intel_dig_port->base.base.dev;
 633         struct drm_i915_private *dev_priv = to_i915(dev);
 634
 635         if (dev_priv->psr.active) {
 636                 i915_reg_t psr_status;
 637                 u32 psr_status_mask;
 638
 639                 if (dev_priv->psr.psr2_enabled) {
 640                         psr_status = EDP_PSR2_STATUS;
 641                         psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
 642
 643                         I915_WRITE(EDP_PSR2_CTL,
 644                                    I915_READ(EDP_PSR2_CTL) &
 645                                    ~(EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE));
 646
 647                 } else {
 648                         psr_status = EDP_PSR_STATUS;
 649                         psr_status_mask = EDP_PSR_STATUS_STATE_MASK;
 650
 651                         I915_WRITE(EDP_PSR_CTL,
 652                                    I915_READ(EDP_PSR_CTL) & ~EDP_PSR_ENABLE);
 653                 }
 654
 655                 /* Wait till PSR is idle */
 656                 if (intel_wait_for_register(dev_priv,
 657                                             psr_status, psr_status_mask, 0,
 658                                             2000))
 659                         DRM_ERROR("Timed out waiting for PSR Idle State\n");
 660
 661                 dev_priv->psr.active = false;
 662         } else {
 663                 if (dev_priv->psr.psr2_enabled)
 664                         WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE);
 665                 else
 666                         WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
 667         }
 668 }
 669
 670 static void intel_psr_disable_locked(struct intel_dp *intel_dp)
 671 {
 672         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 673         struct drm_device *dev = intel_dig_port->base.base.dev;
 674         struct drm_i915_private *dev_priv = to_i915(dev);
 675
 676         lockdep_assert_held(&dev_priv->psr.lock);
 677
 678         if (!dev_priv->psr.enabled)
 679                 return;
 680
 681         intel_psr_disable_source(intel_dp);
 682
 683         /* Disable PSR on Sink */
 684         drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0);
 685
 686         dev_priv->psr.enabled = NULL;
 687 }
 688
 689 /**
 690  * intel_psr_disable - Disable PSR
 691  * @intel_dp: Intel DP
 692  * @old_crtc_state: old CRTC state
 693  *
 694  * This function needs to be called before disabling pipe.
 695  */
 696 void intel_psr_disable(struct intel_dp *intel_dp,
 697                        const struct intel_crtc_state *old_crtc_state)
 698 {
 699         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 700         struct drm_device *dev = intel_dig_port->base.base.dev;
 701         struct drm_i915_private *dev_priv = to_i915(dev);
 702
 703         if (!old_crtc_state->has_psr)
 704                 return;
 705
 706         if (WARN_ON(!CAN_PSR(dev_priv)))
 707                 return;
 708
 709         mutex_lock(&dev_priv->psr.lock);
 710         intel_psr_disable_locked(intel_dp);
 711         mutex_unlock(&dev_priv->psr.lock);
 712         cancel_work_sync(&dev_priv->psr.work);
 713 }
 714
 715 static bool psr_wait_for_idle(struct drm_i915_private *dev_priv)
 716 {
 717         struct intel_dp *intel_dp;
 718         i915_reg_t reg;
 719         u32 mask;
 720         int err;
 721
 722         intel_dp = dev_priv->psr.enabled;
 723         if (!intel_dp)
 724                 return false;
 725
 726         if (dev_priv->psr.psr2_enabled) {
 727                 reg = EDP_PSR2_STATUS;
 728                 mask = EDP_PSR2_STATUS_STATE_MASK;
 729         } else {
 730                 reg = EDP_PSR_STATUS;
 731                 mask = EDP_PSR_STATUS_STATE_MASK;
 732         }
 733
 734         mutex_unlock(&dev_priv->psr.lock);
 735
 736         err = intel_wait_for_register(dev_priv, reg, mask, 0, 50);
 737         if (err)
 738                 DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
 739
 740         /* After the unlocked wait, verify that PSR is still wanted! */
 741         mutex_lock(&dev_priv->psr.lock);
 742         return err == 0 && dev_priv->psr.enabled;
 743 }
 744
 745 static void intel_psr_work(struct work_struct *work)
 746 {
 747         struct drm_i915_private *dev_priv =
 748                 container_of(work, typeof(*dev_priv), psr.work);
 749
 750         mutex_lock(&dev_priv->psr.lock);
 751
 752         if (!dev_priv->psr.enabled)
 753                 goto unlock;
 754
 755         /*
 756          * We have to make sure PSR is ready for re-enable
 757          * otherwise it keeps disabled until next full enable/disable cycle.
 758          * PSR might take some time to get fully disabled
 759          * and be ready for re-enable.
 760          */
 761         if (!psr_wait_for_idle(dev_priv))
 762                 goto unlock;
 763
 764         /*
 765          * The delayed work can race with an invalidate hence we need to
 766          * recheck. Since psr_flush first clears this and then reschedules we
 767          * won't ever miss a flush when bailing out here.
 768          */
 769         if (dev_priv->psr.busy_frontbuffer_bits || dev_priv->psr.active)
 770                 goto unlock;
 771
 772         intel_psr_activate(dev_priv->psr.enabled);
 773 unlock:
 774         mutex_unlock(&dev_priv->psr.lock);
 775 }
 776
 777 static void intel_psr_exit(struct drm_i915_private *dev_priv)
 778 {
 779         u32 val;
 780
 781         if (!dev_priv->psr.active)
 782                 return;
 783
 784         if (dev_priv->psr.psr2_enabled) {
 785                 val = I915_READ(EDP_PSR2_CTL);
 786                 WARN_ON(!(val & EDP_PSR2_ENABLE));
 787                 I915_WRITE(EDP_PSR2_CTL, val & ~EDP_PSR2_ENABLE);
 788         } else {
 789                 val = I915_READ(EDP_PSR_CTL);
 790                 WARN_ON(!(val & EDP_PSR_ENABLE));
 791                 I915_WRITE(EDP_PSR_CTL, val & ~EDP_PSR_ENABLE);
 792         }
 793         dev_priv->psr.active = false;
 794 }
 795
 796 /**
 797  * intel_psr_invalidate - Invalidade PSR
 798  * @dev_priv: i915 device
 799  * @frontbuffer_bits: frontbuffer plane tracking bits
 800  * @origin: which operation caused the invalidate
 801  *
 802  * Since the hardware frontbuffer tracking has gaps we need to integrate
 803  * with the software frontbuffer tracking. This function gets called every
 804  * time frontbuffer rendering starts and a buffer gets dirtied. PSR must be
 805  * disabled if the frontbuffer mask contains a buffer relevant to PSR.
 806  *
 807  * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits."
 808  */
 809 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
 810                           unsigned frontbuffer_bits, enum fb_op_origin origin)
 811 {
 812         struct drm_crtc *crtc;
 813         enum pipe pipe;
 814
 815         if (!CAN_PSR(dev_priv))
 816                 return;
 817
 818         if (origin == ORIGIN_FLIP)
 819                 return;
 820
 821         mutex_lock(&dev_priv->psr.lock);
 822         if (!dev_priv->psr.enabled) {
 823                 mutex_unlock(&dev_priv->psr.lock);
 824                 return;
 825         }
 826
 827         crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
 828         pipe = to_intel_crtc(crtc)->pipe;
 829
 830         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
 831         dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
 832
 833         if (frontbuffer_bits)
 834                 intel_psr_exit(dev_priv);
 835
 836         mutex_unlock(&dev_priv->psr.lock);
 837 }
 838
 839 /**
 840  * intel_psr_flush - Flush PSR
 841  * @dev_priv: i915 device
 842  * @frontbuffer_bits: frontbuffer plane tracking bits
 843  * @origin: which operation caused the flush
 844  *
 845  * Since the hardware frontbuffer tracking has gaps we need to integrate
 846  * with the software frontbuffer tracking. This function gets called every
 847  * time frontbuffer rendering has completed and flushed out to memory. PSR
 848  * can be enabled again if no other frontbuffer relevant to PSR is dirty.
 849  *
 850  * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits.
 851  */
 852 void intel_psr_flush(struct drm_i915_private *dev_priv,
 853                      unsigned frontbuffer_bits, enum fb_op_origin origin)
 854 {
 855         struct drm_crtc *crtc;
 856         enum pipe pipe;
 857
 858         if (!CAN_PSR(dev_priv))
 859                 return;
 860
 861         if (origin == ORIGIN_FLIP)
 862                 return;
 863
 864         mutex_lock(&dev_priv->psr.lock);
 865         if (!dev_priv->psr.enabled) {
 866                 mutex_unlock(&dev_priv->psr.lock);
 867                 return;
 868         }
 869
 870         crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
 871         pipe = to_intel_crtc(crtc)->pipe;
 872
 873         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
 874         dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
 875
 876         /* By definition flush = invalidate + flush */
 877         if (frontbuffer_bits) {
 878                 if (dev_priv->psr.psr2_enabled) {
 879                         intel_psr_exit(dev_priv);
 880                 } else {
 881                         /*
 882                          * Display WA #0884: all
 883                          * This documented WA for bxt can be safely applied
 884                          * broadly so we can force HW tracking to exit PSR
 885                          * instead of disabling and re-enabling.
 886                          * Workaround tells us to write 0 to CUR_SURFLIVE_A,
 887                          * but it makes more sense write to the current active
 888                          * pipe.
 889                          */
 890                         I915_WRITE(CURSURFLIVE(pipe), 0);
 891                 }
 892         }
 893
 894         if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
 895                 schedule_work(&dev_priv->psr.work);
 896         mutex_unlock(&dev_priv->psr.lock);
 897 }
 898
 899 /**
 900  * intel_psr_init - Init basic PSR work and mutex.
 901  * @dev_priv: i915 device private
 902  *
 903  * This function is  called only once at driver load to initialize basic
 904  * PSR stuff.
 905  */
 906 void intel_psr_init(struct drm_i915_private *dev_priv)
 907 {
 908         if (!HAS_PSR(dev_priv))
 909                 return;
 910
 911         dev_priv->psr_mmio_base = IS_HASWELL(dev_priv) ?
 912                 HSW_EDP_PSR_BASE : BDW_EDP_PSR_BASE;
 913
 914         if (!dev_priv->psr.sink_support)
 915                 return;
 916
 917         if (i915_modparams.enable_psr == -1) {
 918                 i915_modparams.enable_psr = dev_priv->vbt.psr.enable;
 919
 920                 /* Per platform default: all disabled. */
 921                 i915_modparams.enable_psr = 0;
 922         }
 923
 924         /* Set link_standby x link_off defaults */
 925         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 926                 /* HSW and BDW require workarounds that we don't implement. */
 927                 dev_priv->psr.link_standby = false;
 928         else
 929                 /* For new platforms let's respect VBT back again */
 930                 dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link;
 931
 932         /* Override link_standby x link_off defaults */
 933         if (i915_modparams.enable_psr == 2 && !dev_priv->psr.link_standby) {
 934                 DRM_DEBUG_KMS("PSR: Forcing link standby\n");
 935                 dev_priv->psr.link_standby = true;
 936         }
 937         if (i915_modparams.enable_psr == 3 && dev_priv->psr.link_standby) {
 938                 DRM_DEBUG_KMS("PSR: Forcing main link off\n");
 939                 dev_priv->psr.link_standby = false;
 940         }
 941
 942         INIT_WORK(&dev_priv->psr.work, intel_psr_work);
 943         mutex_init(&dev_priv->psr.lock);
 944 }
 945
 946 void intel_psr_short_pulse(struct intel_dp *intel_dp)
 947 {
 948         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 949         struct drm_device *dev = intel_dig_port->base.base.dev;
 950         struct drm_i915_private *dev_priv = to_i915(dev);
 951         struct i915_psr *psr = &dev_priv->psr;
 952         u8 val;
 953         const u8 errors = DP_PSR_RFB_STORAGE_ERROR |
 954                           DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR;
 955
 956         if (!CAN_PSR(dev_priv) || !intel_dp_is_edp(intel_dp))
 957                 return;
 958
 959         mutex_lock(&psr->lock);
 960
 961         if (psr->enabled != intel_dp)
 962                 goto exit;
 963
 964         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_STATUS, &val) != 1) {
 965                 DRM_ERROR("PSR_STATUS dpcd read failed\n");
 966                 goto exit;
 967         }
 968
 969         if ((val & DP_PSR_SINK_STATE_MASK) == DP_PSR_SINK_INTERNAL_ERROR) {
 970                 DRM_DEBUG_KMS("PSR sink internal error, disabling PSR\n");
 971                 intel_psr_disable_locked(intel_dp);
 972         }
 973
 974         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ERROR_STATUS, &val) != 1) {
 975                 DRM_ERROR("PSR_ERROR_STATUS dpcd read failed\n");
 976                 goto exit;
 977         }
 978
 979         if (val & DP_PSR_RFB_STORAGE_ERROR)
 980                 DRM_DEBUG_KMS("PSR RFB storage error, disabling PSR\n");
 981         if (val & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR)
 982                 DRM_DEBUG_KMS("PSR VSC SDP uncorrectable error, disabling PSR\n");
 983
 984         if (val & ~errors)
 985                 DRM_ERROR("PSR_ERROR_STATUS unhandled errors %x\n",
 986                           val & ~errors);
 987         if (val & errors)
 988                 intel_psr_disable_locked(intel_dp);
 989         /* clear status register */
 990         drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, val);
 991
 992         /* TODO: handle PSR2 errors */
 993 exit:
 994         mutex_unlock(&psr->lock);
 995 }