drivers/gpu/drm/i915/intel_psr.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * DOC: Panel Self Refresh (PSR/SRD)
  26  *
  27  * Since Haswell Display controller supports Panel Self-Refresh on display
  28  * panels witch have a remote frame buffer (RFB) implemented according to PSR
  29  * spec in eDP1.3. PSR feature allows the display to go to lower standby states
  30  * when system is idle but display is on as it eliminates display refresh
  31  * request to DDR memory completely as long as the frame buffer for that
  32  * display is unchanged.
  33  *
  34  * Panel Self Refresh must be supported by both Hardware (source) and
  35  * Panel (sink).
  36  *
  37  * PSR saves power by caching the framebuffer in the panel RFB, which allows us
  38  * to power down the link and memory controller. For DSI panels the same idea
  39  * is called "manual mode".
  40  *
  41  * The implementation uses the hardware-based PSR support which automatically
  42  * enters/exits self-refresh mode. The hardware takes care of sending the
  43  * required DP aux message and could even retrain the link (that part isn't
  44  * enabled yet though). The hardware also keeps track of any frontbuffer
  45  * changes to know when to exit self-refresh mode again. Unfortunately that
  46  * part doesn't work too well, hence why the i915 PSR support uses the
  47  * software frontbuffer tracking to make sure it doesn't miss a screen
  48  * update. For this integration intel_psr_invalidate() and intel_psr_flush()
  49  * get called by the frontbuffer tracking code. Note that because of locking
  50  * issues the self-refresh re-enable code is done from a work queue, which
  51  * must be correctly synchronized/cancelled when shutting down the pipe."
  52  */
  53
  54 #include <drm/drmP.h>
  55
  56 #include "intel_drv.h"
  57 #include "i915_drv.h"
  58
  59 static bool is_edp_psr(struct intel_dp *intel_dp)
  60 {
  61         return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
  62 }
  63
  64 static bool vlv_is_psr_active_on_pipe(struct drm_device *dev, int pipe)
  65 {
  66         struct drm_i915_private *dev_priv = dev->dev_private;
  67         uint32_t val;
  68
  69         val = I915_READ(VLV_PSRSTAT(pipe)) &
  70               VLV_EDP_PSR_CURR_STATE_MASK;
  71         return (val == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
  72                (val == VLV_EDP_PSR_ACTIVE_SF_UPDATE);
  73 }
  74
  75 static void intel_psr_write_vsc(struct intel_dp *intel_dp,
  76                                     struct edp_vsc_psr *vsc_psr)
  77 {
  78         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
  79         struct drm_device *dev = dig_port->base.base.dev;
  80         struct drm_i915_private *dev_priv = dev->dev_private;
  81         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
  82         u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config->cpu_transcoder);
  83         u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config->cpu_transcoder);
  84         uint32_t *data = (uint32_t *) vsc_psr;
  85         unsigned int i;
  86
  87         /* As per BSPec (Pipe Video Data Island Packet), we need to disable
  88            the video DIP being updated before program video DIP data buffer
  89            registers for DIP being updated. */
  90         I915_WRITE(ctl_reg, 0);
  91         POSTING_READ(ctl_reg);
  92
  93         for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
  94                 if (i < sizeof(struct edp_vsc_psr))
  95                         I915_WRITE(data_reg + i, *data++);
  96                 else
  97                         I915_WRITE(data_reg + i, 0);
  98         }
  99
 100         I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
 101         POSTING_READ(ctl_reg);
 102 }
 103
 104 static void vlv_psr_setup_vsc(struct intel_dp *intel_dp)
 105 {
 106         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 107         struct drm_device *dev = intel_dig_port->base.base.dev;
 108         struct drm_i915_private *dev_priv = dev->dev_private;
 109         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
 110         enum pipe pipe = to_intel_crtc(crtc)->pipe;
 111         uint32_t val;
 112
 113         /* VLV auto-generate VSC package as per EDP 1.3 spec, Table 3.10 */
 114         val  = I915_READ(VLV_VSCSDP(pipe));
 115         val &= ~VLV_EDP_PSR_SDP_FREQ_MASK;
 116         val |= VLV_EDP_PSR_SDP_FREQ_EVFRAME;
 117         I915_WRITE(VLV_VSCSDP(pipe), val);
 118 }
 119
 120 static void skl_psr_setup_su_vsc(struct intel_dp *intel_dp)
 121 {
 122         struct edp_vsc_psr psr_vsc;
 123
 124         /* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */
 125         memset(&psr_vsc, 0, sizeof(psr_vsc));
 126         psr_vsc.sdp_header.HB0 = 0;
 127         psr_vsc.sdp_header.HB1 = 0x7;
 128         psr_vsc.sdp_header.HB2 = 0x3;
 129         psr_vsc.sdp_header.HB3 = 0xb;
 130         intel_psr_write_vsc(intel_dp, &psr_vsc);
 131 }
 132
 133 static void hsw_psr_setup_vsc(struct intel_dp *intel_dp)
 134 {
 135         struct edp_vsc_psr psr_vsc;
 136
 137         /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
 138         memset(&psr_vsc, 0, sizeof(psr_vsc));
 139         psr_vsc.sdp_header.HB0 = 0;
 140         psr_vsc.sdp_header.HB1 = 0x7;
 141         psr_vsc.sdp_header.HB2 = 0x2;
 142         psr_vsc.sdp_header.HB3 = 0x8;
 143         intel_psr_write_vsc(intel_dp, &psr_vsc);
 144 }
 145
 146 static void vlv_psr_enable_sink(struct intel_dp *intel_dp)
 147 {
 148         drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
 149                            DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
 150 }
 151
 152 static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
 153 {
 154         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 155         struct drm_device *dev = dig_port->base.base.dev;
 156         struct drm_i915_private *dev_priv = dev->dev_private;
 157         uint32_t aux_clock_divider;
 158         uint32_t aux_data_reg, aux_ctl_reg;
 159         int precharge = 0x3;
 160         static const uint8_t aux_msg[] = {
 161                 [0] = DP_AUX_NATIVE_WRITE << 4,
 162                 [1] = DP_SET_POWER >> 8,
 163                 [2] = DP_SET_POWER & 0xff,
 164                 [3] = 1 - 1,
 165                 [4] = DP_SET_POWER_D0,
 166         };
 167         int i;
 168
 169         BUILD_BUG_ON(sizeof(aux_msg) > 20);
 170
 171         aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
 172
 173         /* Enable PSR in sink */
 174         if (dev_priv->psr.link_standby)
 175                 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
 176                                    DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
 177         else
 178                 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
 179                                    DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
 180
 181         /* Enable AUX frame sync at sink */
 182         if (dev_priv->psr.aux_frame_sync)
 183                 drm_dp_dpcd_writeb(&intel_dp->aux,
 184                                 DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF,
 185                                 DP_AUX_FRAME_SYNC_ENABLE);
 186
 187         aux_data_reg = (INTEL_INFO(dev)->gen >= 9) ?
 188                                 DPA_AUX_CH_DATA1 : EDP_PSR_AUX_DATA1(dev);
 189         aux_ctl_reg = (INTEL_INFO(dev)->gen >= 9) ?
 190                                 DPA_AUX_CH_CTL : EDP_PSR_AUX_CTL(dev);
 191
 192         /* Setup AUX registers */
 193         for (i = 0; i < sizeof(aux_msg); i += 4)
 194                 I915_WRITE(aux_data_reg + i,
 195                            intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i));
 196
 197         if (INTEL_INFO(dev)->gen >= 9) {
 198                 uint32_t val;
 199
 200                 val = I915_READ(aux_ctl_reg);
 201                 val &= ~DP_AUX_CH_CTL_TIME_OUT_MASK;
 202                 val |= DP_AUX_CH_CTL_TIME_OUT_1600us;
 203                 val &= ~DP_AUX_CH_CTL_MESSAGE_SIZE_MASK;
 204                 val |= (sizeof(aux_msg) << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 205                 /* Use hardcoded data values for PSR, frame sync and GTC */
 206                 val &= ~DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL;
 207                 val &= ~DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL;
 208                 val &= ~DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL;
 209                 I915_WRITE(aux_ctl_reg, val);
 210         } else {
 211                 I915_WRITE(aux_ctl_reg,
 212                    DP_AUX_CH_CTL_TIME_OUT_400us |
 213                    (sizeof(aux_msg) << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 214                    (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 215                    (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
 216         }
 217 }
 218
 219 static void vlv_psr_enable_source(struct intel_dp *intel_dp)
 220 {
 221         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 222         struct drm_device *dev = dig_port->base.base.dev;
 223         struct drm_i915_private *dev_priv = dev->dev_private;
 224         struct drm_crtc *crtc = dig_port->base.base.crtc;
 225         enum pipe pipe = to_intel_crtc(crtc)->pipe;
 226
 227         /* Transition from PSR_state 0 to PSR_state 1, i.e. PSR Inactive */
 228         I915_WRITE(VLV_PSRCTL(pipe),
 229                    VLV_EDP_PSR_MODE_SW_TIMER |
 230                    VLV_EDP_PSR_SRC_TRANSMITTER_STATE |
 231                    VLV_EDP_PSR_ENABLE);
 232 }
 233
 234 static void vlv_psr_activate(struct intel_dp *intel_dp)
 235 {
 236         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 237         struct drm_device *dev = dig_port->base.base.dev;
 238         struct drm_i915_private *dev_priv = dev->dev_private;
 239         struct drm_crtc *crtc = dig_port->base.base.crtc;
 240         enum pipe pipe = to_intel_crtc(crtc)->pipe;
 241
 242         /* Let's do the transition from PSR_state 1 to PSR_state 2
 243          * that is PSR transition to active - static frame transmission.
 244          * Then Hardware is responsible for the transition to PSR_state 3
 245          * that is PSR active - no Remote Frame Buffer (RFB) update.
 246          */
 247         I915_WRITE(VLV_PSRCTL(pipe), I915_READ(VLV_PSRCTL(pipe)) |
 248                    VLV_EDP_PSR_ACTIVE_ENTRY);
 249 }
 250
 251 static void hsw_psr_enable_source(struct intel_dp *intel_dp)
 252 {
 253         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 254         struct drm_device *dev = dig_port->base.base.dev;
 255         struct drm_i915_private *dev_priv = dev->dev_private;
 256
 257         uint32_t max_sleep_time = 0x1f;
 258         /* Lately it was identified that depending on panel idle frame count
 259          * calculated at HW can be off by 1. So let's use what came
 260          * from VBT + 1 and at minimum 2 to be on the safe side.
 261          */
 262         uint32_t idle_frames = dev_priv->vbt.psr.idle_frames ?
 263                                dev_priv->vbt.psr.idle_frames + 1 : 2;
 264         uint32_t val = 0x0;
 265         const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
 266
 267         if (dev_priv->psr.link_standby) {
 268                 val |= EDP_PSR_LINK_STANDBY;
 269                 val |= EDP_PSR_TP2_TP3_TIME_0us;
 270                 val |= EDP_PSR_TP1_TIME_0us;
 271                 val |= EDP_PSR_SKIP_AUX_EXIT;
 272         } else
 273                 val |= EDP_PSR_LINK_DISABLE;
 274
 275         I915_WRITE(EDP_PSR_CTL(dev), val |
 276                    (IS_BROADWELL(dev) ? 0 : link_entry_time) |
 277                    max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
 278                    idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
 279                    EDP_PSR_ENABLE);
 280
 281         if (dev_priv->psr.psr2_support)
 282                 I915_WRITE(EDP_PSR2_CTL, EDP_PSR2_ENABLE |
 283                                 EDP_SU_TRACK_ENABLE | EDP_PSR2_TP2_TIME_100);
 284 }
 285
 286 static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
 287 {
 288         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 289         struct drm_device *dev = dig_port->base.base.dev;
 290         struct drm_i915_private *dev_priv = dev->dev_private;
 291         struct drm_crtc *crtc = dig_port->base.base.crtc;
 292         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 293
 294         lockdep_assert_held(&dev_priv->psr.lock);
 295         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
 296         WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
 297
 298         dev_priv->psr.source_ok = false;
 299
 300         if (IS_HASWELL(dev) && dig_port->port != PORT_A) {
 301                 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
 302                 return false;
 303         }
 304
 305         if (!i915.enable_psr) {
 306                 DRM_DEBUG_KMS("PSR disable by flag\n");
 307                 return false;
 308         }
 309
 310         if (IS_HASWELL(dev) &&
 311             I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config->cpu_transcoder)) &
 312                       S3D_ENABLE) {
 313                 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
 314                 return false;
 315         }
 316
 317         if (IS_HASWELL(dev) &&
 318             intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
 319                 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
 320                 return false;
 321         }
 322
 323         dev_priv->psr.source_ok = true;
 324         return true;
 325 }
 326
 327 static void intel_psr_activate(struct intel_dp *intel_dp)
 328 {
 329         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 330         struct drm_device *dev = intel_dig_port->base.base.dev;
 331         struct drm_i915_private *dev_priv = dev->dev_private;
 332
 333         WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
 334         WARN_ON(dev_priv->psr.active);
 335         lockdep_assert_held(&dev_priv->psr.lock);
 336
 337         /* Enable/Re-enable PSR on the host */
 338         if (HAS_DDI(dev))
 339                 /* On HSW+ after we enable PSR on source it will activate it
 340                  * as soon as it match configure idle_frame count. So
 341                  * we just actually enable it here on activation time.
 342                  */
 343                 hsw_psr_enable_source(intel_dp);
 344         else
 345                 vlv_psr_activate(intel_dp);
 346
 347         dev_priv->psr.active = true;
 348 }
 349
 350 /**
 351  * intel_psr_enable - Enable PSR
 352  * @intel_dp: Intel DP
 353  *
 354  * This function can only be called after the pipe is fully trained and enabled.
 355  */
 356 void intel_psr_enable(struct intel_dp *intel_dp)
 357 {
 358         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 359         struct drm_device *dev = intel_dig_port->base.base.dev;
 360         struct drm_i915_private *dev_priv = dev->dev_private;
 361         struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
 362
 363         if (!HAS_PSR(dev)) {
 364                 DRM_DEBUG_KMS("PSR not supported on this platform\n");
 365                 return;
 366         }
 367
 368         if (!is_edp_psr(intel_dp)) {
 369                 DRM_DEBUG_KMS("PSR not supported by this panel\n");
 370                 return;
 371         }
 372
 373         mutex_lock(&dev_priv->psr.lock);
 374         if (dev_priv->psr.enabled) {
 375                 DRM_DEBUG_KMS("PSR already in use\n");
 376                 goto unlock;
 377         }
 378
 379         if (!intel_psr_match_conditions(intel_dp))
 380                 goto unlock;
 381
 382         /* First we check VBT, but we must respect sink and source
 383          * known restrictions */
 384         dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link;
 385         if ((intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) ||
 386             (IS_BROADWELL(dev) && intel_dig_port->port != PORT_A))
 387                 dev_priv->psr.link_standby = true;
 388
 389         dev_priv->psr.busy_frontbuffer_bits = 0;
 390
 391         if (HAS_DDI(dev)) {
 392                 hsw_psr_setup_vsc(intel_dp);
 393
 394                 if (dev_priv->psr.psr2_support) {
 395                         /* PSR2 is restricted to work with panel resolutions upto 3200x2000 */
 396                         if (crtc->config->pipe_src_w > 3200 ||
 397                                 crtc->config->pipe_src_h > 2000)
 398                                 dev_priv->psr.psr2_support = false;
 399                         else
 400                                 skl_psr_setup_su_vsc(intel_dp);
 401                 }
 402
 403                 /* Avoid continuous PSR exit by masking memup and hpd */
 404                 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
 405                            EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
 406
 407                 /* Enable PSR on the panel */
 408                 hsw_psr_enable_sink(intel_dp);
 409
 410                 if (INTEL_INFO(dev)->gen >= 9)
 411                         intel_psr_activate(intel_dp);
 412         } else {
 413                 vlv_psr_setup_vsc(intel_dp);
 414
 415                 /* Enable PSR on the panel */
 416                 vlv_psr_enable_sink(intel_dp);
 417
 418                 /* On HSW+ enable_source also means go to PSR entry/active
 419                  * state as soon as idle_frame achieved and here would be
 420                  * to soon. However on VLV enable_source just enable PSR
 421                  * but let it on inactive state. So we might do this prior
 422                  * to active transition, i.e. here.
 423                  */
 424                 vlv_psr_enable_source(intel_dp);
 425         }
 426
 427         dev_priv->psr.enabled = intel_dp;
 428 unlock:
 429         mutex_unlock(&dev_priv->psr.lock);
 430 }
 431
 432 static void vlv_psr_disable(struct intel_dp *intel_dp)
 433 {
 434         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 435         struct drm_device *dev = intel_dig_port->base.base.dev;
 436         struct drm_i915_private *dev_priv = dev->dev_private;
 437         struct intel_crtc *intel_crtc =
 438                 to_intel_crtc(intel_dig_port->base.base.crtc);
 439         uint32_t val;
 440
 441         if (dev_priv->psr.active) {
 442                 /* Put VLV PSR back to PSR_state 0 that is PSR Disabled. */
 443                 if (wait_for((I915_READ(VLV_PSRSTAT(intel_crtc->pipe)) &
 444                               VLV_EDP_PSR_IN_TRANS) == 0, 1))
 445                         WARN(1, "PSR transition took longer than expected\n");
 446
 447                 val = I915_READ(VLV_PSRCTL(intel_crtc->pipe));
 448                 val &= ~VLV_EDP_PSR_ACTIVE_ENTRY;
 449                 val &= ~VLV_EDP_PSR_ENABLE;
 450                 val &= ~VLV_EDP_PSR_MODE_MASK;
 451                 I915_WRITE(VLV_PSRCTL(intel_crtc->pipe), val);
 452
 453                 dev_priv->psr.active = false;
 454         } else {
 455                 WARN_ON(vlv_is_psr_active_on_pipe(dev, intel_crtc->pipe));
 456         }
 457 }
 458
 459 static void hsw_psr_disable(struct intel_dp *intel_dp)
 460 {
 461         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 462         struct drm_device *dev = intel_dig_port->base.base.dev;
 463         struct drm_i915_private *dev_priv = dev->dev_private;
 464
 465         if (dev_priv->psr.active) {
 466                 I915_WRITE(EDP_PSR_CTL(dev),
 467                            I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
 468
 469                 /* Wait till PSR is idle */
 470                 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
 471                                EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
 472                         DRM_ERROR("Timed out waiting for PSR Idle State\n");
 473
 474                 dev_priv->psr.active = false;
 475         } else {
 476                 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
 477         }
 478 }
 479
 480 /**
 481  * intel_psr_disable - Disable PSR
 482  * @intel_dp: Intel DP
 483  *
 484  * This function needs to be called before disabling pipe.
 485  */
 486 void intel_psr_disable(struct intel_dp *intel_dp)
 487 {
 488         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 489         struct drm_device *dev = intel_dig_port->base.base.dev;
 490         struct drm_i915_private *dev_priv = dev->dev_private;
 491
 492         mutex_lock(&dev_priv->psr.lock);
 493         if (!dev_priv->psr.enabled) {
 494                 mutex_unlock(&dev_priv->psr.lock);
 495                 return;
 496         }
 497
 498         if (HAS_DDI(dev))
 499                 hsw_psr_disable(intel_dp);
 500         else
 501                 vlv_psr_disable(intel_dp);
 502
 503         dev_priv->psr.enabled = NULL;
 504         mutex_unlock(&dev_priv->psr.lock);
 505
 506         cancel_delayed_work_sync(&dev_priv->psr.work);
 507 }
 508
 509 static void intel_psr_work(struct work_struct *work)
 510 {
 511         struct drm_i915_private *dev_priv =
 512                 container_of(work, typeof(*dev_priv), psr.work.work);
 513         struct intel_dp *intel_dp = dev_priv->psr.enabled;
 514         struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
 515         enum pipe pipe = to_intel_crtc(crtc)->pipe;
 516
 517         /* We have to make sure PSR is ready for re-enable
 518          * otherwise it keeps disabled until next full enable/disable cycle.
 519          * PSR might take some time to get fully disabled
 520          * and be ready for re-enable.
 521          */
 522         if (HAS_DDI(dev_priv->dev)) {
 523                 if (wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev_priv->dev)) &
 524                               EDP_PSR_STATUS_STATE_MASK) == 0, 50)) {
 525                         DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
 526                         return;
 527                 }
 528         } else {
 529                 if (wait_for((I915_READ(VLV_PSRSTAT(pipe)) &
 530                               VLV_EDP_PSR_IN_TRANS) == 0, 1)) {
 531                         DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
 532                         return;
 533                 }
 534         }
 535         mutex_lock(&dev_priv->psr.lock);
 536         intel_dp = dev_priv->psr.enabled;
 537
 538         if (!intel_dp)
 539                 goto unlock;
 540
 541         /*
 542          * The delayed work can race with an invalidate hence we need to
 543          * recheck. Since psr_flush first clears this and then reschedules we
 544          * won't ever miss a flush when bailing out here.
 545          */
 546         if (dev_priv->psr.busy_frontbuffer_bits)
 547                 goto unlock;
 548
 549         intel_psr_activate(intel_dp);
 550 unlock:
 551         mutex_unlock(&dev_priv->psr.lock);
 552 }
 553
 554 static void intel_psr_exit(struct drm_device *dev)
 555 {
 556         struct drm_i915_private *dev_priv = dev->dev_private;
 557         struct intel_dp *intel_dp = dev_priv->psr.enabled;
 558         struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
 559         enum pipe pipe = to_intel_crtc(crtc)->pipe;
 560         u32 val;
 561
 562         if (!dev_priv->psr.active)
 563                 return;
 564
 565         if (HAS_DDI(dev)) {
 566                 val = I915_READ(EDP_PSR_CTL(dev));
 567
 568                 WARN_ON(!(val & EDP_PSR_ENABLE));
 569
 570                 I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);
 571         } else {
 572                 val = I915_READ(VLV_PSRCTL(pipe));
 573
 574                 /* Here we do the transition from PSR_state 3 to PSR_state 5
 575                  * directly once PSR State 4 that is active with single frame
 576                  * update can be skipped. PSR_state 5 that is PSR exit then
 577                  * Hardware is responsible to transition back to PSR_state 1
 578                  * that is PSR inactive. Same state after
 579                  * vlv_edp_psr_enable_source.
 580                  */
 581                 val &= ~VLV_EDP_PSR_ACTIVE_ENTRY;
 582                 I915_WRITE(VLV_PSRCTL(pipe), val);
 583
 584                 /* Send AUX wake up - Spec says after transitioning to PSR
 585                  * active we have to send AUX wake up by writing 01h in DPCD
 586                  * 600h of sink device.
 587                  * XXX: This might slow down the transition, but without this
 588                  * HW doesn't complete the transition to PSR_state 1 and we
 589                  * never get the screen updated.
 590                  */
 591                 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
 592                                    DP_SET_POWER_D0);
 593         }
 594
 595         dev_priv->psr.active = false;
 596 }
 597
 598 /**
 599  * intel_psr_invalidate - Invalidade PSR
 600  * @dev: DRM device
 601  * @frontbuffer_bits: frontbuffer plane tracking bits
 602  *
 603  * Since the hardware frontbuffer tracking has gaps we need to integrate
 604  * with the software frontbuffer tracking. This function gets called every
 605  * time frontbuffer rendering starts and a buffer gets dirtied. PSR must be
 606  * disabled if the frontbuffer mask contains a buffer relevant to PSR.
 607  *
 608  * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits."
 609  */
 610 void intel_psr_invalidate(struct drm_device *dev,
 611                               unsigned frontbuffer_bits)
 612 {
 613         struct drm_i915_private *dev_priv = dev->dev_private;
 614         struct drm_crtc *crtc;
 615         enum pipe pipe;
 616
 617         mutex_lock(&dev_priv->psr.lock);
 618         if (!dev_priv->psr.enabled) {
 619                 mutex_unlock(&dev_priv->psr.lock);
 620                 return;
 621         }
 622
 623         crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
 624         pipe = to_intel_crtc(crtc)->pipe;
 625
 626         intel_psr_exit(dev);
 627
 628         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
 629
 630         dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
 631         mutex_unlock(&dev_priv->psr.lock);
 632 }
 633
 634 /**
 635  * intel_psr_flush - Flush PSR
 636  * @dev: DRM device
 637  * @frontbuffer_bits: frontbuffer plane tracking bits
 638  *
 639  * Since the hardware frontbuffer tracking has gaps we need to integrate
 640  * with the software frontbuffer tracking. This function gets called every
 641  * time frontbuffer rendering has completed and flushed out to memory. PSR
 642  * can be enabled again if no other frontbuffer relevant to PSR is dirty.
 643  *
 644  * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits.
 645  */
 646 void intel_psr_flush(struct drm_device *dev,
 647                          unsigned frontbuffer_bits)
 648 {
 649         struct drm_i915_private *dev_priv = dev->dev_private;
 650         struct drm_crtc *crtc;
 651         enum pipe pipe;
 652
 653         mutex_lock(&dev_priv->psr.lock);
 654         if (!dev_priv->psr.enabled) {
 655                 mutex_unlock(&dev_priv->psr.lock);
 656                 return;
 657         }
 658
 659         crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
 660         pipe = to_intel_crtc(crtc)->pipe;
 661         dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
 662
 663         /*
 664          * On Haswell sprite plane updates don't result in a psr invalidating
 665          * signal in the hardware. Which means we need to manually fake this in
 666          * software for all flushes, not just when we've seen a preceding
 667          * invalidation through frontbuffer rendering.
 668          */
 669         if (IS_HASWELL(dev) &&
 670             (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)))
 671                 intel_psr_exit(dev);
 672
 673         /*
 674          * On Valleyview and Cherryview we don't use hardware tracking so
 675          * any plane updates or cursor moves don't result in a PSR
 676          * invalidating. Which means we need to manually fake this in
 677          * software for all flushes, not just when we've seen a preceding
 678          * invalidation through frontbuffer rendering. */
 679         if (!HAS_DDI(dev))
 680                 intel_psr_exit(dev);
 681
 682         if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
 683                 schedule_delayed_work(&dev_priv->psr.work,
 684                                       msecs_to_jiffies(100));
 685         mutex_unlock(&dev_priv->psr.lock);
 686 }
 687
 688 /**
 689  * intel_psr_init - Init basic PSR work and mutex.
 690  * @dev: DRM device
 691  *
 692  * This function is  called only once at driver load to initialize basic
 693  * PSR stuff.
 694  */
 695 void intel_psr_init(struct drm_device *dev)
 696 {
 697         struct drm_i915_private *dev_priv = dev->dev_private;
 698
 699         INIT_DELAYED_WORK(&dev_priv->psr.work, intel_psr_work);
 700         mutex_init(&dev_priv->psr.lock);
 701 }