1 /* SPDX-License-Identifier: MIT */
3 * Copyright © 2019 Intel Corporation
9 #include <linux/types.h>
11 #include "display/intel_display.h"
12 #include "display/intel_global_state.h"
17 struct drm_i915_private;
19 struct intel_atomic_state;
20 struct intel_bw_state;
22 struct intel_crtc_state;
28 void intel_init_clock_gating(struct drm_i915_private *dev_priv);
29 void intel_suspend_hw(struct drm_i915_private *dev_priv);
30 int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
31 void intel_init_pm(struct drm_i915_private *dev_priv);
32 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
33 void intel_pm_setup(struct drm_i915_private *dev_priv);
34 void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv);
35 void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv);
36 void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv);
37 void skl_wm_get_hw_state(struct drm_i915_private *dev_priv);
38 void intel_wm_state_verify(struct intel_crtc *crtc,
39 struct intel_crtc_state *new_crtc_state);
40 u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *dev_priv);
41 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv);
42 u32 skl_ddb_dbuf_slice_mask(struct drm_i915_private *dev_priv,
43 const struct skl_ddb_entry *entry);
44 void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
45 void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
46 void skl_wm_sanitize(struct drm_i915_private *dev_priv);
47 bool intel_can_enable_sagv(struct drm_i915_private *dev_priv,
48 const struct intel_bw_state *bw_state);
49 void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
50 void intel_sagv_post_plane_update(struct intel_atomic_state *state);
51 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
52 const struct skl_ddb_entry *entries,
53 int num_entries, int ignore_idx);
54 void skl_write_plane_wm(struct intel_plane *plane,
55 const struct intel_crtc_state *crtc_state);
56 void skl_write_cursor_wm(struct intel_plane *plane,
57 const struct intel_crtc_state *crtc_state);
58 bool ilk_disable_lp_wm(struct drm_i915_private *dev_priv);
59 void intel_init_ipc(struct drm_i915_private *dev_priv);
60 void intel_enable_ipc(struct drm_i915_private *dev_priv);
62 bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable);
64 struct intel_dbuf_state {
65 struct intel_global_state base;
67 struct skl_ddb_entry ddb[I915_MAX_PIPES];
68 unsigned int weight[I915_MAX_PIPES];
69 u8 slices[I915_MAX_PIPES];
75 struct intel_dbuf_state *
76 intel_atomic_get_dbuf_state(struct intel_atomic_state *state);
78 #define to_intel_dbuf_state(x) container_of((x), struct intel_dbuf_state, base)
79 #define intel_atomic_get_old_dbuf_state(state) \
80 to_intel_dbuf_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->dbuf.obj))
81 #define intel_atomic_get_new_dbuf_state(state) \
82 to_intel_dbuf_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->dbuf.obj))
84 int intel_dbuf_init(struct drm_i915_private *dev_priv);
85 void intel_dbuf_pre_plane_update(struct intel_atomic_state *state);
86 void intel_dbuf_post_plane_update(struct intel_atomic_state *state);
87 void intel_mbus_dbox_update(struct intel_atomic_state *state);
89 #endif /* __INTEL_PM_H__ */