1 /* SPDX-License-Identifier: MIT */
3 * Copyright © 2019 Intel Corporation
9 #include <linux/types.h>
11 #include "display/intel_display.h"
12 #include "display/intel_global_state.h"
17 struct drm_i915_private;
19 struct intel_atomic_state;
20 struct intel_bw_state;
22 struct intel_crtc_state;
28 void intel_init_clock_gating(struct drm_i915_private *dev_priv);
29 void intel_suspend_hw(struct drm_i915_private *dev_priv);
30 int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
31 void intel_init_pm(struct drm_i915_private *dev_priv);
32 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
33 void intel_pm_setup(struct drm_i915_private *dev_priv);
34 void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv);
35 void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv);
36 void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv);
37 void skl_wm_get_hw_state(struct drm_i915_private *dev_priv);
38 u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *dev_priv);
39 void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
40 struct skl_ddb_entry *ddb_y,
41 struct skl_ddb_entry *ddb_uv);
42 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv);
43 u32 skl_ddb_dbuf_slice_mask(struct drm_i915_private *dev_priv,
44 const struct skl_ddb_entry *entry);
45 void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
46 struct skl_pipe_wm *out);
47 void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
48 void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
49 void skl_wm_sanitize(struct drm_i915_private *dev_priv);
50 bool intel_can_enable_sagv(struct drm_i915_private *dev_priv,
51 const struct intel_bw_state *bw_state);
52 void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
53 void intel_sagv_post_plane_update(struct intel_atomic_state *state);
54 const struct skl_wm_level *skl_plane_wm_level(const struct skl_pipe_wm *pipe_wm,
55 enum plane_id plane_id,
57 const struct skl_wm_level *skl_plane_trans_wm(const struct skl_pipe_wm *pipe_wm,
58 enum plane_id plane_id);
59 bool skl_wm_level_equals(const struct skl_wm_level *l1,
60 const struct skl_wm_level *l2);
61 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
62 const struct skl_ddb_entry *entries,
63 int num_entries, int ignore_idx);
64 void skl_write_plane_wm(struct intel_plane *plane,
65 const struct intel_crtc_state *crtc_state);
66 void skl_write_cursor_wm(struct intel_plane *plane,
67 const struct intel_crtc_state *crtc_state);
68 bool ilk_disable_lp_wm(struct drm_i915_private *dev_priv);
69 void intel_init_ipc(struct drm_i915_private *dev_priv);
70 void intel_enable_ipc(struct drm_i915_private *dev_priv);
72 bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable);
74 struct intel_dbuf_state {
75 struct intel_global_state base;
77 struct skl_ddb_entry ddb[I915_MAX_PIPES];
78 unsigned int weight[I915_MAX_PIPES];
79 u8 slices[I915_MAX_PIPES];
85 struct intel_dbuf_state *
86 intel_atomic_get_dbuf_state(struct intel_atomic_state *state);
88 #define to_intel_dbuf_state(x) container_of((x), struct intel_dbuf_state, base)
89 #define intel_atomic_get_old_dbuf_state(state) \
90 to_intel_dbuf_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->dbuf.obj))
91 #define intel_atomic_get_new_dbuf_state(state) \
92 to_intel_dbuf_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->dbuf.obj))
94 int intel_dbuf_init(struct drm_i915_private *dev_priv);
95 void intel_dbuf_pre_plane_update(struct intel_atomic_state *state);
96 void intel_dbuf_post_plane_update(struct intel_atomic_state *state);
97 void intel_mbus_dbox_update(struct intel_atomic_state *state);
99 #endif /* __INTEL_PM_H__ */